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| author | Trygve Laugstøl <trygvis@inamo.no> | 2017-05-11 12:15:54 +0200 |
|---|---|---|
| committer | Trygve Laugstøl <trygvis@inamo.no> | 2017-05-11 16:58:33 +0200 |
| commit | 4d8f75c97b8f384f8452d27b50b68cf594bc779a (patch) | |
| tree | 6df99c647350d6be144920bee3b5f25d7ff3fc8a /stm32cubemx/Drivers | |
| parent | 8665bdbf682bdff02576a6f4393f09bc56572043 (diff) | |
| download | radio-controller-4d8f75c97b8f384f8452d27b50b68cf594bc779a.tar.gz radio-controller-4d8f75c97b8f384f8452d27b50b68cf594bc779a.tar.bz2 radio-controller-4d8f75c97b8f384f8452d27b50b68cf594bc779a.tar.xz radio-controller-4d8f75c97b8f384f8452d27b50b68cf594bc779a.zip | |
o Cleaning up generated files, removing space at end of line.
Diffstat (limited to 'stm32cubemx/Drivers')
37 files changed, 4923 insertions, 4923 deletions
diff --git a/stm32cubemx/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103x6.h b/stm32cubemx/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103x6.h index f869551..405f697 100644 --- a/stm32cubemx/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103x6.h +++ b/stm32cubemx/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103x6.h @@ -4,15 +4,15 @@ * @author MCD Application Team * @version V4.1.0 * @date 29-April-2016 - * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File. - * This file contains all the peripheral register's definitions, bits - * definitions and memory mapping for STM32F1xx devices. - * + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File. + * This file contains all the peripheral register's definitions, bits + * definitions and memory mapping for STM32F1xx devices. + * * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition * - Macros to access peripheral’s registers hardware - * + * ****************************************************************************** * @attention * @@ -51,19 +51,19 @@ /** @addtogroup stm32f103x6 * @{ */ - + #ifndef __STM32F103x6_H #define __STM32F103x6_H #ifdef __cplusplus extern "C" { -#endif +#endif /** @addtogroup Configuration_section_for_CMSIS * @{ */ /** - * @brief Configuration of the Cortex-M3 Processor and Core Peripherals + * @brief Configuration of the Cortex-M3 Processor and Core Peripherals */ #define __MPU_PRESENT 0 /*!< Other STM32 devices does not provide an MPU */ #define __CM3_REV 0x0200 /*!< Core Revision r2p0 */ @@ -79,8 +79,8 @@ */ /** - * @brief STM32F10x Interrupt Number Definition, according to the selected device - * in @ref Library_configuration_section + * @brief STM32F10x Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section */ /*!< Interrupt Number Definition */ @@ -149,10 +149,10 @@ typedef enum /** @addtogroup Peripheral_registers_structures * @{ - */ + */ -/** - * @brief Analog to Digital Converter +/** + * @brief Analog to Digital Converter */ typedef struct @@ -188,8 +188,8 @@ typedef struct __IO uint32_t DR; /*!< ADC data register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x4C */ } ADC_Common_TypeDef; -/** - * @brief Backup Registers +/** + * @brief Backup Registers */ typedef struct @@ -209,9 +209,9 @@ typedef struct __IO uint32_t CR; __IO uint32_t CSR; } BKP_TypeDef; - -/** - * @brief Controller Area Network TxMailBox + +/** + * @brief Controller Area Network TxMailBox */ typedef struct @@ -222,10 +222,10 @@ typedef struct __IO uint32_t TDHR; } CAN_TxMailBox_TypeDef; -/** - * @brief Controller Area Network FIFOMailBox +/** + * @brief Controller Area Network FIFOMailBox */ - + typedef struct { __IO uint32_t RIR; @@ -234,20 +234,20 @@ typedef struct __IO uint32_t RDHR; } CAN_FIFOMailBox_TypeDef; -/** - * @brief Controller Area Network FilterRegister +/** + * @brief Controller Area Network FilterRegister */ - + typedef struct { __IO uint32_t FR1; __IO uint32_t FR2; } CAN_FilterRegister_TypeDef; -/** - * @brief Controller Area Network +/** + * @brief Controller Area Network */ - + typedef struct { __IO uint32_t MCR; @@ -274,8 +274,8 @@ typedef struct CAN_FilterRegister_TypeDef sFilterRegister[14]; } CAN_TypeDef; -/** - * @brief CRC calculation unit +/** + * @brief CRC calculation unit */ typedef struct @@ -283,12 +283,12 @@ typedef struct __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ uint8_t RESERVED0; /*!< Reserved, Address offset: 0x05 */ - uint16_t RESERVED1; /*!< Reserved, Address offset: 0x06 */ - __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint16_t RESERVED1; /*!< Reserved, Address offset: 0x06 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ } CRC_TypeDef; -/** +/** * @brief Debug MCU */ @@ -298,7 +298,7 @@ typedef struct __IO uint32_t CR; }DBGMCU_TypeDef; -/** +/** * @brief DMA Controller */ @@ -318,7 +318,7 @@ typedef struct -/** +/** * @brief External Interrupt/Event Controller */ @@ -332,7 +332,7 @@ typedef struct __IO uint32_t PR; } EXTI_TypeDef; -/** +/** * @brief FLASH Registers */ @@ -349,10 +349,10 @@ typedef struct __IO uint32_t WRPR; } FLASH_TypeDef; -/** +/** * @brief Option Bytes Registers */ - + typedef struct { __IO uint16_t RDP; @@ -365,7 +365,7 @@ typedef struct __IO uint16_t WRP3; } OB_TypeDef; -/** +/** * @brief General Purpose I/O */ @@ -380,7 +380,7 @@ typedef struct __IO uint32_t LCKR; } GPIO_TypeDef; -/** +/** * @brief Alternate Function I/O */ @@ -390,9 +390,9 @@ typedef struct __IO uint32_t MAPR; __IO uint32_t EXTICR[4]; uint32_t RESERVED0; - __IO uint32_t MAPR2; + __IO uint32_t MAPR2; } AFIO_TypeDef; -/** +/** * @brief Inter Integrated Circuit Interface */ @@ -409,7 +409,7 @@ typedef struct __IO uint32_t TRISE; } I2C_TypeDef; -/** +/** * @brief Independent WATCHDOG */ @@ -421,7 +421,7 @@ typedef struct __IO uint32_t SR; /*!< Status register, Address offset: 0x0C */ } IWDG_TypeDef; -/** +/** * @brief Power Control */ @@ -431,7 +431,7 @@ typedef struct __IO uint32_t CSR; } PWR_TypeDef; -/** +/** * @brief Reset and Clock Control */ @@ -451,7 +451,7 @@ typedef struct } RCC_TypeDef; -/** +/** * @brief Real-Time Clock */ @@ -469,7 +469,7 @@ typedef struct __IO uint32_t ALRL; } RTC_TypeDef; -/** +/** * @brief SD host Interface */ @@ -497,7 +497,7 @@ typedef struct __IO uint32_t FIFO; } SDIO_TypeDef; -/** +/** * @brief Serial Peripheral Interface */ @@ -542,10 +542,10 @@ typedef struct }TIM_TypeDef; -/** +/** * @brief Universal Synchronous Asynchronous Receiver Transmitter */ - + typedef struct { __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */ @@ -557,42 +557,42 @@ typedef struct __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */ } USART_TypeDef; -/** +/** * @brief Universal Serial Bus Full Speed Device */ - + typedef struct { - __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */ - __IO uint16_t RESERVED0; /*!< Reserved */ + __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */ + __IO uint16_t RESERVED0; /*!< Reserved */ __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */ - __IO uint16_t RESERVED1; /*!< Reserved */ + __IO uint16_t RESERVED1; /*!< Reserved */ __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */ - __IO uint16_t RESERVED2; /*!< Reserved */ - __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */ - __IO uint16_t RESERVED3; /*!< Reserved */ + __IO uint16_t RESERVED2; /*!< Reserved */ + __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */ + __IO uint16_t RESERVED3; /*!< Reserved */ __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */ - __IO uint16_t RESERVED4; /*!< Reserved */ + __IO uint16_t RESERVED4; /*!< Reserved */ __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */ - __IO uint16_t RESERVED5; /*!< Reserved */ + __IO uint16_t RESERVED5; /*!< Reserved */ __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */ - __IO uint16_t RESERVED6; /*!< Reserved */ + __IO uint16_t RESERVED6; /*!< Reserved */ __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */ - __IO uint16_t RESERVED7[17]; /*!< Reserved */ + __IO uint16_t RESERVED7[17]; /*!< Reserved */ __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */ - __IO uint16_t RESERVED8; /*!< Reserved */ + __IO uint16_t RESERVED8; /*!< Reserved */ __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */ - __IO uint16_t RESERVED9; /*!< Reserved */ + __IO uint16_t RESERVED9; /*!< Reserved */ __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */ - __IO uint16_t RESERVEDA; /*!< Reserved */ + __IO uint16_t RESERVEDA; /*!< Reserved */ __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */ - __IO uint16_t RESERVEDB; /*!< Reserved */ + __IO uint16_t RESERVEDB; /*!< Reserved */ __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */ - __IO uint16_t RESERVEDC; /*!< Reserved */ + __IO uint16_t RESERVEDC; /*!< Reserved */ } USB_TypeDef; -/** +/** * @brief Window WATCHDOG */ @@ -606,7 +606,7 @@ typedef struct /** * @} */ - + /** @addtogroup Peripheral_memory_map * @{ */ @@ -678,10 +678,10 @@ typedef struct /** * @} */ - + /** @addtogroup Peripheral_declaration * @{ - */ + */ #define TIM2 ((TIM_TypeDef *) TIM2_BASE) #define TIM3 ((TIM_TypeDef *) TIM3_BASE) @@ -729,11 +729,11 @@ typedef struct /** @addtogroup Exported_constants * @{ */ - + /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ - + /******************************************************************************/ /* Peripheral Registers_Bits_Definition */ /******************************************************************************/ @@ -745,17 +745,17 @@ typedef struct /******************************************************************************/ /******************* Bit definition for CRC_DR register *********************/ -#define CRC_DR_DR_Pos (0U) +#define CRC_DR_DR_Pos (0U) #define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ /******************* Bit definition for CRC_IDR register ********************/ -#define CRC_IDR_IDR_Pos (0U) +#define CRC_IDR_IDR_Pos (0U) #define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */ #define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */ /******************** Bit definition for CRC_CR register ********************/ -#define CRC_CR_RESET_Pos (0U) +#define CRC_CR_RESET_Pos (0U) #define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */ #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */ @@ -766,23 +766,23 @@ typedef struct /******************************************************************************/ /******************** Bit definition for PWR_CR register ********************/ -#define PWR_CR_LPDS_Pos (0U) +#define PWR_CR_LPDS_Pos (0U) #define PWR_CR_LPDS_Msk (0x1U << PWR_CR_LPDS_Pos) /*!< 0x00000001 */ #define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-Power Deepsleep */ -#define PWR_CR_PDDS_Pos (1U) +#define PWR_CR_PDDS_Pos (1U) #define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /*!< 0x00000002 */ #define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */ -#define PWR_CR_CWUF_Pos (2U) +#define PWR_CR_CWUF_Pos (2U) #define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /*!< 0x00000004 */ #define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */ -#define PWR_CR_CSBF_Pos (3U) +#define PWR_CR_CSBF_Pos (3U) #define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /*!< 0x00000008 */ #define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */ -#define PWR_CR_PVDE_Pos (4U) +#define PWR_CR_PVDE_Pos (4U) #define PWR_CR_PVDE_Msk (0x1U << PWR_CR_PVDE_Pos) /*!< 0x00000010 */ #define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */ -#define PWR_CR_PLS_Pos (5U) +#define PWR_CR_PLS_Pos (5U) #define PWR_CR_PLS_Msk (0x7U << PWR_CR_PLS_Pos) /*!< 0x000000E0 */ #define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */ #define PWR_CR_PLS_0 (0x1U << PWR_CR_PLS_Pos) /*!< 0x00000020 */ @@ -799,22 +799,22 @@ typedef struct #define PWR_CR_PLS_2V8 ((uint32_t)0x000000C0) /*!< PVD level 2.8V */ #define PWR_CR_PLS_2V9 ((uint32_t)0x000000E0) /*!< PVD level 2.9V */ -#define PWR_CR_DBP_Pos (8U) +#define PWR_CR_DBP_Pos (8U) #define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */ #define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */ /******************* Bit definition for PWR_CSR register ********************/ -#define PWR_CSR_WUF_Pos (0U) +#define PWR_CSR_WUF_Pos (0U) #define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */ #define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */ -#define PWR_CSR_SBF_Pos (1U) +#define PWR_CSR_SBF_Pos (1U) #define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /*!< 0x00000002 */ #define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */ -#define PWR_CSR_PVDO_Pos (2U) +#define PWR_CSR_PVDO_Pos (2U) #define PWR_CSR_PVDO_Msk (0x1U << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */ #define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */ -#define PWR_CSR_EWUP_Pos (8U) +#define PWR_CSR_EWUP_Pos (8U) #define PWR_CSR_EWUP_Msk (0x1U << PWR_CSR_EWUP_Pos) /*!< 0x00000100 */ #define PWR_CSR_EWUP PWR_CSR_EWUP_Msk /*!< Enable WKUP pin */ @@ -825,93 +825,93 @@ typedef struct /******************************************************************************/ /******************* Bit definition for BKP_DR1 register ********************/ -#define BKP_DR1_D_Pos (0U) +#define BKP_DR1_D_Pos (0U) #define BKP_DR1_D_Msk (0xFFFFU << BKP_DR1_D_Pos) /*!< 0x0000FFFF */ #define BKP_DR1_D BKP_DR1_D_Msk /*!< Backup data */ /******************* Bit definition for BKP_DR2 register ********************/ -#define BKP_DR2_D_Pos (0U) +#define BKP_DR2_D_Pos (0U) #define BKP_DR2_D_Msk (0xFFFFU << BKP_DR2_D_Pos) /*!< 0x0000FFFF */ #define BKP_DR2_D BKP_DR2_D_Msk /*!< Backup data */ /******************* Bit definition for BKP_DR3 register ********************/ -#define BKP_DR3_D_Pos (0U) +#define BKP_DR3_D_Pos (0U) #define BKP_DR3_D_Msk (0xFFFFU << BKP_DR3_D_Pos) /*!< 0x0000FFFF */ #define BKP_DR3_D BKP_DR3_D_Msk /*!< Backup data */ /******************* Bit definition for BKP_DR4 register ********************/ -#define BKP_DR4_D_Pos (0U) +#define BKP_DR4_D_Pos (0U) #define BKP_DR4_D_Msk (0xFFFFU << BKP_DR4_D_Pos) /*!< 0x0000FFFF */ #define BKP_DR4_D BKP_DR4_D_Msk /*!< Backup data */ /******************* Bit definition for BKP_DR5 register ********************/ -#define BKP_DR5_D_Pos (0U) +#define BKP_DR5_D_Pos (0U) #define BKP_DR5_D_Msk (0xFFFFU << BKP_DR5_D_Pos) /*!< 0x0000FFFF */ #define BKP_DR5_D BKP_DR5_D_Msk /*!< Backup data */ /******************* Bit definition for BKP_DR6 register ********************/ -#define BKP_DR6_D_Pos (0U) +#define BKP_DR6_D_Pos (0U) #define BKP_DR6_D_Msk (0xFFFFU << BKP_DR6_D_Pos) /*!< 0x0000FFFF */ #define BKP_DR6_D BKP_DR6_D_Msk /*!< Backup data */ /******************* Bit definition for BKP_DR7 register ********************/ -#define BKP_DR7_D_Pos (0U) +#define BKP_DR7_D_Pos (0U) #define BKP_DR7_D_Msk (0xFFFFU << BKP_DR7_D_Pos) /*!< 0x0000FFFF */ #define BKP_DR7_D BKP_DR7_D_Msk /*!< Backup data */ /******************* Bit definition for BKP_DR8 register ********************/ -#define BKP_DR8_D_Pos (0U) +#define BKP_DR8_D_Pos (0U) #define BKP_DR8_D_Msk (0xFFFFU << BKP_DR8_D_Pos) /*!< 0x0000FFFF */ #define BKP_DR8_D BKP_DR8_D_Msk /*!< Backup data */ /******************* Bit definition for BKP_DR9 register ********************/ -#define BKP_DR9_D_Pos (0U) +#define BKP_DR9_D_Pos (0U) #define BKP_DR9_D_Msk (0xFFFFU << BKP_DR9_D_Pos) /*!< 0x0000FFFF */ #define BKP_DR9_D BKP_DR9_D_Msk /*!< Backup data */ /******************* Bit definition for BKP_DR10 register *******************/ -#define BKP_DR10_D_Pos (0U) +#define BKP_DR10_D_Pos (0U) #define BKP_DR10_D_Msk (0xFFFFU << BKP_DR10_D_Pos) /*!< 0x0000FFFF */ #define BKP_DR10_D BKP_DR10_D_Msk /*!< Backup data */ #define RTC_BKP_NUMBER 10 /****************** Bit definition for BKP_RTCCR register *******************/ -#define BKP_RTCCR_CAL_Pos (0U) +#define BKP_RTCCR_CAL_Pos (0U) #define BKP_RTCCR_CAL_Msk (0x7FU << BKP_RTCCR_CAL_Pos) /*!< 0x0000007F */ #define BKP_RTCCR_CAL BKP_RTCCR_CAL_Msk /*!< Calibration value */ -#define BKP_RTCCR_CCO_Pos (7U) +#define BKP_RTCCR_CCO_Pos (7U) #define BKP_RTCCR_CCO_Msk (0x1U << BKP_RTCCR_CCO_Pos) /*!< 0x00000080 */ #define BKP_RTCCR_CCO BKP_RTCCR_CCO_Msk /*!< Calibration Clock Output */ -#define BKP_RTCCR_ASOE_Pos (8U) +#define BKP_RTCCR_ASOE_Pos (8U) #define BKP_RTCCR_ASOE_Msk (0x1U << BKP_RTCCR_ASOE_Pos) /*!< 0x00000100 */ #define BKP_RTCCR_ASOE BKP_RTCCR_ASOE_Msk /*!< Alarm or Second Output Enable */ -#define BKP_RTCCR_ASOS_Pos (9U) +#define BKP_RTCCR_ASOS_Pos (9U) #define BKP_RTCCR_ASOS_Msk (0x1U << BKP_RTCCR_ASOS_Pos) /*!< 0x00000200 */ #define BKP_RTCCR_ASOS BKP_RTCCR_ASOS_Msk /*!< Alarm or Second Output Selection */ /******************** Bit definition for BKP_CR register ********************/ -#define BKP_CR_TPE_Pos (0U) +#define BKP_CR_TPE_Pos (0U) #define BKP_CR_TPE_Msk (0x1U << BKP_CR_TPE_Pos) /*!< 0x00000001 */ #define BKP_CR_TPE BKP_CR_TPE_Msk /*!< TAMPER pin enable */ -#define BKP_CR_TPAL_Pos (1U) +#define BKP_CR_TPAL_Pos (1U) #define BKP_CR_TPAL_Msk (0x1U << BKP_CR_TPAL_Pos) /*!< 0x00000002 */ #define BKP_CR_TPAL BKP_CR_TPAL_Msk /*!< TAMPER pin active level */ /******************* Bit definition for BKP_CSR register ********************/ -#define BKP_CSR_CTE_Pos (0U) +#define BKP_CSR_CTE_Pos (0U) #define BKP_CSR_CTE_Msk (0x1U << BKP_CSR_CTE_Pos) /*!< 0x00000001 */ #define BKP_CSR_CTE BKP_CSR_CTE_Msk /*!< Clear Tamper event */ -#define BKP_CSR_CTI_Pos (1U) +#define BKP_CSR_CTI_Pos (1U) #define BKP_CSR_CTI_Msk (0x1U << BKP_CSR_CTI_Pos) /*!< 0x00000002 */ #define BKP_CSR_CTI BKP_CSR_CTI_Msk /*!< Clear Tamper Interrupt */ -#define BKP_CSR_TPIE_Pos (2U) +#define BKP_CSR_TPIE_Pos (2U) #define BKP_CSR_TPIE_Msk (0x1U << BKP_CSR_TPIE_Pos) /*!< 0x00000004 */ #define BKP_CSR_TPIE BKP_CSR_TPIE_Msk /*!< TAMPER Pin interrupt enable */ -#define BKP_CSR_TEF_Pos (8U) +#define BKP_CSR_TEF_Pos (8U) #define BKP_CSR_TEF_Msk (0x1U << BKP_CSR_TEF_Pos) /*!< 0x00000100 */ #define BKP_CSR_TEF BKP_CSR_TEF_Msk /*!< Tamper Event Flag */ -#define BKP_CSR_TIF_Pos (9U) +#define BKP_CSR_TIF_Pos (9U) #define BKP_CSR_TIF_Msk (0x1U << BKP_CSR_TIF_Pos) /*!< 0x00000200 */ #define BKP_CSR_TIF BKP_CSR_TIF_Msk /*!< Tamper Interrupt Flag */ @@ -922,41 +922,41 @@ typedef struct /******************************************************************************/ /******************** Bit definition for RCC_CR register ********************/ -#define RCC_CR_HSION_Pos (0U) +#define RCC_CR_HSION_Pos (0U) #define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */ #define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */ -#define RCC_CR_HSIRDY_Pos (1U) +#define RCC_CR_HSIRDY_Pos (1U) #define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */ #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */ -#define RCC_CR_HSITRIM_Pos (3U) +#define RCC_CR_HSITRIM_Pos (3U) #define RCC_CR_HSITRIM_Msk (0x1FU << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */ #define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk /*!< Internal High Speed clock trimming */ -#define RCC_CR_HSICAL_Pos (8U) +#define RCC_CR_HSICAL_Pos (8U) #define RCC_CR_HSICAL_Msk (0xFFU << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */ #define RCC_CR_HSICAL RCC_CR_HSICAL_Msk /*!< Internal High Speed clock Calibration */ -#define RCC_CR_HSEON_Pos (16U) +#define RCC_CR_HSEON_Pos (16U) #define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */ #define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */ -#define RCC_CR_HSERDY_Pos (17U) +#define RCC_CR_HSERDY_Pos (17U) #define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */ #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready flag */ -#define RCC_CR_HSEBYP_Pos (18U) +#define RCC_CR_HSEBYP_Pos (18U) #define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */ #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */ -#define RCC_CR_CSSON_Pos (19U) +#define RCC_CR_CSSON_Pos (19U) #define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /*!< 0x00080000 */ #define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< Clock Security System enable */ -#define RCC_CR_PLLON_Pos (24U) +#define RCC_CR_PLLON_Pos (24U) #define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */ #define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< PLL enable */ -#define RCC_CR_PLLRDY_Pos (25U) +#define RCC_CR_PLLRDY_Pos (25U) #define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */ #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */ /******************* Bit definition for RCC_CFGR register *******************/ /*!< SW configuration */ -#define RCC_CFGR_SW_Pos (0U) +#define RCC_CFGR_SW_Pos (0U) #define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */ #define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */ #define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */ @@ -967,7 +967,7 @@ typedef struct #define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */ /*!< SWS configuration */ -#define RCC_CFGR_SWS_Pos (2U) +#define RCC_CFGR_SWS_Pos (2U) #define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */ #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */ #define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */ @@ -978,7 +978,7 @@ typedef struct #define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */ /*!< HPRE configuration */ -#define RCC_CFGR_HPRE_Pos (4U) +#define RCC_CFGR_HPRE_Pos (4U) #define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */ #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */ #define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */ @@ -997,7 +997,7 @@ typedef struct #define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */ /*!< PPRE1 configuration */ -#define RCC_CFGR_PPRE1_Pos (8U) +#define RCC_CFGR_PPRE1_Pos (8U) #define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */ #define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */ #define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */ @@ -1011,7 +1011,7 @@ typedef struct #define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */ /*!< PPRE2 configuration */ -#define RCC_CFGR_PPRE2_Pos (11U) +#define RCC_CFGR_PPRE2_Pos (11U) #define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */ #define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */ #define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */ @@ -1025,7 +1025,7 @@ typedef struct #define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */ /*!< ADCPPRE configuration */ -#define RCC_CFGR_ADCPRE_Pos (14U) +#define RCC_CFGR_ADCPRE_Pos (14U) #define RCC_CFGR_ADCPRE_Msk (0x3U << RCC_CFGR_ADCPRE_Pos) /*!< 0x0000C000 */ #define RCC_CFGR_ADCPRE RCC_CFGR_ADCPRE_Msk /*!< ADCPRE[1:0] bits (ADC prescaler) */ #define RCC_CFGR_ADCPRE_0 (0x1U << RCC_CFGR_ADCPRE_Pos) /*!< 0x00004000 */ @@ -1036,16 +1036,16 @@ typedef struct #define RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) /*!< PCLK2 divided by 6 */ #define RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) /*!< PCLK2 divided by 8 */ -#define RCC_CFGR_PLLSRC_Pos (16U) +#define RCC_CFGR_PLLSRC_Pos (16U) #define RCC_CFGR_PLLSRC_Msk (0x1U << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */ #define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */ -#define RCC_CFGR_PLLXTPRE_Pos (17U) +#define RCC_CFGR_PLLXTPRE_Pos (17U) #define RCC_CFGR_PLLXTPRE_Msk (0x1U << RCC_CFGR_PLLXTPRE_Pos) /*!< 0x00020000 */ #define RCC_CFGR_PLLXTPRE RCC_CFGR_PLLXTPRE_Msk /*!< HSE divider for PLL entry */ /*!< PLLMUL configuration */ -#define RCC_CFGR_PLLMULL_Pos (18U) +#define RCC_CFGR_PLLMULL_Pos (18U) #define RCC_CFGR_PLLMULL_Msk (0xFU << RCC_CFGR_PLLMULL_Pos) /*!< 0x003C0000 */ #define RCC_CFGR_PLLMULL RCC_CFGR_PLLMULL_Msk /*!< PLLMUL[3:0] bits (PLL multiplication factor) */ #define RCC_CFGR_PLLMULL_0 (0x1U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00040000 */ @@ -1057,54 +1057,54 @@ typedef struct #define RCC_CFGR_PLLXTPRE_HSE_DIV2 ((uint32_t)0x00020000) /*!< HSE clock divided by 2 for PLL entry */ #define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */ -#define RCC_CFGR_PLLMULL3_Pos (18U) +#define RCC_CFGR_PLLMULL3_Pos (18U) #define RCC_CFGR_PLLMULL3_Msk (0x1U << RCC_CFGR_PLLMULL3_Pos) /*!< 0x00040000 */ #define RCC_CFGR_PLLMULL3 RCC_CFGR_PLLMULL3_Msk /*!< PLL input clock*3 */ -#define RCC_CFGR_PLLMULL4_Pos (19U) +#define RCC_CFGR_PLLMULL4_Pos (19U) #define RCC_CFGR_PLLMULL4_Msk (0x1U << RCC_CFGR_PLLMULL4_Pos) /*!< 0x00080000 */ #define RCC_CFGR_PLLMULL4 RCC_CFGR_PLLMULL4_Msk /*!< PLL input clock*4 */ -#define RCC_CFGR_PLLMULL5_Pos (18U) +#define RCC_CFGR_PLLMULL5_Pos (18U) #define RCC_CFGR_PLLMULL5_Msk (0x3U << RCC_CFGR_PLLMULL5_Pos) /*!< 0x000C0000 */ #define RCC_CFGR_PLLMULL5 RCC_CFGR_PLLMULL5_Msk /*!< PLL input clock*5 */ -#define RCC_CFGR_PLLMULL6_Pos (20U) +#define RCC_CFGR_PLLMULL6_Pos (20U) #define RCC_CFGR_PLLMULL6_Msk (0x1U << RCC_CFGR_PLLMULL6_Pos) /*!< 0x00100000 */ #define RCC_CFGR_PLLMULL6 RCC_CFGR_PLLMULL6_Msk /*!< PLL input clock*6 */ -#define RCC_CFGR_PLLMULL7_Pos (18U) +#define RCC_CFGR_PLLMULL7_Pos (18U) #define RCC_CFGR_PLLMULL7_Msk (0x5U << RCC_CFGR_PLLMULL7_Pos) /*!< 0x00140000 */ #define RCC_CFGR_PLLMULL7 RCC_CFGR_PLLMULL7_Msk /*!< PLL input clock*7 */ -#define RCC_CFGR_PLLMULL8_Pos (19U) +#define RCC_CFGR_PLLMULL8_Pos (19U) #define RCC_CFGR_PLLMULL8_Msk (0x3U << RCC_CFGR_PLLMULL8_Pos) /*!< 0x00180000 */ #define RCC_CFGR_PLLMULL8 RCC_CFGR_PLLMULL8_Msk /*!< PLL input clock*8 */ -#define RCC_CFGR_PLLMULL9_Pos (18U) +#define RCC_CFGR_PLLMULL9_Pos (18U) #define RCC_CFGR_PLLMULL9_Msk (0x7U << RCC_CFGR_PLLMULL9_Pos) /*!< 0x001C0000 */ #define RCC_CFGR_PLLMULL9 RCC_CFGR_PLLMULL9_Msk /*!< PLL input clock*9 */ -#define RCC_CFGR_PLLMULL10_Pos (21U) +#define RCC_CFGR_PLLMULL10_Pos (21U) #define RCC_CFGR_PLLMULL10_Msk (0x1U << RCC_CFGR_PLLMULL10_Pos) /*!< 0x00200000 */ #define RCC_CFGR_PLLMULL10 RCC_CFGR_PLLMULL10_Msk /*!< PLL input clock10 */ -#define RCC_CFGR_PLLMULL11_Pos (18U) +#define RCC_CFGR_PLLMULL11_Pos (18U) #define RCC_CFGR_PLLMULL11_Msk (0x9U << RCC_CFGR_PLLMULL11_Pos) /*!< 0x00240000 */ #define RCC_CFGR_PLLMULL11 RCC_CFGR_PLLMULL11_Msk /*!< PLL input clock*11 */ -#define RCC_CFGR_PLLMULL12_Pos (19U) +#define RCC_CFGR_PLLMULL12_Pos (19U) #define RCC_CFGR_PLLMULL12_Msk (0x5U << RCC_CFGR_PLLMULL12_Pos) /*!< 0x00280000 */ #define RCC_CFGR_PLLMULL12 RCC_CFGR_PLLMULL12_Msk /*!< PLL input clock*12 */ -#define RCC_CFGR_PLLMULL13_Pos (18U) +#define RCC_CFGR_PLLMULL13_Pos (18U) #define RCC_CFGR_PLLMULL13_Msk (0xBU << RCC_CFGR_PLLMULL13_Pos) /*!< 0x002C0000 */ #define RCC_CFGR_PLLMULL13 RCC_CFGR_PLLMULL13_Msk /*!< PLL input clock*13 */ -#define RCC_CFGR_PLLMULL14_Pos (20U) +#define RCC_CFGR_PLLMULL14_Pos (20U) #define RCC_CFGR_PLLMULL14_Msk (0x3U << RCC_CFGR_PLLMULL14_Pos) /*!< 0x00300000 */ #define RCC_CFGR_PLLMULL14 RCC_CFGR_PLLMULL14_Msk /*!< PLL input clock*14 */ -#define RCC_CFGR_PLLMULL15_Pos (18U) +#define RCC_CFGR_PLLMULL15_Pos (18U) #define RCC_CFGR_PLLMULL15_Msk (0xDU << RCC_CFGR_PLLMULL15_Pos) /*!< 0x00340000 */ #define RCC_CFGR_PLLMULL15 RCC_CFGR_PLLMULL15_Msk /*!< PLL input clock*15 */ -#define RCC_CFGR_PLLMULL16_Pos (19U) +#define RCC_CFGR_PLLMULL16_Pos (19U) #define RCC_CFGR_PLLMULL16_Msk (0x7U << RCC_CFGR_PLLMULL16_Pos) /*!< 0x00380000 */ #define RCC_CFGR_PLLMULL16 RCC_CFGR_PLLMULL16_Msk /*!< PLL input clock*16 */ -#define RCC_CFGR_USBPRE_Pos (22U) +#define RCC_CFGR_USBPRE_Pos (22U) #define RCC_CFGR_USBPRE_Msk (0x1U << RCC_CFGR_USBPRE_Pos) /*!< 0x00400000 */ #define RCC_CFGR_USBPRE RCC_CFGR_USBPRE_Msk /*!< USB Device prescaler */ /*!< MCO configuration */ -#define RCC_CFGR_MCO_Pos (24U) +#define RCC_CFGR_MCO_Pos (24U) #define RCC_CFGR_MCO_Msk (0x7U << RCC_CFGR_MCO_Pos) /*!< 0x07000000 */ #define RCC_CFGR_MCO RCC_CFGR_MCO_Msk /*!< MCO[2:0] bits (Microcontroller Clock Output) */ #define RCC_CFGR_MCO_0 (0x1U << RCC_CFGR_MCO_Pos) /*!< 0x01000000 */ @@ -1129,90 +1129,90 @@ typedef struct #define RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLLCLK_DIV2 /*!<****************** Bit definition for RCC_CIR register ********************/ -#define RCC_CIR_LSIRDYF_Pos (0U) +#define RCC_CIR_LSIRDYF_Pos (0U) #define RCC_CIR_LSIRDYF_Msk (0x1U << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */ #define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk /*!< LSI Ready Interrupt flag */ -#define RCC_CIR_LSERDYF_Pos (1U) +#define RCC_CIR_LSERDYF_Pos (1U) #define RCC_CIR_LSERDYF_Msk (0x1U << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */ #define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk /*!< LSE Ready Interrupt flag */ -#define RCC_CIR_HSIRDYF_Pos (2U) +#define RCC_CIR_HSIRDYF_Pos (2U) #define RCC_CIR_HSIRDYF_Msk (0x1U << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */ #define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk /*!< HSI Ready Interrupt flag */ -#define RCC_CIR_HSERDYF_Pos (3U) +#define RCC_CIR_HSERDYF_Pos (3U) #define RCC_CIR_HSERDYF_Msk (0x1U << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */ #define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk /*!< HSE Ready Interrupt flag */ -#define RCC_CIR_PLLRDYF_Pos (4U) +#define RCC_CIR_PLLRDYF_Pos (4U) #define RCC_CIR_PLLRDYF_Msk (0x1U << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */ #define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk /*!< PLL Ready Interrupt flag */ -#define RCC_CIR_CSSF_Pos (7U) +#define RCC_CIR_CSSF_Pos (7U) #define RCC_CIR_CSSF_Msk (0x1U << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */ #define RCC_CIR_CSSF RCC_CIR_CSSF_Msk /*!< Clock Security System Interrupt flag */ -#define RCC_CIR_LSIRDYIE_Pos (8U) +#define RCC_CIR_LSIRDYIE_Pos (8U) #define RCC_CIR_LSIRDYIE_Msk (0x1U << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */ #define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk /*!< LSI Ready Interrupt Enable */ -#define RCC_CIR_LSERDYIE_Pos (9U) +#define RCC_CIR_LSERDYIE_Pos (9U) #define RCC_CIR_LSERDYIE_Msk (0x1U << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */ #define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk /*!< LSE Ready Interrupt Enable */ -#define RCC_CIR_HSIRDYIE_Pos (10U) +#define RCC_CIR_HSIRDYIE_Pos (10U) #define RCC_CIR_HSIRDYIE_Msk (0x1U << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */ #define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk /*!< HSI Ready Interrupt Enable */ -#define RCC_CIR_HSERDYIE_Pos (11U) +#define RCC_CIR_HSERDYIE_Pos (11U) #define RCC_CIR_HSERDYIE_Msk (0x1U << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */ #define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk /*!< HSE Ready Interrupt Enable */ -#define RCC_CIR_PLLRDYIE_Pos (12U) +#define RCC_CIR_PLLRDYIE_Pos (12U) #define RCC_CIR_PLLRDYIE_Msk (0x1U << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */ #define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk /*!< PLL Ready Interrupt Enable */ -#define RCC_CIR_LSIRDYC_Pos (16U) +#define RCC_CIR_LSIRDYC_Pos (16U) #define RCC_CIR_LSIRDYC_Msk (0x1U << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */ #define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk /*!< LSI Ready Interrupt Clear */ -#define RCC_CIR_LSERDYC_Pos (17U) +#define RCC_CIR_LSERDYC_Pos (17U) #define RCC_CIR_LSERDYC_Msk (0x1U << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */ #define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk /*!< LSE Ready Interrupt Clear */ -#define RCC_CIR_HSIRDYC_Pos (18U) +#define RCC_CIR_HSIRDYC_Pos (18U) #define RCC_CIR_HSIRDYC_Msk (0x1U << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */ #define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk /*!< HSI Ready Interrupt Clear */ -#define RCC_CIR_HSERDYC_Pos (19U) +#define RCC_CIR_HSERDYC_Pos (19U) #define RCC_CIR_HSERDYC_Msk (0x1U << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */ #define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk /*!< HSE Ready Interrupt Clear */ -#define RCC_CIR_PLLRDYC_Pos (20U) +#define RCC_CIR_PLLRDYC_Pos (20U) #define RCC_CIR_PLLRDYC_Msk (0x1U << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */ #define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk /*!< PLL Ready Interrupt Clear */ -#define RCC_CIR_CSSC_Pos (23U) +#define RCC_CIR_CSSC_Pos (23U) #define RCC_CIR_CSSC_Msk (0x1U << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */ #define RCC_CIR_CSSC RCC_CIR_CSSC_Msk /*!< Clock Security System Interrupt Clear */ /***************** Bit definition for RCC_APB2RSTR register *****************/ -#define RCC_APB2RSTR_AFIORST_Pos (0U) +#define RCC_APB2RSTR_AFIORST_Pos (0U) #define RCC_APB2RSTR_AFIORST_Msk (0x1U << RCC_APB2RSTR_AFIORST_Pos) /*!< 0x00000001 */ #define RCC_APB2RSTR_AFIORST RCC_APB2RSTR_AFIORST_Msk /*!< Alternate Function I/O reset */ -#define RCC_APB2RSTR_IOPARST_Pos (2U) +#define RCC_APB2RSTR_IOPARST_Pos (2U) #define RCC_APB2RSTR_IOPARST_Msk (0x1U << RCC_APB2RSTR_IOPARST_Pos) /*!< 0x00000004 */ #define RCC_APB2RSTR_IOPARST RCC_APB2RSTR_IOPARST_Msk /*!< I/O port A reset */ -#define RCC_APB2RSTR_IOPBRST_Pos (3U) +#define RCC_APB2RSTR_IOPBRST_Pos (3U) #define RCC_APB2RSTR_IOPBRST_Msk (0x1U << RCC_APB2RSTR_IOPBRST_Pos) /*!< 0x00000008 */ #define RCC_APB2RSTR_IOPBRST RCC_APB2RSTR_IOPBRST_Msk /*!< I/O port B reset */ -#define RCC_APB2RSTR_IOPCRST_Pos (4U) +#define RCC_APB2RSTR_IOPCRST_Pos (4U) #define RCC_APB2RSTR_IOPCRST_Msk (0x1U << RCC_APB2RSTR_IOPCRST_Pos) /*!< 0x00000010 */ #define RCC_APB2RSTR_IOPCRST RCC_APB2RSTR_IOPCRST_Msk /*!< I/O port C reset */ -#define RCC_APB2RSTR_IOPDRST_Pos (5U) +#define RCC_APB2RSTR_IOPDRST_Pos (5U) #define RCC_APB2RSTR_IOPDRST_Msk (0x1U << RCC_APB2RSTR_IOPDRST_Pos) /*!< 0x00000020 */ #define RCC_APB2RSTR_IOPDRST RCC_APB2RSTR_IOPDRST_Msk /*!< I/O port D reset */ -#define RCC_APB2RSTR_ADC1RST_Pos (9U) +#define RCC_APB2RSTR_ADC1RST_Pos (9U) #define RCC_APB2RSTR_ADC1RST_Msk (0x1U << RCC_APB2RSTR_ADC1RST_Pos) /*!< 0x00000200 */ #define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADC1RST_Msk /*!< ADC 1 interface reset */ -#define RCC_APB2RSTR_ADC2RST_Pos (10U) +#define RCC_APB2RSTR_ADC2RST_Pos (10U) #define RCC_APB2RSTR_ADC2RST_Msk (0x1U << RCC_APB2RSTR_ADC2RST_Pos) /*!< 0x00000400 */ #define RCC_APB2RSTR_ADC2RST RCC_APB2RSTR_ADC2RST_Msk /*!< ADC 2 interface reset */ -#define RCC_APB2RSTR_TIM1RST_Pos (11U) +#define RCC_APB2RSTR_TIM1RST_Pos (11U) #define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */ #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 Timer reset */ -#define RCC_APB2RSTR_SPI1RST_Pos (12U) +#define RCC_APB2RSTR_SPI1RST_Pos (12U) #define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */ #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI 1 reset */ -#define RCC_APB2RSTR_USART1RST_Pos (14U) +#define RCC_APB2RSTR_USART1RST_Pos (14U) #define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */ #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */ @@ -1222,35 +1222,35 @@ typedef struct /***************** Bit definition for RCC_APB1RSTR register *****************/ -#define RCC_APB1RSTR_TIM2RST_Pos (0U) +#define RCC_APB1RSTR_TIM2RST_Pos (0U) #define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */ #define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 reset */ -#define RCC_APB1RSTR_TIM3RST_Pos (1U) +#define RCC_APB1RSTR_TIM3RST_Pos (1U) #define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */ #define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 reset */ -#define RCC_APB1RSTR_WWDGRST_Pos (11U) +#define RCC_APB1RSTR_WWDGRST_Pos (11U) #define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */ #define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */ -#define RCC_APB1RSTR_USART2RST_Pos (17U) +#define RCC_APB1RSTR_USART2RST_Pos (17U) #define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */ #define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 reset */ -#define RCC_APB1RSTR_I2C1RST_Pos (21U) +#define RCC_APB1RSTR_I2C1RST_Pos (21U) #define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */ #define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */ -#define RCC_APB1RSTR_CAN1RST_Pos (25U) +#define RCC_APB1RSTR_CAN1RST_Pos (25U) #define RCC_APB1RSTR_CAN1RST_Msk (0x1U << RCC_APB1RSTR_CAN1RST_Pos) /*!< 0x02000000 */ #define RCC_APB1RSTR_CAN1RST RCC_APB1RSTR_CAN1RST_Msk /*!< CAN1 reset */ -#define RCC_APB1RSTR_BKPRST_Pos (27U) +#define RCC_APB1RSTR_BKPRST_Pos (27U) #define RCC_APB1RSTR_BKPRST_Msk (0x1U << RCC_APB1RSTR_BKPRST_Pos) /*!< 0x08000000 */ #define RCC_APB1RSTR_BKPRST RCC_APB1RSTR_BKPRST_Msk /*!< Backup interface reset */ -#define RCC_APB1RSTR_PWRRST_Pos (28U) +#define RCC_APB1RSTR_PWRRST_Pos (28U) #define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */ #define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< Power interface reset */ -#define RCC_APB1RSTR_USBRST_Pos (23U) +#define RCC_APB1RSTR_USBRST_Pos (23U) #define RCC_APB1RSTR_USBRST_Msk (0x1U << RCC_APB1RSTR_USBRST_Pos) /*!< 0x00800000 */ #define RCC_APB1RSTR_USBRST RCC_APB1RSTR_USBRST_Msk /*!< USB Device reset */ @@ -1260,16 +1260,16 @@ typedef struct /****************** Bit definition for RCC_AHBENR register ******************/ -#define RCC_AHBENR_DMA1EN_Pos (0U) +#define RCC_AHBENR_DMA1EN_Pos (0U) #define RCC_AHBENR_DMA1EN_Msk (0x1U << RCC_AHBENR_DMA1EN_Pos) /*!< 0x00000001 */ #define RCC_AHBENR_DMA1EN RCC_AHBENR_DMA1EN_Msk /*!< DMA1 clock enable */ -#define RCC_AHBENR_SRAMEN_Pos (2U) +#define RCC_AHBENR_SRAMEN_Pos (2U) #define RCC_AHBENR_SRAMEN_Msk (0x1U << RCC_AHBENR_SRAMEN_Pos) /*!< 0x00000004 */ #define RCC_AHBENR_SRAMEN RCC_AHBENR_SRAMEN_Msk /*!< SRAM interface clock enable */ -#define RCC_AHBENR_FLITFEN_Pos (4U) +#define RCC_AHBENR_FLITFEN_Pos (4U) #define RCC_AHBENR_FLITFEN_Msk (0x1U << RCC_AHBENR_FLITFEN_Pos) /*!< 0x00000010 */ #define RCC_AHBENR_FLITFEN RCC_AHBENR_FLITFEN_Msk /*!< FLITF clock enable */ -#define RCC_AHBENR_CRCEN_Pos (6U) +#define RCC_AHBENR_CRCEN_Pos (6U) #define RCC_AHBENR_CRCEN_Msk (0x1U << RCC_AHBENR_CRCEN_Pos) /*!< 0x00000040 */ #define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */ @@ -1277,36 +1277,36 @@ typedef struct /****************** Bit definition for RCC_APB2ENR register *****************/ -#define RCC_APB2ENR_AFIOEN_Pos (0U) +#define RCC_APB2ENR_AFIOEN_Pos (0U) #define RCC_APB2ENR_AFIOEN_Msk (0x1U << RCC_APB2ENR_AFIOEN_Pos) /*!< 0x00000001 */ #define RCC_APB2ENR_AFIOEN RCC_APB2ENR_AFIOEN_Msk /*!< Alternate Function I/O clock enable */ -#define RCC_APB2ENR_IOPAEN_Pos (2U) +#define RCC_APB2ENR_IOPAEN_Pos (2U) #define RCC_APB2ENR_IOPAEN_Msk (0x1U << RCC_APB2ENR_IOPAEN_Pos) /*!< 0x00000004 */ #define RCC_APB2ENR_IOPAEN RCC_APB2ENR_IOPAEN_Msk /*!< I/O port A clock enable */ -#define RCC_APB2ENR_IOPBEN_Pos (3U) +#define RCC_APB2ENR_IOPBEN_Pos (3U) #define RCC_APB2ENR_IOPBEN_Msk (0x1U << RCC_APB2ENR_IOPBEN_Pos) /*!< 0x00000008 */ #define RCC_APB2ENR_IOPBEN RCC_APB2ENR_IOPBEN_Msk /*!< I/O port B clock enable */ -#define RCC_APB2ENR_IOPCEN_Pos (4U) +#define RCC_APB2ENR_IOPCEN_Pos (4U) #define RCC_APB2ENR_IOPCEN_Msk (0x1U << RCC_APB2ENR_IOPCEN_Pos) /*!< 0x00000010 */ #define RCC_APB2ENR_IOPCEN RCC_APB2ENR_IOPCEN_Msk /*!< I/O port C clock enable */ -#define RCC_APB2ENR_IOPDEN_Pos (5U) +#define RCC_APB2ENR_IOPDEN_Pos (5U) #define RCC_APB2ENR_IOPDEN_Msk (0x1U << RCC_APB2ENR_IOPDEN_Pos) /*!< 0x00000020 */ #define RCC_APB2ENR_IOPDEN RCC_APB2ENR_IOPDEN_Msk /*!< I/O port D clock enable */ -#define RCC_APB2ENR_ADC1EN_Pos (9U) +#define RCC_APB2ENR_ADC1EN_Pos (9U) #define RCC_APB2ENR_ADC1EN_Msk (0x1U << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000200 */ #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk /*!< ADC 1 interface clock enable */ -#define RCC_APB2ENR_ADC2EN_Pos (10U) +#define RCC_APB2ENR_ADC2EN_Pos (10U) #define RCC_APB2ENR_ADC2EN_Msk (0x1U << RCC_APB2ENR_ADC2EN_Pos) /*!< 0x00000400 */ #define RCC_APB2ENR_ADC2EN RCC_APB2ENR_ADC2EN_Msk /*!< ADC 2 interface clock enable */ -#define RCC_APB2ENR_TIM1EN_Pos (11U) +#define RCC_APB2ENR_TIM1EN_Pos (11U) #define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */ #define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk /*!< TIM1 Timer clock enable */ -#define RCC_APB2ENR_SPI1EN_Pos (12U) +#define RCC_APB2ENR_SPI1EN_Pos (12U) #define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */ #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI 1 clock enable */ -#define RCC_APB2ENR_USART1EN_Pos (14U) +#define RCC_APB2ENR_USART1EN_Pos (14U) #define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */ #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 clock enable */ @@ -1316,35 +1316,35 @@ typedef struct /***************** Bit definition for RCC_APB1ENR register ******************/ -#define RCC_APB1ENR_TIM2EN_Pos (0U) +#define RCC_APB1ENR_TIM2EN_Pos (0U) #define RCC_APB1ENR_TIM2EN_Msk (0x1U << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */ #define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk /*!< Timer 2 clock enabled*/ -#define RCC_APB1ENR_TIM3EN_Pos (1U) +#define RCC_APB1ENR_TIM3EN_Pos (1U) #define RCC_APB1ENR_TIM3EN_Msk (0x1U << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */ #define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk /*!< Timer 3 clock enable */ -#define RCC_APB1ENR_WWDGEN_Pos (11U) +#define RCC_APB1ENR_WWDGEN_Pos (11U) #define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */ #define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /*!< Window Watchdog clock enable */ -#define RCC_APB1ENR_USART2EN_Pos (17U) +#define RCC_APB1ENR_USART2EN_Pos (17U) #define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */ #define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART 2 clock enable */ -#define RCC_APB1ENR_I2C1EN_Pos (21U) +#define RCC_APB1ENR_I2C1EN_Pos (21U) #define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */ #define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /*!< I2C 1 clock enable */ -#define RCC_APB1ENR_CAN1EN_Pos (25U) +#define RCC_APB1ENR_CAN1EN_Pos (25U) #define RCC_APB1ENR_CAN1EN_Msk (0x1U << RCC_APB1ENR_CAN1EN_Pos) /*!< 0x02000000 */ #define RCC_APB1ENR_CAN1EN RCC_APB1ENR_CAN1EN_Msk /*!< CAN1 clock enable */ -#define RCC_APB1ENR_BKPEN_Pos (27U) +#define RCC_APB1ENR_BKPEN_Pos (27U) #define RCC_APB1ENR_BKPEN_Msk (0x1U << RCC_APB1ENR_BKPEN_Pos) /*!< 0x08000000 */ #define RCC_APB1ENR_BKPEN RCC_APB1ENR_BKPEN_Msk /*!< Backup interface clock enable */ -#define RCC_APB1ENR_PWREN_Pos (28U) +#define RCC_APB1ENR_PWREN_Pos (28U) #define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */ #define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< Power interface clock enable */ -#define RCC_APB1ENR_USBEN_Pos (23U) +#define RCC_APB1ENR_USBEN_Pos (23U) #define RCC_APB1ENR_USBEN_Msk (0x1U << RCC_APB1ENR_USBEN_Pos) /*!< 0x00800000 */ #define RCC_APB1ENR_USBEN RCC_APB1ENR_USBEN_Msk /*!< USB Device clock enable */ @@ -1354,17 +1354,17 @@ typedef struct /******************* Bit definition for RCC_BDCR register *******************/ -#define RCC_BDCR_LSEON_Pos (0U) +#define RCC_BDCR_LSEON_Pos (0U) #define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */ #define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*!< External Low Speed oscillator enable */ -#define RCC_BDCR_LSERDY_Pos (1U) +#define RCC_BDCR_LSERDY_Pos (1U) #define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */ #define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*!< External Low Speed oscillator Ready */ -#define RCC_BDCR_LSEBYP_Pos (2U) +#define RCC_BDCR_LSEBYP_Pos (2U) #define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */ #define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*!< External Low Speed oscillator Bypass */ -#define RCC_BDCR_RTCSEL_Pos (8U) +#define RCC_BDCR_RTCSEL_Pos (8U) #define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */ #define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */ #define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */ @@ -1376,44 +1376,44 @@ typedef struct #define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */ #define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */ -#define RCC_BDCR_RTCEN_Pos (15U) +#define RCC_BDCR_RTCEN_Pos (15U) #define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */ #define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk /*!< RTC clock enable */ -#define RCC_BDCR_BDRST_Pos (16U) +#define RCC_BDCR_BDRST_Pos (16U) #define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */ #define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk /*!< Backup domain software reset */ -/******************* Bit definition for RCC_CSR register ********************/ -#define RCC_CSR_LSION_Pos (0U) +/******************* Bit definition for RCC_CSR register ********************/ +#define RCC_CSR_LSION_Pos (0U) #define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */ #define RCC_CSR_LSION RCC_CSR_LSION_Msk /*!< Internal Low Speed oscillator enable */ -#define RCC_CSR_LSIRDY_Pos (1U) +#define RCC_CSR_LSIRDY_Pos (1U) #define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */ #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /*!< Internal Low Speed oscillator Ready */ -#define RCC_CSR_RMVF_Pos (24U) +#define RCC_CSR_RMVF_Pos (24U) #define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */ #define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /*!< Remove reset flag */ -#define RCC_CSR_PINRSTF_Pos (26U) +#define RCC_CSR_PINRSTF_Pos (26U) #define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */ #define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /*!< PIN reset flag */ -#define RCC_CSR_PORRSTF_Pos (27U) +#define RCC_CSR_PORRSTF_Pos (27U) #define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */ #define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /*!< POR/PDR reset flag */ -#define RCC_CSR_SFTRSTF_Pos (28U) +#define RCC_CSR_SFTRSTF_Pos (28U) #define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */ #define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /*!< Software Reset flag */ -#define RCC_CSR_IWDGRSTF_Pos (29U) +#define RCC_CSR_IWDGRSTF_Pos (29U) #define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */ #define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /*!< Independent Watchdog reset flag */ -#define RCC_CSR_WWDGRSTF_Pos (30U) +#define RCC_CSR_WWDGRSTF_Pos (30U) #define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */ #define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */ -#define RCC_CSR_LPWRRSTF_Pos (31U) +#define RCC_CSR_LPWRRSTF_Pos (31U) #define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */ #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */ - + /******************************************************************************/ /* */ /* General Purpose and Alternate Function I/O */ @@ -1421,521 +1421,521 @@ typedef struct /******************************************************************************/ /******************* Bit definition for GPIO_CRL register *******************/ -#define GPIO_CRL_MODE_Pos (0U) +#define GPIO_CRL_MODE_Pos (0U) #define GPIO_CRL_MODE_Msk (0x33333333U << GPIO_CRL_MODE_Pos) /*!< 0x33333333 */ #define GPIO_CRL_MODE GPIO_CRL_MODE_Msk /*!< Port x mode bits */ -#define GPIO_CRL_MODE0_Pos (0U) +#define GPIO_CRL_MODE0_Pos (0U) #define GPIO_CRL_MODE0_Msk (0x3U << GPIO_CRL_MODE0_Pos) /*!< 0x00000003 */ #define GPIO_CRL_MODE0 GPIO_CRL_MODE0_Msk /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */ #define GPIO_CRL_MODE0_0 (0x1U << GPIO_CRL_MODE0_Pos) /*!< 0x00000001 */ #define GPIO_CRL_MODE0_1 (0x2U << GPIO_CRL_MODE0_Pos) /*!< 0x00000002 */ -#define GPIO_CRL_MODE1_Pos (4U) +#define GPIO_CRL_MODE1_Pos (4U) #define GPIO_CRL_MODE1_Msk (0x3U << GPIO_CRL_MODE1_Pos) /*!< 0x00000030 */ #define GPIO_CRL_MODE1 GPIO_CRL_MODE1_Msk /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */ #define GPIO_CRL_MODE1_0 (0x1U << GPIO_CRL_MODE1_Pos) /*!< 0x00000010 */ #define GPIO_CRL_MODE1_1 (0x2U << GPIO_CRL_MODE1_Pos) /*!< 0x00000020 */ -#define GPIO_CRL_MODE2_Pos (8U) +#define GPIO_CRL_MODE2_Pos (8U) #define GPIO_CRL_MODE2_Msk (0x3U << GPIO_CRL_MODE2_Pos) /*!< 0x00000300 */ #define GPIO_CRL_MODE2 GPIO_CRL_MODE2_Msk /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */ #define GPIO_CRL_MODE2_0 (0x1U << GPIO_CRL_MODE2_Pos) /*!< 0x00000100 */ #define GPIO_CRL_MODE2_1 (0x2U << GPIO_CRL_MODE2_Pos) /*!< 0x00000200 */ -#define GPIO_CRL_MODE3_Pos (12U) +#define GPIO_CRL_MODE3_Pos (12U) #define GPIO_CRL_MODE3_Msk (0x3U << GPIO_CRL_MODE3_Pos) /*!< 0x00003000 */ #define GPIO_CRL_MODE3 GPIO_CRL_MODE3_Msk /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */ #define GPIO_CRL_MODE3_0 (0x1U << GPIO_CRL_MODE3_Pos) /*!< 0x00001000 */ #define GPIO_CRL_MODE3_1 (0x2U << GPIO_CRL_MODE3_Pos) /*!< 0x00002000 */ -#define GPIO_CRL_MODE4_Pos (16U) +#define GPIO_CRL_MODE4_Pos (16U) #define GPIO_CRL_MODE4_Msk (0x3U << GPIO_CRL_MODE4_Pos) /*!< 0x00030000 */ #define GPIO_CRL_MODE4 GPIO_CRL_MODE4_Msk /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */ #define GPIO_CRL_MODE4_0 (0x1U << GPIO_CRL_MODE4_Pos) /*!< 0x00010000 */ #define GPIO_CRL_MODE4_1 (0x2U << GPIO_CRL_MODE4_Pos) /*!< 0x00020000 */ -#define GPIO_CRL_MODE5_Pos (20U) +#define GPIO_CRL_MODE5_Pos (20U) #define GPIO_CRL_MODE5_Msk (0x3U << GPIO_CRL_MODE5_Pos) /*!< 0x00300000 */ #define GPIO_CRL_MODE5 GPIO_CRL_MODE5_Msk /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */ #define GPIO_CRL_MODE5_0 (0x1U << GPIO_CRL_MODE5_Pos) /*!< 0x00100000 */ #define GPIO_CRL_MODE5_1 (0x2U << GPIO_CRL_MODE5_Pos) /*!< 0x00200000 */ -#define GPIO_CRL_MODE6_Pos (24U) +#define GPIO_CRL_MODE6_Pos (24U) #define GPIO_CRL_MODE6_Msk (0x3U << GPIO_CRL_MODE6_Pos) /*!< 0x03000000 */ #define GPIO_CRL_MODE6 GPIO_CRL_MODE6_Msk /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */ #define GPIO_CRL_MODE6_0 (0x1U << GPIO_CRL_MODE6_Pos) /*!< 0x01000000 */ #define GPIO_CRL_MODE6_1 (0x2U << GPIO_CRL_MODE6_Pos) /*!< 0x02000000 */ -#define GPIO_CRL_MODE7_Pos (28U) +#define GPIO_CRL_MODE7_Pos (28U) #define GPIO_CRL_MODE7_Msk (0x3U << GPIO_CRL_MODE7_Pos) /*!< 0x30000000 */ #define GPIO_CRL_MODE7 GPIO_CRL_MODE7_Msk /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */ #define GPIO_CRL_MODE7_0 (0x1U << GPIO_CRL_MODE7_Pos) /*!< 0x10000000 */ #define GPIO_CRL_MODE7_1 (0x2U << GPIO_CRL_MODE7_Pos) /*!< 0x20000000 */ -#define GPIO_CRL_CNF_Pos (2U) +#define GPIO_CRL_CNF_Pos (2U) #define GPIO_CRL_CNF_Msk (0x33333333U << GPIO_CRL_CNF_Pos) /*!< 0xCCCCCCCC */ #define GPIO_CRL_CNF GPIO_CRL_CNF_Msk /*!< Port x configuration bits */ -#define GPIO_CRL_CNF0_Pos (2U) +#define GPIO_CRL_CNF0_Pos (2U) #define GPIO_CRL_CNF0_Msk (0x3U << GPIO_CRL_CNF0_Pos) /*!< 0x0000000C */ #define GPIO_CRL_CNF0 GPIO_CRL_CNF0_Msk /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */ #define GPIO_CRL_CNF0_0 (0x1U << GPIO_CRL_CNF0_Pos) /*!< 0x00000004 */ #define GPIO_CRL_CNF0_1 (0x2U << GPIO_CRL_CNF0_Pos) /*!< 0x00000008 */ -#define GPIO_CRL_CNF1_Pos (6U) +#define GPIO_CRL_CNF1_Pos (6U) #define GPIO_CRL_CNF1_Msk (0x3U << GPIO_CRL_CNF1_Pos) /*!< 0x000000C0 */ #define GPIO_CRL_CNF1 GPIO_CRL_CNF1_Msk /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */ #define GPIO_CRL_CNF1_0 (0x1U << GPIO_CRL_CNF1_Pos) /*!< 0x00000040 */ #define GPIO_CRL_CNF1_1 (0x2U << GPIO_CRL_CNF1_Pos) /*!< 0x00000080 */ -#define GPIO_CRL_CNF2_Pos (10U) +#define GPIO_CRL_CNF2_Pos (10U) #define GPIO_CRL_CNF2_Msk (0x3U << GPIO_CRL_CNF2_Pos) /*!< 0x00000C00 */ #define GPIO_CRL_CNF2 GPIO_CRL_CNF2_Msk /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */ #define GPIO_CRL_CNF2_0 (0x1U << GPIO_CRL_CNF2_Pos) /*!< 0x00000400 */ #define GPIO_CRL_CNF2_1 (0x2U << GPIO_CRL_CNF2_Pos) /*!< 0x00000800 */ -#define GPIO_CRL_CNF3_Pos (14U) +#define GPIO_CRL_CNF3_Pos (14U) #define GPIO_CRL_CNF3_Msk (0x3U << GPIO_CRL_CNF3_Pos) /*!< 0x0000C000 */ #define GPIO_CRL_CNF3 GPIO_CRL_CNF3_Msk /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */ #define GPIO_CRL_CNF3_0 (0x1U << GPIO_CRL_CNF3_Pos) /*!< 0x00004000 */ #define GPIO_CRL_CNF3_1 (0x2U << GPIO_CRL_CNF3_Pos) /*!< 0x00008000 */ -#define GPIO_CRL_CNF4_Pos (18U) +#define GPIO_CRL_CNF4_Pos (18U) #define GPIO_CRL_CNF4_Msk (0x3U << GPIO_CRL_CNF4_Pos) /*!< 0x000C0000 */ #define GPIO_CRL_CNF4 GPIO_CRL_CNF4_Msk /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */ #define GPIO_CRL_CNF4_0 (0x1U << GPIO_CRL_CNF4_Pos) /*!< 0x00040000 */ #define GPIO_CRL_CNF4_1 (0x2U << GPIO_CRL_CNF4_Pos) /*!< 0x00080000 */ -#define GPIO_CRL_CNF5_Pos (22U) +#define GPIO_CRL_CNF5_Pos (22U) #define GPIO_CRL_CNF5_Msk (0x3U << GPIO_CRL_CNF5_Pos) /*!< 0x00C00000 */ #define GPIO_CRL_CNF5 GPIO_CRL_CNF5_Msk /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */ #define GPIO_CRL_CNF5_0 (0x1U << GPIO_CRL_CNF5_Pos) /*!< 0x00400000 */ #define GPIO_CRL_CNF5_1 (0x2U << GPIO_CRL_CNF5_Pos) /*!< 0x00800000 */ -#define GPIO_CRL_CNF6_Pos (26U) +#define GPIO_CRL_CNF6_Pos (26U) #define GPIO_CRL_CNF6_Msk (0x3U << GPIO_CRL_CNF6_Pos) /*!< 0x0C000000 */ #define GPIO_CRL_CNF6 GPIO_CRL_CNF6_Msk /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */ #define GPIO_CRL_CNF6_0 (0x1U << GPIO_CRL_CNF6_Pos) /*!< 0x04000000 */ #define GPIO_CRL_CNF6_1 (0x2U << GPIO_CRL_CNF6_Pos) /*!< 0x08000000 */ -#define GPIO_CRL_CNF7_Pos (30U) +#define GPIO_CRL_CNF7_Pos (30U) #define GPIO_CRL_CNF7_Msk (0x3U << GPIO_CRL_CNF7_Pos) /*!< 0xC0000000 */ #define GPIO_CRL_CNF7 GPIO_CRL_CNF7_Msk /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */ #define GPIO_CRL_CNF7_0 (0x1U << GPIO_CRL_CNF7_Pos) /*!< 0x40000000 */ #define GPIO_CRL_CNF7_1 (0x2U << GPIO_CRL_CNF7_Pos) /*!< 0x80000000 */ /******************* Bit definition for GPIO_CRH register *******************/ -#define GPIO_CRH_MODE_Pos (0U) +#define GPIO_CRH_MODE_Pos (0U) #define GPIO_CRH_MODE_Msk (0x33333333U << GPIO_CRH_MODE_Pos) /*!< 0x33333333 */ #define GPIO_CRH_MODE GPIO_CRH_MODE_Msk /*!< Port x mode bits */ -#define GPIO_CRH_MODE8_Pos (0U) +#define GPIO_CRH_MODE8_Pos (0U) #define GPIO_CRH_MODE8_Msk (0x3U << GPIO_CRH_MODE8_Pos) /*!< 0x00000003 */ #define GPIO_CRH_MODE8 GPIO_CRH_MODE8_Msk /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */ #define GPIO_CRH_MODE8_0 (0x1U << GPIO_CRH_MODE8_Pos) /*!< 0x00000001 */ #define GPIO_CRH_MODE8_1 (0x2U << GPIO_CRH_MODE8_Pos) /*!< 0x00000002 */ -#define GPIO_CRH_MODE9_Pos (4U) +#define GPIO_CRH_MODE9_Pos (4U) #define GPIO_CRH_MODE9_Msk (0x3U << GPIO_CRH_MODE9_Pos) /*!< 0x00000030 */ #define GPIO_CRH_MODE9 GPIO_CRH_MODE9_Msk /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */ #define GPIO_CRH_MODE9_0 (0x1U << GPIO_CRH_MODE9_Pos) /*!< 0x00000010 */ #define GPIO_CRH_MODE9_1 (0x2U << GPIO_CRH_MODE9_Pos) /*!< 0x00000020 */ -#define GPIO_CRH_MODE10_Pos (8U) +#define GPIO_CRH_MODE10_Pos (8U) #define GPIO_CRH_MODE10_Msk (0x3U << GPIO_CRH_MODE10_Pos) /*!< 0x00000300 */ #define GPIO_CRH_MODE10 GPIO_CRH_MODE10_Msk /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */ #define GPIO_CRH_MODE10_0 (0x1U << GPIO_CRH_MODE10_Pos) /*!< 0x00000100 */ #define GPIO_CRH_MODE10_1 (0x2U << GPIO_CRH_MODE10_Pos) /*!< 0x00000200 */ -#define GPIO_CRH_MODE11_Pos (12U) +#define GPIO_CRH_MODE11_Pos (12U) #define GPIO_CRH_MODE11_Msk (0x3U << GPIO_CRH_MODE11_Pos) /*!< 0x00003000 */ #define GPIO_CRH_MODE11 GPIO_CRH_MODE11_Msk /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */ #define GPIO_CRH_MODE11_0 (0x1U << GPIO_CRH_MODE11_Pos) /*!< 0x00001000 */ #define GPIO_CRH_MODE11_1 (0x2U << GPIO_CRH_MODE11_Pos) /*!< 0x00002000 */ -#define GPIO_CRH_MODE12_Pos (16U) +#define GPIO_CRH_MODE12_Pos (16U) #define GPIO_CRH_MODE12_Msk (0x3U << GPIO_CRH_MODE12_Pos) /*!< 0x00030000 */ #define GPIO_CRH_MODE12 GPIO_CRH_MODE12_Msk /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */ #define GPIO_CRH_MODE12_0 (0x1U << GPIO_CRH_MODE12_Pos) /*!< 0x00010000 */ #define GPIO_CRH_MODE12_1 (0x2U << GPIO_CRH_MODE12_Pos) /*!< 0x00020000 */ -#define GPIO_CRH_MODE13_Pos (20U) +#define GPIO_CRH_MODE13_Pos (20U) #define GPIO_CRH_MODE13_Msk (0x3U << GPIO_CRH_MODE13_Pos) /*!< 0x00300000 */ #define GPIO_CRH_MODE13 GPIO_CRH_MODE13_Msk /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */ #define GPIO_CRH_MODE13_0 (0x1U << GPIO_CRH_MODE13_Pos) /*!< 0x00100000 */ #define GPIO_CRH_MODE13_1 (0x2U << GPIO_CRH_MODE13_Pos) /*!< 0x00200000 */ -#define GPIO_CRH_MODE14_Pos (24U) +#define GPIO_CRH_MODE14_Pos (24U) #define GPIO_CRH_MODE14_Msk (0x3U << GPIO_CRH_MODE14_Pos) /*!< 0x03000000 */ #define GPIO_CRH_MODE14 GPIO_CRH_MODE14_Msk /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */ #define GPIO_CRH_MODE14_0 (0x1U << GPIO_CRH_MODE14_Pos) /*!< 0x01000000 */ #define GPIO_CRH_MODE14_1 (0x2U << GPIO_CRH_MODE14_Pos) /*!< 0x02000000 */ -#define GPIO_CRH_MODE15_Pos (28U) +#define GPIO_CRH_MODE15_Pos (28U) #define GPIO_CRH_MODE15_Msk (0x3U << GPIO_CRH_MODE15_Pos) /*!< 0x30000000 */ #define GPIO_CRH_MODE15 GPIO_CRH_MODE15_Msk /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */ #define GPIO_CRH_MODE15_0 (0x1U << GPIO_CRH_MODE15_Pos) /*!< 0x10000000 */ #define GPIO_CRH_MODE15_1 (0x2U << GPIO_CRH_MODE15_Pos) /*!< 0x20000000 */ -#define GPIO_CRH_CNF_Pos (2U) +#define GPIO_CRH_CNF_Pos (2U) #define GPIO_CRH_CNF_Msk (0x33333333U << GPIO_CRH_CNF_Pos) /*!< 0xCCCCCCCC */ #define GPIO_CRH_CNF GPIO_CRH_CNF_Msk /*!< Port x configuration bits */ -#define GPIO_CRH_CNF8_Pos (2U) +#define GPIO_CRH_CNF8_Pos (2U) #define GPIO_CRH_CNF8_Msk (0x3U << GPIO_CRH_CNF8_Pos) /*!< 0x0000000C */ #define GPIO_CRH_CNF8 GPIO_CRH_CNF8_Msk /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */ #define GPIO_CRH_CNF8_0 (0x1U << GPIO_CRH_CNF8_Pos) /*!< 0x00000004 */ #define GPIO_CRH_CNF8_1 (0x2U << GPIO_CRH_CNF8_Pos) /*!< 0x00000008 */ -#define GPIO_CRH_CNF9_Pos (6U) +#define GPIO_CRH_CNF9_Pos (6U) #define GPIO_CRH_CNF9_Msk (0x3U << GPIO_CRH_CNF9_Pos) /*!< 0x000000C0 */ #define GPIO_CRH_CNF9 GPIO_CRH_CNF9_Msk /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */ #define GPIO_CRH_CNF9_0 (0x1U << GPIO_CRH_CNF9_Pos) /*!< 0x00000040 */ #define GPIO_CRH_CNF9_1 (0x2U << GPIO_CRH_CNF9_Pos) /*!< 0x00000080 */ -#define GPIO_CRH_CNF10_Pos (10U) +#define GPIO_CRH_CNF10_Pos (10U) #define GPIO_CRH_CNF10_Msk (0x3U << GPIO_CRH_CNF10_Pos) /*!< 0x00000C00 */ #define GPIO_CRH_CNF10 GPIO_CRH_CNF10_Msk /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */ #define GPIO_CRH_CNF10_0 (0x1U << GPIO_CRH_CNF10_Pos) /*!< 0x00000400 */ #define GPIO_CRH_CNF10_1 (0x2U << GPIO_CRH_CNF10_Pos) /*!< 0x00000800 */ -#define GPIO_CRH_CNF11_Pos (14U) +#define GPIO_CRH_CNF11_Pos (14U) #define GPIO_CRH_CNF11_Msk (0x3U << GPIO_CRH_CNF11_Pos) /*!< 0x0000C000 */ #define GPIO_CRH_CNF11 GPIO_CRH_CNF11_Msk /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */ #define GPIO_CRH_CNF11_0 (0x1U << GPIO_CRH_CNF11_Pos) /*!< 0x00004000 */ #define GPIO_CRH_CNF11_1 (0x2U << GPIO_CRH_CNF11_Pos) /*!< 0x00008000 */ -#define GPIO_CRH_CNF12_Pos (18U) +#define GPIO_CRH_CNF12_Pos (18U) #define GPIO_CRH_CNF12_Msk (0x3U << GPIO_CRH_CNF12_Pos) /*!< 0x000C0000 */ #define GPIO_CRH_CNF12 GPIO_CRH_CNF12_Msk /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */ #define GPIO_CRH_CNF12_0 (0x1U << GPIO_CRH_CNF12_Pos) /*!< 0x00040000 */ #define GPIO_CRH_CNF12_1 (0x2U << GPIO_CRH_CNF12_Pos) /*!< 0x00080000 */ -#define GPIO_CRH_CNF13_Pos (22U) +#define GPIO_CRH_CNF13_Pos (22U) #define GPIO_CRH_CNF13_Msk (0x3U << GPIO_CRH_CNF13_Pos) /*!< 0x00C00000 */ #define GPIO_CRH_CNF13 GPIO_CRH_CNF13_Msk /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */ #define GPIO_CRH_CNF13_0 (0x1U << GPIO_CRH_CNF13_Pos) /*!< 0x00400000 */ #define GPIO_CRH_CNF13_1 (0x2U << GPIO_CRH_CNF13_Pos) /*!< 0x00800000 */ -#define GPIO_CRH_CNF14_Pos (26U) +#define GPIO_CRH_CNF14_Pos (26U) #define GPIO_CRH_CNF14_Msk (0x3U << GPIO_CRH_CNF14_Pos) /*!< 0x0C000000 */ #define GPIO_CRH_CNF14 GPIO_CRH_CNF14_Msk /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */ #define GPIO_CRH_CNF14_0 (0x1U << GPIO_CRH_CNF14_Pos) /*!< 0x04000000 */ #define GPIO_CRH_CNF14_1 (0x2U << GPIO_CRH_CNF14_Pos) /*!< 0x08000000 */ -#define GPIO_CRH_CNF15_Pos (30U) +#define GPIO_CRH_CNF15_Pos (30U) #define GPIO_CRH_CNF15_Msk (0x3U << GPIO_CRH_CNF15_Pos) /*!< 0xC0000000 */ #define GPIO_CRH_CNF15 GPIO_CRH_CNF15_Msk /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */ #define GPIO_CRH_CNF15_0 (0x1U << GPIO_CRH_CNF15_Pos) /*!< 0x40000000 */ #define GPIO_CRH_CNF15_1 (0x2U << GPIO_CRH_CNF15_Pos) /*!< 0x80000000 */ /*!<****************** Bit definition for GPIO_IDR register *******************/ -#define GPIO_IDR_IDR0_Pos (0U) +#define GPIO_IDR_IDR0_Pos (0U) #define GPIO_IDR_IDR0_Msk (0x1U << GPIO_IDR_IDR0_Pos) /*!< 0x00000001 */ #define GPIO_IDR_IDR0 GPIO_IDR_IDR0_Msk /*!< Port input data, bit 0 */ -#define GPIO_IDR_IDR1_Pos (1U) +#define GPIO_IDR_IDR1_Pos (1U) #define GPIO_IDR_IDR1_Msk (0x1U << GPIO_IDR_IDR1_Pos) /*!< 0x00000002 */ #define GPIO_IDR_IDR1 GPIO_IDR_IDR1_Msk /*!< Port input data, bit 1 */ -#define GPIO_IDR_IDR2_Pos (2U) +#define GPIO_IDR_IDR2_Pos (2U) #define GPIO_IDR_IDR2_Msk (0x1U << GPIO_IDR_IDR2_Pos) /*!< 0x00000004 */ #define GPIO_IDR_IDR2 GPIO_IDR_IDR2_Msk /*!< Port input data, bit 2 */ -#define GPIO_IDR_IDR3_Pos (3U) +#define GPIO_IDR_IDR3_Pos (3U) #define GPIO_IDR_IDR3_Msk (0x1U << GPIO_IDR_IDR3_Pos) /*!< 0x00000008 */ #define GPIO_IDR_IDR3 GPIO_IDR_IDR3_Msk /*!< Port input data, bit 3 */ -#define GPIO_IDR_IDR4_Pos (4U) +#define GPIO_IDR_IDR4_Pos (4U) #define GPIO_IDR_IDR4_Msk (0x1U << GPIO_IDR_IDR4_Pos) /*!< 0x00000010 */ #define GPIO_IDR_IDR4 GPIO_IDR_IDR4_Msk /*!< Port input data, bit 4 */ -#define GPIO_IDR_IDR5_Pos (5U) +#define GPIO_IDR_IDR5_Pos (5U) #define GPIO_IDR_IDR5_Msk (0x1U << GPIO_IDR_IDR5_Pos) /*!< 0x00000020 */ #define GPIO_IDR_IDR5 GPIO_IDR_IDR5_Msk /*!< Port input data, bit 5 */ -#define GPIO_IDR_IDR6_Pos (6U) +#define GPIO_IDR_IDR6_Pos (6U) #define GPIO_IDR_IDR6_Msk (0x1U << GPIO_IDR_IDR6_Pos) /*!< 0x00000040 */ #define GPIO_IDR_IDR6 GPIO_IDR_IDR6_Msk /*!< Port input data, bit 6 */ -#define GPIO_IDR_IDR7_Pos (7U) +#define GPIO_IDR_IDR7_Pos (7U) #define GPIO_IDR_IDR7_Msk (0x1U << GPIO_IDR_IDR7_Pos) /*!< 0x00000080 */ #define GPIO_IDR_IDR7 GPIO_IDR_IDR7_Msk /*!< Port input data, bit 7 */ -#define GPIO_IDR_IDR8_Pos (8U) +#define GPIO_IDR_IDR8_Pos (8U) #define GPIO_IDR_IDR8_Msk (0x1U << GPIO_IDR_IDR8_Pos) /*!< 0x00000100 */ #define GPIO_IDR_IDR8 GPIO_IDR_IDR8_Msk /*!< Port input data, bit 8 */ -#define GPIO_IDR_IDR9_Pos (9U) +#define GPIO_IDR_IDR9_Pos (9U) #define GPIO_IDR_IDR9_Msk (0x1U << GPIO_IDR_IDR9_Pos) /*!< 0x00000200 */ #define GPIO_IDR_IDR9 GPIO_IDR_IDR9_Msk /*!< Port input data, bit 9 */ -#define GPIO_IDR_IDR10_Pos (10U) +#define GPIO_IDR_IDR10_Pos (10U) #define GPIO_IDR_IDR10_Msk (0x1U << GPIO_IDR_IDR10_Pos) /*!< 0x00000400 */ #define GPIO_IDR_IDR10 GPIO_IDR_IDR10_Msk /*!< Port input data, bit 10 */ -#define GPIO_IDR_IDR11_Pos (11U) +#define GPIO_IDR_IDR11_Pos (11U) #define GPIO_IDR_IDR11_Msk (0x1U << GPIO_IDR_IDR11_Pos) /*!< 0x00000800 */ #define GPIO_IDR_IDR11 GPIO_IDR_IDR11_Msk /*!< Port input data, bit 11 */ -#define GPIO_IDR_IDR12_Pos (12U) +#define GPIO_IDR_IDR12_Pos (12U) #define GPIO_IDR_IDR12_Msk (0x1U << GPIO_IDR_IDR12_Pos) /*!< 0x00001000 */ #define GPIO_IDR_IDR12 GPIO_IDR_IDR12_Msk /*!< Port input data, bit 12 */ -#define GPIO_IDR_IDR13_Pos (13U) +#define GPIO_IDR_IDR13_Pos (13U) #define GPIO_IDR_IDR13_Msk (0x1U << GPIO_IDR_IDR13_Pos) /*!< 0x00002000 */ #define GPIO_IDR_IDR13 GPIO_IDR_IDR13_Msk /*!< Port input data, bit 13 */ -#define GPIO_IDR_IDR14_Pos (14U) +#define GPIO_IDR_IDR14_Pos (14U) #define GPIO_IDR_IDR14_Msk (0x1U << GPIO_IDR_IDR14_Pos) /*!< 0x00004000 */ #define GPIO_IDR_IDR14 GPIO_IDR_IDR14_Msk /*!< Port input data, bit 14 */ -#define GPIO_IDR_IDR15_Pos (15U) +#define GPIO_IDR_IDR15_Pos (15U) #define GPIO_IDR_IDR15_Msk (0x1U << GPIO_IDR_IDR15_Pos) /*!< 0x00008000 */ #define GPIO_IDR_IDR15 GPIO_IDR_IDR15_Msk /*!< Port input data, bit 15 */ /******************* Bit definition for GPIO_ODR register *******************/ -#define GPIO_ODR_ODR0_Pos (0U) +#define GPIO_ODR_ODR0_Pos (0U) #define GPIO_ODR_ODR0_Msk (0x1U << GPIO_ODR_ODR0_Pos) /*!< 0x00000001 */ #define GPIO_ODR_ODR0 GPIO_ODR_ODR0_Msk /*!< Port output data, bit 0 */ -#define GPIO_ODR_ODR1_Pos (1U) +#define GPIO_ODR_ODR1_Pos (1U) #define GPIO_ODR_ODR1_Msk (0x1U << GPIO_ODR_ODR1_Pos) /*!< 0x00000002 */ #define GPIO_ODR_ODR1 GPIO_ODR_ODR1_Msk /*!< Port output data, bit 1 */ -#define GPIO_ODR_ODR2_Pos (2U) +#define GPIO_ODR_ODR2_Pos (2U) #define GPIO_ODR_ODR2_Msk (0x1U << GPIO_ODR_ODR2_Pos) /*!< 0x00000004 */ #define GPIO_ODR_ODR2 GPIO_ODR_ODR2_Msk /*!< Port output data, bit 2 */ -#define GPIO_ODR_ODR3_Pos (3U) +#define GPIO_ODR_ODR3_Pos (3U) #define GPIO_ODR_ODR3_Msk (0x1U << GPIO_ODR_ODR3_Pos) /*!< 0x00000008 */ #define GPIO_ODR_ODR3 GPIO_ODR_ODR3_Msk /*!< Port output data, bit 3 */ -#define GPIO_ODR_ODR4_Pos (4U) +#define GPIO_ODR_ODR4_Pos (4U) #define GPIO_ODR_ODR4_Msk (0x1U << GPIO_ODR_ODR4_Pos) /*!< 0x00000010 */ #define GPIO_ODR_ODR4 GPIO_ODR_ODR4_Msk /*!< Port output data, bit 4 */ -#define GPIO_ODR_ODR5_Pos (5U) +#define GPIO_ODR_ODR5_Pos (5U) #define GPIO_ODR_ODR5_Msk (0x1U << GPIO_ODR_ODR5_Pos) /*!< 0x00000020 */ #define GPIO_ODR_ODR5 GPIO_ODR_ODR5_Msk /*!< Port output data, bit 5 */ -#define GPIO_ODR_ODR6_Pos (6U) +#define GPIO_ODR_ODR6_Pos (6U) #define GPIO_ODR_ODR6_Msk (0x1U << GPIO_ODR_ODR6_Pos) /*!< 0x00000040 */ #define GPIO_ODR_ODR6 GPIO_ODR_ODR6_Msk /*!< Port output data, bit 6 */ -#define GPIO_ODR_ODR7_Pos (7U) +#define GPIO_ODR_ODR7_Pos (7U) #define GPIO_ODR_ODR7_Msk (0x1U << GPIO_ODR_ODR7_Pos) /*!< 0x00000080 */ #define GPIO_ODR_ODR7 GPIO_ODR_ODR7_Msk /*!< Port output data, bit 7 */ -#define GPIO_ODR_ODR8_Pos (8U) +#define GPIO_ODR_ODR8_Pos (8U) #define GPIO_ODR_ODR8_Msk (0x1U << GPIO_ODR_ODR8_Pos) /*!< 0x00000100 */ #define GPIO_ODR_ODR8 GPIO_ODR_ODR8_Msk /*!< Port output data, bit 8 */ -#define GPIO_ODR_ODR9_Pos (9U) +#define GPIO_ODR_ODR9_Pos (9U) #define GPIO_ODR_ODR9_Msk (0x1U << GPIO_ODR_ODR9_Pos) /*!< 0x00000200 */ #define GPIO_ODR_ODR9 GPIO_ODR_ODR9_Msk /*!< Port output data, bit 9 */ -#define GPIO_ODR_ODR10_Pos (10U) +#define GPIO_ODR_ODR10_Pos (10U) #define GPIO_ODR_ODR10_Msk (0x1U << GPIO_ODR_ODR10_Pos) /*!< 0x00000400 */ #define GPIO_ODR_ODR10 GPIO_ODR_ODR10_Msk /*!< Port output data, bit 10 */ -#define GPIO_ODR_ODR11_Pos (11U) +#define GPIO_ODR_ODR11_Pos (11U) #define GPIO_ODR_ODR11_Msk (0x1U << GPIO_ODR_ODR11_Pos) /*!< 0x00000800 */ #define GPIO_ODR_ODR11 GPIO_ODR_ODR11_Msk /*!< Port output data, bit 11 */ -#define GPIO_ODR_ODR12_Pos (12U) +#define GPIO_ODR_ODR12_Pos (12U) #define GPIO_ODR_ODR12_Msk (0x1U << GPIO_ODR_ODR12_Pos) /*!< 0x00001000 */ #define GPIO_ODR_ODR12 GPIO_ODR_ODR12_Msk /*!< Port output data, bit 12 */ -#define GPIO_ODR_ODR13_Pos (13U) +#define GPIO_ODR_ODR13_Pos (13U) #define GPIO_ODR_ODR13_Msk (0x1U << GPIO_ODR_ODR13_Pos) /*!< 0x00002000 */ #define GPIO_ODR_ODR13 GPIO_ODR_ODR13_Msk /*!< Port output data, bit 13 */ -#define GPIO_ODR_ODR14_Pos (14U) +#define GPIO_ODR_ODR14_Pos (14U) #define GPIO_ODR_ODR14_Msk (0x1U << GPIO_ODR_ODR14_Pos) /*!< 0x00004000 */ #define GPIO_ODR_ODR14 GPIO_ODR_ODR14_Msk /*!< Port output data, bit 14 */ -#define GPIO_ODR_ODR15_Pos (15U) +#define GPIO_ODR_ODR15_Pos (15U) #define GPIO_ODR_ODR15_Msk (0x1U << GPIO_ODR_ODR15_Pos) /*!< 0x00008000 */ #define GPIO_ODR_ODR15 GPIO_ODR_ODR15_Msk /*!< Port output data, bit 15 */ /****************** Bit definition for GPIO_BSRR register *******************/ -#define GPIO_BSRR_BS0_Pos (0U) +#define GPIO_BSRR_BS0_Pos (0U) #define GPIO_BSRR_BS0_Msk (0x1U << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */ #define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk /*!< Port x Set bit 0 */ -#define GPIO_BSRR_BS1_Pos (1U) +#define GPIO_BSRR_BS1_Pos (1U) #define GPIO_BSRR_BS1_Msk (0x1U << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */ #define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk /*!< Port x Set bit 1 */ -#define GPIO_BSRR_BS2_Pos (2U) +#define GPIO_BSRR_BS2_Pos (2U) #define GPIO_BSRR_BS2_Msk (0x1U << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */ #define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk /*!< Port x Set bit 2 */ -#define GPIO_BSRR_BS3_Pos (3U) +#define GPIO_BSRR_BS3_Pos (3U) #define GPIO_BSRR_BS3_Msk (0x1U << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */ #define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk /*!< Port x Set bit 3 */ -#define GPIO_BSRR_BS4_Pos (4U) +#define GPIO_BSRR_BS4_Pos (4U) #define GPIO_BSRR_BS4_Msk (0x1U << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */ #define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk /*!< Port x Set bit 4 */ -#define GPIO_BSRR_BS5_Pos (5U) +#define GPIO_BSRR_BS5_Pos (5U) #define GPIO_BSRR_BS5_Msk (0x1U << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */ #define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk /*!< Port x Set bit 5 */ -#define GPIO_BSRR_BS6_Pos (6U) +#define GPIO_BSRR_BS6_Pos (6U) #define GPIO_BSRR_BS6_Msk (0x1U << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */ #define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk /*!< Port x Set bit 6 */ -#define GPIO_BSRR_BS7_Pos (7U) +#define GPIO_BSRR_BS7_Pos (7U) #define GPIO_BSRR_BS7_Msk (0x1U << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */ #define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk /*!< Port x Set bit 7 */ -#define GPIO_BSRR_BS8_Pos (8U) +#define GPIO_BSRR_BS8_Pos (8U) #define GPIO_BSRR_BS8_Msk (0x1U << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */ #define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk /*!< Port x Set bit 8 */ -#define GPIO_BSRR_BS9_Pos (9U) +#define GPIO_BSRR_BS9_Pos (9U) #define GPIO_BSRR_BS9_Msk (0x1U << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */ #define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk /*!< Port x Set bit 9 */ -#define GPIO_BSRR_BS10_Pos (10U) +#define GPIO_BSRR_BS10_Pos (10U) #define GPIO_BSRR_BS10_Msk (0x1U << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */ #define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk /*!< Port x Set bit 10 */ -#define GPIO_BSRR_BS11_Pos (11U) +#define GPIO_BSRR_BS11_Pos (11U) #define GPIO_BSRR_BS11_Msk (0x1U << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */ #define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk /*!< Port x Set bit 11 */ -#define GPIO_BSRR_BS12_Pos (12U) +#define GPIO_BSRR_BS12_Pos (12U) #define GPIO_BSRR_BS12_Msk (0x1U << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */ #define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk /*!< Port x Set bit 12 */ -#define GPIO_BSRR_BS13_Pos (13U) +#define GPIO_BSRR_BS13_Pos (13U) #define GPIO_BSRR_BS13_Msk (0x1U << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */ #define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk /*!< Port x Set bit 13 */ -#define GPIO_BSRR_BS14_Pos (14U) +#define GPIO_BSRR_BS14_Pos (14U) #define GPIO_BSRR_BS14_Msk (0x1U << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */ #define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk /*!< Port x Set bit 14 */ -#define GPIO_BSRR_BS15_Pos (15U) +#define GPIO_BSRR_BS15_Pos (15U) #define GPIO_BSRR_BS15_Msk (0x1U << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */ #define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk /*!< Port x Set bit 15 */ -#define GPIO_BSRR_BR0_Pos (16U) +#define GPIO_BSRR_BR0_Pos (16U) #define GPIO_BSRR_BR0_Msk (0x1U << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */ #define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk /*!< Port x Reset bit 0 */ -#define GPIO_BSRR_BR1_Pos (17U) +#define GPIO_BSRR_BR1_Pos (17U) #define GPIO_BSRR_BR1_Msk (0x1U << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */ #define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk /*!< Port x Reset bit 1 */ -#define GPIO_BSRR_BR2_Pos (18U) +#define GPIO_BSRR_BR2_Pos (18U) #define GPIO_BSRR_BR2_Msk (0x1U << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */ #define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk /*!< Port x Reset bit 2 */ -#define GPIO_BSRR_BR3_Pos (19U) +#define GPIO_BSRR_BR3_Pos (19U) #define GPIO_BSRR_BR3_Msk (0x1U << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */ #define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk /*!< Port x Reset bit 3 */ -#define GPIO_BSRR_BR4_Pos (20U) +#define GPIO_BSRR_BR4_Pos (20U) #define GPIO_BSRR_BR4_Msk (0x1U << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */ #define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk /*!< Port x Reset bit 4 */ -#define GPIO_BSRR_BR5_Pos (21U) +#define GPIO_BSRR_BR5_Pos (21U) #define GPIO_BSRR_BR5_Msk (0x1U << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */ #define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk /*!< Port x Reset bit 5 */ -#define GPIO_BSRR_BR6_Pos (22U) +#define GPIO_BSRR_BR6_Pos (22U) #define GPIO_BSRR_BR6_Msk (0x1U << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */ #define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk /*!< Port x Reset bit 6 */ -#define GPIO_BSRR_BR7_Pos (23U) +#define GPIO_BSRR_BR7_Pos (23U) #define GPIO_BSRR_BR7_Msk (0x1U << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */ #define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk /*!< Port x Reset bit 7 */ -#define GPIO_BSRR_BR8_Pos (24U) +#define GPIO_BSRR_BR8_Pos (24U) #define GPIO_BSRR_BR8_Msk (0x1U << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */ #define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk /*!< Port x Reset bit 8 */ -#define GPIO_BSRR_BR9_Pos (25U) +#define GPIO_BSRR_BR9_Pos (25U) #define GPIO_BSRR_BR9_Msk (0x1U << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */ #define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk /*!< Port x Reset bit 9 */ -#define GPIO_BSRR_BR10_Pos (26U) +#define GPIO_BSRR_BR10_Pos (26U) #define GPIO_BSRR_BR10_Msk (0x1U << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */ #define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk /*!< Port x Reset bit 10 */ -#define GPIO_BSRR_BR11_Pos (27U) +#define GPIO_BSRR_BR11_Pos (27U) #define GPIO_BSRR_BR11_Msk (0x1U << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */ #define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk /*!< Port x Reset bit 11 */ -#define GPIO_BSRR_BR12_Pos (28U) +#define GPIO_BSRR_BR12_Pos (28U) #define GPIO_BSRR_BR12_Msk (0x1U << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */ #define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk /*!< Port x Reset bit 12 */ -#define GPIO_BSRR_BR13_Pos (29U) +#define GPIO_BSRR_BR13_Pos (29U) #define GPIO_BSRR_BR13_Msk (0x1U << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */ #define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk /*!< Port x Reset bit 13 */ -#define GPIO_BSRR_BR14_Pos (30U) +#define GPIO_BSRR_BR14_Pos (30U) #define GPIO_BSRR_BR14_Msk (0x1U << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */ #define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk /*!< Port x Reset bit 14 */ -#define GPIO_BSRR_BR15_Pos (31U) +#define GPIO_BSRR_BR15_Pos (31U) #define GPIO_BSRR_BR15_Msk (0x1U << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */ #define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk /*!< Port x Reset bit 15 */ /******************* Bit definition for GPIO_BRR register *******************/ -#define GPIO_BRR_BR0_Pos (0U) +#define GPIO_BRR_BR0_Pos (0U) #define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ #define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk /*!< Port x Reset bit 0 */ -#define GPIO_BRR_BR1_Pos (1U) +#define GPIO_BRR_BR1_Pos (1U) #define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ #define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk /*!< Port x Reset bit 1 */ -#define GPIO_BRR_BR2_Pos (2U) +#define GPIO_BRR_BR2_Pos (2U) #define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ #define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk /*!< Port x Reset bit 2 */ -#define GPIO_BRR_BR3_Pos (3U) +#define GPIO_BRR_BR3_Pos (3U) #define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ #define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk /*!< Port x Reset bit 3 */ -#define GPIO_BRR_BR4_Pos (4U) +#define GPIO_BRR_BR4_Pos (4U) #define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ #define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk /*!< Port x Reset bit 4 */ -#define GPIO_BRR_BR5_Pos (5U) +#define GPIO_BRR_BR5_Pos (5U) #define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ #define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk /*!< Port x Reset bit 5 */ -#define GPIO_BRR_BR6_Pos (6U) +#define GPIO_BRR_BR6_Pos (6U) #define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ #define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk /*!< Port x Reset bit 6 */ -#define GPIO_BRR_BR7_Pos (7U) +#define GPIO_BRR_BR7_Pos (7U) #define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ #define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk /*!< Port x Reset bit 7 */ -#define GPIO_BRR_BR8_Pos (8U) +#define GPIO_BRR_BR8_Pos (8U) #define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ #define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk /*!< Port x Reset bit 8 */ -#define GPIO_BRR_BR9_Pos (9U) +#define GPIO_BRR_BR9_Pos (9U) #define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ #define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk /*!< Port x Reset bit 9 */ -#define GPIO_BRR_BR10_Pos (10U) +#define GPIO_BRR_BR10_Pos (10U) #define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ #define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk /*!< Port x Reset bit 10 */ -#define GPIO_BRR_BR11_Pos (11U) +#define GPIO_BRR_BR11_Pos (11U) #define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ #define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk /*!< Port x Reset bit 11 */ -#define GPIO_BRR_BR12_Pos (12U) +#define GPIO_BRR_BR12_Pos (12U) #define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ #define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk /*!< Port x Reset bit 12 */ -#define GPIO_BRR_BR13_Pos (13U) +#define GPIO_BRR_BR13_Pos (13U) #define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ #define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk /*!< Port x Reset bit 13 */ -#define GPIO_BRR_BR14_Pos (14U) +#define GPIO_BRR_BR14_Pos (14U) #define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ #define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk /*!< Port x Reset bit 14 */ -#define GPIO_BRR_BR15_Pos (15U) +#define GPIO_BRR_BR15_Pos (15U) #define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ #define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk /*!< Port x Reset bit 15 */ /****************** Bit definition for GPIO_LCKR register *******************/ -#define GPIO_LCKR_LCK0_Pos (0U) +#define GPIO_LCKR_LCK0_Pos (0U) #define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */ #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk /*!< Port x Lock bit 0 */ -#define GPIO_LCKR_LCK1_Pos (1U) +#define GPIO_LCKR_LCK1_Pos (1U) #define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */ #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk /*!< Port x Lock bit 1 */ -#define GPIO_LCKR_LCK2_Pos (2U) +#define GPIO_LCKR_LCK2_Pos (2U) #define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */ #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk /*!< Port x Lock bit 2 */ -#define GPIO_LCKR_LCK3_Pos (3U) +#define GPIO_LCKR_LCK3_Pos (3U) #define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */ #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk /*!< Port x Lock bit 3 */ -#define GPIO_LCKR_LCK4_Pos (4U) +#define GPIO_LCKR_LCK4_Pos (4U) #define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */ #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk /*!< Port x Lock bit 4 */ -#define GPIO_LCKR_LCK5_Pos (5U) +#define GPIO_LCKR_LCK5_Pos (5U) #define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */ #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk /*!< Port x Lock bit 5 */ -#define GPIO_LCKR_LCK6_Pos (6U) +#define GPIO_LCKR_LCK6_Pos (6U) #define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */ #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk /*!< Port x Lock bit 6 */ -#define GPIO_LCKR_LCK7_Pos (7U) +#define GPIO_LCKR_LCK7_Pos (7U) #define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */ #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk /*!< Port x Lock bit 7 */ -#define GPIO_LCKR_LCK8_Pos (8U) +#define GPIO_LCKR_LCK8_Pos (8U) #define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */ #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk /*!< Port x Lock bit 8 */ -#define GPIO_LCKR_LCK9_Pos (9U) +#define GPIO_LCKR_LCK9_Pos (9U) #define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */ #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk /*!< Port x Lock bit 9 */ -#define GPIO_LCKR_LCK10_Pos (10U) +#define GPIO_LCKR_LCK10_Pos (10U) #define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */ #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk /*!< Port x Lock bit 10 */ -#define GPIO_LCKR_LCK11_Pos (11U) +#define GPIO_LCKR_LCK11_Pos (11U) #define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */ #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk /*!< Port x Lock bit 11 */ -#define GPIO_LCKR_LCK12_Pos (12U) +#define GPIO_LCKR_LCK12_Pos (12U) #define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */ #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk /*!< Port x Lock bit 12 */ -#define GPIO_LCKR_LCK13_Pos (13U) +#define GPIO_LCKR_LCK13_Pos (13U) #define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */ #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk /*!< Port x Lock bit 13 */ -#define GPIO_LCKR_LCK14_Pos (14U) +#define GPIO_LCKR_LCK14_Pos (14U) #define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */ #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk /*!< Port x Lock bit 14 */ -#define GPIO_LCKR_LCK15_Pos (15U) +#define GPIO_LCKR_LCK15_Pos (15U) #define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */ #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk /*!< Port x Lock bit 15 */ -#define GPIO_LCKR_LCKK_Pos (16U) +#define GPIO_LCKR_LCKK_Pos (16U) #define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */ #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk /*!< Lock key */ /*----------------------------------------------------------------------------*/ /****************** Bit definition for AFIO_EVCR register *******************/ -#define AFIO_EVCR_PIN_Pos (0U) +#define AFIO_EVCR_PIN_Pos (0U) #define AFIO_EVCR_PIN_Msk (0xFU << AFIO_EVCR_PIN_Pos) /*!< 0x0000000F */ #define AFIO_EVCR_PIN AFIO_EVCR_PIN_Msk /*!< PIN[3:0] bits (Pin selection) */ #define AFIO_EVCR_PIN_0 (0x1U << AFIO_EVCR_PIN_Pos) /*!< 0x00000001 */ @@ -1945,53 +1945,53 @@ typedef struct /*!< PIN configuration */ #define AFIO_EVCR_PIN_PX0 ((uint32_t)0x00000000) /*!< Pin 0 selected */ -#define AFIO_EVCR_PIN_PX1_Pos (0U) +#define AFIO_EVCR_PIN_PX1_Pos (0U) #define AFIO_EVCR_PIN_PX1_Msk (0x1U << AFIO_EVCR_PIN_PX1_Pos) /*!< 0x00000001 */ #define AFIO_EVCR_PIN_PX1 AFIO_EVCR_PIN_PX1_Msk /*!< Pin 1 selected */ -#define AFIO_EVCR_PIN_PX2_Pos (1U) +#define AFIO_EVCR_PIN_PX2_Pos (1U) #define AFIO_EVCR_PIN_PX2_Msk (0x1U << AFIO_EVCR_PIN_PX2_Pos) /*!< 0x00000002 */ #define AFIO_EVCR_PIN_PX2 AFIO_EVCR_PIN_PX2_Msk /*!< Pin 2 selected */ -#define AFIO_EVCR_PIN_PX3_Pos (0U) +#define AFIO_EVCR_PIN_PX3_Pos (0U) #define AFIO_EVCR_PIN_PX3_Msk (0x3U << AFIO_EVCR_PIN_PX3_Pos) /*!< 0x00000003 */ #define AFIO_EVCR_PIN_PX3 AFIO_EVCR_PIN_PX3_Msk /*!< Pin 3 selected */ -#define AFIO_EVCR_PIN_PX4_Pos (2U) +#define AFIO_EVCR_PIN_PX4_Pos (2U) #define AFIO_EVCR_PIN_PX4_Msk (0x1U << AFIO_EVCR_PIN_PX4_Pos) /*!< 0x00000004 */ #define AFIO_EVCR_PIN_PX4 AFIO_EVCR_PIN_PX4_Msk /*!< Pin 4 selected */ -#define AFIO_EVCR_PIN_PX5_Pos (0U) +#define AFIO_EVCR_PIN_PX5_Pos (0U) #define AFIO_EVCR_PIN_PX5_Msk (0x5U << AFIO_EVCR_PIN_PX5_Pos) /*!< 0x00000005 */ #define AFIO_EVCR_PIN_PX5 AFIO_EVCR_PIN_PX5_Msk /*!< Pin 5 selected */ -#define AFIO_EVCR_PIN_PX6_Pos (1U) +#define AFIO_EVCR_PIN_PX6_Pos (1U) #define AFIO_EVCR_PIN_PX6_Msk (0x3U << AFIO_EVCR_PIN_PX6_Pos) /*!< 0x00000006 */ #define AFIO_EVCR_PIN_PX6 AFIO_EVCR_PIN_PX6_Msk /*!< Pin 6 selected */ -#define AFIO_EVCR_PIN_PX7_Pos (0U) +#define AFIO_EVCR_PIN_PX7_Pos (0U) #define AFIO_EVCR_PIN_PX7_Msk (0x7U << AFIO_EVCR_PIN_PX7_Pos) /*!< 0x00000007 */ #define AFIO_EVCR_PIN_PX7 AFIO_EVCR_PIN_PX7_Msk /*!< Pin 7 selected */ -#define AFIO_EVCR_PIN_PX8_Pos (3U) +#define AFIO_EVCR_PIN_PX8_Pos (3U) #define AFIO_EVCR_PIN_PX8_Msk (0x1U << AFIO_EVCR_PIN_PX8_Pos) /*!< 0x00000008 */ #define AFIO_EVCR_PIN_PX8 AFIO_EVCR_PIN_PX8_Msk /*!< Pin 8 selected */ -#define AFIO_EVCR_PIN_PX9_Pos (0U) +#define AFIO_EVCR_PIN_PX9_Pos (0U) #define AFIO_EVCR_PIN_PX9_Msk (0x9U << AFIO_EVCR_PIN_PX9_Pos) /*!< 0x00000009 */ #define AFIO_EVCR_PIN_PX9 AFIO_EVCR_PIN_PX9_Msk /*!< Pin 9 selected */ -#define AFIO_EVCR_PIN_PX10_Pos (1U) +#define AFIO_EVCR_PIN_PX10_Pos (1U) #define AFIO_EVCR_PIN_PX10_Msk (0x5U << AFIO_EVCR_PIN_PX10_Pos) /*!< 0x0000000A */ #define AFIO_EVCR_PIN_PX10 AFIO_EVCR_PIN_PX10_Msk /*!< Pin 10 selected */ -#define AFIO_EVCR_PIN_PX11_Pos (0U) +#define AFIO_EVCR_PIN_PX11_Pos (0U) #define AFIO_EVCR_PIN_PX11_Msk (0xBU << AFIO_EVCR_PIN_PX11_Pos) /*!< 0x0000000B */ #define AFIO_EVCR_PIN_PX11 AFIO_EVCR_PIN_PX11_Msk /*!< Pin 11 selected */ -#define AFIO_EVCR_PIN_PX12_Pos (2U) +#define AFIO_EVCR_PIN_PX12_Pos (2U) #define AFIO_EVCR_PIN_PX12_Msk (0x3U << AFIO_EVCR_PIN_PX12_Pos) /*!< 0x0000000C */ #define AFIO_EVCR_PIN_PX12 AFIO_EVCR_PIN_PX12_Msk /*!< Pin 12 selected */ -#define AFIO_EVCR_PIN_PX13_Pos (0U) +#define AFIO_EVCR_PIN_PX13_Pos (0U) #define AFIO_EVCR_PIN_PX13_Msk (0xDU << AFIO_EVCR_PIN_PX13_Pos) /*!< 0x0000000D */ #define AFIO_EVCR_PIN_PX13 AFIO_EVCR_PIN_PX13_Msk /*!< Pin 13 selected */ -#define AFIO_EVCR_PIN_PX14_Pos (1U) +#define AFIO_EVCR_PIN_PX14_Pos (1U) #define AFIO_EVCR_PIN_PX14_Msk (0x7U << AFIO_EVCR_PIN_PX14_Pos) /*!< 0x0000000E */ #define AFIO_EVCR_PIN_PX14 AFIO_EVCR_PIN_PX14_Msk /*!< Pin 14 selected */ -#define AFIO_EVCR_PIN_PX15_Pos (0U) +#define AFIO_EVCR_PIN_PX15_Pos (0U) #define AFIO_EVCR_PIN_PX15_Msk (0xFU << AFIO_EVCR_PIN_PX15_Pos) /*!< 0x0000000F */ #define AFIO_EVCR_PIN_PX15 AFIO_EVCR_PIN_PX15_Msk /*!< Pin 15 selected */ -#define AFIO_EVCR_PORT_Pos (4U) +#define AFIO_EVCR_PORT_Pos (4U) #define AFIO_EVCR_PORT_Msk (0x7U << AFIO_EVCR_PORT_Pos) /*!< 0x00000070 */ #define AFIO_EVCR_PORT AFIO_EVCR_PORT_Msk /*!< PORT[2:0] bits (Port selection) */ #define AFIO_EVCR_PORT_0 (0x1U << AFIO_EVCR_PORT_Pos) /*!< 0x00000010 */ @@ -2000,39 +2000,39 @@ typedef struct /*!< PORT configuration */ #define AFIO_EVCR_PORT_PA ((uint32_t)0x00000000) /*!< Port A selected */ -#define AFIO_EVCR_PORT_PB_Pos (4U) +#define AFIO_EVCR_PORT_PB_Pos (4U) #define AFIO_EVCR_PORT_PB_Msk (0x1U << AFIO_EVCR_PORT_PB_Pos) /*!< 0x00000010 */ #define AFIO_EVCR_PORT_PB AFIO_EVCR_PORT_PB_Msk /*!< Port B selected */ -#define AFIO_EVCR_PORT_PC_Pos (5U) +#define AFIO_EVCR_PORT_PC_Pos (5U) #define AFIO_EVCR_PORT_PC_Msk (0x1U << AFIO_EVCR_PORT_PC_Pos) /*!< 0x00000020 */ #define AFIO_EVCR_PORT_PC AFIO_EVCR_PORT_PC_Msk /*!< Port C selected */ -#define AFIO_EVCR_PORT_PD_Pos (4U) +#define AFIO_EVCR_PORT_PD_Pos (4U) #define AFIO_EVCR_PORT_PD_Msk (0x3U << AFIO_EVCR_PORT_PD_Pos) /*!< 0x00000030 */ #define AFIO_EVCR_PORT_PD AFIO_EVCR_PORT_PD_Msk /*!< Port D selected */ -#define AFIO_EVCR_PORT_PE_Pos (6U) +#define AFIO_EVCR_PORT_PE_Pos (6U) #define AFIO_EVCR_PORT_PE_Msk (0x1U << AFIO_EVCR_PORT_PE_Pos) /*!< 0x00000040 */ #define AFIO_EVCR_PORT_PE AFIO_EVCR_PORT_PE_Msk /*!< Port E selected */ -#define AFIO_EVCR_EVOE_Pos (7U) +#define AFIO_EVCR_EVOE_Pos (7U) #define AFIO_EVCR_EVOE_Msk (0x1U << AFIO_EVCR_EVOE_Pos) /*!< 0x00000080 */ #define AFIO_EVCR_EVOE AFIO_EVCR_EVOE_Msk /*!< Event Output Enable */ /****************** Bit definition for AFIO_MAPR register *******************/ -#define AFIO_MAPR_SPI1_REMAP_Pos (0U) +#define AFIO_MAPR_SPI1_REMAP_Pos (0U) #define AFIO_MAPR_SPI1_REMAP_Msk (0x1U << AFIO_MAPR_SPI1_REMAP_Pos) /*!< 0x00000001 */ #define AFIO_MAPR_SPI1_REMAP AFIO_MAPR_SPI1_REMAP_Msk /*!< SPI1 remapping */ -#define AFIO_MAPR_I2C1_REMAP_Pos (1U) +#define AFIO_MAPR_I2C1_REMAP_Pos (1U) #define AFIO_MAPR_I2C1_REMAP_Msk (0x1U << AFIO_MAPR_I2C1_REMAP_Pos) /*!< 0x00000002 */ #define AFIO_MAPR_I2C1_REMAP AFIO_MAPR_I2C1_REMAP_Msk /*!< I2C1 remapping */ -#define AFIO_MAPR_USART1_REMAP_Pos (2U) +#define AFIO_MAPR_USART1_REMAP_Pos (2U) #define AFIO_MAPR_USART1_REMAP_Msk (0x1U << AFIO_MAPR_USART1_REMAP_Pos) /*!< 0x00000004 */ #define AFIO_MAPR_USART1_REMAP AFIO_MAPR_USART1_REMAP_Msk /*!< USART1 remapping */ -#define AFIO_MAPR_USART2_REMAP_Pos (3U) +#define AFIO_MAPR_USART2_REMAP_Pos (3U) #define AFIO_MAPR_USART2_REMAP_Msk (0x1U << AFIO_MAPR_USART2_REMAP_Pos) /*!< 0x00000008 */ #define AFIO_MAPR_USART2_REMAP AFIO_MAPR_USART2_REMAP_Msk /*!< USART2 remapping */ -#define AFIO_MAPR_TIM1_REMAP_Pos (6U) +#define AFIO_MAPR_TIM1_REMAP_Pos (6U) #define AFIO_MAPR_TIM1_REMAP_Msk (0x3U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x000000C0 */ #define AFIO_MAPR_TIM1_REMAP AFIO_MAPR_TIM1_REMAP_Msk /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */ #define AFIO_MAPR_TIM1_REMAP_0 (0x1U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000040 */ @@ -2040,14 +2040,14 @@ typedef struct /*!< TIM1_REMAP configuration */ #define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */ -#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos (6U) +#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos (6U) #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos) /*!< 0x00000040 */ #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */ -#define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos (6U) +#define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos (6U) #define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos) /*!< 0x000000C0 */ #define AFIO_MAPR_TIM1_REMAP_FULLREMAP AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */ -#define AFIO_MAPR_TIM2_REMAP_Pos (8U) +#define AFIO_MAPR_TIM2_REMAP_Pos (8U) #define AFIO_MAPR_TIM2_REMAP_Msk (0x3U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000300 */ #define AFIO_MAPR_TIM2_REMAP AFIO_MAPR_TIM2_REMAP_Msk /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */ #define AFIO_MAPR_TIM2_REMAP_0 (0x1U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000100 */ @@ -2055,17 +2055,17 @@ typedef struct /*!< TIM2_REMAP configuration */ #define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */ -#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos (8U) +#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos (8U) #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk (0x1U << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos) /*!< 0x00000100 */ #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */ -#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos (9U) +#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos (9U) #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk (0x1U << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos) /*!< 0x00000200 */ #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */ -#define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos (8U) +#define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos (8U) #define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos) /*!< 0x00000300 */ #define AFIO_MAPR_TIM2_REMAP_FULLREMAP AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */ -#define AFIO_MAPR_TIM3_REMAP_Pos (10U) +#define AFIO_MAPR_TIM3_REMAP_Pos (10U) #define AFIO_MAPR_TIM3_REMAP_Msk (0x3U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000C00 */ #define AFIO_MAPR_TIM3_REMAP AFIO_MAPR_TIM3_REMAP_Msk /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */ #define AFIO_MAPR_TIM3_REMAP_0 (0x1U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000400 */ @@ -2073,15 +2073,15 @@ typedef struct /*!< TIM3_REMAP configuration */ #define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */ -#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos (11U) +#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos (11U) #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000800 */ #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */ -#define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos (10U) +#define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos (10U) #define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos) /*!< 0x00000C00 */ #define AFIO_MAPR_TIM3_REMAP_FULLREMAP AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */ -#define AFIO_MAPR_CAN_REMAP_Pos (13U) +#define AFIO_MAPR_CAN_REMAP_Pos (13U) #define AFIO_MAPR_CAN_REMAP_Msk (0x3U << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00006000 */ #define AFIO_MAPR_CAN_REMAP AFIO_MAPR_CAN_REMAP_Msk /*!< CAN_REMAP[1:0] bits (CAN Alternate function remapping) */ #define AFIO_MAPR_CAN_REMAP_0 (0x1U << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00002000 */ @@ -2089,19 +2089,19 @@ typedef struct /*!< CAN_REMAP configuration */ #define AFIO_MAPR_CAN_REMAP_REMAP1 ((uint32_t)0x00000000) /*!< CANRX mapped to PA11, CANTX mapped to PA12 */ -#define AFIO_MAPR_CAN_REMAP_REMAP2_Pos (14U) +#define AFIO_MAPR_CAN_REMAP_REMAP2_Pos (14U) #define AFIO_MAPR_CAN_REMAP_REMAP2_Msk (0x1U << AFIO_MAPR_CAN_REMAP_REMAP2_Pos) /*!< 0x00004000 */ #define AFIO_MAPR_CAN_REMAP_REMAP2 AFIO_MAPR_CAN_REMAP_REMAP2_Msk /*!< CANRX mapped to PB8, CANTX mapped to PB9 */ -#define AFIO_MAPR_CAN_REMAP_REMAP3_Pos (13U) +#define AFIO_MAPR_CAN_REMAP_REMAP3_Pos (13U) #define AFIO_MAPR_CAN_REMAP_REMAP3_Msk (0x3U << AFIO_MAPR_CAN_REMAP_REMAP3_Pos) /*!< 0x00006000 */ #define AFIO_MAPR_CAN_REMAP_REMAP3 AFIO_MAPR_CAN_REMAP_REMAP3_Msk /*!< CANRX mapped to PD0, CANTX mapped to PD1 */ -#define AFIO_MAPR_PD01_REMAP_Pos (15U) +#define AFIO_MAPR_PD01_REMAP_Pos (15U) #define AFIO_MAPR_PD01_REMAP_Msk (0x1U << AFIO_MAPR_PD01_REMAP_Pos) /*!< 0x00008000 */ #define AFIO_MAPR_PD01_REMAP AFIO_MAPR_PD01_REMAP_Msk /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ /*!< SWJ_CFG configuration */ -#define AFIO_MAPR_SWJ_CFG_Pos (24U) +#define AFIO_MAPR_SWJ_CFG_Pos (24U) #define AFIO_MAPR_SWJ_CFG_Msk (0x7U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x07000000 */ #define AFIO_MAPR_SWJ_CFG AFIO_MAPR_SWJ_CFG_Msk /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */ #define AFIO_MAPR_SWJ_CFG_0 (0x1U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x01000000 */ @@ -2109,406 +2109,406 @@ typedef struct #define AFIO_MAPR_SWJ_CFG_2 (0x4U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x04000000 */ #define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */ -#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos (24U) +#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos (24U) #define AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk (0x1U << AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos) /*!< 0x01000000 */ #define AFIO_MAPR_SWJ_CFG_NOJNTRST AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */ -#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos (25U) +#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos (25U) #define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk (0x1U << AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos) /*!< 0x02000000 */ #define AFIO_MAPR_SWJ_CFG_JTAGDISABLE AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk /*!< JTAG-DP Disabled and SW-DP Enabled */ -#define AFIO_MAPR_SWJ_CFG_DISABLE_Pos (26U) +#define AFIO_MAPR_SWJ_CFG_DISABLE_Pos (26U) #define AFIO_MAPR_SWJ_CFG_DISABLE_Msk (0x1U << AFIO_MAPR_SWJ_CFG_DISABLE_Pos) /*!< 0x04000000 */ #define AFIO_MAPR_SWJ_CFG_DISABLE AFIO_MAPR_SWJ_CFG_DISABLE_Msk /*!< JTAG-DP Disabled and SW-DP Disabled */ /***************** Bit definition for AFIO_EXTICR1 register *****************/ -#define AFIO_EXTICR1_EXTI0_Pos (0U) +#define AFIO_EXTICR1_EXTI0_Pos (0U) #define AFIO_EXTICR1_EXTI0_Msk (0xFU << AFIO_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */ #define AFIO_EXTICR1_EXTI0 AFIO_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */ -#define AFIO_EXTICR1_EXTI1_Pos (4U) +#define AFIO_EXTICR1_EXTI1_Pos (4U) #define AFIO_EXTICR1_EXTI1_Msk (0xFU << AFIO_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */ #define AFIO_EXTICR1_EXTI1 AFIO_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */ -#define AFIO_EXTICR1_EXTI2_Pos (8U) +#define AFIO_EXTICR1_EXTI2_Pos (8U) #define AFIO_EXTICR1_EXTI2_Msk (0xFU << AFIO_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */ #define AFIO_EXTICR1_EXTI2 AFIO_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */ -#define AFIO_EXTICR1_EXTI3_Pos (12U) +#define AFIO_EXTICR1_EXTI3_Pos (12U) #define AFIO_EXTICR1_EXTI3_Msk (0xFU << AFIO_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */ #define AFIO_EXTICR1_EXTI3 AFIO_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */ /*!< EXTI0 configuration */ #define AFIO_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!< PA[0] pin */ -#define AFIO_EXTICR1_EXTI0_PB_Pos (0U) +#define AFIO_EXTICR1_EXTI0_PB_Pos (0U) #define AFIO_EXTICR1_EXTI0_PB_Msk (0x1U << AFIO_EXTICR1_EXTI0_PB_Pos) /*!< 0x00000001 */ #define AFIO_EXTICR1_EXTI0_PB AFIO_EXTICR1_EXTI0_PB_Msk /*!< PB[0] pin */ -#define AFIO_EXTICR1_EXTI0_PC_Pos (1U) +#define AFIO_EXTICR1_EXTI0_PC_Pos (1U) #define AFIO_EXTICR1_EXTI0_PC_Msk (0x1U << AFIO_EXTICR1_EXTI0_PC_Pos) /*!< 0x00000002 */ #define AFIO_EXTICR1_EXTI0_PC AFIO_EXTICR1_EXTI0_PC_Msk /*!< PC[0] pin */ -#define AFIO_EXTICR1_EXTI0_PD_Pos (0U) +#define AFIO_EXTICR1_EXTI0_PD_Pos (0U) #define AFIO_EXTICR1_EXTI0_PD_Msk (0x3U << AFIO_EXTICR1_EXTI0_PD_Pos) /*!< 0x00000003 */ #define AFIO_EXTICR1_EXTI0_PD AFIO_EXTICR1_EXTI0_PD_Msk /*!< PD[0] pin */ -#define AFIO_EXTICR1_EXTI0_PE_Pos (2U) +#define AFIO_EXTICR1_EXTI0_PE_Pos (2U) #define AFIO_EXTICR1_EXTI0_PE_Msk (0x1U << AFIO_EXTICR1_EXTI0_PE_Pos) /*!< 0x00000004 */ #define AFIO_EXTICR1_EXTI0_PE AFIO_EXTICR1_EXTI0_PE_Msk /*!< PE[0] pin */ -#define AFIO_EXTICR1_EXTI0_PF_Pos (0U) +#define AFIO_EXTICR1_EXTI0_PF_Pos (0U) #define AFIO_EXTICR1_EXTI0_PF_Msk (0x5U << AFIO_EXTICR1_EXTI0_PF_Pos) /*!< 0x00000005 */ #define AFIO_EXTICR1_EXTI0_PF AFIO_EXTICR1_EXTI0_PF_Msk /*!< PF[0] pin */ -#define AFIO_EXTICR1_EXTI0_PG_Pos (1U) +#define AFIO_EXTICR1_EXTI0_PG_Pos (1U) #define AFIO_EXTICR1_EXTI0_PG_Msk (0x3U << AFIO_EXTICR1_EXTI0_PG_Pos) /*!< 0x00000006 */ #define AFIO_EXTICR1_EXTI0_PG AFIO_EXTICR1_EXTI0_PG_Msk /*!< PG[0] pin */ /*!< EXTI1 configuration */ #define AFIO_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!< PA[1] pin */ -#define AFIO_EXTICR1_EXTI1_PB_Pos (4U) +#define AFIO_EXTICR1_EXTI1_PB_Pos (4U) #define AFIO_EXTICR1_EXTI1_PB_Msk (0x1U << AFIO_EXTICR1_EXTI1_PB_Pos) /*!< 0x00000010 */ #define AFIO_EXTICR1_EXTI1_PB AFIO_EXTICR1_EXTI1_PB_Msk /*!< PB[1] pin */ -#define AFIO_EXTICR1_EXTI1_PC_Pos (5U) +#define AFIO_EXTICR1_EXTI1_PC_Pos (5U) #define AFIO_EXTICR1_EXTI1_PC_Msk (0x1U << AFIO_EXTICR1_EXTI1_PC_Pos) /*!< 0x00000020 */ #define AFIO_EXTICR1_EXTI1_PC AFIO_EXTICR1_EXTI1_PC_Msk /*!< PC[1] pin */ -#define AFIO_EXTICR1_EXTI1_PD_Pos (4U) +#define AFIO_EXTICR1_EXTI1_PD_Pos (4U) #define AFIO_EXTICR1_EXTI1_PD_Msk (0x3U << AFIO_EXTICR1_EXTI1_PD_Pos) /*!< 0x00000030 */ #define AFIO_EXTICR1_EXTI1_PD AFIO_EXTICR1_EXTI1_PD_Msk /*!< PD[1] pin */ -#define AFIO_EXTICR1_EXTI1_PE_Pos (6U) +#define AFIO_EXTICR1_EXTI1_PE_Pos (6U) #define AFIO_EXTICR1_EXTI1_PE_Msk (0x1U << AFIO_EXTICR1_EXTI1_PE_Pos) /*!< 0x00000040 */ #define AFIO_EXTICR1_EXTI1_PE AFIO_EXTICR1_EXTI1_PE_Msk /*!< PE[1] pin */ -#define AFIO_EXTICR1_EXTI1_PF_Pos (4U) +#define AFIO_EXTICR1_EXTI1_PF_Pos (4U) #define AFIO_EXTICR1_EXTI1_PF_Msk (0x5U << AFIO_EXTICR1_EXTI1_PF_Pos) /*!< 0x00000050 */ #define AFIO_EXTICR1_EXTI1_PF AFIO_EXTICR1_EXTI1_PF_Msk /*!< PF[1] pin */ -#define AFIO_EXTICR1_EXTI1_PG_Pos (5U) +#define AFIO_EXTICR1_EXTI1_PG_Pos (5U) #define AFIO_EXTICR1_EXTI1_PG_Msk (0x3U << AFIO_EXTICR1_EXTI1_PG_Pos) /*!< 0x00000060 */ #define AFIO_EXTICR1_EXTI1_PG AFIO_EXTICR1_EXTI1_PG_Msk /*!< PG[1] pin */ -/*!< EXTI2 configuration */ +/*!< EXTI2 configuration */ #define AFIO_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!< PA[2] pin */ -#define AFIO_EXTICR1_EXTI2_PB_Pos (8U) +#define AFIO_EXTICR1_EXTI2_PB_Pos (8U) #define AFIO_EXTICR1_EXTI2_PB_Msk (0x1U << AFIO_EXTICR1_EXTI2_PB_Pos) /*!< 0x00000100 */ #define AFIO_EXTICR1_EXTI2_PB AFIO_EXTICR1_EXTI2_PB_Msk /*!< PB[2] pin */ -#define AFIO_EXTICR1_EXTI2_PC_Pos (9U) +#define AFIO_EXTICR1_EXTI2_PC_Pos (9U) #define AFIO_EXTICR1_EXTI2_PC_Msk (0x1U << AFIO_EXTICR1_EXTI2_PC_Pos) /*!< 0x00000200 */ #define AFIO_EXTICR1_EXTI2_PC AFIO_EXTICR1_EXTI2_PC_Msk /*!< PC[2] pin */ -#define AFIO_EXTICR1_EXTI2_PD_Pos (8U) +#define AFIO_EXTICR1_EXTI2_PD_Pos (8U) #define AFIO_EXTICR1_EXTI2_PD_Msk (0x3U << AFIO_EXTICR1_EXTI2_PD_Pos) /*!< 0x00000300 */ #define AFIO_EXTICR1_EXTI2_PD AFIO_EXTICR1_EXTI2_PD_Msk /*!< PD[2] pin */ -#define AFIO_EXTICR1_EXTI2_PE_Pos (10U) +#define AFIO_EXTICR1_EXTI2_PE_Pos (10U) #define AFIO_EXTICR1_EXTI2_PE_Msk (0x1U << AFIO_EXTICR1_EXTI2_PE_Pos) /*!< 0x00000400 */ #define AFIO_EXTICR1_EXTI2_PE AFIO_EXTICR1_EXTI2_PE_Msk /*!< PE[2] pin */ -#define AFIO_EXTICR1_EXTI2_PF_Pos (8U) +#define AFIO_EXTICR1_EXTI2_PF_Pos (8U) #define AFIO_EXTICR1_EXTI2_PF_Msk (0x5U << AFIO_EXTICR1_EXTI2_PF_Pos) /*!< 0x00000500 */ #define AFIO_EXTICR1_EXTI2_PF AFIO_EXTICR1_EXTI2_PF_Msk /*!< PF[2] pin */ -#define AFIO_EXTICR1_EXTI2_PG_Pos (9U) +#define AFIO_EXTICR1_EXTI2_PG_Pos (9U) #define AFIO_EXTICR1_EXTI2_PG_Msk (0x3U << AFIO_EXTICR1_EXTI2_PG_Pos) /*!< 0x00000600 */ #define AFIO_EXTICR1_EXTI2_PG AFIO_EXTICR1_EXTI2_PG_Msk /*!< PG[2] pin */ /*!< EXTI3 configuration */ #define AFIO_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!< PA[3] pin */ -#define AFIO_EXTICR1_EXTI3_PB_Pos (12U) +#define AFIO_EXTICR1_EXTI3_PB_Pos (12U) #define AFIO_EXTICR1_EXTI3_PB_Msk (0x1U << AFIO_EXTICR1_EXTI3_PB_Pos) /*!< 0x00001000 */ #define AFIO_EXTICR1_EXTI3_PB AFIO_EXTICR1_EXTI3_PB_Msk /*!< PB[3] pin */ -#define AFIO_EXTICR1_EXTI3_PC_Pos (13U) +#define AFIO_EXTICR1_EXTI3_PC_Pos (13U) #define AFIO_EXTICR1_EXTI3_PC_Msk (0x1U << AFIO_EXTICR1_EXTI3_PC_Pos) /*!< 0x00002000 */ #define AFIO_EXTICR1_EXTI3_PC AFIO_EXTICR1_EXTI3_PC_Msk /*!< PC[3] pin */ -#define AFIO_EXTICR1_EXTI3_PD_Pos (12U) +#define AFIO_EXTICR1_EXTI3_PD_Pos (12U) #define AFIO_EXTICR1_EXTI3_PD_Msk (0x3U << AFIO_EXTICR1_EXTI3_PD_Pos) /*!< 0x00003000 */ #define AFIO_EXTICR1_EXTI3_PD AFIO_EXTICR1_EXTI3_PD_Msk /*!< PD[3] pin */ -#define AFIO_EXTICR1_EXTI3_PE_Pos (14U) +#define AFIO_EXTICR1_EXTI3_PE_Pos (14U) #define AFIO_EXTICR1_EXTI3_PE_Msk (0x1U << AFIO_EXTICR1_EXTI3_PE_Pos) /*!< 0x00004000 */ #define AFIO_EXTICR1_EXTI3_PE AFIO_EXTICR1_EXTI3_PE_Msk /*!< PE[3] pin */ -#define AFIO_EXTICR1_EXTI3_PF_Pos (12U) +#define AFIO_EXTICR1_EXTI3_PF_Pos (12U) #define AFIO_EXTICR1_EXTI3_PF_Msk (0x5U << AFIO_EXTICR1_EXTI3_PF_Pos) /*!< 0x00005000 */ #define AFIO_EXTICR1_EXTI3_PF AFIO_EXTICR1_EXTI3_PF_Msk /*!< PF[3] pin */ -#define AFIO_EXTICR1_EXTI3_PG_Pos (13U) +#define AFIO_EXTICR1_EXTI3_PG_Pos (13U) #define AFIO_EXTICR1_EXTI3_PG_Msk (0x3U << AFIO_EXTICR1_EXTI3_PG_Pos) /*!< 0x00006000 */ #define AFIO_EXTICR1_EXTI3_PG AFIO_EXTICR1_EXTI3_PG_Msk /*!< PG[3] pin */ /***************** Bit definition for AFIO_EXTICR2 register *****************/ -#define AFIO_EXTICR2_EXTI4_Pos (0U) +#define AFIO_EXTICR2_EXTI4_Pos (0U) #define AFIO_EXTICR2_EXTI4_Msk (0xFU << AFIO_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */ #define AFIO_EXTICR2_EXTI4 AFIO_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */ -#define AFIO_EXTICR2_EXTI5_Pos (4U) +#define AFIO_EXTICR2_EXTI5_Pos (4U) #define AFIO_EXTICR2_EXTI5_Msk (0xFU << AFIO_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */ #define AFIO_EXTICR2_EXTI5 AFIO_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */ -#define AFIO_EXTICR2_EXTI6_Pos (8U) +#define AFIO_EXTICR2_EXTI6_Pos (8U) #define AFIO_EXTICR2_EXTI6_Msk (0xFU << AFIO_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */ #define AFIO_EXTICR2_EXTI6 AFIO_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */ -#define AFIO_EXTICR2_EXTI7_Pos (12U) +#define AFIO_EXTICR2_EXTI7_Pos (12U) #define AFIO_EXTICR2_EXTI7_Msk (0xFU << AFIO_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */ #define AFIO_EXTICR2_EXTI7 AFIO_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */ /*!< EXTI4 configuration */ #define AFIO_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!< PA[4] pin */ -#define AFIO_EXTICR2_EXTI4_PB_Pos (0U) +#define AFIO_EXTICR2_EXTI4_PB_Pos (0U) #define AFIO_EXTICR2_EXTI4_PB_Msk (0x1U << AFIO_EXTICR2_EXTI4_PB_Pos) /*!< 0x00000001 */ #define AFIO_EXTICR2_EXTI4_PB AFIO_EXTICR2_EXTI4_PB_Msk /*!< PB[4] pin */ -#define AFIO_EXTICR2_EXTI4_PC_Pos (1U) +#define AFIO_EXTICR2_EXTI4_PC_Pos (1U) #define AFIO_EXTICR2_EXTI4_PC_Msk (0x1U << AFIO_EXTICR2_EXTI4_PC_Pos) /*!< 0x00000002 */ #define AFIO_EXTICR2_EXTI4_PC AFIO_EXTICR2_EXTI4_PC_Msk /*!< PC[4] pin */ -#define AFIO_EXTICR2_EXTI4_PD_Pos (0U) +#define AFIO_EXTICR2_EXTI4_PD_Pos (0U) #define AFIO_EXTICR2_EXTI4_PD_Msk (0x3U << AFIO_EXTICR2_EXTI4_PD_Pos) /*!< 0x00000003 */ #define AFIO_EXTICR2_EXTI4_PD AFIO_EXTICR2_EXTI4_PD_Msk /*!< PD[4] pin */ -#define AFIO_EXTICR2_EXTI4_PE_Pos (2U) +#define AFIO_EXTICR2_EXTI4_PE_Pos (2U) #define AFIO_EXTICR2_EXTI4_PE_Msk (0x1U << AFIO_EXTICR2_EXTI4_PE_Pos) /*!< 0x00000004 */ #define AFIO_EXTICR2_EXTI4_PE AFIO_EXTICR2_EXTI4_PE_Msk /*!< PE[4] pin */ -#define AFIO_EXTICR2_EXTI4_PF_Pos (0U) +#define AFIO_EXTICR2_EXTI4_PF_Pos (0U) #define AFIO_EXTICR2_EXTI4_PF_Msk (0x5U << AFIO_EXTICR2_EXTI4_PF_Pos) /*!< 0x00000005 */ #define AFIO_EXTICR2_EXTI4_PF AFIO_EXTICR2_EXTI4_PF_Msk /*!< PF[4] pin */ -#define AFIO_EXTICR2_EXTI4_PG_Pos (1U) +#define AFIO_EXTICR2_EXTI4_PG_Pos (1U) #define AFIO_EXTICR2_EXTI4_PG_Msk (0x3U << AFIO_EXTICR2_EXTI4_PG_Pos) /*!< 0x00000006 */ #define AFIO_EXTICR2_EXTI4_PG AFIO_EXTICR2_EXTI4_PG_Msk /*!< PG[4] pin */ /* EXTI5 configuration */ #define AFIO_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!< PA[5] pin */ -#define AFIO_EXTICR2_EXTI5_PB_Pos (4U) +#define AFIO_EXTICR2_EXTI5_PB_Pos (4U) #define AFIO_EXTICR2_EXTI5_PB_Msk (0x1U << AFIO_EXTICR2_EXTI5_PB_Pos) /*!< 0x00000010 */ #define AFIO_EXTICR2_EXTI5_PB AFIO_EXTICR2_EXTI5_PB_Msk /*!< PB[5] pin */ -#define AFIO_EXTICR2_EXTI5_PC_Pos (5U) +#define AFIO_EXTICR2_EXTI5_PC_Pos (5U) #define AFIO_EXTICR2_EXTI5_PC_Msk (0x1U << AFIO_EXTICR2_EXTI5_PC_Pos) /*!< 0x00000020 */ #define AFIO_EXTICR2_EXTI5_PC AFIO_EXTICR2_EXTI5_PC_Msk /*!< PC[5] pin */ -#define AFIO_EXTICR2_EXTI5_PD_Pos (4U) +#define AFIO_EXTICR2_EXTI5_PD_Pos (4U) #define AFIO_EXTICR2_EXTI5_PD_Msk (0x3U << AFIO_EXTICR2_EXTI5_PD_Pos) /*!< 0x00000030 */ #define AFIO_EXTICR2_EXTI5_PD AFIO_EXTICR2_EXTI5_PD_Msk /*!< PD[5] pin */ -#define AFIO_EXTICR2_EXTI5_PE_Pos (6U) +#define AFIO_EXTICR2_EXTI5_PE_Pos (6U) #define AFIO_EXTICR2_EXTI5_PE_Msk (0x1U << AFIO_EXTICR2_EXTI5_PE_Pos) /*!< 0x00000040 */ #define AFIO_EXTICR2_EXTI5_PE AFIO_EXTICR2_EXTI5_PE_Msk /*!< PE[5] pin */ -#define AFIO_EXTICR2_EXTI5_PF_Pos (4U) +#define AFIO_EXTICR2_EXTI5_PF_Pos (4U) #define AFIO_EXTICR2_EXTI5_PF_Msk (0x5U << AFIO_EXTICR2_EXTI5_PF_Pos) /*!< 0x00000050 */ #define AFIO_EXTICR2_EXTI5_PF AFIO_EXTICR2_EXTI5_PF_Msk /*!< PF[5] pin */ -#define AFIO_EXTICR2_EXTI5_PG_Pos (5U) +#define AFIO_EXTICR2_EXTI5_PG_Pos (5U) #define AFIO_EXTICR2_EXTI5_PG_Msk (0x3U << AFIO_EXTICR2_EXTI5_PG_Pos) /*!< 0x00000060 */ #define AFIO_EXTICR2_EXTI5_PG AFIO_EXTICR2_EXTI5_PG_Msk /*!< PG[5] pin */ -/*!< EXTI6 configuration */ +/*!< EXTI6 configuration */ #define AFIO_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!< PA[6] pin */ -#define AFIO_EXTICR2_EXTI6_PB_Pos (8U) +#define AFIO_EXTICR2_EXTI6_PB_Pos (8U) #define AFIO_EXTICR2_EXTI6_PB_Msk (0x1U << AFIO_EXTICR2_EXTI6_PB_Pos) /*!< 0x00000100 */ #define AFIO_EXTICR2_EXTI6_PB AFIO_EXTICR2_EXTI6_PB_Msk /*!< PB[6] pin */ -#define AFIO_EXTICR2_EXTI6_PC_Pos (9U) +#define AFIO_EXTICR2_EXTI6_PC_Pos (9U) #define AFIO_EXTICR2_EXTI6_PC_Msk (0x1U << AFIO_EXTICR2_EXTI6_PC_Pos) /*!< 0x00000200 */ #define AFIO_EXTICR2_EXTI6_PC AFIO_EXTICR2_EXTI6_PC_Msk /*!< PC[6] pin */ -#define AFIO_EXTICR2_EXTI6_PD_Pos (8U) +#define AFIO_EXTICR2_EXTI6_PD_Pos (8U) #define AFIO_EXTICR2_EXTI6_PD_Msk (0x3U << AFIO_EXTICR2_EXTI6_PD_Pos) /*!< 0x00000300 */ #define AFIO_EXTICR2_EXTI6_PD AFIO_EXTICR2_EXTI6_PD_Msk /*!< PD[6] pin */ -#define AFIO_EXTICR2_EXTI6_PE_Pos (10U) +#define AFIO_EXTICR2_EXTI6_PE_Pos (10U) #define AFIO_EXTICR2_EXTI6_PE_Msk (0x1U << AFIO_EXTICR2_EXTI6_PE_Pos) /*!< 0x00000400 */ #define AFIO_EXTICR2_EXTI6_PE AFIO_EXTICR2_EXTI6_PE_Msk /*!< PE[6] pin */ -#define AFIO_EXTICR2_EXTI6_PF_Pos (8U) +#define AFIO_EXTICR2_EXTI6_PF_Pos (8U) #define AFIO_EXTICR2_EXTI6_PF_Msk (0x5U << AFIO_EXTICR2_EXTI6_PF_Pos) /*!< 0x00000500 */ #define AFIO_EXTICR2_EXTI6_PF AFIO_EXTICR2_EXTI6_PF_Msk /*!< PF[6] pin */ -#define AFIO_EXTICR2_EXTI6_PG_Pos (9U) +#define AFIO_EXTICR2_EXTI6_PG_Pos (9U) #define AFIO_EXTICR2_EXTI6_PG_Msk (0x3U << AFIO_EXTICR2_EXTI6_PG_Pos) /*!< 0x00000600 */ #define AFIO_EXTICR2_EXTI6_PG AFIO_EXTICR2_EXTI6_PG_Msk /*!< PG[6] pin */ /*!< EXTI7 configuration */ #define AFIO_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!< PA[7] pin */ -#define AFIO_EXTICR2_EXTI7_PB_Pos (12U) +#define AFIO_EXTICR2_EXTI7_PB_Pos (12U) #define AFIO_EXTICR2_EXTI7_PB_Msk (0x1U << AFIO_EXTICR2_EXTI7_PB_Pos) /*!< 0x00001000 */ #define AFIO_EXTICR2_EXTI7_PB AFIO_EXTICR2_EXTI7_PB_Msk /*!< PB[7] pin */ -#define AFIO_EXTICR2_EXTI7_PC_Pos (13U) +#define AFIO_EXTICR2_EXTI7_PC_Pos (13U) #define AFIO_EXTICR2_EXTI7_PC_Msk (0x1U << AFIO_EXTICR2_EXTI7_PC_Pos) /*!< 0x00002000 */ #define AFIO_EXTICR2_EXTI7_PC AFIO_EXTICR2_EXTI7_PC_Msk /*!< PC[7] pin */ -#define AFIO_EXTICR2_EXTI7_PD_Pos (12U) +#define AFIO_EXTICR2_EXTI7_PD_Pos (12U) #define AFIO_EXTICR2_EXTI7_PD_Msk (0x3U << AFIO_EXTICR2_EXTI7_PD_Pos) /*!< 0x00003000 */ #define AFIO_EXTICR2_EXTI7_PD AFIO_EXTICR2_EXTI7_PD_Msk /*!< PD[7] pin */ -#define AFIO_EXTICR2_EXTI7_PE_Pos (14U) +#define AFIO_EXTICR2_EXTI7_PE_Pos (14U) #define AFIO_EXTICR2_EXTI7_PE_Msk (0x1U << AFIO_EXTICR2_EXTI7_PE_Pos) /*!< 0x00004000 */ #define AFIO_EXTICR2_EXTI7_PE AFIO_EXTICR2_EXTI7_PE_Msk /*!< PE[7] pin */ -#define AFIO_EXTICR2_EXTI7_PF_Pos (12U) +#define AFIO_EXTICR2_EXTI7_PF_Pos (12U) #define AFIO_EXTICR2_EXTI7_PF_Msk (0x5U << AFIO_EXTICR2_EXTI7_PF_Pos) /*!< 0x00005000 */ #define AFIO_EXTICR2_EXTI7_PF AFIO_EXTICR2_EXTI7_PF_Msk /*!< PF[7] pin */ -#define AFIO_EXTICR2_EXTI7_PG_Pos (13U) +#define AFIO_EXTICR2_EXTI7_PG_Pos (13U) #define AFIO_EXTICR2_EXTI7_PG_Msk (0x3U << AFIO_EXTICR2_EXTI7_PG_Pos) /*!< 0x00006000 */ #define AFIO_EXTICR2_EXTI7_PG AFIO_EXTICR2_EXTI7_PG_Msk /*!< PG[7] pin */ /***************** Bit definition for AFIO_EXTICR3 register *****************/ -#define AFIO_EXTICR3_EXTI8_Pos (0U) +#define AFIO_EXTICR3_EXTI8_Pos (0U) #define AFIO_EXTICR3_EXTI8_Msk (0xFU << AFIO_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */ #define AFIO_EXTICR3_EXTI8 AFIO_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */ -#define AFIO_EXTICR3_EXTI9_Pos (4U) +#define AFIO_EXTICR3_EXTI9_Pos (4U) #define AFIO_EXTICR3_EXTI9_Msk (0xFU << AFIO_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */ #define AFIO_EXTICR3_EXTI9 AFIO_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */ -#define AFIO_EXTICR3_EXTI10_Pos (8U) +#define AFIO_EXTICR3_EXTI10_Pos (8U) #define AFIO_EXTICR3_EXTI10_Msk (0xFU << AFIO_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */ #define AFIO_EXTICR3_EXTI10 AFIO_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */ -#define AFIO_EXTICR3_EXTI11_Pos (12U) +#define AFIO_EXTICR3_EXTI11_Pos (12U) #define AFIO_EXTICR3_EXTI11_Msk (0xFU << AFIO_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */ #define AFIO_EXTICR3_EXTI11 AFIO_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */ /*!< EXTI8 configuration */ #define AFIO_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!< PA[8] pin */ -#define AFIO_EXTICR3_EXTI8_PB_Pos (0U) +#define AFIO_EXTICR3_EXTI8_PB_Pos (0U) #define AFIO_EXTICR3_EXTI8_PB_Msk (0x1U << AFIO_EXTICR3_EXTI8_PB_Pos) /*!< 0x00000001 */ #define AFIO_EXTICR3_EXTI8_PB AFIO_EXTICR3_EXTI8_PB_Msk /*!< PB[8] pin */ -#define AFIO_EXTICR3_EXTI8_PC_Pos (1U) +#define AFIO_EXTICR3_EXTI8_PC_Pos (1U) #define AFIO_EXTICR3_EXTI8_PC_Msk (0x1U << AFIO_EXTICR3_EXTI8_PC_Pos) /*!< 0x00000002 */ #define AFIO_EXTICR3_EXTI8_PC AFIO_EXTICR3_EXTI8_PC_Msk /*!< PC[8] pin */ -#define AFIO_EXTICR3_EXTI8_PD_Pos (0U) +#define AFIO_EXTICR3_EXTI8_PD_Pos (0U) #define AFIO_EXTICR3_EXTI8_PD_Msk (0x3U << AFIO_EXTICR3_EXTI8_PD_Pos) /*!< 0x00000003 */ #define AFIO_EXTICR3_EXTI8_PD AFIO_EXTICR3_EXTI8_PD_Msk /*!< PD[8] pin */ -#define AFIO_EXTICR3_EXTI8_PE_Pos (2U) +#define AFIO_EXTICR3_EXTI8_PE_Pos (2U) #define AFIO_EXTICR3_EXTI8_PE_Msk (0x1U << AFIO_EXTICR3_EXTI8_PE_Pos) /*!< 0x00000004 */ #define AFIO_EXTICR3_EXTI8_PE AFIO_EXTICR3_EXTI8_PE_Msk /*!< PE[8] pin */ -#define AFIO_EXTICR3_EXTI8_PF_Pos (0U) +#define AFIO_EXTICR3_EXTI8_PF_Pos (0U) #define AFIO_EXTICR3_EXTI8_PF_Msk (0x5U << AFIO_EXTICR3_EXTI8_PF_Pos) /*!< 0x00000005 */ #define AFIO_EXTICR3_EXTI8_PF AFIO_EXTICR3_EXTI8_PF_Msk /*!< PF[8] pin */ -#define AFIO_EXTICR3_EXTI8_PG_Pos (1U) +#define AFIO_EXTICR3_EXTI8_PG_Pos (1U) #define AFIO_EXTICR3_EXTI8_PG_Msk (0x3U << AFIO_EXTICR3_EXTI8_PG_Pos) /*!< 0x00000006 */ #define AFIO_EXTICR3_EXTI8_PG AFIO_EXTICR3_EXTI8_PG_Msk /*!< PG[8] pin */ /*!< EXTI9 configuration */ #define AFIO_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!< PA[9] pin */ -#define AFIO_EXTICR3_EXTI9_PB_Pos (4U) +#define AFIO_EXTICR3_EXTI9_PB_Pos (4U) #define AFIO_EXTICR3_EXTI9_PB_Msk (0x1U << AFIO_EXTICR3_EXTI9_PB_Pos) /*!< 0x00000010 */ #define AFIO_EXTICR3_EXTI9_PB AFIO_EXTICR3_EXTI9_PB_Msk /*!< PB[9] pin */ -#define AFIO_EXTICR3_EXTI9_PC_Pos (5U) +#define AFIO_EXTICR3_EXTI9_PC_Pos (5U) #define AFIO_EXTICR3_EXTI9_PC_Msk (0x1U << AFIO_EXTICR3_EXTI9_PC_Pos) /*!< 0x00000020 */ #define AFIO_EXTICR3_EXTI9_PC AFIO_EXTICR3_EXTI9_PC_Msk /*!< PC[9] pin */ -#define AFIO_EXTICR3_EXTI9_PD_Pos (4U) +#define AFIO_EXTICR3_EXTI9_PD_Pos (4U) #define AFIO_EXTICR3_EXTI9_PD_Msk (0x3U << AFIO_EXTICR3_EXTI9_PD_Pos) /*!< 0x00000030 */ #define AFIO_EXTICR3_EXTI9_PD AFIO_EXTICR3_EXTI9_PD_Msk /*!< PD[9] pin */ -#define AFIO_EXTICR3_EXTI9_PE_Pos (6U) +#define AFIO_EXTICR3_EXTI9_PE_Pos (6U) #define AFIO_EXTICR3_EXTI9_PE_Msk (0x1U << AFIO_EXTICR3_EXTI9_PE_Pos) /*!< 0x00000040 */ #define AFIO_EXTICR3_EXTI9_PE AFIO_EXTICR3_EXTI9_PE_Msk /*!< PE[9] pin */ -#define AFIO_EXTICR3_EXTI9_PF_Pos (4U) +#define AFIO_EXTICR3_EXTI9_PF_Pos (4U) #define AFIO_EXTICR3_EXTI9_PF_Msk (0x5U << AFIO_EXTICR3_EXTI9_PF_Pos) /*!< 0x00000050 */ #define AFIO_EXTICR3_EXTI9_PF AFIO_EXTICR3_EXTI9_PF_Msk /*!< PF[9] pin */ -#define AFIO_EXTICR3_EXTI9_PG_Pos (5U) +#define AFIO_EXTICR3_EXTI9_PG_Pos (5U) #define AFIO_EXTICR3_EXTI9_PG_Msk (0x3U << AFIO_EXTICR3_EXTI9_PG_Pos) /*!< 0x00000060 */ #define AFIO_EXTICR3_EXTI9_PG AFIO_EXTICR3_EXTI9_PG_Msk /*!< PG[9] pin */ -/*!< EXTI10 configuration */ +/*!< EXTI10 configuration */ #define AFIO_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!< PA[10] pin */ -#define AFIO_EXTICR3_EXTI10_PB_Pos (8U) +#define AFIO_EXTICR3_EXTI10_PB_Pos (8U) #define AFIO_EXTICR3_EXTI10_PB_Msk (0x1U << AFIO_EXTICR3_EXTI10_PB_Pos) /*!< 0x00000100 */ #define AFIO_EXTICR3_EXTI10_PB AFIO_EXTICR3_EXTI10_PB_Msk /*!< PB[10] pin */ -#define AFIO_EXTICR3_EXTI10_PC_Pos (9U) +#define AFIO_EXTICR3_EXTI10_PC_Pos (9U) #define AFIO_EXTICR3_EXTI10_PC_Msk (0x1U << AFIO_EXTICR3_EXTI10_PC_Pos) /*!< 0x00000200 */ #define AFIO_EXTICR3_EXTI10_PC AFIO_EXTICR3_EXTI10_PC_Msk /*!< PC[10] pin */ -#define AFIO_EXTICR3_EXTI10_PD_Pos (8U) +#define AFIO_EXTICR3_EXTI10_PD_Pos (8U) #define AFIO_EXTICR3_EXTI10_PD_Msk (0x3U << AFIO_EXTICR3_EXTI10_PD_Pos) /*!< 0x00000300 */ #define AFIO_EXTICR3_EXTI10_PD AFIO_EXTICR3_EXTI10_PD_Msk /*!< PD[10] pin */ -#define AFIO_EXTICR3_EXTI10_PE_Pos (10U) +#define AFIO_EXTICR3_EXTI10_PE_Pos (10U) #define AFIO_EXTICR3_EXTI10_PE_Msk (0x1U << AFIO_EXTICR3_EXTI10_PE_Pos) /*!< 0x00000400 */ #define AFIO_EXTICR3_EXTI10_PE AFIO_EXTICR3_EXTI10_PE_Msk /*!< PE[10] pin */ -#define AFIO_EXTICR3_EXTI10_PF_Pos (8U) +#define AFIO_EXTICR3_EXTI10_PF_Pos (8U) #define AFIO_EXTICR3_EXTI10_PF_Msk (0x5U << AFIO_EXTICR3_EXTI10_PF_Pos) /*!< 0x00000500 */ #define AFIO_EXTICR3_EXTI10_PF AFIO_EXTICR3_EXTI10_PF_Msk /*!< PF[10] pin */ -#define AFIO_EXTICR3_EXTI10_PG_Pos (9U) +#define AFIO_EXTICR3_EXTI10_PG_Pos (9U) #define AFIO_EXTICR3_EXTI10_PG_Msk (0x3U << AFIO_EXTICR3_EXTI10_PG_Pos) /*!< 0x00000600 */ #define AFIO_EXTICR3_EXTI10_PG AFIO_EXTICR3_EXTI10_PG_Msk /*!< PG[10] pin */ /*!< EXTI11 configuration */ #define AFIO_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!< PA[11] pin */ -#define AFIO_EXTICR3_EXTI11_PB_Pos (12U) +#define AFIO_EXTICR3_EXTI11_PB_Pos (12U) #define AFIO_EXTICR3_EXTI11_PB_Msk (0x1U << AFIO_EXTICR3_EXTI11_PB_Pos) /*!< 0x00001000 */ #define AFIO_EXTICR3_EXTI11_PB AFIO_EXTICR3_EXTI11_PB_Msk /*!< PB[11] pin */ -#define AFIO_EXTICR3_EXTI11_PC_Pos (13U) +#define AFIO_EXTICR3_EXTI11_PC_Pos (13U) #define AFIO_EXTICR3_EXTI11_PC_Msk (0x1U << AFIO_EXTICR3_EXTI11_PC_Pos) /*!< 0x00002000 */ #define AFIO_EXTICR3_EXTI11_PC AFIO_EXTICR3_EXTI11_PC_Msk /*!< PC[11] pin */ -#define AFIO_EXTICR3_EXTI11_PD_Pos (12U) +#define AFIO_EXTICR3_EXTI11_PD_Pos (12U) #define AFIO_EXTICR3_EXTI11_PD_Msk (0x3U << AFIO_EXTICR3_EXTI11_PD_Pos) /*!< 0x00003000 */ #define AFIO_EXTICR3_EXTI11_PD AFIO_EXTICR3_EXTI11_PD_Msk /*!< PD[11] pin */ -#define AFIO_EXTICR3_EXTI11_PE_Pos (14U) +#define AFIO_EXTICR3_EXTI11_PE_Pos (14U) #define AFIO_EXTICR3_EXTI11_PE_Msk (0x1U << AFIO_EXTICR3_EXTI11_PE_Pos) /*!< 0x00004000 */ #define AFIO_EXTICR3_EXTI11_PE AFIO_EXTICR3_EXTI11_PE_Msk /*!< PE[11] pin */ -#define AFIO_EXTICR3_EXTI11_PF_Pos (12U) +#define AFIO_EXTICR3_EXTI11_PF_Pos (12U) #define AFIO_EXTICR3_EXTI11_PF_Msk (0x5U << AFIO_EXTICR3_EXTI11_PF_Pos) /*!< 0x00005000 */ #define AFIO_EXTICR3_EXTI11_PF AFIO_EXTICR3_EXTI11_PF_Msk /*!< PF[11] pin */ -#define AFIO_EXTICR3_EXTI11_PG_Pos (13U) +#define AFIO_EXTICR3_EXTI11_PG_Pos (13U) #define AFIO_EXTICR3_EXTI11_PG_Msk (0x3U << AFIO_EXTICR3_EXTI11_PG_Pos) /*!< 0x00006000 */ #define AFIO_EXTICR3_EXTI11_PG AFIO_EXTICR3_EXTI11_PG_Msk /*!< PG[11] pin */ /***************** Bit definition for AFIO_EXTICR4 register *****************/ -#define AFIO_EXTICR4_EXTI12_Pos (0U) +#define AFIO_EXTICR4_EXTI12_Pos (0U) #define AFIO_EXTICR4_EXTI12_Msk (0xFU << AFIO_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */ #define AFIO_EXTICR4_EXTI12 AFIO_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */ -#define AFIO_EXTICR4_EXTI13_Pos (4U) +#define AFIO_EXTICR4_EXTI13_Pos (4U) #define AFIO_EXTICR4_EXTI13_Msk (0xFU << AFIO_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */ #define AFIO_EXTICR4_EXTI13 AFIO_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */ -#define AFIO_EXTICR4_EXTI14_Pos (8U) +#define AFIO_EXTICR4_EXTI14_Pos (8U) #define AFIO_EXTICR4_EXTI14_Msk (0xFU << AFIO_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */ #define AFIO_EXTICR4_EXTI14 AFIO_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */ -#define AFIO_EXTICR4_EXTI15_Pos (12U) +#define AFIO_EXTICR4_EXTI15_Pos (12U) #define AFIO_EXTICR4_EXTI15_Msk (0xFU << AFIO_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */ #define AFIO_EXTICR4_EXTI15 AFIO_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */ /* EXTI12 configuration */ #define AFIO_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!< PA[12] pin */ -#define AFIO_EXTICR4_EXTI12_PB_Pos (0U) +#define AFIO_EXTICR4_EXTI12_PB_Pos (0U) #define AFIO_EXTICR4_EXTI12_PB_Msk (0x1U << AFIO_EXTICR4_EXTI12_PB_Pos) /*!< 0x00000001 */ #define AFIO_EXTICR4_EXTI12_PB AFIO_EXTICR4_EXTI12_PB_Msk /*!< PB[12] pin */ -#define AFIO_EXTICR4_EXTI12_PC_Pos (1U) +#define AFIO_EXTICR4_EXTI12_PC_Pos (1U) #define AFIO_EXTICR4_EXTI12_PC_Msk (0x1U << AFIO_EXTICR4_EXTI12_PC_Pos) /*!< 0x00000002 */ #define AFIO_EXTICR4_EXTI12_PC AFIO_EXTICR4_EXTI12_PC_Msk /*!< PC[12] pin */ -#define AFIO_EXTICR4_EXTI12_PD_Pos (0U) +#define AFIO_EXTICR4_EXTI12_PD_Pos (0U) #define AFIO_EXTICR4_EXTI12_PD_Msk (0x3U << AFIO_EXTICR4_EXTI12_PD_Pos) /*!< 0x00000003 */ #define AFIO_EXTICR4_EXTI12_PD AFIO_EXTICR4_EXTI12_PD_Msk /*!< PD[12] pin */ -#define AFIO_EXTICR4_EXTI12_PE_Pos (2U) +#define AFIO_EXTICR4_EXTI12_PE_Pos (2U) #define AFIO_EXTICR4_EXTI12_PE_Msk (0x1U << AFIO_EXTICR4_EXTI12_PE_Pos) /*!< 0x00000004 */ #define AFIO_EXTICR4_EXTI12_PE AFIO_EXTICR4_EXTI12_PE_Msk /*!< PE[12] pin */ -#define AFIO_EXTICR4_EXTI12_PF_Pos (0U) +#define AFIO_EXTICR4_EXTI12_PF_Pos (0U) #define AFIO_EXTICR4_EXTI12_PF_Msk (0x5U << AFIO_EXTICR4_EXTI12_PF_Pos) /*!< 0x00000005 */ #define AFIO_EXTICR4_EXTI12_PF AFIO_EXTICR4_EXTI12_PF_Msk /*!< PF[12] pin */ -#define AFIO_EXTICR4_EXTI12_PG_Pos (1U) +#define AFIO_EXTICR4_EXTI12_PG_Pos (1U) #define AFIO_EXTICR4_EXTI12_PG_Msk (0x3U << AFIO_EXTICR4_EXTI12_PG_Pos) /*!< 0x00000006 */ #define AFIO_EXTICR4_EXTI12_PG AFIO_EXTICR4_EXTI12_PG_Msk /*!< PG[12] pin */ /* EXTI13 configuration */ #define AFIO_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!< PA[13] pin */ -#define AFIO_EXTICR4_EXTI13_PB_Pos (4U) +#define AFIO_EXTICR4_EXTI13_PB_Pos (4U) #define AFIO_EXTICR4_EXTI13_PB_Msk (0x1U << AFIO_EXTICR4_EXTI13_PB_Pos) /*!< 0x00000010 */ #define AFIO_EXTICR4_EXTI13_PB AFIO_EXTICR4_EXTI13_PB_Msk /*!< PB[13] pin */ -#define AFIO_EXTICR4_EXTI13_PC_Pos (5U) +#define AFIO_EXTICR4_EXTI13_PC_Pos (5U) #define AFIO_EXTICR4_EXTI13_PC_Msk (0x1U << AFIO_EXTICR4_EXTI13_PC_Pos) /*!< 0x00000020 */ #define AFIO_EXTICR4_EXTI13_PC AFIO_EXTICR4_EXTI13_PC_Msk /*!< PC[13] pin */ -#define AFIO_EXTICR4_EXTI13_PD_Pos (4U) +#define AFIO_EXTICR4_EXTI13_PD_Pos (4U) #define AFIO_EXTICR4_EXTI13_PD_Msk (0x3U << AFIO_EXTICR4_EXTI13_PD_Pos) /*!< 0x00000030 */ #define AFIO_EXTICR4_EXTI13_PD AFIO_EXTICR4_EXTI13_PD_Msk /*!< PD[13] pin */ -#define AFIO_EXTICR4_EXTI13_PE_Pos (6U) +#define AFIO_EXTICR4_EXTI13_PE_Pos (6U) #define AFIO_EXTICR4_EXTI13_PE_Msk (0x1U << AFIO_EXTICR4_EXTI13_PE_Pos) /*!< 0x00000040 */ #define AFIO_EXTICR4_EXTI13_PE AFIO_EXTICR4_EXTI13_PE_Msk /*!< PE[13] pin */ -#define AFIO_EXTICR4_EXTI13_PF_Pos (4U) +#define AFIO_EXTICR4_EXTI13_PF_Pos (4U) #define AFIO_EXTICR4_EXTI13_PF_Msk (0x5U << AFIO_EXTICR4_EXTI13_PF_Pos) /*!< 0x00000050 */ #define AFIO_EXTICR4_EXTI13_PF AFIO_EXTICR4_EXTI13_PF_Msk /*!< PF[13] pin */ -#define AFIO_EXTICR4_EXTI13_PG_Pos (5U) +#define AFIO_EXTICR4_EXTI13_PG_Pos (5U) #define AFIO_EXTICR4_EXTI13_PG_Msk (0x3U << AFIO_EXTICR4_EXTI13_PG_Pos) /*!< 0x00000060 */ #define AFIO_EXTICR4_EXTI13_PG AFIO_EXTICR4_EXTI13_PG_Msk /*!< PG[13] pin */ -/*!< EXTI14 configuration */ +/*!< EXTI14 configuration */ #define AFIO_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!< PA[14] pin */ -#define AFIO_EXTICR4_EXTI14_PB_Pos (8U) +#define AFIO_EXTICR4_EXTI14_PB_Pos (8U) #define AFIO_EXTICR4_EXTI14_PB_Msk (0x1U << AFIO_EXTICR4_EXTI14_PB_Pos) /*!< 0x00000100 */ #define AFIO_EXTICR4_EXTI14_PB AFIO_EXTICR4_EXTI14_PB_Msk /*!< PB[14] pin */ -#define AFIO_EXTICR4_EXTI14_PC_Pos (9U) +#define AFIO_EXTICR4_EXTI14_PC_Pos (9U) #define AFIO_EXTICR4_EXTI14_PC_Msk (0x1U << AFIO_EXTICR4_EXTI14_PC_Pos) /*!< 0x00000200 */ #define AFIO_EXTICR4_EXTI14_PC AFIO_EXTICR4_EXTI14_PC_Msk /*!< PC[14] pin */ -#define AFIO_EXTICR4_EXTI14_PD_Pos (8U) +#define AFIO_EXTICR4_EXTI14_PD_Pos (8U) #define AFIO_EXTICR4_EXTI14_PD_Msk (0x3U << AFIO_EXTICR4_EXTI14_PD_Pos) /*!< 0x00000300 */ #define AFIO_EXTICR4_EXTI14_PD AFIO_EXTICR4_EXTI14_PD_Msk /*!< PD[14] pin */ -#define AFIO_EXTICR4_EXTI14_PE_Pos (10U) +#define AFIO_EXTICR4_EXTI14_PE_Pos (10U) #define AFIO_EXTICR4_EXTI14_PE_Msk (0x1U << AFIO_EXTICR4_EXTI14_PE_Pos) /*!< 0x00000400 */ #define AFIO_EXTICR4_EXTI14_PE AFIO_EXTICR4_EXTI14_PE_Msk /*!< PE[14] pin */ -#define AFIO_EXTICR4_EXTI14_PF_Pos (8U) +#define AFIO_EXTICR4_EXTI14_PF_Pos (8U) #define AFIO_EXTICR4_EXTI14_PF_Msk (0x5U << AFIO_EXTICR4_EXTI14_PF_Pos) /*!< 0x00000500 */ #define AFIO_EXTICR4_EXTI14_PF AFIO_EXTICR4_EXTI14_PF_Msk /*!< PF[14] pin */ -#define AFIO_EXTICR4_EXTI14_PG_Pos (9U) +#define AFIO_EXTICR4_EXTI14_PG_Pos (9U) #define AFIO_EXTICR4_EXTI14_PG_Msk (0x3U << AFIO_EXTICR4_EXTI14_PG_Pos) /*!< 0x00000600 */ #define AFIO_EXTICR4_EXTI14_PG AFIO_EXTICR4_EXTI14_PG_Msk /*!< PG[14] pin */ /*!< EXTI15 configuration */ #define AFIO_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!< PA[15] pin */ -#define AFIO_EXTICR4_EXTI15_PB_Pos (12U) +#define AFIO_EXTICR4_EXTI15_PB_Pos (12U) #define AFIO_EXTICR4_EXTI15_PB_Msk (0x1U << AFIO_EXTICR4_EXTI15_PB_Pos) /*!< 0x00001000 */ #define AFIO_EXTICR4_EXTI15_PB AFIO_EXTICR4_EXTI15_PB_Msk /*!< PB[15] pin */ -#define AFIO_EXTICR4_EXTI15_PC_Pos (13U) +#define AFIO_EXTICR4_EXTI15_PC_Pos (13U) #define AFIO_EXTICR4_EXTI15_PC_Msk (0x1U << AFIO_EXTICR4_EXTI15_PC_Pos) /*!< 0x00002000 */ #define AFIO_EXTICR4_EXTI15_PC AFIO_EXTICR4_EXTI15_PC_Msk /*!< PC[15] pin */ -#define AFIO_EXTICR4_EXTI15_PD_Pos (12U) +#define AFIO_EXTICR4_EXTI15_PD_Pos (12U) #define AFIO_EXTICR4_EXTI15_PD_Msk (0x3U << AFIO_EXTICR4_EXTI15_PD_Pos) /*!< 0x00003000 */ #define AFIO_EXTICR4_EXTI15_PD AFIO_EXTICR4_EXTI15_PD_Msk /*!< PD[15] pin */ -#define AFIO_EXTICR4_EXTI15_PE_Pos (14U) +#define AFIO_EXTICR4_EXTI15_PE_Pos (14U) #define AFIO_EXTICR4_EXTI15_PE_Msk (0x1U << AFIO_EXTICR4_EXTI15_PE_Pos) /*!< 0x00004000 */ #define AFIO_EXTICR4_EXTI15_PE AFIO_EXTICR4_EXTI15_PE_Msk /*!< PE[15] pin */ -#define AFIO_EXTICR4_EXTI15_PF_Pos (12U) +#define AFIO_EXTICR4_EXTI15_PF_Pos (12U) #define AFIO_EXTICR4_EXTI15_PF_Msk (0x5U << AFIO_EXTICR4_EXTI15_PF_Pos) /*!< 0x00005000 */ #define AFIO_EXTICR4_EXTI15_PF AFIO_EXTICR4_EXTI15_PF_Msk /*!< PF[15] pin */ -#define AFIO_EXTICR4_EXTI15_PG_Pos (13U) +#define AFIO_EXTICR4_EXTI15_PG_Pos (13U) #define AFIO_EXTICR4_EXTI15_PG_Msk (0x3U << AFIO_EXTICR4_EXTI15_PG_Pos) /*!< 0x00006000 */ #define AFIO_EXTICR4_EXTI15_PG AFIO_EXTICR4_EXTI15_PG_Msk /*!< PG[15] pin */ @@ -2546,7 +2546,7 @@ typedef struct /******************************************************************************/ /****************** Bit definition for NVIC_ISER register *******************/ -#define NVIC_ISER_SETENA_Pos (0U) +#define NVIC_ISER_SETENA_Pos (0U) #define NVIC_ISER_SETENA_Msk (0xFFFFFFFFU << NVIC_ISER_SETENA_Pos) /*!< 0xFFFFFFFF */ #define NVIC_ISER_SETENA NVIC_ISER_SETENA_Msk /*!< Interrupt set enable bits */ #define NVIC_ISER_SETENA_0 (0x00000001U << NVIC_ISER_SETENA_Pos) /*!< 0x00000001 */ @@ -2583,7 +2583,7 @@ typedef struct #define NVIC_ISER_SETENA_31 (0x80000000U << NVIC_ISER_SETENA_Pos) /*!< 0x80000000 */ /****************** Bit definition for NVIC_ICER register *******************/ -#define NVIC_ICER_CLRENA_Pos (0U) +#define NVIC_ICER_CLRENA_Pos (0U) #define NVIC_ICER_CLRENA_Msk (0xFFFFFFFFU << NVIC_ICER_CLRENA_Pos) /*!< 0xFFFFFFFF */ #define NVIC_ICER_CLRENA NVIC_ICER_CLRENA_Msk /*!< Interrupt clear-enable bits */ #define NVIC_ICER_CLRENA_0 (0x00000001U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000001 */ @@ -2620,7 +2620,7 @@ typedef struct #define NVIC_ICER_CLRENA_31 (0x80000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x80000000 */ /****************** Bit definition for NVIC_ISPR register *******************/ -#define NVIC_ISPR_SETPEND_Pos (0U) +#define NVIC_ISPR_SETPEND_Pos (0U) #define NVIC_ISPR_SETPEND_Msk (0xFFFFFFFFU << NVIC_ISPR_SETPEND_Pos) /*!< 0xFFFFFFFF */ #define NVIC_ISPR_SETPEND NVIC_ISPR_SETPEND_Msk /*!< Interrupt set-pending bits */ #define NVIC_ISPR_SETPEND_0 (0x00000001U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000001 */ @@ -2657,7 +2657,7 @@ typedef struct #define NVIC_ISPR_SETPEND_31 (0x80000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x80000000 */ /****************** Bit definition for NVIC_ICPR register *******************/ -#define NVIC_ICPR_CLRPEND_Pos (0U) +#define NVIC_ICPR_CLRPEND_Pos (0U) #define NVIC_ICPR_CLRPEND_Msk (0xFFFFFFFFU << NVIC_ICPR_CLRPEND_Pos) /*!< 0xFFFFFFFF */ #define NVIC_ICPR_CLRPEND NVIC_ICPR_CLRPEND_Msk /*!< Interrupt clear-pending bits */ #define NVIC_ICPR_CLRPEND_0 (0x00000001U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000001 */ @@ -2694,7 +2694,7 @@ typedef struct #define NVIC_ICPR_CLRPEND_31 (0x80000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x80000000 */ /****************** Bit definition for NVIC_IABR register *******************/ -#define NVIC_IABR_ACTIVE_Pos (0U) +#define NVIC_IABR_ACTIVE_Pos (0U) #define NVIC_IABR_ACTIVE_Msk (0xFFFFFFFFU << NVIC_IABR_ACTIVE_Pos) /*!< 0xFFFFFFFF */ #define NVIC_IABR_ACTIVE NVIC_IABR_ACTIVE_Msk /*!< Interrupt active flags */ #define NVIC_IABR_ACTIVE_0 (0x00000001U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000001 */ @@ -2838,16 +2838,16 @@ typedef struct #define SCB_CCR_STKALIGN ((uint32_t)0x00000200) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */ /******************* Bit definition for SCB_SHPR register ********************/ -#define SCB_SHPR_PRI_N_Pos (0U) +#define SCB_SHPR_PRI_N_Pos (0U) #define SCB_SHPR_PRI_N_Msk (0xFFU << SCB_SHPR_PRI_N_Pos) /*!< 0x000000FF */ #define SCB_SHPR_PRI_N SCB_SHPR_PRI_N_Msk /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */ -#define SCB_SHPR_PRI_N1_Pos (8U) +#define SCB_SHPR_PRI_N1_Pos (8U) #define SCB_SHPR_PRI_N1_Msk (0xFFU << SCB_SHPR_PRI_N1_Pos) /*!< 0x0000FF00 */ #define SCB_SHPR_PRI_N1 SCB_SHPR_PRI_N1_Msk /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */ -#define SCB_SHPR_PRI_N2_Pos (16U) +#define SCB_SHPR_PRI_N2_Pos (16U) #define SCB_SHPR_PRI_N2_Msk (0xFFU << SCB_SHPR_PRI_N2_Pos) /*!< 0x00FF0000 */ #define SCB_SHPR_PRI_N2 SCB_SHPR_PRI_N2_Msk /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */ -#define SCB_SHPR_PRI_N3_Pos (24U) +#define SCB_SHPR_PRI_N3_Pos (24U) #define SCB_SHPR_PRI_N3_Msk (0xFFU << SCB_SHPR_PRI_N3_Pos) /*!< 0xFF000000 */ #define SCB_SHPR_PRI_N3 SCB_SHPR_PRI_N3_Msk /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */ @@ -2869,57 +2869,57 @@ typedef struct /******************* Bit definition for SCB_CFSR register *******************/ /*!< MFSR */ -#define SCB_CFSR_IACCVIOL_Pos (0U) +#define SCB_CFSR_IACCVIOL_Pos (0U) #define SCB_CFSR_IACCVIOL_Msk (0x1U << SCB_CFSR_IACCVIOL_Pos) /*!< 0x00000001 */ #define SCB_CFSR_IACCVIOL SCB_CFSR_IACCVIOL_Msk /*!< Instruction access violation */ -#define SCB_CFSR_DACCVIOL_Pos (1U) +#define SCB_CFSR_DACCVIOL_Pos (1U) #define SCB_CFSR_DACCVIOL_Msk (0x1U << SCB_CFSR_DACCVIOL_Pos) /*!< 0x00000002 */ #define SCB_CFSR_DACCVIOL SCB_CFSR_DACCVIOL_Msk /*!< Data access violation */ -#define SCB_CFSR_MUNSTKERR_Pos (3U) +#define SCB_CFSR_MUNSTKERR_Pos (3U) #define SCB_CFSR_MUNSTKERR_Msk (0x1U << SCB_CFSR_MUNSTKERR_Pos) /*!< 0x00000008 */ #define SCB_CFSR_MUNSTKERR SCB_CFSR_MUNSTKERR_Msk /*!< Unstacking error */ -#define SCB_CFSR_MSTKERR_Pos (4U) +#define SCB_CFSR_MSTKERR_Pos (4U) #define SCB_CFSR_MSTKERR_Msk (0x1U << SCB_CFSR_MSTKERR_Pos) /*!< 0x00000010 */ #define SCB_CFSR_MSTKERR SCB_CFSR_MSTKERR_Msk /*!< Stacking error */ -#define SCB_CFSR_MMARVALID_Pos (7U) +#define SCB_CFSR_MMARVALID_Pos (7U) #define SCB_CFSR_MMARVALID_Msk (0x1U << SCB_CFSR_MMARVALID_Pos) /*!< 0x00000080 */ #define SCB_CFSR_MMARVALID SCB_CFSR_MMARVALID_Msk /*!< Memory Manage Address Register address valid flag */ /*!< BFSR */ -#define SCB_CFSR_IBUSERR_Pos (8U) +#define SCB_CFSR_IBUSERR_Pos (8U) #define SCB_CFSR_IBUSERR_Msk (0x1U << SCB_CFSR_IBUSERR_Pos) /*!< 0x00000100 */ #define SCB_CFSR_IBUSERR SCB_CFSR_IBUSERR_Msk /*!< Instruction bus error flag */ -#define SCB_CFSR_PRECISERR_Pos (9U) +#define SCB_CFSR_PRECISERR_Pos (9U) #define SCB_CFSR_PRECISERR_Msk (0x1U << SCB_CFSR_PRECISERR_Pos) /*!< 0x00000200 */ #define SCB_CFSR_PRECISERR SCB_CFSR_PRECISERR_Msk /*!< Precise data bus error */ -#define SCB_CFSR_IMPRECISERR_Pos (10U) +#define SCB_CFSR_IMPRECISERR_Pos (10U) #define SCB_CFSR_IMPRECISERR_Msk (0x1U << SCB_CFSR_IMPRECISERR_Pos) /*!< 0x00000400 */ #define SCB_CFSR_IMPRECISERR SCB_CFSR_IMPRECISERR_Msk /*!< Imprecise data bus error */ -#define SCB_CFSR_UNSTKERR_Pos (11U) +#define SCB_CFSR_UNSTKERR_Pos (11U) #define SCB_CFSR_UNSTKERR_Msk (0x1U << SCB_CFSR_UNSTKERR_Pos) /*!< 0x00000800 */ #define SCB_CFSR_UNSTKERR SCB_CFSR_UNSTKERR_Msk /*!< Unstacking error */ -#define SCB_CFSR_STKERR_Pos (12U) +#define SCB_CFSR_STKERR_Pos (12U) #define SCB_CFSR_STKERR_Msk (0x1U << SCB_CFSR_STKERR_Pos) /*!< 0x00001000 */ #define SCB_CFSR_STKERR SCB_CFSR_STKERR_Msk /*!< Stacking error */ -#define SCB_CFSR_BFARVALID_Pos (15U) +#define SCB_CFSR_BFARVALID_Pos (15U) #define SCB_CFSR_BFARVALID_Msk (0x1U << SCB_CFSR_BFARVALID_Pos) /*!< 0x00008000 */ #define SCB_CFSR_BFARVALID SCB_CFSR_BFARVALID_Msk /*!< Bus Fault Address Register address valid flag */ /*!< UFSR */ -#define SCB_CFSR_UNDEFINSTR_Pos (16U) +#define SCB_CFSR_UNDEFINSTR_Pos (16U) #define SCB_CFSR_UNDEFINSTR_Msk (0x1U << SCB_CFSR_UNDEFINSTR_Pos) /*!< 0x00010000 */ #define SCB_CFSR_UNDEFINSTR SCB_CFSR_UNDEFINSTR_Msk /*!< The processor attempt to execute an undefined instruction */ -#define SCB_CFSR_INVSTATE_Pos (17U) +#define SCB_CFSR_INVSTATE_Pos (17U) #define SCB_CFSR_INVSTATE_Msk (0x1U << SCB_CFSR_INVSTATE_Pos) /*!< 0x00020000 */ #define SCB_CFSR_INVSTATE SCB_CFSR_INVSTATE_Msk /*!< Invalid combination of EPSR and instruction */ -#define SCB_CFSR_INVPC_Pos (18U) +#define SCB_CFSR_INVPC_Pos (18U) #define SCB_CFSR_INVPC_Msk (0x1U << SCB_CFSR_INVPC_Pos) /*!< 0x00040000 */ #define SCB_CFSR_INVPC SCB_CFSR_INVPC_Msk /*!< Attempt to load EXC_RETURN into pc illegally */ -#define SCB_CFSR_NOCP_Pos (19U) +#define SCB_CFSR_NOCP_Pos (19U) #define SCB_CFSR_NOCP_Msk (0x1U << SCB_CFSR_NOCP_Pos) /*!< 0x00080000 */ #define SCB_CFSR_NOCP SCB_CFSR_NOCP_Msk /*!< Attempt to use a coprocessor instruction */ -#define SCB_CFSR_UNALIGNED_Pos (24U) +#define SCB_CFSR_UNALIGNED_Pos (24U) #define SCB_CFSR_UNALIGNED_Msk (0x1U << SCB_CFSR_UNALIGNED_Pos) /*!< 0x01000000 */ #define SCB_CFSR_UNALIGNED SCB_CFSR_UNALIGNED_Msk /*!< Fault occurs when there is an attempt to make an unaligned memory access */ -#define SCB_CFSR_DIVBYZERO_Pos (25U) +#define SCB_CFSR_DIVBYZERO_Pos (25U) #define SCB_CFSR_DIVBYZERO_Msk (0x1U << SCB_CFSR_DIVBYZERO_Pos) /*!< 0x02000000 */ #define SCB_CFSR_DIVBYZERO SCB_CFSR_DIVBYZERO_Msk /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */ @@ -2936,17 +2936,17 @@ typedef struct #define SCB_DFSR_EXTERNAL ((uint32_t)0x00000010) /*!< External debug request flag */ /******************* Bit definition for SCB_MMFAR register ******************/ -#define SCB_MMFAR_ADDRESS_Pos (0U) +#define SCB_MMFAR_ADDRESS_Pos (0U) #define SCB_MMFAR_ADDRESS_Msk (0xFFFFFFFFU << SCB_MMFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */ #define SCB_MMFAR_ADDRESS SCB_MMFAR_ADDRESS_Msk /*!< Mem Manage fault address field */ /******************* Bit definition for SCB_BFAR register *******************/ -#define SCB_BFAR_ADDRESS_Pos (0U) +#define SCB_BFAR_ADDRESS_Pos (0U) #define SCB_BFAR_ADDRESS_Msk (0xFFFFFFFFU << SCB_BFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */ #define SCB_BFAR_ADDRESS SCB_BFAR_ADDRESS_Msk /*!< Bus fault address field */ /******************* Bit definition for SCB_afsr register *******************/ -#define SCB_AFSR_IMPDEF_Pos (0U) +#define SCB_AFSR_IMPDEF_Pos (0U) #define SCB_AFSR_IMPDEF_Msk (0xFFFFFFFFU << SCB_AFSR_IMPDEF_Pos) /*!< 0xFFFFFFFF */ #define SCB_AFSR_IMPDEF SCB_AFSR_IMPDEF_Msk /*!< Implementation defined */ @@ -2957,64 +2957,64 @@ typedef struct /******************************************************************************/ /******************* Bit definition for EXTI_IMR register *******************/ -#define EXTI_IMR_MR0_Pos (0U) +#define EXTI_IMR_MR0_Pos (0U) #define EXTI_IMR_MR0_Msk (0x1U << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */ #define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */ -#define EXTI_IMR_MR1_Pos (1U) +#define EXTI_IMR_MR1_Pos (1U) #define EXTI_IMR_MR1_Msk (0x1U << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */ #define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */ -#define EXTI_IMR_MR2_Pos (2U) +#define EXTI_IMR_MR2_Pos (2U) #define EXTI_IMR_MR2_Msk (0x1U << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */ #define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */ -#define EXTI_IMR_MR3_Pos (3U) +#define EXTI_IMR_MR3_Pos (3U) #define EXTI_IMR_MR3_Msk (0x1U << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */ #define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */ -#define EXTI_IMR_MR4_Pos (4U) +#define EXTI_IMR_MR4_Pos (4U) #define EXTI_IMR_MR4_Msk (0x1U << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */ #define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */ -#define EXTI_IMR_MR5_Pos (5U) +#define EXTI_IMR_MR5_Pos (5U) #define EXTI_IMR_MR5_Msk (0x1U << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */ #define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */ -#define EXTI_IMR_MR6_Pos (6U) +#define EXTI_IMR_MR6_Pos (6U) #define EXTI_IMR_MR6_Msk (0x1U << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */ #define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */ -#define EXTI_IMR_MR7_Pos (7U) +#define EXTI_IMR_MR7_Pos (7U) #define EXTI_IMR_MR7_Msk (0x1U << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */ #define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */ -#define EXTI_IMR_MR8_Pos (8U) +#define EXTI_IMR_MR8_Pos (8U) #define EXTI_IMR_MR8_Msk (0x1U << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */ #define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */ -#define EXTI_IMR_MR9_Pos (9U) +#define EXTI_IMR_MR9_Pos (9U) #define EXTI_IMR_MR9_Msk (0x1U << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */ #define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */ -#define EXTI_IMR_MR10_Pos (10U) +#define EXTI_IMR_MR10_Pos (10U) #define EXTI_IMR_MR10_Msk (0x1U << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */ #define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */ -#define EXTI_IMR_MR11_Pos (11U) +#define EXTI_IMR_MR11_Pos (11U) #define EXTI_IMR_MR11_Msk (0x1U << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */ #define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */ -#define EXTI_IMR_MR12_Pos (12U) +#define EXTI_IMR_MR12_Pos (12U) #define EXTI_IMR_MR12_Msk (0x1U << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */ #define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */ -#define EXTI_IMR_MR13_Pos (13U) +#define EXTI_IMR_MR13_Pos (13U) #define EXTI_IMR_MR13_Msk (0x1U << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */ #define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */ -#define EXTI_IMR_MR14_Pos (14U) +#define EXTI_IMR_MR14_Pos (14U) #define EXTI_IMR_MR14_Msk (0x1U << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */ #define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */ -#define EXTI_IMR_MR15_Pos (15U) +#define EXTI_IMR_MR15_Pos (15U) #define EXTI_IMR_MR15_Msk (0x1U << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */ #define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */ -#define EXTI_IMR_MR16_Pos (16U) +#define EXTI_IMR_MR16_Pos (16U) #define EXTI_IMR_MR16_Msk (0x1U << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */ #define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */ -#define EXTI_IMR_MR17_Pos (17U) +#define EXTI_IMR_MR17_Pos (17U) #define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */ #define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */ -#define EXTI_IMR_MR18_Pos (18U) +#define EXTI_IMR_MR18_Pos (18U) #define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */ #define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */ -#define EXTI_IMR_MR19_Pos (19U) +#define EXTI_IMR_MR19_Pos (19U) #define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */ #define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */ @@ -3041,64 +3041,64 @@ typedef struct #define EXTI_IMR_IM19 EXTI_IMR_MR19 /******************* Bit definition for EXTI_EMR register *******************/ -#define EXTI_EMR_MR0_Pos (0U) +#define EXTI_EMR_MR0_Pos (0U) #define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */ #define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */ -#define EXTI_EMR_MR1_Pos (1U) +#define EXTI_EMR_MR1_Pos (1U) #define EXTI_EMR_MR1_Msk (0x1U << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */ #define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */ -#define EXTI_EMR_MR2_Pos (2U) +#define EXTI_EMR_MR2_Pos (2U) #define EXTI_EMR_MR2_Msk (0x1U << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */ #define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */ -#define EXTI_EMR_MR3_Pos (3U) +#define EXTI_EMR_MR3_Pos (3U) #define EXTI_EMR_MR3_Msk (0x1U << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */ #define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */ -#define EXTI_EMR_MR4_Pos (4U) +#define EXTI_EMR_MR4_Pos (4U) #define EXTI_EMR_MR4_Msk (0x1U << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */ #define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */ -#define EXTI_EMR_MR5_Pos (5U) +#define EXTI_EMR_MR5_Pos (5U) #define EXTI_EMR_MR5_Msk (0x1U << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */ #define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */ -#define EXTI_EMR_MR6_Pos (6U) +#define EXTI_EMR_MR6_Pos (6U) #define EXTI_EMR_MR6_Msk (0x1U << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */ #define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */ -#define EXTI_EMR_MR7_Pos (7U) +#define EXTI_EMR_MR7_Pos (7U) #define EXTI_EMR_MR7_Msk (0x1U << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */ #define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */ -#define EXTI_EMR_MR8_Pos (8U) +#define EXTI_EMR_MR8_Pos (8U) #define EXTI_EMR_MR8_Msk (0x1U << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */ #define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */ -#define EXTI_EMR_MR9_Pos (9U) +#define EXTI_EMR_MR9_Pos (9U) #define EXTI_EMR_MR9_Msk (0x1U << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */ #define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */ -#define EXTI_EMR_MR10_Pos (10U) +#define EXTI_EMR_MR10_Pos (10U) #define EXTI_EMR_MR10_Msk (0x1U << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */ #define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */ -#define EXTI_EMR_MR11_Pos (11U) +#define EXTI_EMR_MR11_Pos (11U) #define EXTI_EMR_MR11_Msk (0x1U << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */ #define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */ -#define EXTI_EMR_MR12_Pos (12U) +#define EXTI_EMR_MR12_Pos (12U) #define EXTI_EMR_MR12_Msk (0x1U << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */ #define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */ -#define EXTI_EMR_MR13_Pos (13U) +#define EXTI_EMR_MR13_Pos (13U) #define EXTI_EMR_MR13_Msk (0x1U << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */ #define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */ -#define EXTI_EMR_MR14_Pos (14U) +#define EXTI_EMR_MR14_Pos (14U) #define EXTI_EMR_MR14_Msk (0x1U << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */ #define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */ -#define EXTI_EMR_MR15_Pos (15U) +#define EXTI_EMR_MR15_Pos (15U) #define EXTI_EMR_MR15_Msk (0x1U << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */ #define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */ -#define EXTI_EMR_MR16_Pos (16U) +#define EXTI_EMR_MR16_Pos (16U) #define EXTI_EMR_MR16_Msk (0x1U << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */ #define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */ -#define EXTI_EMR_MR17_Pos (17U) +#define EXTI_EMR_MR17_Pos (17U) #define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */ #define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */ -#define EXTI_EMR_MR18_Pos (18U) +#define EXTI_EMR_MR18_Pos (18U) #define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */ #define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */ -#define EXTI_EMR_MR19_Pos (19U) +#define EXTI_EMR_MR19_Pos (19U) #define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */ #define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */ @@ -3125,64 +3125,64 @@ typedef struct #define EXTI_EMR_EM19 EXTI_EMR_MR19 /****************** Bit definition for EXTI_RTSR register *******************/ -#define EXTI_RTSR_TR0_Pos (0U) +#define EXTI_RTSR_TR0_Pos (0U) #define EXTI_RTSR_TR0_Msk (0x1U << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */ #define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */ -#define EXTI_RTSR_TR1_Pos (1U) +#define EXTI_RTSR_TR1_Pos (1U) #define EXTI_RTSR_TR1_Msk (0x1U << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */ #define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */ -#define EXTI_RTSR_TR2_Pos (2U) +#define EXTI_RTSR_TR2_Pos (2U) #define EXTI_RTSR_TR2_Msk (0x1U << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */ #define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */ -#define EXTI_RTSR_TR3_Pos (3U) +#define EXTI_RTSR_TR3_Pos (3U) #define EXTI_RTSR_TR3_Msk (0x1U << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */ #define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */ -#define EXTI_RTSR_TR4_Pos (4U) +#define EXTI_RTSR_TR4_Pos (4U) #define EXTI_RTSR_TR4_Msk (0x1U << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */ #define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */ -#define EXTI_RTSR_TR5_Pos (5U) +#define EXTI_RTSR_TR5_Pos (5U) #define EXTI_RTSR_TR5_Msk (0x1U << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */ #define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */ -#define EXTI_RTSR_TR6_Pos (6U) +#define EXTI_RTSR_TR6_Pos (6U) #define EXTI_RTSR_TR6_Msk (0x1U << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */ #define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */ -#define EXTI_RTSR_TR7_Pos (7U) +#define EXTI_RTSR_TR7_Pos (7U) #define EXTI_RTSR_TR7_Msk (0x1U << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */ #define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */ -#define EXTI_RTSR_TR8_Pos (8U) +#define EXTI_RTSR_TR8_Pos (8U) #define EXTI_RTSR_TR8_Msk (0x1U << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */ #define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */ -#define EXTI_RTSR_TR9_Pos (9U) +#define EXTI_RTSR_TR9_Pos (9U) #define EXTI_RTSR_TR9_Msk (0x1U << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */ #define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */ -#define EXTI_RTSR_TR10_Pos (10U) +#define EXTI_RTSR_TR10_Pos (10U) #define EXTI_RTSR_TR10_Msk (0x1U << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */ #define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */ -#define EXTI_RTSR_TR11_Pos (11U) +#define EXTI_RTSR_TR11_Pos (11U) #define EXTI_RTSR_TR11_Msk (0x1U << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */ #define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */ -#define EXTI_RTSR_TR12_Pos (12U) +#define EXTI_RTSR_TR12_Pos (12U) #define EXTI_RTSR_TR12_Msk (0x1U << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */ #define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */ -#define EXTI_RTSR_TR13_Pos (13U) +#define EXTI_RTSR_TR13_Pos (13U) #define EXTI_RTSR_TR13_Msk (0x1U << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */ #define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */ -#define EXTI_RTSR_TR14_Pos (14U) +#define EXTI_RTSR_TR14_Pos (14U) #define EXTI_RTSR_TR14_Msk (0x1U << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */ #define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */ -#define EXTI_RTSR_TR15_Pos (15U) +#define EXTI_RTSR_TR15_Pos (15U) #define EXTI_RTSR_TR15_Msk (0x1U << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */ #define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */ -#define EXTI_RTSR_TR16_Pos (16U) +#define EXTI_RTSR_TR16_Pos (16U) #define EXTI_RTSR_TR16_Msk (0x1U << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */ #define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */ -#define EXTI_RTSR_TR17_Pos (17U) +#define EXTI_RTSR_TR17_Pos (17U) #define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */ #define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */ -#define EXTI_RTSR_TR18_Pos (18U) +#define EXTI_RTSR_TR18_Pos (18U) #define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */ #define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */ -#define EXTI_RTSR_TR19_Pos (19U) +#define EXTI_RTSR_TR19_Pos (19U) #define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */ #define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */ @@ -3209,64 +3209,64 @@ typedef struct #define EXTI_RTSR_RT19 EXTI_RTSR_TR19 /****************** Bit definition for EXTI_FTSR register *******************/ -#define EXTI_FTSR_TR0_Pos (0U) +#define EXTI_FTSR_TR0_Pos (0U) #define EXTI_FTSR_TR0_Msk (0x1U << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */ #define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */ -#define EXTI_FTSR_TR1_Pos (1U) +#define EXTI_FTSR_TR1_Pos (1U) #define EXTI_FTSR_TR1_Msk (0x1U << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */ #define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */ -#define EXTI_FTSR_TR2_Pos (2U) +#define EXTI_FTSR_TR2_Pos (2U) #define EXTI_FTSR_TR2_Msk (0x1U << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */ #define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */ -#define EXTI_FTSR_TR3_Pos (3U) +#define EXTI_FTSR_TR3_Pos (3U) #define EXTI_FTSR_TR3_Msk (0x1U << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */ #define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */ -#define EXTI_FTSR_TR4_Pos (4U) +#define EXTI_FTSR_TR4_Pos (4U) #define EXTI_FTSR_TR4_Msk (0x1U << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */ #define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */ -#define EXTI_FTSR_TR5_Pos (5U) +#define EXTI_FTSR_TR5_Pos (5U) #define EXTI_FTSR_TR5_Msk (0x1U << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */ #define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */ -#define EXTI_FTSR_TR6_Pos (6U) +#define EXTI_FTSR_TR6_Pos (6U) #define EXTI_FTSR_TR6_Msk (0x1U << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */ #define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */ -#define EXTI_FTSR_TR7_Pos (7U) +#define EXTI_FTSR_TR7_Pos (7U) #define EXTI_FTSR_TR7_Msk (0x1U << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */ #define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */ -#define EXTI_FTSR_TR8_Pos (8U) +#define EXTI_FTSR_TR8_Pos (8U) #define EXTI_FTSR_TR8_Msk (0x1U << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */ #define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */ -#define EXTI_FTSR_TR9_Pos (9U) +#define EXTI_FTSR_TR9_Pos (9U) #define EXTI_FTSR_TR9_Msk (0x1U << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */ #define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */ -#define EXTI_FTSR_TR10_Pos (10U) +#define EXTI_FTSR_TR10_Pos (10U) #define EXTI_FTSR_TR10_Msk (0x1U << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */ #define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */ -#define EXTI_FTSR_TR11_Pos (11U) +#define EXTI_FTSR_TR11_Pos (11U) #define EXTI_FTSR_TR11_Msk (0x1U << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */ #define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */ -#define EXTI_FTSR_TR12_Pos (12U) +#define EXTI_FTSR_TR12_Pos (12U) #define EXTI_FTSR_TR12_Msk (0x1U << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */ #define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */ -#define EXTI_FTSR_TR13_Pos (13U) +#define EXTI_FTSR_TR13_Pos (13U) #define EXTI_FTSR_TR13_Msk (0x1U << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */ #define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */ -#define EXTI_FTSR_TR14_Pos (14U) +#define EXTI_FTSR_TR14_Pos (14U) #define EXTI_FTSR_TR14_Msk (0x1U << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */ #define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */ -#define EXTI_FTSR_TR15_Pos (15U) +#define EXTI_FTSR_TR15_Pos (15U) #define EXTI_FTSR_TR15_Msk (0x1U << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */ #define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */ -#define EXTI_FTSR_TR16_Pos (16U) +#define EXTI_FTSR_TR16_Pos (16U) #define EXTI_FTSR_TR16_Msk (0x1U << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */ #define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */ -#define EXTI_FTSR_TR17_Pos (17U) +#define EXTI_FTSR_TR17_Pos (17U) #define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */ #define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */ -#define EXTI_FTSR_TR18_Pos (18U) +#define EXTI_FTSR_TR18_Pos (18U) #define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */ #define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */ -#define EXTI_FTSR_TR19_Pos (19U) +#define EXTI_FTSR_TR19_Pos (19U) #define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */ #define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */ @@ -3293,64 +3293,64 @@ typedef struct #define EXTI_FTSR_FT19 EXTI_FTSR_TR19 /****************** Bit definition for EXTI_SWIER register ******************/ -#define EXTI_SWIER_SWIER0_Pos (0U) +#define EXTI_SWIER_SWIER0_Pos (0U) #define EXTI_SWIER_SWIER0_Msk (0x1U << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */ #define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */ -#define EXTI_SWIER_SWIER1_Pos (1U) +#define EXTI_SWIER_SWIER1_Pos (1U) #define EXTI_SWIER_SWIER1_Msk (0x1U << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */ #define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */ -#define EXTI_SWIER_SWIER2_Pos (2U) +#define EXTI_SWIER_SWIER2_Pos (2U) #define EXTI_SWIER_SWIER2_Msk (0x1U << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */ #define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */ -#define EXTI_SWIER_SWIER3_Pos (3U) +#define EXTI_SWIER_SWIER3_Pos (3U) #define EXTI_SWIER_SWIER3_Msk (0x1U << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */ #define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */ -#define EXTI_SWIER_SWIER4_Pos (4U) +#define EXTI_SWIER_SWIER4_Pos (4U) #define EXTI_SWIER_SWIER4_Msk (0x1U << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */ #define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */ -#define EXTI_SWIER_SWIER5_Pos (5U) +#define EXTI_SWIER_SWIER5_Pos (5U) #define EXTI_SWIER_SWIER5_Msk (0x1U << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */ #define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */ -#define EXTI_SWIER_SWIER6_Pos (6U) +#define EXTI_SWIER_SWIER6_Pos (6U) #define EXTI_SWIER_SWIER6_Msk (0x1U << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */ #define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */ -#define EXTI_SWIER_SWIER7_Pos (7U) +#define EXTI_SWIER_SWIER7_Pos (7U) #define EXTI_SWIER_SWIER7_Msk (0x1U << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */ #define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */ -#define EXTI_SWIER_SWIER8_Pos (8U) +#define EXTI_SWIER_SWIER8_Pos (8U) #define EXTI_SWIER_SWIER8_Msk (0x1U << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */ #define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */ -#define EXTI_SWIER_SWIER9_Pos (9U) +#define EXTI_SWIER_SWIER9_Pos (9U) #define EXTI_SWIER_SWIER9_Msk (0x1U << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */ #define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */ -#define EXTI_SWIER_SWIER10_Pos (10U) +#define EXTI_SWIER_SWIER10_Pos (10U) #define EXTI_SWIER_SWIER10_Msk (0x1U << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */ #define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */ -#define EXTI_SWIER_SWIER11_Pos (11U) +#define EXTI_SWIER_SWIER11_Pos (11U) #define EXTI_SWIER_SWIER11_Msk (0x1U << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */ #define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */ -#define EXTI_SWIER_SWIER12_Pos (12U) +#define EXTI_SWIER_SWIER12_Pos (12U) #define EXTI_SWIER_SWIER12_Msk (0x1U << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */ #define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */ -#define EXTI_SWIER_SWIER13_Pos (13U) +#define EXTI_SWIER_SWIER13_Pos (13U) #define EXTI_SWIER_SWIER13_Msk (0x1U << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */ #define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */ -#define EXTI_SWIER_SWIER14_Pos (14U) +#define EXTI_SWIER_SWIER14_Pos (14U) #define EXTI_SWIER_SWIER14_Msk (0x1U << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */ #define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */ -#define EXTI_SWIER_SWIER15_Pos (15U) +#define EXTI_SWIER_SWIER15_Pos (15U) #define EXTI_SWIER_SWIER15_Msk (0x1U << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */ #define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */ -#define EXTI_SWIER_SWIER16_Pos (16U) +#define EXTI_SWIER_SWIER16_Pos (16U) #define EXTI_SWIER_SWIER16_Msk (0x1U << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */ #define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */ -#define EXTI_SWIER_SWIER17_Pos (17U) +#define EXTI_SWIER_SWIER17_Pos (17U) #define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */ #define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */ -#define EXTI_SWIER_SWIER18_Pos (18U) +#define EXTI_SWIER_SWIER18_Pos (18U) #define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */ #define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */ -#define EXTI_SWIER_SWIER19_Pos (19U) +#define EXTI_SWIER_SWIER19_Pos (19U) #define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */ #define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */ @@ -3377,64 +3377,64 @@ typedef struct #define EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19 /******************* Bit definition for EXTI_PR register ********************/ -#define EXTI_PR_PR0_Pos (0U) +#define EXTI_PR_PR0_Pos (0U) #define EXTI_PR_PR0_Msk (0x1U << EXTI_PR_PR0_Pos) /*!< 0x00000001 */ #define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */ -#define EXTI_PR_PR1_Pos (1U) +#define EXTI_PR_PR1_Pos (1U) #define EXTI_PR_PR1_Msk (0x1U << EXTI_PR_PR1_Pos) /*!< 0x00000002 */ #define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */ -#define EXTI_PR_PR2_Pos (2U) +#define EXTI_PR_PR2_Pos (2U) #define EXTI_PR_PR2_Msk (0x1U << EXTI_PR_PR2_Pos) /*!< 0x00000004 */ #define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */ -#define EXTI_PR_PR3_Pos (3U) +#define EXTI_PR_PR3_Pos (3U) #define EXTI_PR_PR3_Msk (0x1U << EXTI_PR_PR3_Pos) /*!< 0x00000008 */ #define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */ -#define EXTI_PR_PR4_Pos (4U) +#define EXTI_PR_PR4_Pos (4U) #define EXTI_PR_PR4_Msk (0x1U << EXTI_PR_PR4_Pos) /*!< 0x00000010 */ #define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */ -#define EXTI_PR_PR5_Pos (5U) +#define EXTI_PR_PR5_Pos (5U) #define EXTI_PR_PR5_Msk (0x1U << EXTI_PR_PR5_Pos) /*!< 0x00000020 */ #define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */ -#define EXTI_PR_PR6_Pos (6U) +#define EXTI_PR_PR6_Pos (6U) #define EXTI_PR_PR6_Msk (0x1U << EXTI_PR_PR6_Pos) /*!< 0x00000040 */ #define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */ -#define EXTI_PR_PR7_Pos (7U) +#define EXTI_PR_PR7_Pos (7U) #define EXTI_PR_PR7_Msk (0x1U << EXTI_PR_PR7_Pos) /*!< 0x00000080 */ #define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */ -#define EXTI_PR_PR8_Pos (8U) +#define EXTI_PR_PR8_Pos (8U) #define EXTI_PR_PR8_Msk (0x1U << EXTI_PR_PR8_Pos) /*!< 0x00000100 */ #define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */ -#define EXTI_PR_PR9_Pos (9U) +#define EXTI_PR_PR9_Pos (9U) #define EXTI_PR_PR9_Msk (0x1U << EXTI_PR_PR9_Pos) /*!< 0x00000200 */ #define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */ -#define EXTI_PR_PR10_Pos (10U) +#define EXTI_PR_PR10_Pos (10U) #define EXTI_PR_PR10_Msk (0x1U << EXTI_PR_PR10_Pos) /*!< 0x00000400 */ #define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */ -#define EXTI_PR_PR11_Pos (11U) +#define EXTI_PR_PR11_Pos (11U) #define EXTI_PR_PR11_Msk (0x1U << EXTI_PR_PR11_Pos) /*!< 0x00000800 */ #define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */ -#define EXTI_PR_PR12_Pos (12U) +#define EXTI_PR_PR12_Pos (12U) #define EXTI_PR_PR12_Msk (0x1U << EXTI_PR_PR12_Pos) /*!< 0x00001000 */ #define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */ -#define EXTI_PR_PR13_Pos (13U) +#define EXTI_PR_PR13_Pos (13U) #define EXTI_PR_PR13_Msk (0x1U << EXTI_PR_PR13_Pos) /*!< 0x00002000 */ #define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */ -#define EXTI_PR_PR14_Pos (14U) +#define EXTI_PR_PR14_Pos (14U) #define EXTI_PR_PR14_Msk (0x1U << EXTI_PR_PR14_Pos) /*!< 0x00004000 */ #define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */ -#define EXTI_PR_PR15_Pos (15U) +#define EXTI_PR_PR15_Pos (15U) #define EXTI_PR_PR15_Msk (0x1U << EXTI_PR_PR15_Pos) /*!< 0x00008000 */ #define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */ -#define EXTI_PR_PR16_Pos (16U) +#define EXTI_PR_PR16_Pos (16U) #define EXTI_PR_PR16_Msk (0x1U << EXTI_PR_PR16_Pos) /*!< 0x00010000 */ #define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */ -#define EXTI_PR_PR17_Pos (17U) +#define EXTI_PR_PR17_Pos (17U) #define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */ #define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */ -#define EXTI_PR_PR18_Pos (18U) +#define EXTI_PR_PR18_Pos (18U) #define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */ #define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */ -#define EXTI_PR_PR19_Pos (19U) +#define EXTI_PR_PR19_Pos (19U) #define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */ #define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */ @@ -3467,237 +3467,237 @@ typedef struct /******************************************************************************/ /******************* Bit definition for DMA_ISR register ********************/ -#define DMA_ISR_GIF1_Pos (0U) +#define DMA_ISR_GIF1_Pos (0U) #define DMA_ISR_GIF1_Msk (0x1U << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */ #define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */ -#define DMA_ISR_TCIF1_Pos (1U) +#define DMA_ISR_TCIF1_Pos (1U) #define DMA_ISR_TCIF1_Msk (0x1U << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */ #define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */ -#define DMA_ISR_HTIF1_Pos (2U) +#define DMA_ISR_HTIF1_Pos (2U) #define DMA_ISR_HTIF1_Msk (0x1U << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */ #define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */ -#define DMA_ISR_TEIF1_Pos (3U) +#define DMA_ISR_TEIF1_Pos (3U) #define DMA_ISR_TEIF1_Msk (0x1U << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */ #define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */ -#define DMA_ISR_GIF2_Pos (4U) +#define DMA_ISR_GIF2_Pos (4U) #define DMA_ISR_GIF2_Msk (0x1U << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */ #define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */ -#define DMA_ISR_TCIF2_Pos (5U) +#define DMA_ISR_TCIF2_Pos (5U) #define DMA_ISR_TCIF2_Msk (0x1U << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */ #define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */ -#define DMA_ISR_HTIF2_Pos (6U) +#define DMA_ISR_HTIF2_Pos (6U) #define DMA_ISR_HTIF2_Msk (0x1U << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */ #define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */ -#define DMA_ISR_TEIF2_Pos (7U) +#define DMA_ISR_TEIF2_Pos (7U) #define DMA_ISR_TEIF2_Msk (0x1U << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */ #define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */ -#define DMA_ISR_GIF3_Pos (8U) +#define DMA_ISR_GIF3_Pos (8U) #define DMA_ISR_GIF3_Msk (0x1U << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */ #define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */ -#define DMA_ISR_TCIF3_Pos (9U) +#define DMA_ISR_TCIF3_Pos (9U) #define DMA_ISR_TCIF3_Msk (0x1U << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */ #define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */ -#define DMA_ISR_HTIF3_Pos (10U) +#define DMA_ISR_HTIF3_Pos (10U) #define DMA_ISR_HTIF3_Msk (0x1U << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */ #define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */ -#define DMA_ISR_TEIF3_Pos (11U) +#define DMA_ISR_TEIF3_Pos (11U) #define DMA_ISR_TEIF3_Msk (0x1U << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */ #define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */ -#define DMA_ISR_GIF4_Pos (12U) +#define DMA_ISR_GIF4_Pos (12U) #define DMA_ISR_GIF4_Msk (0x1U << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */ #define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */ -#define DMA_ISR_TCIF4_Pos (13U) +#define DMA_ISR_TCIF4_Pos (13U) #define DMA_ISR_TCIF4_Msk (0x1U << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */ #define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */ -#define DMA_ISR_HTIF4_Pos (14U) +#define DMA_ISR_HTIF4_Pos (14U) #define DMA_ISR_HTIF4_Msk (0x1U << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */ #define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */ -#define DMA_ISR_TEIF4_Pos (15U) +#define DMA_ISR_TEIF4_Pos (15U) #define DMA_ISR_TEIF4_Msk (0x1U << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */ #define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */ -#define DMA_ISR_GIF5_Pos (16U) +#define DMA_ISR_GIF5_Pos (16U) #define DMA_ISR_GIF5_Msk (0x1U << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */ #define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */ -#define DMA_ISR_TCIF5_Pos (17U) +#define DMA_ISR_TCIF5_Pos (17U) #define DMA_ISR_TCIF5_Msk (0x1U << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */ #define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */ -#define DMA_ISR_HTIF5_Pos (18U) +#define DMA_ISR_HTIF5_Pos (18U) #define DMA_ISR_HTIF5_Msk (0x1U << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */ #define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */ -#define DMA_ISR_TEIF5_Pos (19U) +#define DMA_ISR_TEIF5_Pos (19U) #define DMA_ISR_TEIF5_Msk (0x1U << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */ #define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */ -#define DMA_ISR_GIF6_Pos (20U) +#define DMA_ISR_GIF6_Pos (20U) #define DMA_ISR_GIF6_Msk (0x1U << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */ #define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */ -#define DMA_ISR_TCIF6_Pos (21U) +#define DMA_ISR_TCIF6_Pos (21U) #define DMA_ISR_TCIF6_Msk (0x1U << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */ #define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */ -#define DMA_ISR_HTIF6_Pos (22U) +#define DMA_ISR_HTIF6_Pos (22U) #define DMA_ISR_HTIF6_Msk (0x1U << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */ #define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */ -#define DMA_ISR_TEIF6_Pos (23U) +#define DMA_ISR_TEIF6_Pos (23U) #define DMA_ISR_TEIF6_Msk (0x1U << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */ #define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */ -#define DMA_ISR_GIF7_Pos (24U) +#define DMA_ISR_GIF7_Pos (24U) #define DMA_ISR_GIF7_Msk (0x1U << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */ #define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */ -#define DMA_ISR_TCIF7_Pos (25U) +#define DMA_ISR_TCIF7_Pos (25U) #define DMA_ISR_TCIF7_Msk (0x1U << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */ #define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */ -#define DMA_ISR_HTIF7_Pos (26U) +#define DMA_ISR_HTIF7_Pos (26U) #define DMA_ISR_HTIF7_Msk (0x1U << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */ #define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */ -#define DMA_ISR_TEIF7_Pos (27U) +#define DMA_ISR_TEIF7_Pos (27U) #define DMA_ISR_TEIF7_Msk (0x1U << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */ #define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */ /******************* Bit definition for DMA_IFCR register *******************/ -#define DMA_IFCR_CGIF1_Pos (0U) +#define DMA_IFCR_CGIF1_Pos (0U) #define DMA_IFCR_CGIF1_Msk (0x1U << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */ #define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */ -#define DMA_IFCR_CTCIF1_Pos (1U) +#define DMA_IFCR_CTCIF1_Pos (1U) #define DMA_IFCR_CTCIF1_Msk (0x1U << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */ #define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */ -#define DMA_IFCR_CHTIF1_Pos (2U) +#define DMA_IFCR_CHTIF1_Pos (2U) #define DMA_IFCR_CHTIF1_Msk (0x1U << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */ #define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */ -#define DMA_IFCR_CTEIF1_Pos (3U) +#define DMA_IFCR_CTEIF1_Pos (3U) #define DMA_IFCR_CTEIF1_Msk (0x1U << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */ #define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */ -#define DMA_IFCR_CGIF2_Pos (4U) +#define DMA_IFCR_CGIF2_Pos (4U) #define DMA_IFCR_CGIF2_Msk (0x1U << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */ #define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */ -#define DMA_IFCR_CTCIF2_Pos (5U) +#define DMA_IFCR_CTCIF2_Pos (5U) #define DMA_IFCR_CTCIF2_Msk (0x1U << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */ #define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */ -#define DMA_IFCR_CHTIF2_Pos (6U) +#define DMA_IFCR_CHTIF2_Pos (6U) #define DMA_IFCR_CHTIF2_Msk (0x1U << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */ #define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */ -#define DMA_IFCR_CTEIF2_Pos (7U) +#define DMA_IFCR_CTEIF2_Pos (7U) #define DMA_IFCR_CTEIF2_Msk (0x1U << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */ #define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */ -#define DMA_IFCR_CGIF3_Pos (8U) +#define DMA_IFCR_CGIF3_Pos (8U) #define DMA_IFCR_CGIF3_Msk (0x1U << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */ #define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */ -#define DMA_IFCR_CTCIF3_Pos (9U) +#define DMA_IFCR_CTCIF3_Pos (9U) #define DMA_IFCR_CTCIF3_Msk (0x1U << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */ #define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */ -#define DMA_IFCR_CHTIF3_Pos (10U) +#define DMA_IFCR_CHTIF3_Pos (10U) #define DMA_IFCR_CHTIF3_Msk (0x1U << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */ #define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */ -#define DMA_IFCR_CTEIF3_Pos (11U) +#define DMA_IFCR_CTEIF3_Pos (11U) #define DMA_IFCR_CTEIF3_Msk (0x1U << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */ #define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */ -#define DMA_IFCR_CGIF4_Pos (12U) +#define DMA_IFCR_CGIF4_Pos (12U) #define DMA_IFCR_CGIF4_Msk (0x1U << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */ #define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */ -#define DMA_IFCR_CTCIF4_Pos (13U) +#define DMA_IFCR_CTCIF4_Pos (13U) #define DMA_IFCR_CTCIF4_Msk (0x1U << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */ #define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */ -#define DMA_IFCR_CHTIF4_Pos (14U) +#define DMA_IFCR_CHTIF4_Pos (14U) #define DMA_IFCR_CHTIF4_Msk (0x1U << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */ #define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */ -#define DMA_IFCR_CTEIF4_Pos (15U) +#define DMA_IFCR_CTEIF4_Pos (15U) #define DMA_IFCR_CTEIF4_Msk (0x1U << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */ #define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */ -#define DMA_IFCR_CGIF5_Pos (16U) +#define DMA_IFCR_CGIF5_Pos (16U) #define DMA_IFCR_CGIF5_Msk (0x1U << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */ #define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */ -#define DMA_IFCR_CTCIF5_Pos (17U) +#define DMA_IFCR_CTCIF5_Pos (17U) #define DMA_IFCR_CTCIF5_Msk (0x1U << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */ #define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */ -#define DMA_IFCR_CHTIF5_Pos (18U) +#define DMA_IFCR_CHTIF5_Pos (18U) #define DMA_IFCR_CHTIF5_Msk (0x1U << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */ #define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */ -#define DMA_IFCR_CTEIF5_Pos (19U) +#define DMA_IFCR_CTEIF5_Pos (19U) #define DMA_IFCR_CTEIF5_Msk (0x1U << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */ #define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */ -#define DMA_IFCR_CGIF6_Pos (20U) +#define DMA_IFCR_CGIF6_Pos (20U) #define DMA_IFCR_CGIF6_Msk (0x1U << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */ #define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */ -#define DMA_IFCR_CTCIF6_Pos (21U) +#define DMA_IFCR_CTCIF6_Pos (21U) #define DMA_IFCR_CTCIF6_Msk (0x1U << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */ #define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */ -#define DMA_IFCR_CHTIF6_Pos (22U) +#define DMA_IFCR_CHTIF6_Pos (22U) #define DMA_IFCR_CHTIF6_Msk (0x1U << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */ #define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */ -#define DMA_IFCR_CTEIF6_Pos (23U) +#define DMA_IFCR_CTEIF6_Pos (23U) #define DMA_IFCR_CTEIF6_Msk (0x1U << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */ #define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */ -#define DMA_IFCR_CGIF7_Pos (24U) +#define DMA_IFCR_CGIF7_Pos (24U) #define DMA_IFCR_CGIF7_Msk (0x1U << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */ #define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */ -#define DMA_IFCR_CTCIF7_Pos (25U) +#define DMA_IFCR_CTCIF7_Pos (25U) #define DMA_IFCR_CTCIF7_Msk (0x1U << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */ #define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */ -#define DMA_IFCR_CHTIF7_Pos (26U) +#define DMA_IFCR_CHTIF7_Pos (26U) #define DMA_IFCR_CHTIF7_Msk (0x1U << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */ #define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */ -#define DMA_IFCR_CTEIF7_Pos (27U) +#define DMA_IFCR_CTEIF7_Pos (27U) #define DMA_IFCR_CTEIF7_Msk (0x1U << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */ #define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */ /******************* Bit definition for DMA_CCR register *******************/ -#define DMA_CCR_EN_Pos (0U) +#define DMA_CCR_EN_Pos (0U) #define DMA_CCR_EN_Msk (0x1U << DMA_CCR_EN_Pos) /*!< 0x00000001 */ #define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */ -#define DMA_CCR_TCIE_Pos (1U) +#define DMA_CCR_TCIE_Pos (1U) #define DMA_CCR_TCIE_Msk (0x1U << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */ #define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */ -#define DMA_CCR_HTIE_Pos (2U) +#define DMA_CCR_HTIE_Pos (2U) #define DMA_CCR_HTIE_Msk (0x1U << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */ #define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */ -#define DMA_CCR_TEIE_Pos (3U) +#define DMA_CCR_TEIE_Pos (3U) #define DMA_CCR_TEIE_Msk (0x1U << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */ #define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */ -#define DMA_CCR_DIR_Pos (4U) +#define DMA_CCR_DIR_Pos (4U) #define DMA_CCR_DIR_Msk (0x1U << DMA_CCR_DIR_Pos) /*!< 0x00000010 */ #define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */ -#define DMA_CCR_CIRC_Pos (5U) +#define DMA_CCR_CIRC_Pos (5U) #define DMA_CCR_CIRC_Msk (0x1U << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */ #define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */ -#define DMA_CCR_PINC_Pos (6U) +#define DMA_CCR_PINC_Pos (6U) #define DMA_CCR_PINC_Msk (0x1U << DMA_CCR_PINC_Pos) /*!< 0x00000040 */ #define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */ -#define DMA_CCR_MINC_Pos (7U) +#define DMA_CCR_MINC_Pos (7U) #define DMA_CCR_MINC_Msk (0x1U << DMA_CCR_MINC_Pos) /*!< 0x00000080 */ #define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */ -#define DMA_CCR_PSIZE_Pos (8U) +#define DMA_CCR_PSIZE_Pos (8U) #define DMA_CCR_PSIZE_Msk (0x3U << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */ #define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */ #define DMA_CCR_PSIZE_0 (0x1U << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */ #define DMA_CCR_PSIZE_1 (0x2U << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */ -#define DMA_CCR_MSIZE_Pos (10U) +#define DMA_CCR_MSIZE_Pos (10U) #define DMA_CCR_MSIZE_Msk (0x3U << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */ #define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */ #define DMA_CCR_MSIZE_0 (0x1U << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */ #define DMA_CCR_MSIZE_1 (0x2U << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */ -#define DMA_CCR_PL_Pos (12U) +#define DMA_CCR_PL_Pos (12U) #define DMA_CCR_PL_Msk (0x3U << DMA_CCR_PL_Pos) /*!< 0x00003000 */ #define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level) */ #define DMA_CCR_PL_0 (0x1U << DMA_CCR_PL_Pos) /*!< 0x00001000 */ #define DMA_CCR_PL_1 (0x2U << DMA_CCR_PL_Pos) /*!< 0x00002000 */ -#define DMA_CCR_MEM2MEM_Pos (14U) +#define DMA_CCR_MEM2MEM_Pos (14U) #define DMA_CCR_MEM2MEM_Msk (0x1U << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */ #define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */ /****************** Bit definition for DMA_CNDTR register ******************/ -#define DMA_CNDTR_NDT_Pos (0U) +#define DMA_CNDTR_NDT_Pos (0U) #define DMA_CNDTR_NDT_Msk (0xFFFFU << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */ #define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */ /****************** Bit definition for DMA_CPAR register *******************/ -#define DMA_CPAR_PA_Pos (0U) +#define DMA_CPAR_PA_Pos (0U) #define DMA_CPAR_PA_Msk (0xFFFFFFFFU << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */ #define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */ /****************** Bit definition for DMA_CMAR register *******************/ -#define DMA_CMAR_MA_Pos (0U) +#define DMA_CMAR_MA_Pos (0U) #define DMA_CMAR_MA_Msk (0xFFFFFFFFU << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */ #define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */ @@ -3713,19 +3713,19 @@ typedef struct #define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ /******************** Bit definition for ADC_SR register ********************/ -#define ADC_SR_AWD_Pos (0U) +#define ADC_SR_AWD_Pos (0U) #define ADC_SR_AWD_Msk (0x1U << ADC_SR_AWD_Pos) /*!< 0x00000001 */ #define ADC_SR_AWD ADC_SR_AWD_Msk /*!< ADC analog watchdog 1 flag */ -#define ADC_SR_EOS_Pos (1U) +#define ADC_SR_EOS_Pos (1U) #define ADC_SR_EOS_Msk (0x1U << ADC_SR_EOS_Pos) /*!< 0x00000002 */ #define ADC_SR_EOS ADC_SR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ -#define ADC_SR_JEOS_Pos (2U) +#define ADC_SR_JEOS_Pos (2U) #define ADC_SR_JEOS_Msk (0x1U << ADC_SR_JEOS_Pos) /*!< 0x00000004 */ #define ADC_SR_JEOS ADC_SR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ -#define ADC_SR_JSTRT_Pos (3U) +#define ADC_SR_JSTRT_Pos (3U) #define ADC_SR_JSTRT_Msk (0x1U << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */ #define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!< ADC group injected conversion start flag */ -#define ADC_SR_STRT_Pos (4U) +#define ADC_SR_STRT_Pos (4U) #define ADC_SR_STRT_Msk (0x1U << ADC_SR_STRT_Pos) /*!< 0x00000010 */ #define ADC_SR_STRT ADC_SR_STRT_Msk /*!< ADC group regular conversion start flag */ @@ -3734,7 +3734,7 @@ typedef struct #define ADC_SR_JEOC (ADC_SR_JEOS) /******************* Bit definition for ADC_CR1 register ********************/ -#define ADC_CR1_AWDCH_Pos (0U) +#define ADC_CR1_AWDCH_Pos (0U) #define ADC_CR1_AWDCH_Msk (0x1FU << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */ #define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ #define ADC_CR1_AWDCH_0 (0x01U << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */ @@ -3743,39 +3743,39 @@ typedef struct #define ADC_CR1_AWDCH_3 (0x08U << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */ #define ADC_CR1_AWDCH_4 (0x10U << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */ -#define ADC_CR1_EOSIE_Pos (5U) +#define ADC_CR1_EOSIE_Pos (5U) #define ADC_CR1_EOSIE_Msk (0x1U << ADC_CR1_EOSIE_Pos) /*!< 0x00000020 */ #define ADC_CR1_EOSIE ADC_CR1_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ -#define ADC_CR1_AWDIE_Pos (6U) +#define ADC_CR1_AWDIE_Pos (6U) #define ADC_CR1_AWDIE_Msk (0x1U << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */ #define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!< ADC analog watchdog 1 interrupt */ -#define ADC_CR1_JEOSIE_Pos (7U) +#define ADC_CR1_JEOSIE_Pos (7U) #define ADC_CR1_JEOSIE_Msk (0x1U << ADC_CR1_JEOSIE_Pos) /*!< 0x00000080 */ #define ADC_CR1_JEOSIE ADC_CR1_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ -#define ADC_CR1_SCAN_Pos (8U) +#define ADC_CR1_SCAN_Pos (8U) #define ADC_CR1_SCAN_Msk (0x1U << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */ #define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!< ADC scan mode */ -#define ADC_CR1_AWDSGL_Pos (9U) +#define ADC_CR1_AWDSGL_Pos (9U) #define ADC_CR1_AWDSGL_Msk (0x1U << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */ #define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ -#define ADC_CR1_JAUTO_Pos (10U) +#define ADC_CR1_JAUTO_Pos (10U) #define ADC_CR1_JAUTO_Msk (0x1U << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */ #define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ -#define ADC_CR1_DISCEN_Pos (11U) +#define ADC_CR1_DISCEN_Pos (11U) #define ADC_CR1_DISCEN_Msk (0x1U << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */ #define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ -#define ADC_CR1_JDISCEN_Pos (12U) +#define ADC_CR1_JDISCEN_Pos (12U) #define ADC_CR1_JDISCEN_Msk (0x1U << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */ #define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */ -#define ADC_CR1_DISCNUM_Pos (13U) +#define ADC_CR1_DISCNUM_Pos (13U) #define ADC_CR1_DISCNUM_Msk (0x7U << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */ #define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */ #define ADC_CR1_DISCNUM_0 (0x1U << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */ #define ADC_CR1_DISCNUM_1 (0x2U << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */ #define ADC_CR1_DISCNUM_2 (0x4U << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */ -#define ADC_CR1_DUALMOD_Pos (16U) +#define ADC_CR1_DUALMOD_Pos (16U) #define ADC_CR1_DUALMOD_Msk (0xFU << ADC_CR1_DUALMOD_Pos) /*!< 0x000F0000 */ #define ADC_CR1_DUALMOD ADC_CR1_DUALMOD_Msk /*!< ADC multimode mode selection */ #define ADC_CR1_DUALMOD_0 (0x1U << ADC_CR1_DUALMOD_Pos) /*!< 0x00010000 */ @@ -3783,10 +3783,10 @@ typedef struct #define ADC_CR1_DUALMOD_2 (0x4U << ADC_CR1_DUALMOD_Pos) /*!< 0x00040000 */ #define ADC_CR1_DUALMOD_3 (0x8U << ADC_CR1_DUALMOD_Pos) /*!< 0x00080000 */ -#define ADC_CR1_JAWDEN_Pos (22U) +#define ADC_CR1_JAWDEN_Pos (22U) #define ADC_CR1_JAWDEN_Msk (0x1U << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */ #define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ -#define ADC_CR1_AWDEN_Pos (23U) +#define ADC_CR1_AWDEN_Pos (23U) #define ADC_CR1_AWDEN_Msk (0x1U << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */ #define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ @@ -3795,107 +3795,107 @@ typedef struct #define ADC_CR1_JEOCIE (ADC_CR1_JEOSIE) /******************* Bit definition for ADC_CR2 register ********************/ -#define ADC_CR2_ADON_Pos (0U) +#define ADC_CR2_ADON_Pos (0U) #define ADC_CR2_ADON_Msk (0x1U << ADC_CR2_ADON_Pos) /*!< 0x00000001 */ #define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!< ADC enable */ -#define ADC_CR2_CONT_Pos (1U) +#define ADC_CR2_CONT_Pos (1U) #define ADC_CR2_CONT_Msk (0x1U << ADC_CR2_CONT_Pos) /*!< 0x00000002 */ #define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!< ADC group regular continuous conversion mode */ -#define ADC_CR2_CAL_Pos (2U) +#define ADC_CR2_CAL_Pos (2U) #define ADC_CR2_CAL_Msk (0x1U << ADC_CR2_CAL_Pos) /*!< 0x00000004 */ #define ADC_CR2_CAL ADC_CR2_CAL_Msk /*!< ADC calibration start */ -#define ADC_CR2_RSTCAL_Pos (3U) +#define ADC_CR2_RSTCAL_Pos (3U) #define ADC_CR2_RSTCAL_Msk (0x1U << ADC_CR2_RSTCAL_Pos) /*!< 0x00000008 */ #define ADC_CR2_RSTCAL ADC_CR2_RSTCAL_Msk /*!< ADC calibration reset */ -#define ADC_CR2_DMA_Pos (8U) +#define ADC_CR2_DMA_Pos (8U) #define ADC_CR2_DMA_Msk (0x1U << ADC_CR2_DMA_Pos) /*!< 0x00000100 */ #define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!< ADC DMA transfer enable */ -#define ADC_CR2_ALIGN_Pos (11U) +#define ADC_CR2_ALIGN_Pos (11U) #define ADC_CR2_ALIGN_Msk (0x1U << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */ #define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignement */ -#define ADC_CR2_JEXTSEL_Pos (12U) +#define ADC_CR2_JEXTSEL_Pos (12U) #define ADC_CR2_JEXTSEL_Msk (0x7U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00007000 */ #define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!< ADC group injected external trigger source */ #define ADC_CR2_JEXTSEL_0 (0x1U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00001000 */ #define ADC_CR2_JEXTSEL_1 (0x2U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00002000 */ #define ADC_CR2_JEXTSEL_2 (0x4U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00004000 */ -#define ADC_CR2_JEXTTRIG_Pos (15U) +#define ADC_CR2_JEXTTRIG_Pos (15U) #define ADC_CR2_JEXTTRIG_Msk (0x1U << ADC_CR2_JEXTTRIG_Pos) /*!< 0x00008000 */ #define ADC_CR2_JEXTTRIG ADC_CR2_JEXTTRIG_Msk /*!< ADC group injected external trigger enable */ -#define ADC_CR2_EXTSEL_Pos (17U) +#define ADC_CR2_EXTSEL_Pos (17U) #define ADC_CR2_EXTSEL_Msk (0x7U << ADC_CR2_EXTSEL_Pos) /*!< 0x000E0000 */ #define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!< ADC group regular external trigger source */ #define ADC_CR2_EXTSEL_0 (0x1U << ADC_CR2_EXTSEL_Pos) /*!< 0x00020000 */ #define ADC_CR2_EXTSEL_1 (0x2U << ADC_CR2_EXTSEL_Pos) /*!< 0x00040000 */ #define ADC_CR2_EXTSEL_2 (0x4U << ADC_CR2_EXTSEL_Pos) /*!< 0x00080000 */ -#define ADC_CR2_EXTTRIG_Pos (20U) +#define ADC_CR2_EXTTRIG_Pos (20U) #define ADC_CR2_EXTTRIG_Msk (0x1U << ADC_CR2_EXTTRIG_Pos) /*!< 0x00100000 */ #define ADC_CR2_EXTTRIG ADC_CR2_EXTTRIG_Msk /*!< ADC group regular external trigger enable */ -#define ADC_CR2_JSWSTART_Pos (21U) +#define ADC_CR2_JSWSTART_Pos (21U) #define ADC_CR2_JSWSTART_Msk (0x1U << ADC_CR2_JSWSTART_Pos) /*!< 0x00200000 */ #define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!< ADC group injected conversion start */ -#define ADC_CR2_SWSTART_Pos (22U) +#define ADC_CR2_SWSTART_Pos (22U) #define ADC_CR2_SWSTART_Msk (0x1U << ADC_CR2_SWSTART_Pos) /*!< 0x00400000 */ #define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!< ADC group regular conversion start */ -#define ADC_CR2_TSVREFE_Pos (23U) +#define ADC_CR2_TSVREFE_Pos (23U) #define ADC_CR2_TSVREFE_Msk (0x1U << ADC_CR2_TSVREFE_Pos) /*!< 0x00800000 */ #define ADC_CR2_TSVREFE ADC_CR2_TSVREFE_Msk /*!< ADC internal path to VrefInt and temperature sensor enable */ /****************** Bit definition for ADC_SMPR1 register *******************/ -#define ADC_SMPR1_SMP10_Pos (0U) +#define ADC_SMPR1_SMP10_Pos (0U) #define ADC_SMPR1_SMP10_Msk (0x7U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000007 */ #define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /*!< ADC channel 10 sampling time selection */ #define ADC_SMPR1_SMP10_0 (0x1U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000001 */ #define ADC_SMPR1_SMP10_1 (0x2U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000002 */ #define ADC_SMPR1_SMP10_2 (0x4U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000004 */ -#define ADC_SMPR1_SMP11_Pos (3U) +#define ADC_SMPR1_SMP11_Pos (3U) #define ADC_SMPR1_SMP11_Msk (0x7U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000038 */ #define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /*!< ADC channel 11 sampling time selection */ #define ADC_SMPR1_SMP11_0 (0x1U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000008 */ #define ADC_SMPR1_SMP11_1 (0x2U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000010 */ #define ADC_SMPR1_SMP11_2 (0x4U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000020 */ -#define ADC_SMPR1_SMP12_Pos (6U) +#define ADC_SMPR1_SMP12_Pos (6U) #define ADC_SMPR1_SMP12_Msk (0x7U << ADC_SMPR1_SMP12_Pos) /*!< 0x000001C0 */ #define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /*!< ADC channel 12 sampling time selection */ #define ADC_SMPR1_SMP12_0 (0x1U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000040 */ #define ADC_SMPR1_SMP12_1 (0x2U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000080 */ #define ADC_SMPR1_SMP12_2 (0x4U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000100 */ -#define ADC_SMPR1_SMP13_Pos (9U) +#define ADC_SMPR1_SMP13_Pos (9U) #define ADC_SMPR1_SMP13_Msk (0x7U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000E00 */ #define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /*!< ADC channel 13 sampling time selection */ #define ADC_SMPR1_SMP13_0 (0x1U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000200 */ #define ADC_SMPR1_SMP13_1 (0x2U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000400 */ #define ADC_SMPR1_SMP13_2 (0x4U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000800 */ -#define ADC_SMPR1_SMP14_Pos (12U) +#define ADC_SMPR1_SMP14_Pos (12U) #define ADC_SMPR1_SMP14_Msk (0x7U << ADC_SMPR1_SMP14_Pos) /*!< 0x00007000 */ #define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /*!< ADC channel 14 sampling time selection */ #define ADC_SMPR1_SMP14_0 (0x1U << ADC_SMPR1_SMP14_Pos) /*!< 0x00001000 */ #define ADC_SMPR1_SMP14_1 (0x2U << ADC_SMPR1_SMP14_Pos) /*!< 0x00002000 */ #define ADC_SMPR1_SMP14_2 (0x4U << ADC_SMPR1_SMP14_Pos) /*!< 0x00004000 */ -#define ADC_SMPR1_SMP15_Pos (15U) +#define ADC_SMPR1_SMP15_Pos (15U) #define ADC_SMPR1_SMP15_Msk (0x7U << ADC_SMPR1_SMP15_Pos) /*!< 0x00038000 */ #define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /*!< ADC channel 15 sampling time selection */ #define ADC_SMPR1_SMP15_0 (0x1U << ADC_SMPR1_SMP15_Pos) /*!< 0x00008000 */ #define ADC_SMPR1_SMP15_1 (0x2U << ADC_SMPR1_SMP15_Pos) /*!< 0x00010000 */ #define ADC_SMPR1_SMP15_2 (0x4U << ADC_SMPR1_SMP15_Pos) /*!< 0x00020000 */ -#define ADC_SMPR1_SMP16_Pos (18U) +#define ADC_SMPR1_SMP16_Pos (18U) #define ADC_SMPR1_SMP16_Msk (0x7U << ADC_SMPR1_SMP16_Pos) /*!< 0x001C0000 */ #define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /*!< ADC channel 16 sampling time selection */ #define ADC_SMPR1_SMP16_0 (0x1U << ADC_SMPR1_SMP16_Pos) /*!< 0x00040000 */ #define ADC_SMPR1_SMP16_1 (0x2U << ADC_SMPR1_SMP16_Pos) /*!< 0x00080000 */ #define ADC_SMPR1_SMP16_2 (0x4U << ADC_SMPR1_SMP16_Pos) /*!< 0x00100000 */ -#define ADC_SMPR1_SMP17_Pos (21U) +#define ADC_SMPR1_SMP17_Pos (21U) #define ADC_SMPR1_SMP17_Msk (0x7U << ADC_SMPR1_SMP17_Pos) /*!< 0x00E00000 */ #define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /*!< ADC channel 17 sampling time selection */ #define ADC_SMPR1_SMP17_0 (0x1U << ADC_SMPR1_SMP17_Pos) /*!< 0x00200000 */ @@ -3903,70 +3903,70 @@ typedef struct #define ADC_SMPR1_SMP17_2 (0x4U << ADC_SMPR1_SMP17_Pos) /*!< 0x00800000 */ /****************** Bit definition for ADC_SMPR2 register *******************/ -#define ADC_SMPR2_SMP0_Pos (0U) +#define ADC_SMPR2_SMP0_Pos (0U) #define ADC_SMPR2_SMP0_Msk (0x7U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000007 */ #define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /*!< ADC channel 0 sampling time selection */ #define ADC_SMPR2_SMP0_0 (0x1U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000001 */ #define ADC_SMPR2_SMP0_1 (0x2U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000002 */ #define ADC_SMPR2_SMP0_2 (0x4U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000004 */ -#define ADC_SMPR2_SMP1_Pos (3U) +#define ADC_SMPR2_SMP1_Pos (3U) #define ADC_SMPR2_SMP1_Msk (0x7U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000038 */ #define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /*!< ADC channel 1 sampling time selection */ #define ADC_SMPR2_SMP1_0 (0x1U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000008 */ #define ADC_SMPR2_SMP1_1 (0x2U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000010 */ #define ADC_SMPR2_SMP1_2 (0x4U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000020 */ -#define ADC_SMPR2_SMP2_Pos (6U) +#define ADC_SMPR2_SMP2_Pos (6U) #define ADC_SMPR2_SMP2_Msk (0x7U << ADC_SMPR2_SMP2_Pos) /*!< 0x000001C0 */ #define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /*!< ADC channel 2 sampling time selection */ #define ADC_SMPR2_SMP2_0 (0x1U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000040 */ #define ADC_SMPR2_SMP2_1 (0x2U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000080 */ #define ADC_SMPR2_SMP2_2 (0x4U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000100 */ -#define ADC_SMPR2_SMP3_Pos (9U) +#define ADC_SMPR2_SMP3_Pos (9U) #define ADC_SMPR2_SMP3_Msk (0x7U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000E00 */ #define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /*!< ADC channel 3 sampling time selection */ #define ADC_SMPR2_SMP3_0 (0x1U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000200 */ #define ADC_SMPR2_SMP3_1 (0x2U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000400 */ #define ADC_SMPR2_SMP3_2 (0x4U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000800 */ -#define ADC_SMPR2_SMP4_Pos (12U) +#define ADC_SMPR2_SMP4_Pos (12U) #define ADC_SMPR2_SMP4_Msk (0x7U << ADC_SMPR2_SMP4_Pos) /*!< 0x00007000 */ #define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /*!< ADC channel 4 sampling time selection */ #define ADC_SMPR2_SMP4_0 (0x1U << ADC_SMPR2_SMP4_Pos) /*!< 0x00001000 */ #define ADC_SMPR2_SMP4_1 (0x2U << ADC_SMPR2_SMP4_Pos) /*!< 0x00002000 */ #define ADC_SMPR2_SMP4_2 (0x4U << ADC_SMPR2_SMP4_Pos) /*!< 0x00004000 */ -#define ADC_SMPR2_SMP5_Pos (15U) +#define ADC_SMPR2_SMP5_Pos (15U) #define ADC_SMPR2_SMP5_Msk (0x7U << ADC_SMPR2_SMP5_Pos) /*!< 0x00038000 */ #define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /*!< ADC channel 5 sampling time selection */ #define ADC_SMPR2_SMP5_0 (0x1U << ADC_SMPR2_SMP5_Pos) /*!< 0x00008000 */ #define ADC_SMPR2_SMP5_1 (0x2U << ADC_SMPR2_SMP5_Pos) /*!< 0x00010000 */ #define ADC_SMPR2_SMP5_2 (0x4U << ADC_SMPR2_SMP5_Pos) /*!< 0x00020000 */ -#define ADC_SMPR2_SMP6_Pos (18U) +#define ADC_SMPR2_SMP6_Pos (18U) #define ADC_SMPR2_SMP6_Msk (0x7U << ADC_SMPR2_SMP6_Pos) /*!< 0x001C0000 */ #define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /*!< ADC channel 6 sampling time selection */ #define ADC_SMPR2_SMP6_0 (0x1U << ADC_SMPR2_SMP6_Pos) /*!< 0x00040000 */ #define ADC_SMPR2_SMP6_1 (0x2U << ADC_SMPR2_SMP6_Pos) /*!< 0x00080000 */ #define ADC_SMPR2_SMP6_2 (0x4U << ADC_SMPR2_SMP6_Pos) /*!< 0x00100000 */ -#define ADC_SMPR2_SMP7_Pos (21U) +#define ADC_SMPR2_SMP7_Pos (21U) #define ADC_SMPR2_SMP7_Msk (0x7U << ADC_SMPR2_SMP7_Pos) /*!< 0x00E00000 */ #define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /*!< ADC channel 7 sampling time selection */ #define ADC_SMPR2_SMP7_0 (0x1U << ADC_SMPR2_SMP7_Pos) /*!< 0x00200000 */ #define ADC_SMPR2_SMP7_1 (0x2U << ADC_SMPR2_SMP7_Pos) /*!< 0x00400000 */ #define ADC_SMPR2_SMP7_2 (0x4U << ADC_SMPR2_SMP7_Pos) /*!< 0x00800000 */ -#define ADC_SMPR2_SMP8_Pos (24U) +#define ADC_SMPR2_SMP8_Pos (24U) #define ADC_SMPR2_SMP8_Msk (0x7U << ADC_SMPR2_SMP8_Pos) /*!< 0x07000000 */ #define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /*!< ADC channel 8 sampling time selection */ #define ADC_SMPR2_SMP8_0 (0x1U << ADC_SMPR2_SMP8_Pos) /*!< 0x01000000 */ #define ADC_SMPR2_SMP8_1 (0x2U << ADC_SMPR2_SMP8_Pos) /*!< 0x02000000 */ #define ADC_SMPR2_SMP8_2 (0x4U << ADC_SMPR2_SMP8_Pos) /*!< 0x04000000 */ -#define ADC_SMPR2_SMP9_Pos (27U) +#define ADC_SMPR2_SMP9_Pos (27U) #define ADC_SMPR2_SMP9_Msk (0x7U << ADC_SMPR2_SMP9_Pos) /*!< 0x38000000 */ #define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /*!< ADC channel 9 sampling time selection */ #define ADC_SMPR2_SMP9_0 (0x1U << ADC_SMPR2_SMP9_Pos) /*!< 0x08000000 */ @@ -3974,37 +3974,37 @@ typedef struct #define ADC_SMPR2_SMP9_2 (0x4U << ADC_SMPR2_SMP9_Pos) /*!< 0x20000000 */ /****************** Bit definition for ADC_JOFR1 register *******************/ -#define ADC_JOFR1_JOFFSET1_Pos (0U) +#define ADC_JOFR1_JOFFSET1_Pos (0U) #define ADC_JOFR1_JOFFSET1_Msk (0xFFFU << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */ #define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!< ADC group injected sequencer rank 1 offset value */ /****************** Bit definition for ADC_JOFR2 register *******************/ -#define ADC_JOFR2_JOFFSET2_Pos (0U) +#define ADC_JOFR2_JOFFSET2_Pos (0U) #define ADC_JOFR2_JOFFSET2_Msk (0xFFFU << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */ #define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!< ADC group injected sequencer rank 2 offset value */ /****************** Bit definition for ADC_JOFR3 register *******************/ -#define ADC_JOFR3_JOFFSET3_Pos (0U) +#define ADC_JOFR3_JOFFSET3_Pos (0U) #define ADC_JOFR3_JOFFSET3_Msk (0xFFFU << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */ #define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!< ADC group injected sequencer rank 3 offset value */ /****************** Bit definition for ADC_JOFR4 register *******************/ -#define ADC_JOFR4_JOFFSET4_Pos (0U) +#define ADC_JOFR4_JOFFSET4_Pos (0U) #define ADC_JOFR4_JOFFSET4_Msk (0xFFFU << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */ #define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!< ADC group injected sequencer rank 4 offset value */ /******************* Bit definition for ADC_HTR register ********************/ -#define ADC_HTR_HT_Pos (0U) +#define ADC_HTR_HT_Pos (0U) #define ADC_HTR_HT_Msk (0xFFFU << ADC_HTR_HT_Pos) /*!< 0x00000FFF */ #define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC analog watchdog 1 threshold high */ /******************* Bit definition for ADC_LTR register ********************/ -#define ADC_LTR_LT_Pos (0U) +#define ADC_LTR_LT_Pos (0U) #define ADC_LTR_LT_Msk (0xFFFU << ADC_LTR_LT_Pos) /*!< 0x00000FFF */ #define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC analog watchdog 1 threshold low */ /******************* Bit definition for ADC_SQR1 register *******************/ -#define ADC_SQR1_SQ13_Pos (0U) +#define ADC_SQR1_SQ13_Pos (0U) #define ADC_SQR1_SQ13_Msk (0x1FU << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */ #define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ #define ADC_SQR1_SQ13_0 (0x01U << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */ @@ -4013,7 +4013,7 @@ typedef struct #define ADC_SQR1_SQ13_3 (0x08U << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */ #define ADC_SQR1_SQ13_4 (0x10U << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */ -#define ADC_SQR1_SQ14_Pos (5U) +#define ADC_SQR1_SQ14_Pos (5U) #define ADC_SQR1_SQ14_Msk (0x1FU << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */ #define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ #define ADC_SQR1_SQ14_0 (0x01U << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */ @@ -4022,7 +4022,7 @@ typedef struct #define ADC_SQR1_SQ14_3 (0x08U << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */ #define ADC_SQR1_SQ14_4 (0x10U << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */ -#define ADC_SQR1_SQ15_Pos (10U) +#define ADC_SQR1_SQ15_Pos (10U) #define ADC_SQR1_SQ15_Msk (0x1FU << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */ #define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ #define ADC_SQR1_SQ15_0 (0x01U << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */ @@ -4031,7 +4031,7 @@ typedef struct #define ADC_SQR1_SQ15_3 (0x08U << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */ #define ADC_SQR1_SQ15_4 (0x10U << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */ -#define ADC_SQR1_SQ16_Pos (15U) +#define ADC_SQR1_SQ16_Pos (15U) #define ADC_SQR1_SQ16_Msk (0x1FU << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */ #define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ #define ADC_SQR1_SQ16_0 (0x01U << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */ @@ -4040,7 +4040,7 @@ typedef struct #define ADC_SQR1_SQ16_3 (0x08U << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */ #define ADC_SQR1_SQ16_4 (0x10U << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */ -#define ADC_SQR1_L_Pos (20U) +#define ADC_SQR1_L_Pos (20U) #define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x00F00000 */ #define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ #define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00100000 */ @@ -4049,7 +4049,7 @@ typedef struct #define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00800000 */ /******************* Bit definition for ADC_SQR2 register *******************/ -#define ADC_SQR2_SQ7_Pos (0U) +#define ADC_SQR2_SQ7_Pos (0U) #define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */ #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ #define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */ @@ -4058,7 +4058,7 @@ typedef struct #define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */ #define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */ -#define ADC_SQR2_SQ8_Pos (5U) +#define ADC_SQR2_SQ8_Pos (5U) #define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */ #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ #define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */ @@ -4067,7 +4067,7 @@ typedef struct #define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */ #define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */ -#define ADC_SQR2_SQ9_Pos (10U) +#define ADC_SQR2_SQ9_Pos (10U) #define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */ #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ #define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */ @@ -4076,7 +4076,7 @@ typedef struct #define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */ #define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */ -#define ADC_SQR2_SQ10_Pos (15U) +#define ADC_SQR2_SQ10_Pos (15U) #define ADC_SQR2_SQ10_Msk (0x1FU << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */ #define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ #define ADC_SQR2_SQ10_0 (0x01U << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */ @@ -4085,7 +4085,7 @@ typedef struct #define ADC_SQR2_SQ10_3 (0x08U << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */ #define ADC_SQR2_SQ10_4 (0x10U << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */ -#define ADC_SQR2_SQ11_Pos (20U) +#define ADC_SQR2_SQ11_Pos (20U) #define ADC_SQR2_SQ11_Msk (0x1FU << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */ #define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!< ADC group regular sequencer rank 1 */ #define ADC_SQR2_SQ11_0 (0x01U << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */ @@ -4094,7 +4094,7 @@ typedef struct #define ADC_SQR2_SQ11_3 (0x08U << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */ #define ADC_SQR2_SQ11_4 (0x10U << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */ -#define ADC_SQR2_SQ12_Pos (25U) +#define ADC_SQR2_SQ12_Pos (25U) #define ADC_SQR2_SQ12_Msk (0x1FU << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */ #define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ #define ADC_SQR2_SQ12_0 (0x01U << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */ @@ -4104,7 +4104,7 @@ typedef struct #define ADC_SQR2_SQ12_4 (0x10U << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */ /******************* Bit definition for ADC_SQR3 register *******************/ -#define ADC_SQR3_SQ1_Pos (0U) +#define ADC_SQR3_SQ1_Pos (0U) #define ADC_SQR3_SQ1_Msk (0x1FU << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */ #define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ #define ADC_SQR3_SQ1_0 (0x01U << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */ @@ -4113,7 +4113,7 @@ typedef struct #define ADC_SQR3_SQ1_3 (0x08U << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */ #define ADC_SQR3_SQ1_4 (0x10U << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */ -#define ADC_SQR3_SQ2_Pos (5U) +#define ADC_SQR3_SQ2_Pos (5U) #define ADC_SQR3_SQ2_Msk (0x1FU << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */ #define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ #define ADC_SQR3_SQ2_0 (0x01U << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */ @@ -4122,7 +4122,7 @@ typedef struct #define ADC_SQR3_SQ2_3 (0x08U << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */ #define ADC_SQR3_SQ2_4 (0x10U << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */ -#define ADC_SQR3_SQ3_Pos (10U) +#define ADC_SQR3_SQ3_Pos (10U) #define ADC_SQR3_SQ3_Msk (0x1FU << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */ #define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ #define ADC_SQR3_SQ3_0 (0x01U << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */ @@ -4131,7 +4131,7 @@ typedef struct #define ADC_SQR3_SQ3_3 (0x08U << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */ #define ADC_SQR3_SQ3_4 (0x10U << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */ -#define ADC_SQR3_SQ4_Pos (15U) +#define ADC_SQR3_SQ4_Pos (15U) #define ADC_SQR3_SQ4_Msk (0x1FU << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */ #define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ #define ADC_SQR3_SQ4_0 (0x01U << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */ @@ -4140,7 +4140,7 @@ typedef struct #define ADC_SQR3_SQ4_3 (0x08U << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */ #define ADC_SQR3_SQ4_4 (0x10U << ADC_SQR3_SQ4_Pos) /*!< 0x00080000 */ -#define ADC_SQR3_SQ5_Pos (20U) +#define ADC_SQR3_SQ5_Pos (20U) #define ADC_SQR3_SQ5_Msk (0x1FU << ADC_SQR3_SQ5_Pos) /*!< 0x01F00000 */ #define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ #define ADC_SQR3_SQ5_0 (0x01U << ADC_SQR3_SQ5_Pos) /*!< 0x00100000 */ @@ -4149,7 +4149,7 @@ typedef struct #define ADC_SQR3_SQ5_3 (0x08U << ADC_SQR3_SQ5_Pos) /*!< 0x00800000 */ #define ADC_SQR3_SQ5_4 (0x10U << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */ -#define ADC_SQR3_SQ6_Pos (25U) +#define ADC_SQR3_SQ6_Pos (25U) #define ADC_SQR3_SQ6_Msk (0x1FU << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */ #define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ #define ADC_SQR3_SQ6_0 (0x01U << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */ @@ -4159,7 +4159,7 @@ typedef struct #define ADC_SQR3_SQ6_4 (0x10U << ADC_SQR3_SQ6_Pos) /*!< 0x20000000 */ /******************* Bit definition for ADC_JSQR register *******************/ -#define ADC_JSQR_JSQ1_Pos (0U) +#define ADC_JSQR_JSQ1_Pos (0U) #define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */ #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ #define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */ @@ -4168,7 +4168,7 @@ typedef struct #define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */ #define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */ -#define ADC_JSQR_JSQ2_Pos (5U) +#define ADC_JSQR_JSQ2_Pos (5U) #define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */ #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ #define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */ @@ -4177,7 +4177,7 @@ typedef struct #define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */ #define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */ -#define ADC_JSQR_JSQ3_Pos (10U) +#define ADC_JSQR_JSQ3_Pos (10U) #define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */ #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ #define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */ @@ -4186,7 +4186,7 @@ typedef struct #define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */ #define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */ -#define ADC_JSQR_JSQ4_Pos (15U) +#define ADC_JSQR_JSQ4_Pos (15U) #define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */ #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ #define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */ @@ -4195,37 +4195,37 @@ typedef struct #define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */ #define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */ -#define ADC_JSQR_JL_Pos (20U) +#define ADC_JSQR_JL_Pos (20U) #define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00300000 */ #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ #define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00100000 */ #define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00200000 */ /******************* Bit definition for ADC_JDR1 register *******************/ -#define ADC_JDR1_JDATA_Pos (0U) +#define ADC_JDR1_JDATA_Pos (0U) #define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ /******************* Bit definition for ADC_JDR2 register *******************/ -#define ADC_JDR2_JDATA_Pos (0U) +#define ADC_JDR2_JDATA_Pos (0U) #define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ /******************* Bit definition for ADC_JDR3 register *******************/ -#define ADC_JDR3_JDATA_Pos (0U) +#define ADC_JDR3_JDATA_Pos (0U) #define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ /******************* Bit definition for ADC_JDR4 register *******************/ -#define ADC_JDR4_JDATA_Pos (0U) +#define ADC_JDR4_JDATA_Pos (0U) #define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ /******************** Bit definition for ADC_DR register ********************/ -#define ADC_DR_DATA_Pos (0U) +#define ADC_DR_DATA_Pos (0U) #define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */ #define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */ -#define ADC_DR_ADC2DATA_Pos (16U) +#define ADC_DR_ADC2DATA_Pos (16U) #define ADC_DR_ADC2DATA_Msk (0xFFFFU << ADC_DR_ADC2DATA_Pos) /*!< 0xFFFF0000 */ #define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk /*!< ADC group regular conversion data for ADC slave, in multimode */ @@ -4236,105 +4236,105 @@ typedef struct /* */ /*****************************************************************************/ /******************* Bit definition for TIM_CR1 register *******************/ -#define TIM_CR1_CEN_Pos (0U) +#define TIM_CR1_CEN_Pos (0U) #define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */ #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */ -#define TIM_CR1_UDIS_Pos (1U) +#define TIM_CR1_UDIS_Pos (1U) #define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */ #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */ -#define TIM_CR1_URS_Pos (2U) +#define TIM_CR1_URS_Pos (2U) #define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /*!< 0x00000004 */ #define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */ -#define TIM_CR1_OPM_Pos (3U) +#define TIM_CR1_OPM_Pos (3U) #define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /*!< 0x00000008 */ #define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */ -#define TIM_CR1_DIR_Pos (4U) +#define TIM_CR1_DIR_Pos (4U) #define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /*!< 0x00000010 */ #define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */ -#define TIM_CR1_CMS_Pos (5U) +#define TIM_CR1_CMS_Pos (5U) #define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /*!< 0x00000060 */ #define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */ #define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /*!< 0x00000020 */ #define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /*!< 0x00000040 */ -#define TIM_CR1_ARPE_Pos (7U) +#define TIM_CR1_ARPE_Pos (7U) #define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */ #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */ -#define TIM_CR1_CKD_Pos (8U) +#define TIM_CR1_CKD_Pos (8U) #define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /*!< 0x00000300 */ #define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */ #define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /*!< 0x00000100 */ #define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /*!< 0x00000200 */ /******************* Bit definition for TIM_CR2 register *******************/ -#define TIM_CR2_CCPC_Pos (0U) +#define TIM_CR2_CCPC_Pos (0U) #define TIM_CR2_CCPC_Msk (0x1U << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */ #define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */ -#define TIM_CR2_CCUS_Pos (2U) +#define TIM_CR2_CCUS_Pos (2U) #define TIM_CR2_CCUS_Msk (0x1U << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */ #define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */ -#define TIM_CR2_CCDS_Pos (3U) +#define TIM_CR2_CCDS_Pos (3U) #define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */ #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */ -#define TIM_CR2_MMS_Pos (4U) +#define TIM_CR2_MMS_Pos (4U) #define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */ #define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */ #define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x00000010 */ #define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x00000020 */ #define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x00000040 */ -#define TIM_CR2_TI1S_Pos (7U) +#define TIM_CR2_TI1S_Pos (7U) #define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */ #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */ -#define TIM_CR2_OIS1_Pos (8U) +#define TIM_CR2_OIS1_Pos (8U) #define TIM_CR2_OIS1_Msk (0x1U << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */ #define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */ -#define TIM_CR2_OIS1N_Pos (9U) +#define TIM_CR2_OIS1N_Pos (9U) #define TIM_CR2_OIS1N_Msk (0x1U << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */ #define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */ -#define TIM_CR2_OIS2_Pos (10U) +#define TIM_CR2_OIS2_Pos (10U) #define TIM_CR2_OIS2_Msk (0x1U << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */ #define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */ -#define TIM_CR2_OIS2N_Pos (11U) +#define TIM_CR2_OIS2N_Pos (11U) #define TIM_CR2_OIS2N_Msk (0x1U << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */ #define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */ -#define TIM_CR2_OIS3_Pos (12U) +#define TIM_CR2_OIS3_Pos (12U) #define TIM_CR2_OIS3_Msk (0x1U << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */ #define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */ -#define TIM_CR2_OIS3N_Pos (13U) +#define TIM_CR2_OIS3N_Pos (13U) #define TIM_CR2_OIS3N_Msk (0x1U << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */ #define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */ -#define TIM_CR2_OIS4_Pos (14U) +#define TIM_CR2_OIS4_Pos (14U) #define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */ #define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */ /******************* Bit definition for TIM_SMCR register ******************/ -#define TIM_SMCR_SMS_Pos (0U) +#define TIM_SMCR_SMS_Pos (0U) #define TIM_SMCR_SMS_Msk (0x7U << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */ #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */ #define TIM_SMCR_SMS_0 (0x1U << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */ #define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */ #define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */ -#define TIM_SMCR_OCCS_Pos (3U) +#define TIM_SMCR_OCCS_Pos (3U) #define TIM_SMCR_OCCS_Msk (0x1U << TIM_SMCR_OCCS_Pos) /*!< 0x00000008 */ #define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear selection */ -#define TIM_SMCR_TS_Pos (4U) +#define TIM_SMCR_TS_Pos (4U) #define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */ #define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */ #define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /*!< 0x00000010 */ #define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /*!< 0x00000020 */ #define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /*!< 0x00000040 */ -#define TIM_SMCR_MSM_Pos (7U) +#define TIM_SMCR_MSM_Pos (7U) #define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */ #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */ -#define TIM_SMCR_ETF_Pos (8U) +#define TIM_SMCR_ETF_Pos (8U) #define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */ #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */ #define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */ @@ -4342,188 +4342,188 @@ typedef struct #define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */ #define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */ -#define TIM_SMCR_ETPS_Pos (12U) +#define TIM_SMCR_ETPS_Pos (12U) #define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */ #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */ #define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */ #define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */ -#define TIM_SMCR_ECE_Pos (14U) +#define TIM_SMCR_ECE_Pos (14U) #define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */ #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */ -#define TIM_SMCR_ETP_Pos (15U) +#define TIM_SMCR_ETP_Pos (15U) #define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */ #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */ /******************* Bit definition for TIM_DIER register ******************/ -#define TIM_DIER_UIE_Pos (0U) +#define TIM_DIER_UIE_Pos (0U) #define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /*!< 0x00000001 */ #define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */ -#define TIM_DIER_CC1IE_Pos (1U) +#define TIM_DIER_CC1IE_Pos (1U) #define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */ #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */ -#define TIM_DIER_CC2IE_Pos (2U) +#define TIM_DIER_CC2IE_Pos (2U) #define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */ #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */ -#define TIM_DIER_CC3IE_Pos (3U) +#define TIM_DIER_CC3IE_Pos (3U) #define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */ #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */ -#define TIM_DIER_CC4IE_Pos (4U) +#define TIM_DIER_CC4IE_Pos (4U) #define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */ #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */ -#define TIM_DIER_COMIE_Pos (5U) +#define TIM_DIER_COMIE_Pos (5U) #define TIM_DIER_COMIE_Msk (0x1U << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */ #define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */ -#define TIM_DIER_TIE_Pos (6U) +#define TIM_DIER_TIE_Pos (6U) #define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /*!< 0x00000040 */ #define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */ -#define TIM_DIER_BIE_Pos (7U) +#define TIM_DIER_BIE_Pos (7U) #define TIM_DIER_BIE_Msk (0x1U << TIM_DIER_BIE_Pos) /*!< 0x00000080 */ #define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */ -#define TIM_DIER_UDE_Pos (8U) +#define TIM_DIER_UDE_Pos (8U) #define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /*!< 0x00000100 */ #define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */ -#define TIM_DIER_CC1DE_Pos (9U) +#define TIM_DIER_CC1DE_Pos (9U) #define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */ #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */ -#define TIM_DIER_CC2DE_Pos (10U) +#define TIM_DIER_CC2DE_Pos (10U) #define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */ #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */ -#define TIM_DIER_CC3DE_Pos (11U) +#define TIM_DIER_CC3DE_Pos (11U) #define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */ #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */ -#define TIM_DIER_CC4DE_Pos (12U) +#define TIM_DIER_CC4DE_Pos (12U) #define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */ #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */ -#define TIM_DIER_COMDE_Pos (13U) +#define TIM_DIER_COMDE_Pos (13U) #define TIM_DIER_COMDE_Msk (0x1U << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */ #define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */ -#define TIM_DIER_TDE_Pos (14U) +#define TIM_DIER_TDE_Pos (14U) #define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /*!< 0x00004000 */ #define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */ /******************** Bit definition for TIM_SR register *******************/ -#define TIM_SR_UIF_Pos (0U) +#define TIM_SR_UIF_Pos (0U) #define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */ #define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */ -#define TIM_SR_CC1IF_Pos (1U) +#define TIM_SR_CC1IF_Pos (1U) #define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */ #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */ -#define TIM_SR_CC2IF_Pos (2U) +#define TIM_SR_CC2IF_Pos (2U) #define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */ #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */ -#define TIM_SR_CC3IF_Pos (3U) +#define TIM_SR_CC3IF_Pos (3U) #define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */ #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */ -#define TIM_SR_CC4IF_Pos (4U) +#define TIM_SR_CC4IF_Pos (4U) #define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */ #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */ -#define TIM_SR_COMIF_Pos (5U) +#define TIM_SR_COMIF_Pos (5U) #define TIM_SR_COMIF_Msk (0x1U << TIM_SR_COMIF_Pos) /*!< 0x00000020 */ #define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */ -#define TIM_SR_TIF_Pos (6U) +#define TIM_SR_TIF_Pos (6U) #define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */ #define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */ -#define TIM_SR_BIF_Pos (7U) +#define TIM_SR_BIF_Pos (7U) #define TIM_SR_BIF_Msk (0x1U << TIM_SR_BIF_Pos) /*!< 0x00000080 */ #define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */ -#define TIM_SR_CC1OF_Pos (9U) +#define TIM_SR_CC1OF_Pos (9U) #define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */ #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */ -#define TIM_SR_CC2OF_Pos (10U) +#define TIM_SR_CC2OF_Pos (10U) #define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */ #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */ -#define TIM_SR_CC3OF_Pos (11U) +#define TIM_SR_CC3OF_Pos (11U) #define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */ #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */ -#define TIM_SR_CC4OF_Pos (12U) +#define TIM_SR_CC4OF_Pos (12U) #define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */ #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */ /******************* Bit definition for TIM_EGR register *******************/ -#define TIM_EGR_UG_Pos (0U) +#define TIM_EGR_UG_Pos (0U) #define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /*!< 0x00000001 */ #define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */ -#define TIM_EGR_CC1G_Pos (1U) +#define TIM_EGR_CC1G_Pos (1U) #define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */ #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */ -#define TIM_EGR_CC2G_Pos (2U) +#define TIM_EGR_CC2G_Pos (2U) #define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */ #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */ -#define TIM_EGR_CC3G_Pos (3U) +#define TIM_EGR_CC3G_Pos (3U) #define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */ #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */ -#define TIM_EGR_CC4G_Pos (4U) +#define TIM_EGR_CC4G_Pos (4U) #define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */ #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */ -#define TIM_EGR_COMG_Pos (5U) +#define TIM_EGR_COMG_Pos (5U) #define TIM_EGR_COMG_Msk (0x1U << TIM_EGR_COMG_Pos) /*!< 0x00000020 */ #define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */ -#define TIM_EGR_TG_Pos (6U) +#define TIM_EGR_TG_Pos (6U) #define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /*!< 0x00000040 */ #define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */ -#define TIM_EGR_BG_Pos (7U) +#define TIM_EGR_BG_Pos (7U) #define TIM_EGR_BG_Msk (0x1U << TIM_EGR_BG_Pos) /*!< 0x00000080 */ #define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */ /****************** Bit definition for TIM_CCMR1 register ******************/ -#define TIM_CCMR1_CC1S_Pos (0U) +#define TIM_CCMR1_CC1S_Pos (0U) #define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */ #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */ #define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */ #define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */ -#define TIM_CCMR1_OC1FE_Pos (2U) +#define TIM_CCMR1_OC1FE_Pos (2U) #define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */ #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */ -#define TIM_CCMR1_OC1PE_Pos (3U) +#define TIM_CCMR1_OC1PE_Pos (3U) #define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */ #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */ -#define TIM_CCMR1_OC1M_Pos (4U) +#define TIM_CCMR1_OC1M_Pos (4U) #define TIM_CCMR1_OC1M_Msk (0x7U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */ #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */ #define TIM_CCMR1_OC1M_0 (0x1U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */ #define TIM_CCMR1_OC1M_1 (0x2U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */ #define TIM_CCMR1_OC1M_2 (0x4U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */ -#define TIM_CCMR1_OC1CE_Pos (7U) +#define TIM_CCMR1_OC1CE_Pos (7U) #define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */ #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */ -#define TIM_CCMR1_CC2S_Pos (8U) +#define TIM_CCMR1_CC2S_Pos (8U) #define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */ #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */ #define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */ #define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */ -#define TIM_CCMR1_OC2FE_Pos (10U) +#define TIM_CCMR1_OC2FE_Pos (10U) #define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */ #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */ -#define TIM_CCMR1_OC2PE_Pos (11U) +#define TIM_CCMR1_OC2PE_Pos (11U) #define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */ #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */ -#define TIM_CCMR1_OC2M_Pos (12U) +#define TIM_CCMR1_OC2M_Pos (12U) #define TIM_CCMR1_OC2M_Msk (0x7U << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */ #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */ #define TIM_CCMR1_OC2M_0 (0x1U << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */ #define TIM_CCMR1_OC2M_1 (0x2U << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */ #define TIM_CCMR1_OC2M_2 (0x4U << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */ -#define TIM_CCMR1_OC2CE_Pos (15U) +#define TIM_CCMR1_OC2CE_Pos (15U) #define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */ #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */ /*---------------------------------------------------------------------------*/ -#define TIM_CCMR1_IC1PSC_Pos (2U) +#define TIM_CCMR1_IC1PSC_Pos (2U) #define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */ #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ #define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */ #define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */ -#define TIM_CCMR1_IC1F_Pos (4U) +#define TIM_CCMR1_IC1F_Pos (4U) #define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */ #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */ #define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */ @@ -4531,13 +4531,13 @@ typedef struct #define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */ #define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */ -#define TIM_CCMR1_IC2PSC_Pos (10U) +#define TIM_CCMR1_IC2PSC_Pos (10U) #define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */ #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ #define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */ #define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */ -#define TIM_CCMR1_IC2F_Pos (12U) +#define TIM_CCMR1_IC2F_Pos (12U) #define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */ #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */ #define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */ @@ -4546,63 +4546,63 @@ typedef struct #define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */ /****************** Bit definition for TIM_CCMR2 register ******************/ -#define TIM_CCMR2_CC3S_Pos (0U) +#define TIM_CCMR2_CC3S_Pos (0U) #define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */ #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */ #define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */ #define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */ -#define TIM_CCMR2_OC3FE_Pos (2U) +#define TIM_CCMR2_OC3FE_Pos (2U) #define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */ #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */ -#define TIM_CCMR2_OC3PE_Pos (3U) +#define TIM_CCMR2_OC3PE_Pos (3U) #define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */ #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */ -#define TIM_CCMR2_OC3M_Pos (4U) +#define TIM_CCMR2_OC3M_Pos (4U) #define TIM_CCMR2_OC3M_Msk (0x7U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */ #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */ #define TIM_CCMR2_OC3M_0 (0x1U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */ #define TIM_CCMR2_OC3M_1 (0x2U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */ #define TIM_CCMR2_OC3M_2 (0x4U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */ -#define TIM_CCMR2_OC3CE_Pos (7U) +#define TIM_CCMR2_OC3CE_Pos (7U) #define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */ #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */ -#define TIM_CCMR2_CC4S_Pos (8U) +#define TIM_CCMR2_CC4S_Pos (8U) #define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */ #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */ #define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */ #define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */ -#define TIM_CCMR2_OC4FE_Pos (10U) +#define TIM_CCMR2_OC4FE_Pos (10U) #define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */ #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */ -#define TIM_CCMR2_OC4PE_Pos (11U) +#define TIM_CCMR2_OC4PE_Pos (11U) #define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */ #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */ -#define TIM_CCMR2_OC4M_Pos (12U) +#define TIM_CCMR2_OC4M_Pos (12U) #define TIM_CCMR2_OC4M_Msk (0x7U << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */ #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */ #define TIM_CCMR2_OC4M_0 (0x1U << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */ #define TIM_CCMR2_OC4M_1 (0x2U << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */ #define TIM_CCMR2_OC4M_2 (0x4U << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */ -#define TIM_CCMR2_OC4CE_Pos (15U) +#define TIM_CCMR2_OC4CE_Pos (15U) #define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */ #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */ /*---------------------------------------------------------------------------*/ -#define TIM_CCMR2_IC3PSC_Pos (2U) +#define TIM_CCMR2_IC3PSC_Pos (2U) #define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */ #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ #define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */ #define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */ -#define TIM_CCMR2_IC3F_Pos (4U) +#define TIM_CCMR2_IC3F_Pos (4U) #define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */ #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */ #define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */ @@ -4610,13 +4610,13 @@ typedef struct #define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */ #define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */ -#define TIM_CCMR2_IC4PSC_Pos (10U) +#define TIM_CCMR2_IC4PSC_Pos (10U) #define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */ #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ #define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */ #define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */ -#define TIM_CCMR2_IC4F_Pos (12U) +#define TIM_CCMR2_IC4F_Pos (12U) #define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */ #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */ #define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */ @@ -4625,94 +4625,94 @@ typedef struct #define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */ /******************* Bit definition for TIM_CCER register ******************/ -#define TIM_CCER_CC1E_Pos (0U) +#define TIM_CCER_CC1E_Pos (0U) #define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */ #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */ -#define TIM_CCER_CC1P_Pos (1U) +#define TIM_CCER_CC1P_Pos (1U) #define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */ #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */ -#define TIM_CCER_CC1NE_Pos (2U) +#define TIM_CCER_CC1NE_Pos (2U) #define TIM_CCER_CC1NE_Msk (0x1U << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */ #define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */ -#define TIM_CCER_CC1NP_Pos (3U) +#define TIM_CCER_CC1NP_Pos (3U) #define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */ #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */ -#define TIM_CCER_CC2E_Pos (4U) +#define TIM_CCER_CC2E_Pos (4U) #define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */ #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */ -#define TIM_CCER_CC2P_Pos (5U) +#define TIM_CCER_CC2P_Pos (5U) #define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */ #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */ -#define TIM_CCER_CC2NE_Pos (6U) +#define TIM_CCER_CC2NE_Pos (6U) #define TIM_CCER_CC2NE_Msk (0x1U << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */ #define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */ -#define TIM_CCER_CC2NP_Pos (7U) +#define TIM_CCER_CC2NP_Pos (7U) #define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */ #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */ -#define TIM_CCER_CC3E_Pos (8U) +#define TIM_CCER_CC3E_Pos (8U) #define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */ #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */ -#define TIM_CCER_CC3P_Pos (9U) +#define TIM_CCER_CC3P_Pos (9U) #define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */ #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */ -#define TIM_CCER_CC3NE_Pos (10U) +#define TIM_CCER_CC3NE_Pos (10U) #define TIM_CCER_CC3NE_Msk (0x1U << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */ #define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */ -#define TIM_CCER_CC3NP_Pos (11U) +#define TIM_CCER_CC3NP_Pos (11U) #define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */ #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */ -#define TIM_CCER_CC4E_Pos (12U) +#define TIM_CCER_CC4E_Pos (12U) #define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */ #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */ -#define TIM_CCER_CC4P_Pos (13U) +#define TIM_CCER_CC4P_Pos (13U) #define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */ #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */ -#define TIM_CCER_CC4NP_Pos (15U) +#define TIM_CCER_CC4NP_Pos (15U) #define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */ #define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */ /******************* Bit definition for TIM_CNT register *******************/ -#define TIM_CNT_CNT_Pos (0U) +#define TIM_CNT_CNT_Pos (0U) #define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */ #define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */ /******************* Bit definition for TIM_PSC register *******************/ -#define TIM_PSC_PSC_Pos (0U) +#define TIM_PSC_PSC_Pos (0U) #define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */ #define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */ /******************* Bit definition for TIM_ARR register *******************/ -#define TIM_ARR_ARR_Pos (0U) +#define TIM_ARR_ARR_Pos (0U) #define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */ #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */ /******************* Bit definition for TIM_RCR register *******************/ -#define TIM_RCR_REP_Pos (0U) +#define TIM_RCR_REP_Pos (0U) #define TIM_RCR_REP_Msk (0xFFU << TIM_RCR_REP_Pos) /*!< 0x000000FF */ #define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */ /******************* Bit definition for TIM_CCR1 register ******************/ -#define TIM_CCR1_CCR1_Pos (0U) +#define TIM_CCR1_CCR1_Pos (0U) #define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */ #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */ /******************* Bit definition for TIM_CCR2 register ******************/ -#define TIM_CCR2_CCR2_Pos (0U) +#define TIM_CCR2_CCR2_Pos (0U) #define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */ #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */ /******************* Bit definition for TIM_CCR3 register ******************/ -#define TIM_CCR3_CCR3_Pos (0U) +#define TIM_CCR3_CCR3_Pos (0U) #define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */ #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */ /******************* Bit definition for TIM_CCR4 register ******************/ -#define TIM_CCR4_CCR4_Pos (0U) +#define TIM_CCR4_CCR4_Pos (0U) #define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */ #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */ /******************* Bit definition for TIM_BDTR register ******************/ -#define TIM_BDTR_DTG_Pos (0U) +#define TIM_BDTR_DTG_Pos (0U) #define TIM_BDTR_DTG_Msk (0xFFU << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */ #define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */ #define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */ @@ -4724,33 +4724,33 @@ typedef struct #define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */ #define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) /*!< 0x00000080 */ -#define TIM_BDTR_LOCK_Pos (8U) +#define TIM_BDTR_LOCK_Pos (8U) #define TIM_BDTR_LOCK_Msk (0x3U << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */ #define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */ #define TIM_BDTR_LOCK_0 (0x1U << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */ #define TIM_BDTR_LOCK_1 (0x2U << TIM_BDTR_LOCK_Pos) /*!< 0x00000200 */ -#define TIM_BDTR_OSSI_Pos (10U) +#define TIM_BDTR_OSSI_Pos (10U) #define TIM_BDTR_OSSI_Msk (0x1U << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */ #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */ -#define TIM_BDTR_OSSR_Pos (11U) +#define TIM_BDTR_OSSR_Pos (11U) #define TIM_BDTR_OSSR_Msk (0x1U << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */ #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */ -#define TIM_BDTR_BKE_Pos (12U) +#define TIM_BDTR_BKE_Pos (12U) #define TIM_BDTR_BKE_Msk (0x1U << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */ #define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable */ -#define TIM_BDTR_BKP_Pos (13U) +#define TIM_BDTR_BKP_Pos (13U) #define TIM_BDTR_BKP_Msk (0x1U << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */ #define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity */ -#define TIM_BDTR_AOE_Pos (14U) +#define TIM_BDTR_AOE_Pos (14U) #define TIM_BDTR_AOE_Msk (0x1U << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */ #define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */ -#define TIM_BDTR_MOE_Pos (15U) +#define TIM_BDTR_MOE_Pos (15U) #define TIM_BDTR_MOE_Msk (0x1U << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */ #define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */ /******************* Bit definition for TIM_DCR register *******************/ -#define TIM_DCR_DBA_Pos (0U) +#define TIM_DCR_DBA_Pos (0U) #define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /*!< 0x0000001F */ #define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */ #define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /*!< 0x00000001 */ @@ -4759,7 +4759,7 @@ typedef struct #define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /*!< 0x00000008 */ #define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /*!< 0x00000010 */ -#define TIM_DCR_DBL_Pos (8U) +#define TIM_DCR_DBL_Pos (8U) #define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */ #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */ #define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x00000100 */ @@ -4769,7 +4769,7 @@ typedef struct #define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x00001000 */ /******************* Bit definition for TIM_DMAR register ******************/ -#define TIM_DMAR_DMAB_Pos (0U) +#define TIM_DMAR_DMAB_Pos (0U) #define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */ #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */ @@ -4782,73 +4782,73 @@ typedef struct /******************************************************************************/ /******************* Bit definition for RTC_CRH register ********************/ -#define RTC_CRH_SECIE_Pos (0U) +#define RTC_CRH_SECIE_Pos (0U) #define RTC_CRH_SECIE_Msk (0x1U << RTC_CRH_SECIE_Pos) /*!< 0x00000001 */ #define RTC_CRH_SECIE RTC_CRH_SECIE_Msk /*!< Second Interrupt Enable */ -#define RTC_CRH_ALRIE_Pos (1U) +#define RTC_CRH_ALRIE_Pos (1U) #define RTC_CRH_ALRIE_Msk (0x1U << RTC_CRH_ALRIE_Pos) /*!< 0x00000002 */ #define RTC_CRH_ALRIE RTC_CRH_ALRIE_Msk /*!< Alarm Interrupt Enable */ -#define RTC_CRH_OWIE_Pos (2U) +#define RTC_CRH_OWIE_Pos (2U) #define RTC_CRH_OWIE_Msk (0x1U << RTC_CRH_OWIE_Pos) /*!< 0x00000004 */ #define RTC_CRH_OWIE RTC_CRH_OWIE_Msk /*!< OverfloW Interrupt Enable */ /******************* Bit definition for RTC_CRL register ********************/ -#define RTC_CRL_SECF_Pos (0U) +#define RTC_CRL_SECF_Pos (0U) #define RTC_CRL_SECF_Msk (0x1U << RTC_CRL_SECF_Pos) /*!< 0x00000001 */ #define RTC_CRL_SECF RTC_CRL_SECF_Msk /*!< Second Flag */ -#define RTC_CRL_ALRF_Pos (1U) +#define RTC_CRL_ALRF_Pos (1U) #define RTC_CRL_ALRF_Msk (0x1U << RTC_CRL_ALRF_Pos) /*!< 0x00000002 */ #define RTC_CRL_ALRF RTC_CRL_ALRF_Msk /*!< Alarm Flag */ -#define RTC_CRL_OWF_Pos (2U) +#define RTC_CRL_OWF_Pos (2U) #define RTC_CRL_OWF_Msk (0x1U << RTC_CRL_OWF_Pos) /*!< 0x00000004 */ #define RTC_CRL_OWF RTC_CRL_OWF_Msk /*!< OverfloW Flag */ -#define RTC_CRL_RSF_Pos (3U) +#define RTC_CRL_RSF_Pos (3U) #define RTC_CRL_RSF_Msk (0x1U << RTC_CRL_RSF_Pos) /*!< 0x00000008 */ #define RTC_CRL_RSF RTC_CRL_RSF_Msk /*!< Registers Synchronized Flag */ -#define RTC_CRL_CNF_Pos (4U) +#define RTC_CRL_CNF_Pos (4U) #define RTC_CRL_CNF_Msk (0x1U << RTC_CRL_CNF_Pos) /*!< 0x00000010 */ #define RTC_CRL_CNF RTC_CRL_CNF_Msk /*!< Configuration Flag */ -#define RTC_CRL_RTOFF_Pos (5U) +#define RTC_CRL_RTOFF_Pos (5U) #define RTC_CRL_RTOFF_Msk (0x1U << RTC_CRL_RTOFF_Pos) /*!< 0x00000020 */ #define RTC_CRL_RTOFF RTC_CRL_RTOFF_Msk /*!< RTC operation OFF */ /******************* Bit definition for RTC_PRLH register *******************/ -#define RTC_PRLH_PRL_Pos (0U) +#define RTC_PRLH_PRL_Pos (0U) #define RTC_PRLH_PRL_Msk (0xFU << RTC_PRLH_PRL_Pos) /*!< 0x0000000F */ #define RTC_PRLH_PRL RTC_PRLH_PRL_Msk /*!< RTC Prescaler Reload Value High */ /******************* Bit definition for RTC_PRLL register *******************/ -#define RTC_PRLL_PRL_Pos (0U) +#define RTC_PRLL_PRL_Pos (0U) #define RTC_PRLL_PRL_Msk (0xFFFFU << RTC_PRLL_PRL_Pos) /*!< 0x0000FFFF */ #define RTC_PRLL_PRL RTC_PRLL_PRL_Msk /*!< RTC Prescaler Reload Value Low */ /******************* Bit definition for RTC_DIVH register *******************/ -#define RTC_DIVH_RTC_DIV_Pos (0U) +#define RTC_DIVH_RTC_DIV_Pos (0U) #define RTC_DIVH_RTC_DIV_Msk (0xFU << RTC_DIVH_RTC_DIV_Pos) /*!< 0x0000000F */ #define RTC_DIVH_RTC_DIV RTC_DIVH_RTC_DIV_Msk /*!< RTC Clock Divider High */ /******************* Bit definition for RTC_DIVL register *******************/ -#define RTC_DIVL_RTC_DIV_Pos (0U) +#define RTC_DIVL_RTC_DIV_Pos (0U) #define RTC_DIVL_RTC_DIV_Msk (0xFFFFU << RTC_DIVL_RTC_DIV_Pos) /*!< 0x0000FFFF */ #define RTC_DIVL_RTC_DIV RTC_DIVL_RTC_DIV_Msk /*!< RTC Clock Divider Low */ /******************* Bit definition for RTC_CNTH register *******************/ -#define RTC_CNTH_RTC_CNT_Pos (0U) +#define RTC_CNTH_RTC_CNT_Pos (0U) #define RTC_CNTH_RTC_CNT_Msk (0xFFFFU << RTC_CNTH_RTC_CNT_Pos) /*!< 0x0000FFFF */ #define RTC_CNTH_RTC_CNT RTC_CNTH_RTC_CNT_Msk /*!< RTC Counter High */ /******************* Bit definition for RTC_CNTL register *******************/ -#define RTC_CNTL_RTC_CNT_Pos (0U) +#define RTC_CNTL_RTC_CNT_Pos (0U) #define RTC_CNTL_RTC_CNT_Msk (0xFFFFU << RTC_CNTL_RTC_CNT_Pos) /*!< 0x0000FFFF */ #define RTC_CNTL_RTC_CNT RTC_CNTL_RTC_CNT_Msk /*!< RTC Counter Low */ /******************* Bit definition for RTC_ALRH register *******************/ -#define RTC_ALRH_RTC_ALR_Pos (0U) +#define RTC_ALRH_RTC_ALR_Pos (0U) #define RTC_ALRH_RTC_ALR_Msk (0xFFFFU << RTC_ALRH_RTC_ALR_Pos) /*!< 0x0000FFFF */ #define RTC_ALRH_RTC_ALR RTC_ALRH_RTC_ALR_Msk /*!< RTC Alarm High */ /******************* Bit definition for RTC_ALRL register *******************/ -#define RTC_ALRL_RTC_ALR_Pos (0U) +#define RTC_ALRL_RTC_ALR_Pos (0U) #define RTC_ALRL_RTC_ALR_Msk (0xFFFFU << RTC_ALRL_RTC_ALR_Pos) /*!< 0x0000FFFF */ #define RTC_ALRL_RTC_ALR RTC_ALRL_RTC_ALR_Msk /*!< RTC Alarm Low */ @@ -4859,12 +4859,12 @@ typedef struct /******************************************************************************/ /******************* Bit definition for IWDG_KR register ********************/ -#define IWDG_KR_KEY_Pos (0U) +#define IWDG_KR_KEY_Pos (0U) #define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */ #define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!< Key value (write only, read 0000h) */ /******************* Bit definition for IWDG_PR register ********************/ -#define IWDG_PR_PR_Pos (0U) +#define IWDG_PR_PR_Pos (0U) #define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */ #define IWDG_PR_PR IWDG_PR_PR_Msk /*!< PR[2:0] (Prescaler divider) */ #define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x00000001 */ @@ -4872,15 +4872,15 @@ typedef struct #define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x00000004 */ /******************* Bit definition for IWDG_RLR register *******************/ -#define IWDG_RLR_RL_Pos (0U) +#define IWDG_RLR_RL_Pos (0U) #define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */ #define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!< Watchdog counter reload value */ /******************* Bit definition for IWDG_SR register ********************/ -#define IWDG_SR_PVU_Pos (0U) +#define IWDG_SR_PVU_Pos (0U) #define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */ #define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */ -#define IWDG_SR_RVU_Pos (1U) +#define IWDG_SR_RVU_Pos (1U) #define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */ #define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */ @@ -4891,7 +4891,7 @@ typedef struct /******************************************************************************/ /******************* Bit definition for WWDG_CR register ********************/ -#define WWDG_CR_T_Pos (0U) +#define WWDG_CR_T_Pos (0U) #define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /*!< 0x0000007F */ #define WWDG_CR_T WWDG_CR_T_Msk /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */ #define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x00000001 */ @@ -4911,12 +4911,12 @@ typedef struct #define WWDG_CR_T5 WWDG_CR_T_5 #define WWDG_CR_T6 WWDG_CR_T_6 -#define WWDG_CR_WDGA_Pos (7U) +#define WWDG_CR_WDGA_Pos (7U) #define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */ #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!< Activation bit */ /******************* Bit definition for WWDG_CFR register *******************/ -#define WWDG_CFR_W_Pos (0U) +#define WWDG_CFR_W_Pos (0U) #define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /*!< 0x0000007F */ #define WWDG_CFR_W WWDG_CFR_W_Msk /*!< W[6:0] bits (7-bit window value) */ #define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x00000001 */ @@ -4936,7 +4936,7 @@ typedef struct #define WWDG_CFR_W5 WWDG_CFR_W_5 #define WWDG_CFR_W6 WWDG_CFR_W_6 -#define WWDG_CFR_WDGTB_Pos (7U) +#define WWDG_CFR_WDGTB_Pos (7U) #define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */ #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!< WDGTB[1:0] bits (Timer Base) */ #define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000080 */ @@ -4946,12 +4946,12 @@ typedef struct #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0 #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1 -#define WWDG_CFR_EWI_Pos (9U) +#define WWDG_CFR_EWI_Pos (9U) #define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */ #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!< Early Wakeup Interrupt */ /******************* Bit definition for WWDG_SR register ********************/ -#define WWDG_SR_EWIF_Pos (0U) +#define WWDG_SR_EWIF_Pos (0U) #define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */ #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!< Early Wakeup Interrupt Flag */ @@ -4963,132 +4963,132 @@ typedef struct /******************************************************************************/ /****************** Bit definition for SDIO_POWER register ******************/ -#define SDIO_POWER_PWRCTRL_Pos (0U) +#define SDIO_POWER_PWRCTRL_Pos (0U) #define SDIO_POWER_PWRCTRL_Msk (0x3U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x00000003 */ #define SDIO_POWER_PWRCTRL SDIO_POWER_PWRCTRL_Msk /*!< PWRCTRL[1:0] bits (Power supply control bits) */ #define SDIO_POWER_PWRCTRL_0 (0x1U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x01 */ #define SDIO_POWER_PWRCTRL_1 (0x2U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x02 */ /****************** Bit definition for SDIO_CLKCR register ******************/ -#define SDIO_CLKCR_CLKDIV_Pos (0U) +#define SDIO_CLKCR_CLKDIV_Pos (0U) #define SDIO_CLKCR_CLKDIV_Msk (0xFFU << SDIO_CLKCR_CLKDIV_Pos) /*!< 0x000000FF */ #define SDIO_CLKCR_CLKDIV SDIO_CLKCR_CLKDIV_Msk /*!< Clock divide factor */ -#define SDIO_CLKCR_CLKEN_Pos (8U) +#define SDIO_CLKCR_CLKEN_Pos (8U) #define SDIO_CLKCR_CLKEN_Msk (0x1U << SDIO_CLKCR_CLKEN_Pos) /*!< 0x00000100 */ #define SDIO_CLKCR_CLKEN SDIO_CLKCR_CLKEN_Msk /*!< Clock enable bit */ -#define SDIO_CLKCR_PWRSAV_Pos (9U) +#define SDIO_CLKCR_PWRSAV_Pos (9U) #define SDIO_CLKCR_PWRSAV_Msk (0x1U << SDIO_CLKCR_PWRSAV_Pos) /*!< 0x00000200 */ #define SDIO_CLKCR_PWRSAV SDIO_CLKCR_PWRSAV_Msk /*!< Power saving configuration bit */ -#define SDIO_CLKCR_BYPASS_Pos (10U) +#define SDIO_CLKCR_BYPASS_Pos (10U) #define SDIO_CLKCR_BYPASS_Msk (0x1U << SDIO_CLKCR_BYPASS_Pos) /*!< 0x00000400 */ #define SDIO_CLKCR_BYPASS SDIO_CLKCR_BYPASS_Msk /*!< Clock divider bypass enable bit */ -#define SDIO_CLKCR_WIDBUS_Pos (11U) +#define SDIO_CLKCR_WIDBUS_Pos (11U) #define SDIO_CLKCR_WIDBUS_Msk (0x3U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x00001800 */ #define SDIO_CLKCR_WIDBUS SDIO_CLKCR_WIDBUS_Msk /*!< WIDBUS[1:0] bits (Wide bus mode enable bit) */ #define SDIO_CLKCR_WIDBUS_0 (0x1U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x0800 */ #define SDIO_CLKCR_WIDBUS_1 (0x2U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x1000 */ -#define SDIO_CLKCR_NEGEDGE_Pos (13U) +#define SDIO_CLKCR_NEGEDGE_Pos (13U) #define SDIO_CLKCR_NEGEDGE_Msk (0x1U << SDIO_CLKCR_NEGEDGE_Pos) /*!< 0x00002000 */ #define SDIO_CLKCR_NEGEDGE SDIO_CLKCR_NEGEDGE_Msk /*!< SDIO_CK dephasing selection bit */ -#define SDIO_CLKCR_HWFC_EN_Pos (14U) +#define SDIO_CLKCR_HWFC_EN_Pos (14U) #define SDIO_CLKCR_HWFC_EN_Msk (0x1U << SDIO_CLKCR_HWFC_EN_Pos) /*!< 0x00004000 */ #define SDIO_CLKCR_HWFC_EN SDIO_CLKCR_HWFC_EN_Msk /*!< HW Flow Control enable */ /******************* Bit definition for SDIO_ARG register *******************/ -#define SDIO_ARG_CMDARG_Pos (0U) +#define SDIO_ARG_CMDARG_Pos (0U) #define SDIO_ARG_CMDARG_Msk (0xFFFFFFFFU << SDIO_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */ #define SDIO_ARG_CMDARG SDIO_ARG_CMDARG_Msk /*!< Command argument */ /******************* Bit definition for SDIO_CMD register *******************/ -#define SDIO_CMD_CMDINDEX_Pos (0U) +#define SDIO_CMD_CMDINDEX_Pos (0U) #define SDIO_CMD_CMDINDEX_Msk (0x3FU << SDIO_CMD_CMDINDEX_Pos) /*!< 0x0000003F */ #define SDIO_CMD_CMDINDEX SDIO_CMD_CMDINDEX_Msk /*!< Command Index */ -#define SDIO_CMD_WAITRESP_Pos (6U) +#define SDIO_CMD_WAITRESP_Pos (6U) #define SDIO_CMD_WAITRESP_Msk (0x3U << SDIO_CMD_WAITRESP_Pos) /*!< 0x000000C0 */ #define SDIO_CMD_WAITRESP SDIO_CMD_WAITRESP_Msk /*!< WAITRESP[1:0] bits (Wait for response bits) */ #define SDIO_CMD_WAITRESP_0 (0x1U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0040 */ #define SDIO_CMD_WAITRESP_1 (0x2U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0080 */ -#define SDIO_CMD_WAITINT_Pos (8U) +#define SDIO_CMD_WAITINT_Pos (8U) #define SDIO_CMD_WAITINT_Msk (0x1U << SDIO_CMD_WAITINT_Pos) /*!< 0x00000100 */ #define SDIO_CMD_WAITINT SDIO_CMD_WAITINT_Msk /*!< CPSM Waits for Interrupt Request */ -#define SDIO_CMD_WAITPEND_Pos (9U) +#define SDIO_CMD_WAITPEND_Pos (9U) #define SDIO_CMD_WAITPEND_Msk (0x1U << SDIO_CMD_WAITPEND_Pos) /*!< 0x00000200 */ #define SDIO_CMD_WAITPEND SDIO_CMD_WAITPEND_Msk /*!< CPSM Waits for ends of data transfer (CmdPend internal signal) */ -#define SDIO_CMD_CPSMEN_Pos (10U) +#define SDIO_CMD_CPSMEN_Pos (10U) #define SDIO_CMD_CPSMEN_Msk (0x1U << SDIO_CMD_CPSMEN_Pos) /*!< 0x00000400 */ #define SDIO_CMD_CPSMEN SDIO_CMD_CPSMEN_Msk /*!< Command path state machine (CPSM) Enable bit */ -#define SDIO_CMD_SDIOSUSPEND_Pos (11U) +#define SDIO_CMD_SDIOSUSPEND_Pos (11U) #define SDIO_CMD_SDIOSUSPEND_Msk (0x1U << SDIO_CMD_SDIOSUSPEND_Pos) /*!< 0x00000800 */ #define SDIO_CMD_SDIOSUSPEND SDIO_CMD_SDIOSUSPEND_Msk /*!< SD I/O suspend command */ -#define SDIO_CMD_ENCMDCOMPL_Pos (12U) +#define SDIO_CMD_ENCMDCOMPL_Pos (12U) #define SDIO_CMD_ENCMDCOMPL_Msk (0x1U << SDIO_CMD_ENCMDCOMPL_Pos) /*!< 0x00001000 */ #define SDIO_CMD_ENCMDCOMPL SDIO_CMD_ENCMDCOMPL_Msk /*!< Enable CMD completion */ -#define SDIO_CMD_NIEN_Pos (13U) +#define SDIO_CMD_NIEN_Pos (13U) #define SDIO_CMD_NIEN_Msk (0x1U << SDIO_CMD_NIEN_Pos) /*!< 0x00002000 */ #define SDIO_CMD_NIEN SDIO_CMD_NIEN_Msk /*!< Not Interrupt Enable */ -#define SDIO_CMD_CEATACMD_Pos (14U) +#define SDIO_CMD_CEATACMD_Pos (14U) #define SDIO_CMD_CEATACMD_Msk (0x1U << SDIO_CMD_CEATACMD_Pos) /*!< 0x00004000 */ #define SDIO_CMD_CEATACMD SDIO_CMD_CEATACMD_Msk /*!< CE-ATA command */ /***************** Bit definition for SDIO_RESPCMD register *****************/ -#define SDIO_RESPCMD_RESPCMD_Pos (0U) +#define SDIO_RESPCMD_RESPCMD_Pos (0U) #define SDIO_RESPCMD_RESPCMD_Msk (0x3FU << SDIO_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */ #define SDIO_RESPCMD_RESPCMD SDIO_RESPCMD_RESPCMD_Msk /*!< Response command index */ /****************** Bit definition for SDIO_RESP0 register ******************/ -#define SDIO_RESP0_CARDSTATUS0_Pos (0U) +#define SDIO_RESP0_CARDSTATUS0_Pos (0U) #define SDIO_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFU << SDIO_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */ #define SDIO_RESP0_CARDSTATUS0 SDIO_RESP0_CARDSTATUS0_Msk /*!< Card Status */ /****************** Bit definition for SDIO_RESP1 register ******************/ -#define SDIO_RESP1_CARDSTATUS1_Pos (0U) +#define SDIO_RESP1_CARDSTATUS1_Pos (0U) #define SDIO_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFU << SDIO_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */ #define SDIO_RESP1_CARDSTATUS1 SDIO_RESP1_CARDSTATUS1_Msk /*!< Card Status */ /****************** Bit definition for SDIO_RESP2 register ******************/ -#define SDIO_RESP2_CARDSTATUS2_Pos (0U) +#define SDIO_RESP2_CARDSTATUS2_Pos (0U) #define SDIO_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFU << SDIO_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */ #define SDIO_RESP2_CARDSTATUS2 SDIO_RESP2_CARDSTATUS2_Msk /*!< Card Status */ /****************** Bit definition for SDIO_RESP3 register ******************/ -#define SDIO_RESP3_CARDSTATUS3_Pos (0U) +#define SDIO_RESP3_CARDSTATUS3_Pos (0U) #define SDIO_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFU << SDIO_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */ #define SDIO_RESP3_CARDSTATUS3 SDIO_RESP3_CARDSTATUS3_Msk /*!< Card Status */ /****************** Bit definition for SDIO_RESP4 register ******************/ -#define SDIO_RESP4_CARDSTATUS4_Pos (0U) +#define SDIO_RESP4_CARDSTATUS4_Pos (0U) #define SDIO_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFU << SDIO_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */ #define SDIO_RESP4_CARDSTATUS4 SDIO_RESP4_CARDSTATUS4_Msk /*!< Card Status */ /****************** Bit definition for SDIO_DTIMER register *****************/ -#define SDIO_DTIMER_DATATIME_Pos (0U) +#define SDIO_DTIMER_DATATIME_Pos (0U) #define SDIO_DTIMER_DATATIME_Msk (0xFFFFFFFFU << SDIO_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */ #define SDIO_DTIMER_DATATIME SDIO_DTIMER_DATATIME_Msk /*!< Data timeout period. */ /****************** Bit definition for SDIO_DLEN register *******************/ -#define SDIO_DLEN_DATALENGTH_Pos (0U) +#define SDIO_DLEN_DATALENGTH_Pos (0U) #define SDIO_DLEN_DATALENGTH_Msk (0x1FFFFFFU << SDIO_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */ #define SDIO_DLEN_DATALENGTH SDIO_DLEN_DATALENGTH_Msk /*!< Data length value */ /****************** Bit definition for SDIO_DCTRL register ******************/ -#define SDIO_DCTRL_DTEN_Pos (0U) +#define SDIO_DCTRL_DTEN_Pos (0U) #define SDIO_DCTRL_DTEN_Msk (0x1U << SDIO_DCTRL_DTEN_Pos) /*!< 0x00000001 */ #define SDIO_DCTRL_DTEN SDIO_DCTRL_DTEN_Msk /*!< Data transfer enabled bit */ -#define SDIO_DCTRL_DTDIR_Pos (1U) +#define SDIO_DCTRL_DTDIR_Pos (1U) #define SDIO_DCTRL_DTDIR_Msk (0x1U << SDIO_DCTRL_DTDIR_Pos) /*!< 0x00000002 */ #define SDIO_DCTRL_DTDIR SDIO_DCTRL_DTDIR_Msk /*!< Data transfer direction selection */ -#define SDIO_DCTRL_DTMODE_Pos (2U) +#define SDIO_DCTRL_DTMODE_Pos (2U) #define SDIO_DCTRL_DTMODE_Msk (0x1U << SDIO_DCTRL_DTMODE_Pos) /*!< 0x00000004 */ #define SDIO_DCTRL_DTMODE SDIO_DCTRL_DTMODE_Msk /*!< Data transfer mode selection */ -#define SDIO_DCTRL_DMAEN_Pos (3U) +#define SDIO_DCTRL_DMAEN_Pos (3U) #define SDIO_DCTRL_DMAEN_Msk (0x1U << SDIO_DCTRL_DMAEN_Pos) /*!< 0x00000008 */ #define SDIO_DCTRL_DMAEN SDIO_DCTRL_DMAEN_Msk /*!< DMA enabled bit */ -#define SDIO_DCTRL_DBLOCKSIZE_Pos (4U) +#define SDIO_DCTRL_DBLOCKSIZE_Pos (4U) #define SDIO_DCTRL_DBLOCKSIZE_Msk (0xFU << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */ #define SDIO_DCTRL_DBLOCKSIZE SDIO_DCTRL_DBLOCKSIZE_Msk /*!< DBLOCKSIZE[3:0] bits (Data block size) */ #define SDIO_DCTRL_DBLOCKSIZE_0 (0x1U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0010 */ @@ -5096,220 +5096,220 @@ typedef struct #define SDIO_DCTRL_DBLOCKSIZE_2 (0x4U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0040 */ #define SDIO_DCTRL_DBLOCKSIZE_3 (0x8U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0080 */ -#define SDIO_DCTRL_RWSTART_Pos (8U) +#define SDIO_DCTRL_RWSTART_Pos (8U) #define SDIO_DCTRL_RWSTART_Msk (0x1U << SDIO_DCTRL_RWSTART_Pos) /*!< 0x00000100 */ #define SDIO_DCTRL_RWSTART SDIO_DCTRL_RWSTART_Msk /*!< Read wait start */ -#define SDIO_DCTRL_RWSTOP_Pos (9U) +#define SDIO_DCTRL_RWSTOP_Pos (9U) #define SDIO_DCTRL_RWSTOP_Msk (0x1U << SDIO_DCTRL_RWSTOP_Pos) /*!< 0x00000200 */ #define SDIO_DCTRL_RWSTOP SDIO_DCTRL_RWSTOP_Msk /*!< Read wait stop */ -#define SDIO_DCTRL_RWMOD_Pos (10U) +#define SDIO_DCTRL_RWMOD_Pos (10U) #define SDIO_DCTRL_RWMOD_Msk (0x1U << SDIO_DCTRL_RWMOD_Pos) /*!< 0x00000400 */ #define SDIO_DCTRL_RWMOD SDIO_DCTRL_RWMOD_Msk /*!< Read wait mode */ -#define SDIO_DCTRL_SDIOEN_Pos (11U) +#define SDIO_DCTRL_SDIOEN_Pos (11U) #define SDIO_DCTRL_SDIOEN_Msk (0x1U << SDIO_DCTRL_SDIOEN_Pos) /*!< 0x00000800 */ #define SDIO_DCTRL_SDIOEN SDIO_DCTRL_SDIOEN_Msk /*!< SD I/O enable functions */ /****************** Bit definition for SDIO_DCOUNT register *****************/ -#define SDIO_DCOUNT_DATACOUNT_Pos (0U) +#define SDIO_DCOUNT_DATACOUNT_Pos (0U) #define SDIO_DCOUNT_DATACOUNT_Msk (0x1FFFFFFU << SDIO_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */ #define SDIO_DCOUNT_DATACOUNT SDIO_DCOUNT_DATACOUNT_Msk /*!< Data count value */ /****************** Bit definition for SDIO_STA register ********************/ -#define SDIO_STA_CCRCFAIL_Pos (0U) +#define SDIO_STA_CCRCFAIL_Pos (0U) #define SDIO_STA_CCRCFAIL_Msk (0x1U << SDIO_STA_CCRCFAIL_Pos) /*!< 0x00000001 */ #define SDIO_STA_CCRCFAIL SDIO_STA_CCRCFAIL_Msk /*!< Command response received (CRC check failed) */ -#define SDIO_STA_DCRCFAIL_Pos (1U) +#define SDIO_STA_DCRCFAIL_Pos (1U) #define SDIO_STA_DCRCFAIL_Msk (0x1U << SDIO_STA_DCRCFAIL_Pos) /*!< 0x00000002 */ #define SDIO_STA_DCRCFAIL SDIO_STA_DCRCFAIL_Msk /*!< Data block sent/received (CRC check failed) */ -#define SDIO_STA_CTIMEOUT_Pos (2U) +#define SDIO_STA_CTIMEOUT_Pos (2U) #define SDIO_STA_CTIMEOUT_Msk (0x1U << SDIO_STA_CTIMEOUT_Pos) /*!< 0x00000004 */ #define SDIO_STA_CTIMEOUT SDIO_STA_CTIMEOUT_Msk /*!< Command response timeout */ -#define SDIO_STA_DTIMEOUT_Pos (3U) +#define SDIO_STA_DTIMEOUT_Pos (3U) #define SDIO_STA_DTIMEOUT_Msk (0x1U << SDIO_STA_DTIMEOUT_Pos) /*!< 0x00000008 */ #define SDIO_STA_DTIMEOUT SDIO_STA_DTIMEOUT_Msk /*!< Data timeout */ -#define SDIO_STA_TXUNDERR_Pos (4U) +#define SDIO_STA_TXUNDERR_Pos (4U) #define SDIO_STA_TXUNDERR_Msk (0x1U << SDIO_STA_TXUNDERR_Pos) /*!< 0x00000010 */ #define SDIO_STA_TXUNDERR SDIO_STA_TXUNDERR_Msk /*!< Transmit FIFO underrun error */ -#define SDIO_STA_RXOVERR_Pos (5U) +#define SDIO_STA_RXOVERR_Pos (5U) #define SDIO_STA_RXOVERR_Msk (0x1U << SDIO_STA_RXOVERR_Pos) /*!< 0x00000020 */ #define SDIO_STA_RXOVERR SDIO_STA_RXOVERR_Msk /*!< Received FIFO overrun error */ -#define SDIO_STA_CMDREND_Pos (6U) +#define SDIO_STA_CMDREND_Pos (6U) #define SDIO_STA_CMDREND_Msk (0x1U << SDIO_STA_CMDREND_Pos) /*!< 0x00000040 */ #define SDIO_STA_CMDREND SDIO_STA_CMDREND_Msk /*!< Command response received (CRC check passed) */ -#define SDIO_STA_CMDSENT_Pos (7U) +#define SDIO_STA_CMDSENT_Pos (7U) #define SDIO_STA_CMDSENT_Msk (0x1U << SDIO_STA_CMDSENT_Pos) /*!< 0x00000080 */ #define SDIO_STA_CMDSENT SDIO_STA_CMDSENT_Msk /*!< Command sent (no response required) */ -#define SDIO_STA_DATAEND_Pos (8U) +#define SDIO_STA_DATAEND_Pos (8U) #define SDIO_STA_DATAEND_Msk (0x1U << SDIO_STA_DATAEND_Pos) /*!< 0x00000100 */ #define SDIO_STA_DATAEND SDIO_STA_DATAEND_Msk /*!< Data end (data counter, SDIDCOUNT, is zero) */ -#define SDIO_STA_STBITERR_Pos (9U) +#define SDIO_STA_STBITERR_Pos (9U) #define SDIO_STA_STBITERR_Msk (0x1U << SDIO_STA_STBITERR_Pos) /*!< 0x00000200 */ #define SDIO_STA_STBITERR SDIO_STA_STBITERR_Msk /*!< Start bit not detected on all data signals in wide bus mode */ -#define SDIO_STA_DBCKEND_Pos (10U) +#define SDIO_STA_DBCKEND_Pos (10U) #define SDIO_STA_DBCKEND_Msk (0x1U << SDIO_STA_DBCKEND_Pos) /*!< 0x00000400 */ #define SDIO_STA_DBCKEND SDIO_STA_DBCKEND_Msk /*!< Data block sent/received (CRC check passed) */ -#define SDIO_STA_CMDACT_Pos (11U) +#define SDIO_STA_CMDACT_Pos (11U) #define SDIO_STA_CMDACT_Msk (0x1U << SDIO_STA_CMDACT_Pos) /*!< 0x00000800 */ #define SDIO_STA_CMDACT SDIO_STA_CMDACT_Msk /*!< Command transfer in progress */ -#define SDIO_STA_TXACT_Pos (12U) +#define SDIO_STA_TXACT_Pos (12U) #define SDIO_STA_TXACT_Msk (0x1U << SDIO_STA_TXACT_Pos) /*!< 0x00001000 */ #define SDIO_STA_TXACT SDIO_STA_TXACT_Msk /*!< Data transmit in progress */ -#define SDIO_STA_RXACT_Pos (13U) +#define SDIO_STA_RXACT_Pos (13U) #define SDIO_STA_RXACT_Msk (0x1U << SDIO_STA_RXACT_Pos) /*!< 0x00002000 */ #define SDIO_STA_RXACT SDIO_STA_RXACT_Msk /*!< Data receive in progress */ -#define SDIO_STA_TXFIFOHE_Pos (14U) +#define SDIO_STA_TXFIFOHE_Pos (14U) #define SDIO_STA_TXFIFOHE_Msk (0x1U << SDIO_STA_TXFIFOHE_Pos) /*!< 0x00004000 */ #define SDIO_STA_TXFIFOHE SDIO_STA_TXFIFOHE_Msk /*!< Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */ -#define SDIO_STA_RXFIFOHF_Pos (15U) +#define SDIO_STA_RXFIFOHF_Pos (15U) #define SDIO_STA_RXFIFOHF_Msk (0x1U << SDIO_STA_RXFIFOHF_Pos) /*!< 0x00008000 */ #define SDIO_STA_RXFIFOHF SDIO_STA_RXFIFOHF_Msk /*!< Receive FIFO Half Full: there are at least 8 words in the FIFO */ -#define SDIO_STA_TXFIFOF_Pos (16U) +#define SDIO_STA_TXFIFOF_Pos (16U) #define SDIO_STA_TXFIFOF_Msk (0x1U << SDIO_STA_TXFIFOF_Pos) /*!< 0x00010000 */ #define SDIO_STA_TXFIFOF SDIO_STA_TXFIFOF_Msk /*!< Transmit FIFO full */ -#define SDIO_STA_RXFIFOF_Pos (17U) +#define SDIO_STA_RXFIFOF_Pos (17U) #define SDIO_STA_RXFIFOF_Msk (0x1U << SDIO_STA_RXFIFOF_Pos) /*!< 0x00020000 */ #define SDIO_STA_RXFIFOF SDIO_STA_RXFIFOF_Msk /*!< Receive FIFO full */ -#define SDIO_STA_TXFIFOE_Pos (18U) +#define SDIO_STA_TXFIFOE_Pos (18U) #define SDIO_STA_TXFIFOE_Msk (0x1U << SDIO_STA_TXFIFOE_Pos) /*!< 0x00040000 */ #define SDIO_STA_TXFIFOE SDIO_STA_TXFIFOE_Msk /*!< Transmit FIFO empty */ -#define SDIO_STA_RXFIFOE_Pos (19U) +#define SDIO_STA_RXFIFOE_Pos (19U) #define SDIO_STA_RXFIFOE_Msk (0x1U << SDIO_STA_RXFIFOE_Pos) /*!< 0x00080000 */ #define SDIO_STA_RXFIFOE SDIO_STA_RXFIFOE_Msk /*!< Receive FIFO empty */ -#define SDIO_STA_TXDAVL_Pos (20U) +#define SDIO_STA_TXDAVL_Pos (20U) #define SDIO_STA_TXDAVL_Msk (0x1U << SDIO_STA_TXDAVL_Pos) /*!< 0x00100000 */ #define SDIO_STA_TXDAVL SDIO_STA_TXDAVL_Msk /*!< Data available in transmit FIFO */ -#define SDIO_STA_RXDAVL_Pos (21U) +#define SDIO_STA_RXDAVL_Pos (21U) #define SDIO_STA_RXDAVL_Msk (0x1U << SDIO_STA_RXDAVL_Pos) /*!< 0x00200000 */ #define SDIO_STA_RXDAVL SDIO_STA_RXDAVL_Msk /*!< Data available in receive FIFO */ -#define SDIO_STA_SDIOIT_Pos (22U) +#define SDIO_STA_SDIOIT_Pos (22U) #define SDIO_STA_SDIOIT_Msk (0x1U << SDIO_STA_SDIOIT_Pos) /*!< 0x00400000 */ #define SDIO_STA_SDIOIT SDIO_STA_SDIOIT_Msk /*!< SDIO interrupt received */ -#define SDIO_STA_CEATAEND_Pos (23U) +#define SDIO_STA_CEATAEND_Pos (23U) #define SDIO_STA_CEATAEND_Msk (0x1U << SDIO_STA_CEATAEND_Pos) /*!< 0x00800000 */ #define SDIO_STA_CEATAEND SDIO_STA_CEATAEND_Msk /*!< CE-ATA command completion signal received for CMD61 */ /******************* Bit definition for SDIO_ICR register *******************/ -#define SDIO_ICR_CCRCFAILC_Pos (0U) +#define SDIO_ICR_CCRCFAILC_Pos (0U) #define SDIO_ICR_CCRCFAILC_Msk (0x1U << SDIO_ICR_CCRCFAILC_Pos) /*!< 0x00000001 */ #define SDIO_ICR_CCRCFAILC SDIO_ICR_CCRCFAILC_Msk /*!< CCRCFAIL flag clear bit */ -#define SDIO_ICR_DCRCFAILC_Pos (1U) +#define SDIO_ICR_DCRCFAILC_Pos (1U) #define SDIO_ICR_DCRCFAILC_Msk (0x1U << SDIO_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */ #define SDIO_ICR_DCRCFAILC SDIO_ICR_DCRCFAILC_Msk /*!< DCRCFAIL flag clear bit */ -#define SDIO_ICR_CTIMEOUTC_Pos (2U) +#define SDIO_ICR_CTIMEOUTC_Pos (2U) #define SDIO_ICR_CTIMEOUTC_Msk (0x1U << SDIO_ICR_CTIMEOUTC_Pos) /*!< 0x00000004 */ #define SDIO_ICR_CTIMEOUTC SDIO_ICR_CTIMEOUTC_Msk /*!< CTIMEOUT flag clear bit */ -#define SDIO_ICR_DTIMEOUTC_Pos (3U) +#define SDIO_ICR_DTIMEOUTC_Pos (3U) #define SDIO_ICR_DTIMEOUTC_Msk (0x1U << SDIO_ICR_DTIMEOUTC_Pos) /*!< 0x00000008 */ #define SDIO_ICR_DTIMEOUTC SDIO_ICR_DTIMEOUTC_Msk /*!< DTIMEOUT flag clear bit */ -#define SDIO_ICR_TXUNDERRC_Pos (4U) +#define SDIO_ICR_TXUNDERRC_Pos (4U) #define SDIO_ICR_TXUNDERRC_Msk (0x1U << SDIO_ICR_TXUNDERRC_Pos) /*!< 0x00000010 */ #define SDIO_ICR_TXUNDERRC SDIO_ICR_TXUNDERRC_Msk /*!< TXUNDERR flag clear bit */ -#define SDIO_ICR_RXOVERRC_Pos (5U) +#define SDIO_ICR_RXOVERRC_Pos (5U) #define SDIO_ICR_RXOVERRC_Msk (0x1U << SDIO_ICR_RXOVERRC_Pos) /*!< 0x00000020 */ #define SDIO_ICR_RXOVERRC SDIO_ICR_RXOVERRC_Msk /*!< RXOVERR flag clear bit */ -#define SDIO_ICR_CMDRENDC_Pos (6U) +#define SDIO_ICR_CMDRENDC_Pos (6U) #define SDIO_ICR_CMDRENDC_Msk (0x1U << SDIO_ICR_CMDRENDC_Pos) /*!< 0x00000040 */ #define SDIO_ICR_CMDRENDC SDIO_ICR_CMDRENDC_Msk /*!< CMDREND flag clear bit */ -#define SDIO_ICR_CMDSENTC_Pos (7U) +#define SDIO_ICR_CMDSENTC_Pos (7U) #define SDIO_ICR_CMDSENTC_Msk (0x1U << SDIO_ICR_CMDSENTC_Pos) /*!< 0x00000080 */ #define SDIO_ICR_CMDSENTC SDIO_ICR_CMDSENTC_Msk /*!< CMDSENT flag clear bit */ -#define SDIO_ICR_DATAENDC_Pos (8U) +#define SDIO_ICR_DATAENDC_Pos (8U) #define SDIO_ICR_DATAENDC_Msk (0x1U << SDIO_ICR_DATAENDC_Pos) /*!< 0x00000100 */ #define SDIO_ICR_DATAENDC SDIO_ICR_DATAENDC_Msk /*!< DATAEND flag clear bit */ -#define SDIO_ICR_STBITERRC_Pos (9U) +#define SDIO_ICR_STBITERRC_Pos (9U) #define SDIO_ICR_STBITERRC_Msk (0x1U << SDIO_ICR_STBITERRC_Pos) /*!< 0x00000200 */ #define SDIO_ICR_STBITERRC SDIO_ICR_STBITERRC_Msk /*!< STBITERR flag clear bit */ -#define SDIO_ICR_DBCKENDC_Pos (10U) +#define SDIO_ICR_DBCKENDC_Pos (10U) #define SDIO_ICR_DBCKENDC_Msk (0x1U << SDIO_ICR_DBCKENDC_Pos) /*!< 0x00000400 */ #define SDIO_ICR_DBCKENDC SDIO_ICR_DBCKENDC_Msk /*!< DBCKEND flag clear bit */ -#define SDIO_ICR_SDIOITC_Pos (22U) +#define SDIO_ICR_SDIOITC_Pos (22U) #define SDIO_ICR_SDIOITC_Msk (0x1U << SDIO_ICR_SDIOITC_Pos) /*!< 0x00400000 */ #define SDIO_ICR_SDIOITC SDIO_ICR_SDIOITC_Msk /*!< SDIOIT flag clear bit */ -#define SDIO_ICR_CEATAENDC_Pos (23U) +#define SDIO_ICR_CEATAENDC_Pos (23U) #define SDIO_ICR_CEATAENDC_Msk (0x1U << SDIO_ICR_CEATAENDC_Pos) /*!< 0x00800000 */ #define SDIO_ICR_CEATAENDC SDIO_ICR_CEATAENDC_Msk /*!< CEATAEND flag clear bit */ /****************** Bit definition for SDIO_MASK register *******************/ -#define SDIO_MASK_CCRCFAILIE_Pos (0U) +#define SDIO_MASK_CCRCFAILIE_Pos (0U) #define SDIO_MASK_CCRCFAILIE_Msk (0x1U << SDIO_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */ #define SDIO_MASK_CCRCFAILIE SDIO_MASK_CCRCFAILIE_Msk /*!< Command CRC Fail Interrupt Enable */ -#define SDIO_MASK_DCRCFAILIE_Pos (1U) +#define SDIO_MASK_DCRCFAILIE_Pos (1U) #define SDIO_MASK_DCRCFAILIE_Msk (0x1U << SDIO_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */ #define SDIO_MASK_DCRCFAILIE SDIO_MASK_DCRCFAILIE_Msk /*!< Data CRC Fail Interrupt Enable */ -#define SDIO_MASK_CTIMEOUTIE_Pos (2U) +#define SDIO_MASK_CTIMEOUTIE_Pos (2U) #define SDIO_MASK_CTIMEOUTIE_Msk (0x1U << SDIO_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */ #define SDIO_MASK_CTIMEOUTIE SDIO_MASK_CTIMEOUTIE_Msk /*!< Command TimeOut Interrupt Enable */ -#define SDIO_MASK_DTIMEOUTIE_Pos (3U) +#define SDIO_MASK_DTIMEOUTIE_Pos (3U) #define SDIO_MASK_DTIMEOUTIE_Msk (0x1U << SDIO_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */ #define SDIO_MASK_DTIMEOUTIE SDIO_MASK_DTIMEOUTIE_Msk /*!< Data TimeOut Interrupt Enable */ -#define SDIO_MASK_TXUNDERRIE_Pos (4U) +#define SDIO_MASK_TXUNDERRIE_Pos (4U) #define SDIO_MASK_TXUNDERRIE_Msk (0x1U << SDIO_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */ #define SDIO_MASK_TXUNDERRIE SDIO_MASK_TXUNDERRIE_Msk /*!< Tx FIFO UnderRun Error Interrupt Enable */ -#define SDIO_MASK_RXOVERRIE_Pos (5U) +#define SDIO_MASK_RXOVERRIE_Pos (5U) #define SDIO_MASK_RXOVERRIE_Msk (0x1U << SDIO_MASK_RXOVERRIE_Pos) /*!< 0x00000020 */ #define SDIO_MASK_RXOVERRIE SDIO_MASK_RXOVERRIE_Msk /*!< Rx FIFO OverRun Error Interrupt Enable */ -#define SDIO_MASK_CMDRENDIE_Pos (6U) +#define SDIO_MASK_CMDRENDIE_Pos (6U) #define SDIO_MASK_CMDRENDIE_Msk (0x1U << SDIO_MASK_CMDRENDIE_Pos) /*!< 0x00000040 */ #define SDIO_MASK_CMDRENDIE SDIO_MASK_CMDRENDIE_Msk /*!< Command Response Received Interrupt Enable */ -#define SDIO_MASK_CMDSENTIE_Pos (7U) +#define SDIO_MASK_CMDSENTIE_Pos (7U) #define SDIO_MASK_CMDSENTIE_Msk (0x1U << SDIO_MASK_CMDSENTIE_Pos) /*!< 0x00000080 */ #define SDIO_MASK_CMDSENTIE SDIO_MASK_CMDSENTIE_Msk /*!< Command Sent Interrupt Enable */ -#define SDIO_MASK_DATAENDIE_Pos (8U) +#define SDIO_MASK_DATAENDIE_Pos (8U) #define SDIO_MASK_DATAENDIE_Msk (0x1U << SDIO_MASK_DATAENDIE_Pos) /*!< 0x00000100 */ #define SDIO_MASK_DATAENDIE SDIO_MASK_DATAENDIE_Msk /*!< Data End Interrupt Enable */ -#define SDIO_MASK_STBITERRIE_Pos (9U) +#define SDIO_MASK_STBITERRIE_Pos (9U) #define SDIO_MASK_STBITERRIE_Msk (0x1U << SDIO_MASK_STBITERRIE_Pos) /*!< 0x00000200 */ #define SDIO_MASK_STBITERRIE SDIO_MASK_STBITERRIE_Msk /*!< Start Bit Error Interrupt Enable */ -#define SDIO_MASK_DBCKENDIE_Pos (10U) +#define SDIO_MASK_DBCKENDIE_Pos (10U) #define SDIO_MASK_DBCKENDIE_Msk (0x1U << SDIO_MASK_DBCKENDIE_Pos) /*!< 0x00000400 */ #define SDIO_MASK_DBCKENDIE SDIO_MASK_DBCKENDIE_Msk /*!< Data Block End Interrupt Enable */ -#define SDIO_MASK_CMDACTIE_Pos (11U) +#define SDIO_MASK_CMDACTIE_Pos (11U) #define SDIO_MASK_CMDACTIE_Msk (0x1U << SDIO_MASK_CMDACTIE_Pos) /*!< 0x00000800 */ #define SDIO_MASK_CMDACTIE SDIO_MASK_CMDACTIE_Msk /*!< Command Acting Interrupt Enable */ -#define SDIO_MASK_TXACTIE_Pos (12U) +#define SDIO_MASK_TXACTIE_Pos (12U) #define SDIO_MASK_TXACTIE_Msk (0x1U << SDIO_MASK_TXACTIE_Pos) /*!< 0x00001000 */ #define SDIO_MASK_TXACTIE SDIO_MASK_TXACTIE_Msk /*!< Data Transmit Acting Interrupt Enable */ -#define SDIO_MASK_RXACTIE_Pos (13U) +#define SDIO_MASK_RXACTIE_Pos (13U) #define SDIO_MASK_RXACTIE_Msk (0x1U << SDIO_MASK_RXACTIE_Pos) /*!< 0x00002000 */ #define SDIO_MASK_RXACTIE SDIO_MASK_RXACTIE_Msk /*!< Data receive acting interrupt enabled */ -#define SDIO_MASK_TXFIFOHEIE_Pos (14U) +#define SDIO_MASK_TXFIFOHEIE_Pos (14U) #define SDIO_MASK_TXFIFOHEIE_Msk (0x1U << SDIO_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */ #define SDIO_MASK_TXFIFOHEIE SDIO_MASK_TXFIFOHEIE_Msk /*!< Tx FIFO Half Empty interrupt Enable */ -#define SDIO_MASK_RXFIFOHFIE_Pos (15U) +#define SDIO_MASK_RXFIFOHFIE_Pos (15U) #define SDIO_MASK_RXFIFOHFIE_Msk (0x1U << SDIO_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */ #define SDIO_MASK_RXFIFOHFIE SDIO_MASK_RXFIFOHFIE_Msk /*!< Rx FIFO Half Full interrupt Enable */ -#define SDIO_MASK_TXFIFOFIE_Pos (16U) +#define SDIO_MASK_TXFIFOFIE_Pos (16U) #define SDIO_MASK_TXFIFOFIE_Msk (0x1U << SDIO_MASK_TXFIFOFIE_Pos) /*!< 0x00010000 */ #define SDIO_MASK_TXFIFOFIE SDIO_MASK_TXFIFOFIE_Msk /*!< Tx FIFO Full interrupt Enable */ -#define SDIO_MASK_RXFIFOFIE_Pos (17U) +#define SDIO_MASK_RXFIFOFIE_Pos (17U) #define SDIO_MASK_RXFIFOFIE_Msk (0x1U << SDIO_MASK_RXFIFOFIE_Pos) /*!< 0x00020000 */ #define SDIO_MASK_RXFIFOFIE SDIO_MASK_RXFIFOFIE_Msk /*!< Rx FIFO Full interrupt Enable */ -#define SDIO_MASK_TXFIFOEIE_Pos (18U) +#define SDIO_MASK_TXFIFOEIE_Pos (18U) #define SDIO_MASK_TXFIFOEIE_Msk (0x1U << SDIO_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */ #define SDIO_MASK_TXFIFOEIE SDIO_MASK_TXFIFOEIE_Msk /*!< Tx FIFO Empty interrupt Enable */ -#define SDIO_MASK_RXFIFOEIE_Pos (19U) +#define SDIO_MASK_RXFIFOEIE_Pos (19U) #define SDIO_MASK_RXFIFOEIE_Msk (0x1U << SDIO_MASK_RXFIFOEIE_Pos) /*!< 0x00080000 */ #define SDIO_MASK_RXFIFOEIE SDIO_MASK_RXFIFOEIE_Msk /*!< Rx FIFO Empty interrupt Enable */ -#define SDIO_MASK_TXDAVLIE_Pos (20U) +#define SDIO_MASK_TXDAVLIE_Pos (20U) #define SDIO_MASK_TXDAVLIE_Msk (0x1U << SDIO_MASK_TXDAVLIE_Pos) /*!< 0x00100000 */ #define SDIO_MASK_TXDAVLIE SDIO_MASK_TXDAVLIE_Msk /*!< Data available in Tx FIFO interrupt Enable */ -#define SDIO_MASK_RXDAVLIE_Pos (21U) +#define SDIO_MASK_RXDAVLIE_Pos (21U) #define SDIO_MASK_RXDAVLIE_Msk (0x1U << SDIO_MASK_RXDAVLIE_Pos) /*!< 0x00200000 */ #define SDIO_MASK_RXDAVLIE SDIO_MASK_RXDAVLIE_Msk /*!< Data available in Rx FIFO interrupt Enable */ -#define SDIO_MASK_SDIOITIE_Pos (22U) +#define SDIO_MASK_SDIOITIE_Pos (22U) #define SDIO_MASK_SDIOITIE_Msk (0x1U << SDIO_MASK_SDIOITIE_Pos) /*!< 0x00400000 */ #define SDIO_MASK_SDIOITIE SDIO_MASK_SDIOITIE_Msk /*!< SDIO Mode Interrupt Received interrupt Enable */ -#define SDIO_MASK_CEATAENDIE_Pos (23U) +#define SDIO_MASK_CEATAENDIE_Pos (23U) #define SDIO_MASK_CEATAENDIE_Msk (0x1U << SDIO_MASK_CEATAENDIE_Pos) /*!< 0x00800000 */ #define SDIO_MASK_CEATAENDIE SDIO_MASK_CEATAENDIE_Msk /*!< CE-ATA command completion signal received Interrupt Enable */ /***************** Bit definition for SDIO_FIFOCNT register *****************/ -#define SDIO_FIFOCNT_FIFOCOUNT_Pos (0U) +#define SDIO_FIFOCNT_FIFOCOUNT_Pos (0U) #define SDIO_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFU << SDIO_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */ #define SDIO_FIFOCNT_FIFOCOUNT SDIO_FIFOCNT_FIFOCOUNT_Msk /*!< Remaining number of words to be written to or read from the FIFO */ /****************** Bit definition for SDIO_FIFO register *******************/ -#define SDIO_FIFO_FIFODATA_Pos (0U) +#define SDIO_FIFO_FIFODATA_Pos (0U) #define SDIO_FIFO_FIFODATA_Msk (0xFFFFFFFFU << SDIO_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */ #define SDIO_FIFO_FIFODATA SDIO_FIFO_FIFODATA_Msk /*!< Receive and transmit FIFO data */ @@ -5329,42 +5329,42 @@ typedef struct #define USB_EP6R (USB_BASE + 0x00000018) /*!< Endpoint 6 register address */ #define USB_EP7R (USB_BASE + 0x0000001C) /*!< Endpoint 7 register address */ -/* bit positions */ -#define USB_EP_CTR_RX_Pos (15U) +/* bit positions */ +#define USB_EP_CTR_RX_Pos (15U) #define USB_EP_CTR_RX_Msk (0x1U << USB_EP_CTR_RX_Pos) /*!< 0x00008000 */ #define USB_EP_CTR_RX USB_EP_CTR_RX_Msk /*!< EndPoint Correct TRansfer RX */ -#define USB_EP_DTOG_RX_Pos (14U) +#define USB_EP_DTOG_RX_Pos (14U) #define USB_EP_DTOG_RX_Msk (0x1U << USB_EP_DTOG_RX_Pos) /*!< 0x00004000 */ #define USB_EP_DTOG_RX USB_EP_DTOG_RX_Msk /*!< EndPoint Data TOGGLE RX */ -#define USB_EPRX_STAT_Pos (12U) +#define USB_EPRX_STAT_Pos (12U) #define USB_EPRX_STAT_Msk (0x3U << USB_EPRX_STAT_Pos) /*!< 0x00003000 */ #define USB_EPRX_STAT USB_EPRX_STAT_Msk /*!< EndPoint RX STATus bit field */ -#define USB_EP_SETUP_Pos (11U) +#define USB_EP_SETUP_Pos (11U) #define USB_EP_SETUP_Msk (0x1U << USB_EP_SETUP_Pos) /*!< 0x00000800 */ #define USB_EP_SETUP USB_EP_SETUP_Msk /*!< EndPoint SETUP */ -#define USB_EP_T_FIELD_Pos (9U) +#define USB_EP_T_FIELD_Pos (9U) #define USB_EP_T_FIELD_Msk (0x3U << USB_EP_T_FIELD_Pos) /*!< 0x00000600 */ #define USB_EP_T_FIELD USB_EP_T_FIELD_Msk /*!< EndPoint TYPE */ -#define USB_EP_KIND_Pos (8U) +#define USB_EP_KIND_Pos (8U) #define USB_EP_KIND_Msk (0x1U << USB_EP_KIND_Pos) /*!< 0x00000100 */ #define USB_EP_KIND USB_EP_KIND_Msk /*!< EndPoint KIND */ -#define USB_EP_CTR_TX_Pos (7U) +#define USB_EP_CTR_TX_Pos (7U) #define USB_EP_CTR_TX_Msk (0x1U << USB_EP_CTR_TX_Pos) /*!< 0x00000080 */ #define USB_EP_CTR_TX USB_EP_CTR_TX_Msk /*!< EndPoint Correct TRansfer TX */ -#define USB_EP_DTOG_TX_Pos (6U) +#define USB_EP_DTOG_TX_Pos (6U) #define USB_EP_DTOG_TX_Msk (0x1U << USB_EP_DTOG_TX_Pos) /*!< 0x00000040 */ #define USB_EP_DTOG_TX USB_EP_DTOG_TX_Msk /*!< EndPoint Data TOGGLE TX */ -#define USB_EPTX_STAT_Pos (4U) +#define USB_EPTX_STAT_Pos (4U) #define USB_EPTX_STAT_Msk (0x3U << USB_EPTX_STAT_Pos) /*!< 0x00000030 */ #define USB_EPTX_STAT USB_EPTX_STAT_Msk /*!< EndPoint TX STATus bit field */ -#define USB_EPADDR_FIELD_Pos (0U) +#define USB_EPADDR_FIELD_Pos (0U) #define USB_EPADDR_FIELD_Msk (0xFU << USB_EPADDR_FIELD_Pos) /*!< 0x0000000F */ #define USB_EPADDR_FIELD USB_EPADDR_FIELD_Msk /*!< EndPoint ADDRess FIELD */ /* EndPoint REGister MASK (no toggle fields) */ #define USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD) /*!< EP_TYPE[1:0] EndPoint TYPE */ -#define USB_EP_TYPE_MASK_Pos (9U) +#define USB_EP_TYPE_MASK_Pos (9U) #define USB_EP_TYPE_MASK_Msk (0x3U << USB_EP_TYPE_MASK_Pos) /*!< 0x00000600 */ #define USB_EP_TYPE_MASK USB_EP_TYPE_MASK_Msk /*!< EndPoint TYPE Mask */ #define USB_EP_BULK ((uint32_t)0x00000000) /*!< EndPoint BULK */ @@ -5372,7 +5372,7 @@ typedef struct #define USB_EP_ISOCHRONOUS ((uint32_t)0x00000400) /*!< EndPoint ISOCHRONOUS */ #define USB_EP_INTERRUPT ((uint32_t)0x00000600) /*!< EndPoint INTERRUPT */ #define USB_EP_T_MASK (~USB_EP_T_FIELD & USB_EPREG_MASK) - + #define USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */ /*!< STAT_TX[1:0] STATus for TX transfer */ #define USB_EP_TX_DIS ((uint32_t)0x00000000) /*!< EndPoint TX DISabled */ @@ -5392,563 +5392,563 @@ typedef struct #define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK) /******************* Bit definition for USB_EP0R register *******************/ -#define USB_EP0R_EA_Pos (0U) +#define USB_EP0R_EA_Pos (0U) #define USB_EP0R_EA_Msk (0xFU << USB_EP0R_EA_Pos) /*!< 0x0000000F */ #define USB_EP0R_EA USB_EP0R_EA_Msk /*!< Endpoint Address */ -#define USB_EP0R_STAT_TX_Pos (4U) +#define USB_EP0R_STAT_TX_Pos (4U) #define USB_EP0R_STAT_TX_Msk (0x3U << USB_EP0R_STAT_TX_Pos) /*!< 0x00000030 */ #define USB_EP0R_STAT_TX USB_EP0R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ #define USB_EP0R_STAT_TX_0 (0x1U << USB_EP0R_STAT_TX_Pos) /*!< 0x00000010 */ #define USB_EP0R_STAT_TX_1 (0x2U << USB_EP0R_STAT_TX_Pos) /*!< 0x00000020 */ -#define USB_EP0R_DTOG_TX_Pos (6U) +#define USB_EP0R_DTOG_TX_Pos (6U) #define USB_EP0R_DTOG_TX_Msk (0x1U << USB_EP0R_DTOG_TX_Pos) /*!< 0x00000040 */ #define USB_EP0R_DTOG_TX USB_EP0R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */ -#define USB_EP0R_CTR_TX_Pos (7U) +#define USB_EP0R_CTR_TX_Pos (7U) #define USB_EP0R_CTR_TX_Msk (0x1U << USB_EP0R_CTR_TX_Pos) /*!< 0x00000080 */ #define USB_EP0R_CTR_TX USB_EP0R_CTR_TX_Msk /*!< Correct Transfer for transmission */ -#define USB_EP0R_EP_KIND_Pos (8U) +#define USB_EP0R_EP_KIND_Pos (8U) #define USB_EP0R_EP_KIND_Msk (0x1U << USB_EP0R_EP_KIND_Pos) /*!< 0x00000100 */ #define USB_EP0R_EP_KIND USB_EP0R_EP_KIND_Msk /*!< Endpoint Kind */ - -#define USB_EP0R_EP_TYPE_Pos (9U) + +#define USB_EP0R_EP_TYPE_Pos (9U) #define USB_EP0R_EP_TYPE_Msk (0x3U << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000600 */ #define USB_EP0R_EP_TYPE USB_EP0R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */ #define USB_EP0R_EP_TYPE_0 (0x1U << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000200 */ #define USB_EP0R_EP_TYPE_1 (0x2U << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000400 */ -#define USB_EP0R_SETUP_Pos (11U) +#define USB_EP0R_SETUP_Pos (11U) #define USB_EP0R_SETUP_Msk (0x1U << USB_EP0R_SETUP_Pos) /*!< 0x00000800 */ #define USB_EP0R_SETUP USB_EP0R_SETUP_Msk /*!< Setup transaction completed */ -#define USB_EP0R_STAT_RX_Pos (12U) +#define USB_EP0R_STAT_RX_Pos (12U) #define USB_EP0R_STAT_RX_Msk (0x3U << USB_EP0R_STAT_RX_Pos) /*!< 0x00003000 */ #define USB_EP0R_STAT_RX USB_EP0R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ #define USB_EP0R_STAT_RX_0 (0x1U << USB_EP0R_STAT_RX_Pos) /*!< 0x00001000 */ #define USB_EP0R_STAT_RX_1 (0x2U << USB_EP0R_STAT_RX_Pos) /*!< 0x00002000 */ -#define USB_EP0R_DTOG_RX_Pos (14U) +#define USB_EP0R_DTOG_RX_Pos (14U) #define USB_EP0R_DTOG_RX_Msk (0x1U << USB_EP0R_DTOG_RX_Pos) /*!< 0x00004000 */ #define USB_EP0R_DTOG_RX USB_EP0R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */ -#define USB_EP0R_CTR_RX_Pos (15U) +#define USB_EP0R_CTR_RX_Pos (15U) #define USB_EP0R_CTR_RX_Msk (0x1U << USB_EP0R_CTR_RX_Pos) /*!< 0x00008000 */ #define USB_EP0R_CTR_RX USB_EP0R_CTR_RX_Msk /*!< Correct Transfer for reception */ /******************* Bit definition for USB_EP1R register *******************/ -#define USB_EP1R_EA_Pos (0U) +#define USB_EP1R_EA_Pos (0U) #define USB_EP1R_EA_Msk (0xFU << USB_EP1R_EA_Pos) /*!< 0x0000000F */ #define USB_EP1R_EA USB_EP1R_EA_Msk /*!< Endpoint Address */ - -#define USB_EP1R_STAT_TX_Pos (4U) + +#define USB_EP1R_STAT_TX_Pos (4U) #define USB_EP1R_STAT_TX_Msk (0x3U << USB_EP1R_STAT_TX_Pos) /*!< 0x00000030 */ #define USB_EP1R_STAT_TX USB_EP1R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ #define USB_EP1R_STAT_TX_0 (0x1U << USB_EP1R_STAT_TX_Pos) /*!< 0x00000010 */ #define USB_EP1R_STAT_TX_1 (0x2U << USB_EP1R_STAT_TX_Pos) /*!< 0x00000020 */ -#define USB_EP1R_DTOG_TX_Pos (6U) +#define USB_EP1R_DTOG_TX_Pos (6U) #define USB_EP1R_DTOG_TX_Msk (0x1U << USB_EP1R_DTOG_TX_Pos) /*!< 0x00000040 */ #define USB_EP1R_DTOG_TX USB_EP1R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */ -#define USB_EP1R_CTR_TX_Pos (7U) +#define USB_EP1R_CTR_TX_Pos (7U) #define USB_EP1R_CTR_TX_Msk (0x1U << USB_EP1R_CTR_TX_Pos) /*!< 0x00000080 */ #define USB_EP1R_CTR_TX USB_EP1R_CTR_TX_Msk /*!< Correct Transfer for transmission */ -#define USB_EP1R_EP_KIND_Pos (8U) +#define USB_EP1R_EP_KIND_Pos (8U) #define USB_EP1R_EP_KIND_Msk (0x1U << USB_EP1R_EP_KIND_Pos) /*!< 0x00000100 */ #define USB_EP1R_EP_KIND USB_EP1R_EP_KIND_Msk /*!< Endpoint Kind */ -#define USB_EP1R_EP_TYPE_Pos (9U) +#define USB_EP1R_EP_TYPE_Pos (9U) #define USB_EP1R_EP_TYPE_Msk (0x3U << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000600 */ #define USB_EP1R_EP_TYPE USB_EP1R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */ #define USB_EP1R_EP_TYPE_0 (0x1U << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000200 */ #define USB_EP1R_EP_TYPE_1 (0x2U << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000400 */ -#define USB_EP1R_SETUP_Pos (11U) +#define USB_EP1R_SETUP_Pos (11U) #define USB_EP1R_SETUP_Msk (0x1U << USB_EP1R_SETUP_Pos) /*!< 0x00000800 */ #define USB_EP1R_SETUP USB_EP1R_SETUP_Msk /*!< Setup transaction completed */ - -#define USB_EP1R_STAT_RX_Pos (12U) + +#define USB_EP1R_STAT_RX_Pos (12U) #define USB_EP1R_STAT_RX_Msk (0x3U << USB_EP1R_STAT_RX_Pos) /*!< 0x00003000 */ #define USB_EP1R_STAT_RX USB_EP1R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ #define USB_EP1R_STAT_RX_0 (0x1U << USB_EP1R_STAT_RX_Pos) /*!< 0x00001000 */ #define USB_EP1R_STAT_RX_1 (0x2U << USB_EP1R_STAT_RX_Pos) /*!< 0x00002000 */ -#define USB_EP1R_DTOG_RX_Pos (14U) +#define USB_EP1R_DTOG_RX_Pos (14U) #define USB_EP1R_DTOG_RX_Msk (0x1U << USB_EP1R_DTOG_RX_Pos) /*!< 0x00004000 */ #define USB_EP1R_DTOG_RX USB_EP1R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */ -#define USB_EP1R_CTR_RX_Pos (15U) +#define USB_EP1R_CTR_RX_Pos (15U) #define USB_EP1R_CTR_RX_Msk (0x1U << USB_EP1R_CTR_RX_Pos) /*!< 0x00008000 */ #define USB_EP1R_CTR_RX USB_EP1R_CTR_RX_Msk /*!< Correct Transfer for reception */ /******************* Bit definition for USB_EP2R register *******************/ -#define USB_EP2R_EA_Pos (0U) +#define USB_EP2R_EA_Pos (0U) #define USB_EP2R_EA_Msk (0xFU << USB_EP2R_EA_Pos) /*!< 0x0000000F */ #define USB_EP2R_EA USB_EP2R_EA_Msk /*!< Endpoint Address */ -#define USB_EP2R_STAT_TX_Pos (4U) +#define USB_EP2R_STAT_TX_Pos (4U) #define USB_EP2R_STAT_TX_Msk (0x3U << USB_EP2R_STAT_TX_Pos) /*!< 0x00000030 */ #define USB_EP2R_STAT_TX USB_EP2R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ #define USB_EP2R_STAT_TX_0 (0x1U << USB_EP2R_STAT_TX_Pos) /*!< 0x00000010 */ #define USB_EP2R_STAT_TX_1 (0x2U << USB_EP2R_STAT_TX_Pos) /*!< 0x00000020 */ -#define USB_EP2R_DTOG_TX_Pos (6U) +#define USB_EP2R_DTOG_TX_Pos (6U) #define USB_EP2R_DTOG_TX_Msk (0x1U << USB_EP2R_DTOG_TX_Pos) /*!< 0x00000040 */ #define USB_EP2R_DTOG_TX USB_EP2R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */ -#define USB_EP2R_CTR_TX_Pos (7U) +#define USB_EP2R_CTR_TX_Pos (7U) #define USB_EP2R_CTR_TX_Msk (0x1U << USB_EP2R_CTR_TX_Pos) /*!< 0x00000080 */ #define USB_EP2R_CTR_TX USB_EP2R_CTR_TX_Msk /*!< Correct Transfer for transmission */ -#define USB_EP2R_EP_KIND_Pos (8U) +#define USB_EP2R_EP_KIND_Pos (8U) #define USB_EP2R_EP_KIND_Msk (0x1U << USB_EP2R_EP_KIND_Pos) /*!< 0x00000100 */ #define USB_EP2R_EP_KIND USB_EP2R_EP_KIND_Msk /*!< Endpoint Kind */ -#define USB_EP2R_EP_TYPE_Pos (9U) +#define USB_EP2R_EP_TYPE_Pos (9U) #define USB_EP2R_EP_TYPE_Msk (0x3U << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000600 */ #define USB_EP2R_EP_TYPE USB_EP2R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */ #define USB_EP2R_EP_TYPE_0 (0x1U << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000200 */ #define USB_EP2R_EP_TYPE_1 (0x2U << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000400 */ -#define USB_EP2R_SETUP_Pos (11U) +#define USB_EP2R_SETUP_Pos (11U) #define USB_EP2R_SETUP_Msk (0x1U << USB_EP2R_SETUP_Pos) /*!< 0x00000800 */ #define USB_EP2R_SETUP USB_EP2R_SETUP_Msk /*!< Setup transaction completed */ -#define USB_EP2R_STAT_RX_Pos (12U) +#define USB_EP2R_STAT_RX_Pos (12U) #define USB_EP2R_STAT_RX_Msk (0x3U << USB_EP2R_STAT_RX_Pos) /*!< 0x00003000 */ #define USB_EP2R_STAT_RX USB_EP2R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ #define USB_EP2R_STAT_RX_0 (0x1U << USB_EP2R_STAT_RX_Pos) /*!< 0x00001000 */ #define USB_EP2R_STAT_RX_1 (0x2U << USB_EP2R_STAT_RX_Pos) /*!< 0x00002000 */ -#define USB_EP2R_DTOG_RX_Pos (14U) +#define USB_EP2R_DTOG_RX_Pos (14U) #define USB_EP2R_DTOG_RX_Msk (0x1U << USB_EP2R_DTOG_RX_Pos) /*!< 0x00004000 */ #define USB_EP2R_DTOG_RX USB_EP2R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */ -#define USB_EP2R_CTR_RX_Pos (15U) +#define USB_EP2R_CTR_RX_Pos (15U) #define USB_EP2R_CTR_RX_Msk (0x1U << USB_EP2R_CTR_RX_Pos) /*!< 0x00008000 */ #define USB_EP2R_CTR_RX USB_EP2R_CTR_RX_Msk /*!< Correct Transfer for reception */ /******************* Bit definition for USB_EP3R register *******************/ -#define USB_EP3R_EA_Pos (0U) +#define USB_EP3R_EA_Pos (0U) #define USB_EP3R_EA_Msk (0xFU << USB_EP3R_EA_Pos) /*!< 0x0000000F */ #define USB_EP3R_EA USB_EP3R_EA_Msk /*!< Endpoint Address */ -#define USB_EP3R_STAT_TX_Pos (4U) +#define USB_EP3R_STAT_TX_Pos (4U) #define USB_EP3R_STAT_TX_Msk (0x3U << USB_EP3R_STAT_TX_Pos) /*!< 0x00000030 */ #define USB_EP3R_STAT_TX USB_EP3R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ #define USB_EP3R_STAT_TX_0 (0x1U << USB_EP3R_STAT_TX_Pos) /*!< 0x00000010 */ #define USB_EP3R_STAT_TX_1 (0x2U << USB_EP3R_STAT_TX_Pos) /*!< 0x00000020 */ -#define USB_EP3R_DTOG_TX_Pos (6U) +#define USB_EP3R_DTOG_TX_Pos (6U) #define USB_EP3R_DTOG_TX_Msk (0x1U << USB_EP3R_DTOG_TX_Pos) /*!< 0x00000040 */ #define USB_EP3R_DTOG_TX USB_EP3R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */ -#define USB_EP3R_CTR_TX_Pos (7U) +#define USB_EP3R_CTR_TX_Pos (7U) #define USB_EP3R_CTR_TX_Msk (0x1U << USB_EP3R_CTR_TX_Pos) /*!< 0x00000080 */ #define USB_EP3R_CTR_TX USB_EP3R_CTR_TX_Msk /*!< Correct Transfer for transmission */ -#define USB_EP3R_EP_KIND_Pos (8U) +#define USB_EP3R_EP_KIND_Pos (8U) #define USB_EP3R_EP_KIND_Msk (0x1U << USB_EP3R_EP_KIND_Pos) /*!< 0x00000100 */ #define USB_EP3R_EP_KIND USB_EP3R_EP_KIND_Msk /*!< Endpoint Kind */ -#define USB_EP3R_EP_TYPE_Pos (9U) +#define USB_EP3R_EP_TYPE_Pos (9U) #define USB_EP3R_EP_TYPE_Msk (0x3U << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000600 */ #define USB_EP3R_EP_TYPE USB_EP3R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */ #define USB_EP3R_EP_TYPE_0 (0x1U << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000200 */ #define USB_EP3R_EP_TYPE_1 (0x2U << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000400 */ -#define USB_EP3R_SETUP_Pos (11U) +#define USB_EP3R_SETUP_Pos (11U) #define USB_EP3R_SETUP_Msk (0x1U << USB_EP3R_SETUP_Pos) /*!< 0x00000800 */ #define USB_EP3R_SETUP USB_EP3R_SETUP_Msk /*!< Setup transaction completed */ -#define USB_EP3R_STAT_RX_Pos (12U) +#define USB_EP3R_STAT_RX_Pos (12U) #define USB_EP3R_STAT_RX_Msk (0x3U << USB_EP3R_STAT_RX_Pos) /*!< 0x00003000 */ #define USB_EP3R_STAT_RX USB_EP3R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ #define USB_EP3R_STAT_RX_0 (0x1U << USB_EP3R_STAT_RX_Pos) /*!< 0x00001000 */ #define USB_EP3R_STAT_RX_1 (0x2U << USB_EP3R_STAT_RX_Pos) /*!< 0x00002000 */ -#define USB_EP3R_DTOG_RX_Pos (14U) +#define USB_EP3R_DTOG_RX_Pos (14U) #define USB_EP3R_DTOG_RX_Msk (0x1U << USB_EP3R_DTOG_RX_Pos) /*!< 0x00004000 */ #define USB_EP3R_DTOG_RX USB_EP3R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */ -#define USB_EP3R_CTR_RX_Pos (15U) +#define USB_EP3R_CTR_RX_Pos (15U) #define USB_EP3R_CTR_RX_Msk (0x1U << USB_EP3R_CTR_RX_Pos) /*!< 0x00008000 */ #define USB_EP3R_CTR_RX USB_EP3R_CTR_RX_Msk /*!< Correct Transfer for reception */ /******************* Bit definition for USB_EP4R register *******************/ -#define USB_EP4R_EA_Pos (0U) +#define USB_EP4R_EA_Pos (0U) #define USB_EP4R_EA_Msk (0xFU << USB_EP4R_EA_Pos) /*!< 0x0000000F */ #define USB_EP4R_EA USB_EP4R_EA_Msk /*!< Endpoint Address */ -#define USB_EP4R_STAT_TX_Pos (4U) +#define USB_EP4R_STAT_TX_Pos (4U) #define USB_EP4R_STAT_TX_Msk (0x3U << USB_EP4R_STAT_TX_Pos) /*!< 0x00000030 */ #define USB_EP4R_STAT_TX USB_EP4R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ #define USB_EP4R_STAT_TX_0 (0x1U << USB_EP4R_STAT_TX_Pos) /*!< 0x00000010 */ #define USB_EP4R_STAT_TX_1 (0x2U << USB_EP4R_STAT_TX_Pos) /*!< 0x00000020 */ -#define USB_EP4R_DTOG_TX_Pos (6U) +#define USB_EP4R_DTOG_TX_Pos (6U) #define USB_EP4R_DTOG_TX_Msk (0x1U << USB_EP4R_DTOG_TX_Pos) /*!< 0x00000040 */ #define USB_EP4R_DTOG_TX USB_EP4R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */ -#define USB_EP4R_CTR_TX_Pos (7U) +#define USB_EP4R_CTR_TX_Pos (7U) #define USB_EP4R_CTR_TX_Msk (0x1U << USB_EP4R_CTR_TX_Pos) /*!< 0x00000080 */ #define USB_EP4R_CTR_TX USB_EP4R_CTR_TX_Msk /*!< Correct Transfer for transmission */ -#define USB_EP4R_EP_KIND_Pos (8U) +#define USB_EP4R_EP_KIND_Pos (8U) #define USB_EP4R_EP_KIND_Msk (0x1U << USB_EP4R_EP_KIND_Pos) /*!< 0x00000100 */ #define USB_EP4R_EP_KIND USB_EP4R_EP_KIND_Msk /*!< Endpoint Kind */ -#define USB_EP4R_EP_TYPE_Pos (9U) +#define USB_EP4R_EP_TYPE_Pos (9U) #define USB_EP4R_EP_TYPE_Msk (0x3U << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000600 */ #define USB_EP4R_EP_TYPE USB_EP4R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */ #define USB_EP4R_EP_TYPE_0 (0x1U << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000200 */ #define USB_EP4R_EP_TYPE_1 (0x2U << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000400 */ -#define USB_EP4R_SETUP_Pos (11U) +#define USB_EP4R_SETUP_Pos (11U) #define USB_EP4R_SETUP_Msk (0x1U << USB_EP4R_SETUP_Pos) /*!< 0x00000800 */ #define USB_EP4R_SETUP USB_EP4R_SETUP_Msk /*!< Setup transaction completed */ -#define USB_EP4R_STAT_RX_Pos (12U) +#define USB_EP4R_STAT_RX_Pos (12U) #define USB_EP4R_STAT_RX_Msk (0x3U << USB_EP4R_STAT_RX_Pos) /*!< 0x00003000 */ #define USB_EP4R_STAT_RX USB_EP4R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ #define USB_EP4R_STAT_RX_0 (0x1U << USB_EP4R_STAT_RX_Pos) /*!< 0x00001000 */ #define USB_EP4R_STAT_RX_1 (0x2U << USB_EP4R_STAT_RX_Pos) /*!< 0x00002000 */ -#define USB_EP4R_DTOG_RX_Pos (14U) +#define USB_EP4R_DTOG_RX_Pos (14U) #define USB_EP4R_DTOG_RX_Msk (0x1U << USB_EP4R_DTOG_RX_Pos) /*!< 0x00004000 */ #define USB_EP4R_DTOG_RX USB_EP4R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */ -#define USB_EP4R_CTR_RX_Pos (15U) +#define USB_EP4R_CTR_RX_Pos (15U) #define USB_EP4R_CTR_RX_Msk (0x1U << USB_EP4R_CTR_RX_Pos) /*!< 0x00008000 */ #define USB_EP4R_CTR_RX USB_EP4R_CTR_RX_Msk /*!< Correct Transfer for reception */ /******************* Bit definition for USB_EP5R register *******************/ -#define USB_EP5R_EA_Pos (0U) +#define USB_EP5R_EA_Pos (0U) #define USB_EP5R_EA_Msk (0xFU << USB_EP5R_EA_Pos) /*!< 0x0000000F */ #define USB_EP5R_EA USB_EP5R_EA_Msk /*!< Endpoint Address */ -#define USB_EP5R_STAT_TX_Pos (4U) +#define USB_EP5R_STAT_TX_Pos (4U) #define USB_EP5R_STAT_TX_Msk (0x3U << USB_EP5R_STAT_TX_Pos) /*!< 0x00000030 */ #define USB_EP5R_STAT_TX USB_EP5R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ #define USB_EP5R_STAT_TX_0 (0x1U << USB_EP5R_STAT_TX_Pos) /*!< 0x00000010 */ #define USB_EP5R_STAT_TX_1 (0x2U << USB_EP5R_STAT_TX_Pos) /*!< 0x00000020 */ -#define USB_EP5R_DTOG_TX_Pos (6U) +#define USB_EP5R_DTOG_TX_Pos (6U) #define USB_EP5R_DTOG_TX_Msk (0x1U << USB_EP5R_DTOG_TX_Pos) /*!< 0x00000040 */ #define USB_EP5R_DTOG_TX USB_EP5R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */ -#define USB_EP5R_CTR_TX_Pos (7U) +#define USB_EP5R_CTR_TX_Pos (7U) #define USB_EP5R_CTR_TX_Msk (0x1U << USB_EP5R_CTR_TX_Pos) /*!< 0x00000080 */ #define USB_EP5R_CTR_TX USB_EP5R_CTR_TX_Msk /*!< Correct Transfer for transmission */ -#define USB_EP5R_EP_KIND_Pos (8U) +#define USB_EP5R_EP_KIND_Pos (8U) #define USB_EP5R_EP_KIND_Msk (0x1U << USB_EP5R_EP_KIND_Pos) /*!< 0x00000100 */ #define USB_EP5R_EP_KIND USB_EP5R_EP_KIND_Msk /*!< Endpoint Kind */ -#define USB_EP5R_EP_TYPE_Pos (9U) +#define USB_EP5R_EP_TYPE_Pos (9U) #define USB_EP5R_EP_TYPE_Msk (0x3U << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000600 */ #define USB_EP5R_EP_TYPE USB_EP5R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */ #define USB_EP5R_EP_TYPE_0 (0x1U << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000200 */ #define USB_EP5R_EP_TYPE_1 (0x2U << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000400 */ -#define USB_EP5R_SETUP_Pos (11U) +#define USB_EP5R_SETUP_Pos (11U) #define USB_EP5R_SETUP_Msk (0x1U << USB_EP5R_SETUP_Pos) /*!< 0x00000800 */ #define USB_EP5R_SETUP USB_EP5R_SETUP_Msk /*!< Setup transaction completed */ -#define USB_EP5R_STAT_RX_Pos (12U) +#define USB_EP5R_STAT_RX_Pos (12U) #define USB_EP5R_STAT_RX_Msk (0x3U << USB_EP5R_STAT_RX_Pos) /*!< 0x00003000 */ #define USB_EP5R_STAT_RX USB_EP5R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ #define USB_EP5R_STAT_RX_0 (0x1U << USB_EP5R_STAT_RX_Pos) /*!< 0x00001000 */ #define USB_EP5R_STAT_RX_1 (0x2U << USB_EP5R_STAT_RX_Pos) /*!< 0x00002000 */ -#define USB_EP5R_DTOG_RX_Pos (14U) +#define USB_EP5R_DTOG_RX_Pos (14U) #define USB_EP5R_DTOG_RX_Msk (0x1U << USB_EP5R_DTOG_RX_Pos) /*!< 0x00004000 */ #define USB_EP5R_DTOG_RX USB_EP5R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */ -#define USB_EP5R_CTR_RX_Pos (15U) +#define USB_EP5R_CTR_RX_Pos (15U) #define USB_EP5R_CTR_RX_Msk (0x1U << USB_EP5R_CTR_RX_Pos) /*!< 0x00008000 */ #define USB_EP5R_CTR_RX USB_EP5R_CTR_RX_Msk /*!< Correct Transfer for reception */ /******************* Bit definition for USB_EP6R register *******************/ -#define USB_EP6R_EA_Pos (0U) +#define USB_EP6R_EA_Pos (0U) #define USB_EP6R_EA_Msk (0xFU << USB_EP6R_EA_Pos) /*!< 0x0000000F */ #define USB_EP6R_EA USB_EP6R_EA_Msk /*!< Endpoint Address */ -#define USB_EP6R_STAT_TX_Pos (4U) +#define USB_EP6R_STAT_TX_Pos (4U) #define USB_EP6R_STAT_TX_Msk (0x3U << USB_EP6R_STAT_TX_Pos) /*!< 0x00000030 */ #define USB_EP6R_STAT_TX USB_EP6R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ #define USB_EP6R_STAT_TX_0 (0x1U << USB_EP6R_STAT_TX_Pos) /*!< 0x00000010 */ #define USB_EP6R_STAT_TX_1 (0x2U << USB_EP6R_STAT_TX_Pos) /*!< 0x00000020 */ -#define USB_EP6R_DTOG_TX_Pos (6U) +#define USB_EP6R_DTOG_TX_Pos (6U) #define USB_EP6R_DTOG_TX_Msk (0x1U << USB_EP6R_DTOG_TX_Pos) /*!< 0x00000040 */ #define USB_EP6R_DTOG_TX USB_EP6R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */ -#define USB_EP6R_CTR_TX_Pos (7U) +#define USB_EP6R_CTR_TX_Pos (7U) #define USB_EP6R_CTR_TX_Msk (0x1U << USB_EP6R_CTR_TX_Pos) /*!< 0x00000080 */ #define USB_EP6R_CTR_TX USB_EP6R_CTR_TX_Msk /*!< Correct Transfer for transmission */ -#define USB_EP6R_EP_KIND_Pos (8U) +#define USB_EP6R_EP_KIND_Pos (8U) #define USB_EP6R_EP_KIND_Msk (0x1U << USB_EP6R_EP_KIND_Pos) /*!< 0x00000100 */ #define USB_EP6R_EP_KIND USB_EP6R_EP_KIND_Msk /*!< Endpoint Kind */ -#define USB_EP6R_EP_TYPE_Pos (9U) +#define USB_EP6R_EP_TYPE_Pos (9U) #define USB_EP6R_EP_TYPE_Msk (0x3U << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000600 */ #define USB_EP6R_EP_TYPE USB_EP6R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */ #define USB_EP6R_EP_TYPE_0 (0x1U << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000200 */ #define USB_EP6R_EP_TYPE_1 (0x2U << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000400 */ -#define USB_EP6R_SETUP_Pos (11U) +#define USB_EP6R_SETUP_Pos (11U) #define USB_EP6R_SETUP_Msk (0x1U << USB_EP6R_SETUP_Pos) /*!< 0x00000800 */ #define USB_EP6R_SETUP USB_EP6R_SETUP_Msk /*!< Setup transaction completed */ -#define USB_EP6R_STAT_RX_Pos (12U) +#define USB_EP6R_STAT_RX_Pos (12U) #define USB_EP6R_STAT_RX_Msk (0x3U << USB_EP6R_STAT_RX_Pos) /*!< 0x00003000 */ #define USB_EP6R_STAT_RX USB_EP6R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ #define USB_EP6R_STAT_RX_0 (0x1U << USB_EP6R_STAT_RX_Pos) /*!< 0x00001000 */ #define USB_EP6R_STAT_RX_1 (0x2U << USB_EP6R_STAT_RX_Pos) /*!< 0x00002000 */ -#define USB_EP6R_DTOG_RX_Pos (14U) +#define USB_EP6R_DTOG_RX_Pos (14U) #define USB_EP6R_DTOG_RX_Msk (0x1U << USB_EP6R_DTOG_RX_Pos) /*!< 0x00004000 */ #define USB_EP6R_DTOG_RX USB_EP6R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */ -#define USB_EP6R_CTR_RX_Pos (15U) +#define USB_EP6R_CTR_RX_Pos (15U) #define USB_EP6R_CTR_RX_Msk (0x1U << USB_EP6R_CTR_RX_Pos) /*!< 0x00008000 */ #define USB_EP6R_CTR_RX USB_EP6R_CTR_RX_Msk /*!< Correct Transfer for reception */ /******************* Bit definition for USB_EP7R register *******************/ -#define USB_EP7R_EA_Pos (0U) +#define USB_EP7R_EA_Pos (0U) #define USB_EP7R_EA_Msk (0xFU << USB_EP7R_EA_Pos) /*!< 0x0000000F */ #define USB_EP7R_EA USB_EP7R_EA_Msk /*!< Endpoint Address */ -#define USB_EP7R_STAT_TX_Pos (4U) +#define USB_EP7R_STAT_TX_Pos (4U) #define USB_EP7R_STAT_TX_Msk (0x3U << USB_EP7R_STAT_TX_Pos) /*!< 0x00000030 */ #define USB_EP7R_STAT_TX USB_EP7R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ #define USB_EP7R_STAT_TX_0 (0x1U << USB_EP7R_STAT_TX_Pos) /*!< 0x00000010 */ #define USB_EP7R_STAT_TX_1 (0x2U << USB_EP7R_STAT_TX_Pos) /*!< 0x00000020 */ -#define USB_EP7R_DTOG_TX_Pos (6U) +#define USB_EP7R_DTOG_TX_Pos (6U) #define USB_EP7R_DTOG_TX_Msk (0x1U << USB_EP7R_DTOG_TX_Pos) /*!< 0x00000040 */ #define USB_EP7R_DTOG_TX USB_EP7R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */ -#define USB_EP7R_CTR_TX_Pos (7U) +#define USB_EP7R_CTR_TX_Pos (7U) #define USB_EP7R_CTR_TX_Msk (0x1U << USB_EP7R_CTR_TX_Pos) /*!< 0x00000080 */ #define USB_EP7R_CTR_TX USB_EP7R_CTR_TX_Msk /*!< Correct Transfer for transmission */ -#define USB_EP7R_EP_KIND_Pos (8U) +#define USB_EP7R_EP_KIND_Pos (8U) #define USB_EP7R_EP_KIND_Msk (0x1U << USB_EP7R_EP_KIND_Pos) /*!< 0x00000100 */ #define USB_EP7R_EP_KIND USB_EP7R_EP_KIND_Msk /*!< Endpoint Kind */ -#define USB_EP7R_EP_TYPE_Pos (9U) +#define USB_EP7R_EP_TYPE_Pos (9U) #define USB_EP7R_EP_TYPE_Msk (0x3U << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000600 */ #define USB_EP7R_EP_TYPE USB_EP7R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */ #define USB_EP7R_EP_TYPE_0 (0x1U << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000200 */ #define USB_EP7R_EP_TYPE_1 (0x2U << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000400 */ -#define USB_EP7R_SETUP_Pos (11U) +#define USB_EP7R_SETUP_Pos (11U) #define USB_EP7R_SETUP_Msk (0x1U << USB_EP7R_SETUP_Pos) /*!< 0x00000800 */ #define USB_EP7R_SETUP USB_EP7R_SETUP_Msk /*!< Setup transaction completed */ -#define USB_EP7R_STAT_RX_Pos (12U) +#define USB_EP7R_STAT_RX_Pos (12U) #define USB_EP7R_STAT_RX_Msk (0x3U << USB_EP7R_STAT_RX_Pos) /*!< 0x00003000 */ #define USB_EP7R_STAT_RX USB_EP7R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ #define USB_EP7R_STAT_RX_0 (0x1U << USB_EP7R_STAT_RX_Pos) /*!< 0x00001000 */ #define USB_EP7R_STAT_RX_1 (0x2U << USB_EP7R_STAT_RX_Pos) /*!< 0x00002000 */ -#define USB_EP7R_DTOG_RX_Pos (14U) +#define USB_EP7R_DTOG_RX_Pos (14U) #define USB_EP7R_DTOG_RX_Msk (0x1U << USB_EP7R_DTOG_RX_Pos) /*!< 0x00004000 */ #define USB_EP7R_DTOG_RX USB_EP7R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */ -#define USB_EP7R_CTR_RX_Pos (15U) +#define USB_EP7R_CTR_RX_Pos (15U) #define USB_EP7R_CTR_RX_Msk (0x1U << USB_EP7R_CTR_RX_Pos) /*!< 0x00008000 */ #define USB_EP7R_CTR_RX USB_EP7R_CTR_RX_Msk /*!< Correct Transfer for reception */ /*!< Common registers */ /******************* Bit definition for USB_CNTR register *******************/ -#define USB_CNTR_FRES_Pos (0U) +#define USB_CNTR_FRES_Pos (0U) #define USB_CNTR_FRES_Msk (0x1U << USB_CNTR_FRES_Pos) /*!< 0x00000001 */ #define USB_CNTR_FRES USB_CNTR_FRES_Msk /*!< Force USB Reset */ -#define USB_CNTR_PDWN_Pos (1U) +#define USB_CNTR_PDWN_Pos (1U) #define USB_CNTR_PDWN_Msk (0x1U << USB_CNTR_PDWN_Pos) /*!< 0x00000002 */ #define USB_CNTR_PDWN USB_CNTR_PDWN_Msk /*!< Power down */ -#define USB_CNTR_LP_MODE_Pos (2U) +#define USB_CNTR_LP_MODE_Pos (2U) #define USB_CNTR_LP_MODE_Msk (0x1U << USB_CNTR_LP_MODE_Pos) /*!< 0x00000004 */ #define USB_CNTR_LP_MODE USB_CNTR_LP_MODE_Msk /*!< Low-power mode */ -#define USB_CNTR_FSUSP_Pos (3U) +#define USB_CNTR_FSUSP_Pos (3U) #define USB_CNTR_FSUSP_Msk (0x1U << USB_CNTR_FSUSP_Pos) /*!< 0x00000008 */ #define USB_CNTR_FSUSP USB_CNTR_FSUSP_Msk /*!< Force suspend */ -#define USB_CNTR_RESUME_Pos (4U) +#define USB_CNTR_RESUME_Pos (4U) #define USB_CNTR_RESUME_Msk (0x1U << USB_CNTR_RESUME_Pos) /*!< 0x00000010 */ #define USB_CNTR_RESUME USB_CNTR_RESUME_Msk /*!< Resume request */ -#define USB_CNTR_ESOFM_Pos (8U) +#define USB_CNTR_ESOFM_Pos (8U) #define USB_CNTR_ESOFM_Msk (0x1U << USB_CNTR_ESOFM_Pos) /*!< 0x00000100 */ #define USB_CNTR_ESOFM USB_CNTR_ESOFM_Msk /*!< Expected Start Of Frame Interrupt Mask */ -#define USB_CNTR_SOFM_Pos (9U) +#define USB_CNTR_SOFM_Pos (9U) #define USB_CNTR_SOFM_Msk (0x1U << USB_CNTR_SOFM_Pos) /*!< 0x00000200 */ #define USB_CNTR_SOFM USB_CNTR_SOFM_Msk /*!< Start Of Frame Interrupt Mask */ -#define USB_CNTR_RESETM_Pos (10U) +#define USB_CNTR_RESETM_Pos (10U) #define USB_CNTR_RESETM_Msk (0x1U << USB_CNTR_RESETM_Pos) /*!< 0x00000400 */ #define USB_CNTR_RESETM USB_CNTR_RESETM_Msk /*!< RESET Interrupt Mask */ -#define USB_CNTR_SUSPM_Pos (11U) +#define USB_CNTR_SUSPM_Pos (11U) #define USB_CNTR_SUSPM_Msk (0x1U << USB_CNTR_SUSPM_Pos) /*!< 0x00000800 */ #define USB_CNTR_SUSPM USB_CNTR_SUSPM_Msk /*!< Suspend mode Interrupt Mask */ -#define USB_CNTR_WKUPM_Pos (12U) +#define USB_CNTR_WKUPM_Pos (12U) #define USB_CNTR_WKUPM_Msk (0x1U << USB_CNTR_WKUPM_Pos) /*!< 0x00001000 */ #define USB_CNTR_WKUPM USB_CNTR_WKUPM_Msk /*!< Wakeup Interrupt Mask */ -#define USB_CNTR_ERRM_Pos (13U) +#define USB_CNTR_ERRM_Pos (13U) #define USB_CNTR_ERRM_Msk (0x1U << USB_CNTR_ERRM_Pos) /*!< 0x00002000 */ #define USB_CNTR_ERRM USB_CNTR_ERRM_Msk /*!< Error Interrupt Mask */ -#define USB_CNTR_PMAOVRM_Pos (14U) +#define USB_CNTR_PMAOVRM_Pos (14U) #define USB_CNTR_PMAOVRM_Msk (0x1U << USB_CNTR_PMAOVRM_Pos) /*!< 0x00004000 */ #define USB_CNTR_PMAOVRM USB_CNTR_PMAOVRM_Msk /*!< Packet Memory Area Over / Underrun Interrupt Mask */ -#define USB_CNTR_CTRM_Pos (15U) +#define USB_CNTR_CTRM_Pos (15U) #define USB_CNTR_CTRM_Msk (0x1U << USB_CNTR_CTRM_Pos) /*!< 0x00008000 */ #define USB_CNTR_CTRM USB_CNTR_CTRM_Msk /*!< Correct Transfer Interrupt Mask */ /******************* Bit definition for USB_ISTR register *******************/ -#define USB_ISTR_EP_ID_Pos (0U) +#define USB_ISTR_EP_ID_Pos (0U) #define USB_ISTR_EP_ID_Msk (0xFU << USB_ISTR_EP_ID_Pos) /*!< 0x0000000F */ #define USB_ISTR_EP_ID USB_ISTR_EP_ID_Msk /*!< Endpoint Identifier */ -#define USB_ISTR_DIR_Pos (4U) +#define USB_ISTR_DIR_Pos (4U) #define USB_ISTR_DIR_Msk (0x1U << USB_ISTR_DIR_Pos) /*!< 0x00000010 */ #define USB_ISTR_DIR USB_ISTR_DIR_Msk /*!< Direction of transaction */ -#define USB_ISTR_ESOF_Pos (8U) +#define USB_ISTR_ESOF_Pos (8U) #define USB_ISTR_ESOF_Msk (0x1U << USB_ISTR_ESOF_Pos) /*!< 0x00000100 */ #define USB_ISTR_ESOF USB_ISTR_ESOF_Msk /*!< Expected Start Of Frame */ -#define USB_ISTR_SOF_Pos (9U) +#define USB_ISTR_SOF_Pos (9U) #define USB_ISTR_SOF_Msk (0x1U << USB_ISTR_SOF_Pos) /*!< 0x00000200 */ #define USB_ISTR_SOF USB_ISTR_SOF_Msk /*!< Start Of Frame */ -#define USB_ISTR_RESET_Pos (10U) +#define USB_ISTR_RESET_Pos (10U) #define USB_ISTR_RESET_Msk (0x1U << USB_ISTR_RESET_Pos) /*!< 0x00000400 */ #define USB_ISTR_RESET USB_ISTR_RESET_Msk /*!< USB RESET request */ -#define USB_ISTR_SUSP_Pos (11U) +#define USB_ISTR_SUSP_Pos (11U) #define USB_ISTR_SUSP_Msk (0x1U << USB_ISTR_SUSP_Pos) /*!< 0x00000800 */ #define USB_ISTR_SUSP USB_ISTR_SUSP_Msk /*!< Suspend mode request */ -#define USB_ISTR_WKUP_Pos (12U) +#define USB_ISTR_WKUP_Pos (12U) #define USB_ISTR_WKUP_Msk (0x1U << USB_ISTR_WKUP_Pos) /*!< 0x00001000 */ #define USB_ISTR_WKUP USB_ISTR_WKUP_Msk /*!< Wake up */ -#define USB_ISTR_ERR_Pos (13U) +#define USB_ISTR_ERR_Pos (13U) #define USB_ISTR_ERR_Msk (0x1U << USB_ISTR_ERR_Pos) /*!< 0x00002000 */ #define USB_ISTR_ERR USB_ISTR_ERR_Msk /*!< Error */ -#define USB_ISTR_PMAOVR_Pos (14U) +#define USB_ISTR_PMAOVR_Pos (14U) #define USB_ISTR_PMAOVR_Msk (0x1U << USB_ISTR_PMAOVR_Pos) /*!< 0x00004000 */ #define USB_ISTR_PMAOVR USB_ISTR_PMAOVR_Msk /*!< Packet Memory Area Over / Underrun */ -#define USB_ISTR_CTR_Pos (15U) +#define USB_ISTR_CTR_Pos (15U) #define USB_ISTR_CTR_Msk (0x1U << USB_ISTR_CTR_Pos) /*!< 0x00008000 */ #define USB_ISTR_CTR USB_ISTR_CTR_Msk /*!< Correct Transfer */ /******************* Bit definition for USB_FNR register ********************/ -#define USB_FNR_FN_Pos (0U) +#define USB_FNR_FN_Pos (0U) #define USB_FNR_FN_Msk (0x7FFU << USB_FNR_FN_Pos) /*!< 0x000007FF */ #define USB_FNR_FN USB_FNR_FN_Msk /*!< Frame Number */ -#define USB_FNR_LSOF_Pos (11U) +#define USB_FNR_LSOF_Pos (11U) #define USB_FNR_LSOF_Msk (0x3U << USB_FNR_LSOF_Pos) /*!< 0x00001800 */ #define USB_FNR_LSOF USB_FNR_LSOF_Msk /*!< Lost SOF */ -#define USB_FNR_LCK_Pos (13U) +#define USB_FNR_LCK_Pos (13U) #define USB_FNR_LCK_Msk (0x1U << USB_FNR_LCK_Pos) /*!< 0x00002000 */ #define USB_FNR_LCK USB_FNR_LCK_Msk /*!< Locked */ -#define USB_FNR_RXDM_Pos (14U) +#define USB_FNR_RXDM_Pos (14U) #define USB_FNR_RXDM_Msk (0x1U << USB_FNR_RXDM_Pos) /*!< 0x00004000 */ #define USB_FNR_RXDM USB_FNR_RXDM_Msk /*!< Receive Data - Line Status */ -#define USB_FNR_RXDP_Pos (15U) +#define USB_FNR_RXDP_Pos (15U) #define USB_FNR_RXDP_Msk (0x1U << USB_FNR_RXDP_Pos) /*!< 0x00008000 */ #define USB_FNR_RXDP USB_FNR_RXDP_Msk /*!< Receive Data + Line Status */ /****************** Bit definition for USB_DADDR register *******************/ -#define USB_DADDR_ADD_Pos (0U) +#define USB_DADDR_ADD_Pos (0U) #define USB_DADDR_ADD_Msk (0x7FU << USB_DADDR_ADD_Pos) /*!< 0x0000007F */ #define USB_DADDR_ADD USB_DADDR_ADD_Msk /*!< ADD[6:0] bits (Device Address) */ -#define USB_DADDR_ADD0_Pos (0U) +#define USB_DADDR_ADD0_Pos (0U) #define USB_DADDR_ADD0_Msk (0x1U << USB_DADDR_ADD0_Pos) /*!< 0x00000001 */ #define USB_DADDR_ADD0 USB_DADDR_ADD0_Msk /*!< Bit 0 */ -#define USB_DADDR_ADD1_Pos (1U) +#define USB_DADDR_ADD1_Pos (1U) #define USB_DADDR_ADD1_Msk (0x1U << USB_DADDR_ADD1_Pos) /*!< 0x00000002 */ #define USB_DADDR_ADD1 USB_DADDR_ADD1_Msk /*!< Bit 1 */ -#define USB_DADDR_ADD2_Pos (2U) +#define USB_DADDR_ADD2_Pos (2U) #define USB_DADDR_ADD2_Msk (0x1U << USB_DADDR_ADD2_Pos) /*!< 0x00000004 */ #define USB_DADDR_ADD2 USB_DADDR_ADD2_Msk /*!< Bit 2 */ -#define USB_DADDR_ADD3_Pos (3U) +#define USB_DADDR_ADD3_Pos (3U) #define USB_DADDR_ADD3_Msk (0x1U << USB_DADDR_ADD3_Pos) /*!< 0x00000008 */ #define USB_DADDR_ADD3 USB_DADDR_ADD3_Msk /*!< Bit 3 */ -#define USB_DADDR_ADD4_Pos (4U) +#define USB_DADDR_ADD4_Pos (4U) #define USB_DADDR_ADD4_Msk (0x1U << USB_DADDR_ADD4_Pos) /*!< 0x00000010 */ #define USB_DADDR_ADD4 USB_DADDR_ADD4_Msk /*!< Bit 4 */ -#define USB_DADDR_ADD5_Pos (5U) +#define USB_DADDR_ADD5_Pos (5U) #define USB_DADDR_ADD5_Msk (0x1U << USB_DADDR_ADD5_Pos) /*!< 0x00000020 */ #define USB_DADDR_ADD5 USB_DADDR_ADD5_Msk /*!< Bit 5 */ -#define USB_DADDR_ADD6_Pos (6U) +#define USB_DADDR_ADD6_Pos (6U) #define USB_DADDR_ADD6_Msk (0x1U << USB_DADDR_ADD6_Pos) /*!< 0x00000040 */ #define USB_DADDR_ADD6 USB_DADDR_ADD6_Msk /*!< Bit 6 */ -#define USB_DADDR_EF_Pos (7U) +#define USB_DADDR_EF_Pos (7U) #define USB_DADDR_EF_Msk (0x1U << USB_DADDR_EF_Pos) /*!< 0x00000080 */ #define USB_DADDR_EF USB_DADDR_EF_Msk /*!< Enable Function */ -/****************** Bit definition for USB_BTABLE register ******************/ -#define USB_BTABLE_BTABLE_Pos (3U) +/****************** Bit definition for USB_BTABLE register ******************/ +#define USB_BTABLE_BTABLE_Pos (3U) #define USB_BTABLE_BTABLE_Msk (0x1FFFU << USB_BTABLE_BTABLE_Pos) /*!< 0x0000FFF8 */ #define USB_BTABLE_BTABLE USB_BTABLE_BTABLE_Msk /*!< Buffer Table */ /*!< Buffer descriptor table */ /***************** Bit definition for USB_ADDR0_TX register *****************/ -#define USB_ADDR0_TX_ADDR0_TX_Pos (1U) +#define USB_ADDR0_TX_ADDR0_TX_Pos (1U) #define USB_ADDR0_TX_ADDR0_TX_Msk (0x7FFFU << USB_ADDR0_TX_ADDR0_TX_Pos) /*!< 0x0000FFFE */ #define USB_ADDR0_TX_ADDR0_TX USB_ADDR0_TX_ADDR0_TX_Msk /*!< Transmission Buffer Address 0 */ /***************** Bit definition for USB_ADDR1_TX register *****************/ -#define USB_ADDR1_TX_ADDR1_TX_Pos (1U) +#define USB_ADDR1_TX_ADDR1_TX_Pos (1U) #define USB_ADDR1_TX_ADDR1_TX_Msk (0x7FFFU << USB_ADDR1_TX_ADDR1_TX_Pos) /*!< 0x0000FFFE */ #define USB_ADDR1_TX_ADDR1_TX USB_ADDR1_TX_ADDR1_TX_Msk /*!< Transmission Buffer Address 1 */ /***************** Bit definition for USB_ADDR2_TX register *****************/ -#define USB_ADDR2_TX_ADDR2_TX_Pos (1U) +#define USB_ADDR2_TX_ADDR2_TX_Pos (1U) #define USB_ADDR2_TX_ADDR2_TX_Msk (0x7FFFU << USB_ADDR2_TX_ADDR2_TX_Pos) /*!< 0x0000FFFE */ #define USB_ADDR2_TX_ADDR2_TX USB_ADDR2_TX_ADDR2_TX_Msk /*!< Transmission Buffer Address 2 */ /***************** Bit definition for USB_ADDR3_TX register *****************/ -#define USB_ADDR3_TX_ADDR3_TX_Pos (1U) +#define USB_ADDR3_TX_ADDR3_TX_Pos (1U) #define USB_ADDR3_TX_ADDR3_TX_Msk (0x7FFFU << USB_ADDR3_TX_ADDR3_TX_Pos) /*!< 0x0000FFFE */ #define USB_ADDR3_TX_ADDR3_TX USB_ADDR3_TX_ADDR3_TX_Msk /*!< Transmission Buffer Address 3 */ /***************** Bit definition for USB_ADDR4_TX register *****************/ -#define USB_ADDR4_TX_ADDR4_TX_Pos (1U) +#define USB_ADDR4_TX_ADDR4_TX_Pos (1U) #define USB_ADDR4_TX_ADDR4_TX_Msk (0x7FFFU << USB_ADDR4_TX_ADDR4_TX_Pos) /*!< 0x0000FFFE */ #define USB_ADDR4_TX_ADDR4_TX USB_ADDR4_TX_ADDR4_TX_Msk /*!< Transmission Buffer Address 4 */ /***************** Bit definition for USB_ADDR5_TX register *****************/ -#define USB_ADDR5_TX_ADDR5_TX_Pos (1U) +#define USB_ADDR5_TX_ADDR5_TX_Pos (1U) #define USB_ADDR5_TX_ADDR5_TX_Msk (0x7FFFU << USB_ADDR5_TX_ADDR5_TX_Pos) /*!< 0x0000FFFE */ #define USB_ADDR5_TX_ADDR5_TX USB_ADDR5_TX_ADDR5_TX_Msk /*!< Transmission Buffer Address 5 */ /***************** Bit definition for USB_ADDR6_TX register *****************/ -#define USB_ADDR6_TX_ADDR6_TX_Pos (1U) +#define USB_ADDR6_TX_ADDR6_TX_Pos (1U) #define USB_ADDR6_TX_ADDR6_TX_Msk (0x7FFFU << USB_ADDR6_TX_ADDR6_TX_Pos) /*!< 0x0000FFFE */ #define USB_ADDR6_TX_ADDR6_TX USB_ADDR6_TX_ADDR6_TX_Msk /*!< Transmission Buffer Address 6 */ /***************** Bit definition for USB_ADDR7_TX register *****************/ -#define USB_ADDR7_TX_ADDR7_TX_Pos (1U) +#define USB_ADDR7_TX_ADDR7_TX_Pos (1U) #define USB_ADDR7_TX_ADDR7_TX_Msk (0x7FFFU << USB_ADDR7_TX_ADDR7_TX_Pos) /*!< 0x0000FFFE */ #define USB_ADDR7_TX_ADDR7_TX USB_ADDR7_TX_ADDR7_TX_Msk /*!< Transmission Buffer Address 7 */ /*----------------------------------------------------------------------------*/ /***************** Bit definition for USB_COUNT0_TX register ****************/ -#define USB_COUNT0_TX_COUNT0_TX_Pos (0U) +#define USB_COUNT0_TX_COUNT0_TX_Pos (0U) #define USB_COUNT0_TX_COUNT0_TX_Msk (0x3FFU << USB_COUNT0_TX_COUNT0_TX_Pos) /*!< 0x000003FF */ #define USB_COUNT0_TX_COUNT0_TX USB_COUNT0_TX_COUNT0_TX_Msk /*!< Transmission Byte Count 0 */ /***************** Bit definition for USB_COUNT1_TX register ****************/ -#define USB_COUNT1_TX_COUNT1_TX_Pos (0U) +#define USB_COUNT1_TX_COUNT1_TX_Pos (0U) #define USB_COUNT1_TX_COUNT1_TX_Msk (0x3FFU << USB_COUNT1_TX_COUNT1_TX_Pos) /*!< 0x000003FF */ #define USB_COUNT1_TX_COUNT1_TX USB_COUNT1_TX_COUNT1_TX_Msk /*!< Transmission Byte Count 1 */ /***************** Bit definition for USB_COUNT2_TX register ****************/ -#define USB_COUNT2_TX_COUNT2_TX_Pos (0U) +#define USB_COUNT2_TX_COUNT2_TX_Pos (0U) #define USB_COUNT2_TX_COUNT2_TX_Msk (0x3FFU << USB_COUNT2_TX_COUNT2_TX_Pos) /*!< 0x000003FF */ #define USB_COUNT2_TX_COUNT2_TX USB_COUNT2_TX_COUNT2_TX_Msk /*!< Transmission Byte Count 2 */ /***************** Bit definition for USB_COUNT3_TX register ****************/ -#define USB_COUNT3_TX_COUNT3_TX_Pos (0U) +#define USB_COUNT3_TX_COUNT3_TX_Pos (0U) #define USB_COUNT3_TX_COUNT3_TX_Msk (0x3FFU << USB_COUNT3_TX_COUNT3_TX_Pos) /*!< 0x000003FF */ #define USB_COUNT3_TX_COUNT3_TX USB_COUNT3_TX_COUNT3_TX_Msk /*!< Transmission Byte Count 3 */ /***************** Bit definition for USB_COUNT4_TX register ****************/ -#define USB_COUNT4_TX_COUNT4_TX_Pos (0U) +#define USB_COUNT4_TX_COUNT4_TX_Pos (0U) #define USB_COUNT4_TX_COUNT4_TX_Msk (0x3FFU << USB_COUNT4_TX_COUNT4_TX_Pos) /*!< 0x000003FF */ #define USB_COUNT4_TX_COUNT4_TX USB_COUNT4_TX_COUNT4_TX_Msk /*!< Transmission Byte Count 4 */ /***************** Bit definition for USB_COUNT5_TX register ****************/ -#define USB_COUNT5_TX_COUNT5_TX_Pos (0U) +#define USB_COUNT5_TX_COUNT5_TX_Pos (0U) #define USB_COUNT5_TX_COUNT5_TX_Msk (0x3FFU << USB_COUNT5_TX_COUNT5_TX_Pos) /*!< 0x000003FF */ #define USB_COUNT5_TX_COUNT5_TX USB_COUNT5_TX_COUNT5_TX_Msk /*!< Transmission Byte Count 5 */ /***************** Bit definition for USB_COUNT6_TX register ****************/ -#define USB_COUNT6_TX_COUNT6_TX_Pos (0U) +#define USB_COUNT6_TX_COUNT6_TX_Pos (0U) #define USB_COUNT6_TX_COUNT6_TX_Msk (0x3FFU << USB_COUNT6_TX_COUNT6_TX_Pos) /*!< 0x000003FF */ #define USB_COUNT6_TX_COUNT6_TX USB_COUNT6_TX_COUNT6_TX_Msk /*!< Transmission Byte Count 6 */ /***************** Bit definition for USB_COUNT7_TX register ****************/ -#define USB_COUNT7_TX_COUNT7_TX_Pos (0U) +#define USB_COUNT7_TX_COUNT7_TX_Pos (0U) #define USB_COUNT7_TX_COUNT7_TX_Msk (0x3FFU << USB_COUNT7_TX_COUNT7_TX_Pos) /*!< 0x000003FF */ #define USB_COUNT7_TX_COUNT7_TX USB_COUNT7_TX_COUNT7_TX_Msk /*!< Transmission Byte Count 7 */ @@ -6005,53 +6005,53 @@ typedef struct /*----------------------------------------------------------------------------*/ /***************** Bit definition for USB_ADDR0_RX register *****************/ -#define USB_ADDR0_RX_ADDR0_RX_Pos (1U) +#define USB_ADDR0_RX_ADDR0_RX_Pos (1U) #define USB_ADDR0_RX_ADDR0_RX_Msk (0x7FFFU << USB_ADDR0_RX_ADDR0_RX_Pos) /*!< 0x0000FFFE */ #define USB_ADDR0_RX_ADDR0_RX USB_ADDR0_RX_ADDR0_RX_Msk /*!< Reception Buffer Address 0 */ /***************** Bit definition for USB_ADDR1_RX register *****************/ -#define USB_ADDR1_RX_ADDR1_RX_Pos (1U) +#define USB_ADDR1_RX_ADDR1_RX_Pos (1U) #define USB_ADDR1_RX_ADDR1_RX_Msk (0x7FFFU << USB_ADDR1_RX_ADDR1_RX_Pos) /*!< 0x0000FFFE */ #define USB_ADDR1_RX_ADDR1_RX USB_ADDR1_RX_ADDR1_RX_Msk /*!< Reception Buffer Address 1 */ /***************** Bit definition for USB_ADDR2_RX register *****************/ -#define USB_ADDR2_RX_ADDR2_RX_Pos (1U) +#define USB_ADDR2_RX_ADDR2_RX_Pos (1U) #define USB_ADDR2_RX_ADDR2_RX_Msk (0x7FFFU << USB_ADDR2_RX_ADDR2_RX_Pos) /*!< 0x0000FFFE */ #define USB_ADDR2_RX_ADDR2_RX USB_ADDR2_RX_ADDR2_RX_Msk /*!< Reception Buffer Address 2 */ /***************** Bit definition for USB_ADDR3_RX register *****************/ -#define USB_ADDR3_RX_ADDR3_RX_Pos (1U) +#define USB_ADDR3_RX_ADDR3_RX_Pos (1U) #define USB_ADDR3_RX_ADDR3_RX_Msk (0x7FFFU << USB_ADDR3_RX_ADDR3_RX_Pos) /*!< 0x0000FFFE */ #define USB_ADDR3_RX_ADDR3_RX USB_ADDR3_RX_ADDR3_RX_Msk /*!< Reception Buffer Address 3 */ /***************** Bit definition for USB_ADDR4_RX register *****************/ -#define USB_ADDR4_RX_ADDR4_RX_Pos (1U) +#define USB_ADDR4_RX_ADDR4_RX_Pos (1U) #define USB_ADDR4_RX_ADDR4_RX_Msk (0x7FFFU << USB_ADDR4_RX_ADDR4_RX_Pos) /*!< 0x0000FFFE */ #define USB_ADDR4_RX_ADDR4_RX USB_ADDR4_RX_ADDR4_RX_Msk /*!< Reception Buffer Address 4 */ /***************** Bit definition for USB_ADDR5_RX register *****************/ -#define USB_ADDR5_RX_ADDR5_RX_Pos (1U) +#define USB_ADDR5_RX_ADDR5_RX_Pos (1U) #define USB_ADDR5_RX_ADDR5_RX_Msk (0x7FFFU << USB_ADDR5_RX_ADDR5_RX_Pos) /*!< 0x0000FFFE */ #define USB_ADDR5_RX_ADDR5_RX USB_ADDR5_RX_ADDR5_RX_Msk /*!< Reception Buffer Address 5 */ /***************** Bit definition for USB_ADDR6_RX register *****************/ -#define USB_ADDR6_RX_ADDR6_RX_Pos (1U) +#define USB_ADDR6_RX_ADDR6_RX_Pos (1U) #define USB_ADDR6_RX_ADDR6_RX_Msk (0x7FFFU << USB_ADDR6_RX_ADDR6_RX_Pos) /*!< 0x0000FFFE */ #define USB_ADDR6_RX_ADDR6_RX USB_ADDR6_RX_ADDR6_RX_Msk /*!< Reception Buffer Address 6 */ /***************** Bit definition for USB_ADDR7_RX register *****************/ -#define USB_ADDR7_RX_ADDR7_RX_Pos (1U) +#define USB_ADDR7_RX_ADDR7_RX_Pos (1U) #define USB_ADDR7_RX_ADDR7_RX_Msk (0x7FFFU << USB_ADDR7_RX_ADDR7_RX_Pos) /*!< 0x0000FFFE */ #define USB_ADDR7_RX_ADDR7_RX USB_ADDR7_RX_ADDR7_RX_Msk /*!< Reception Buffer Address 7 */ /*----------------------------------------------------------------------------*/ /***************** Bit definition for USB_COUNT0_RX register ****************/ -#define USB_COUNT0_RX_COUNT0_RX_Pos (0U) +#define USB_COUNT0_RX_COUNT0_RX_Pos (0U) #define USB_COUNT0_RX_COUNT0_RX_Msk (0x3FFU << USB_COUNT0_RX_COUNT0_RX_Pos) /*!< 0x000003FF */ #define USB_COUNT0_RX_COUNT0_RX USB_COUNT0_RX_COUNT0_RX_Msk /*!< Reception Byte Count */ -#define USB_COUNT0_RX_NUM_BLOCK_Pos (10U) +#define USB_COUNT0_RX_NUM_BLOCK_Pos (10U) #define USB_COUNT0_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ #define USB_COUNT0_RX_NUM_BLOCK USB_COUNT0_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ #define USB_COUNT0_RX_NUM_BLOCK_0 (0x01U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ @@ -6060,16 +6060,16 @@ typedef struct #define USB_COUNT0_RX_NUM_BLOCK_3 (0x08U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ #define USB_COUNT0_RX_NUM_BLOCK_4 (0x10U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ -#define USB_COUNT0_RX_BLSIZE_Pos (15U) +#define USB_COUNT0_RX_BLSIZE_Pos (15U) #define USB_COUNT0_RX_BLSIZE_Msk (0x1U << USB_COUNT0_RX_BLSIZE_Pos) /*!< 0x00008000 */ #define USB_COUNT0_RX_BLSIZE USB_COUNT0_RX_BLSIZE_Msk /*!< BLock SIZE */ /***************** Bit definition for USB_COUNT1_RX register ****************/ -#define USB_COUNT1_RX_COUNT1_RX_Pos (0U) +#define USB_COUNT1_RX_COUNT1_RX_Pos (0U) #define USB_COUNT1_RX_COUNT1_RX_Msk (0x3FFU << USB_COUNT1_RX_COUNT1_RX_Pos) /*!< 0x000003FF */ #define USB_COUNT1_RX_COUNT1_RX USB_COUNT1_RX_COUNT1_RX_Msk /*!< Reception Byte Count */ -#define USB_COUNT1_RX_NUM_BLOCK_Pos (10U) +#define USB_COUNT1_RX_NUM_BLOCK_Pos (10U) #define USB_COUNT1_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ #define USB_COUNT1_RX_NUM_BLOCK USB_COUNT1_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ #define USB_COUNT1_RX_NUM_BLOCK_0 (0x01U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ @@ -6078,16 +6078,16 @@ typedef struct #define USB_COUNT1_RX_NUM_BLOCK_3 (0x08U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ #define USB_COUNT1_RX_NUM_BLOCK_4 (0x10U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ -#define USB_COUNT1_RX_BLSIZE_Pos (15U) +#define USB_COUNT1_RX_BLSIZE_Pos (15U) #define USB_COUNT1_RX_BLSIZE_Msk (0x1U << USB_COUNT1_RX_BLSIZE_Pos) /*!< 0x00008000 */ #define USB_COUNT1_RX_BLSIZE USB_COUNT1_RX_BLSIZE_Msk /*!< BLock SIZE */ /***************** Bit definition for USB_COUNT2_RX register ****************/ -#define USB_COUNT2_RX_COUNT2_RX_Pos (0U) +#define USB_COUNT2_RX_COUNT2_RX_Pos (0U) #define USB_COUNT2_RX_COUNT2_RX_Msk (0x3FFU << USB_COUNT2_RX_COUNT2_RX_Pos) /*!< 0x000003FF */ #define USB_COUNT2_RX_COUNT2_RX USB_COUNT2_RX_COUNT2_RX_Msk /*!< Reception Byte Count */ -#define USB_COUNT2_RX_NUM_BLOCK_Pos (10U) +#define USB_COUNT2_RX_NUM_BLOCK_Pos (10U) #define USB_COUNT2_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ #define USB_COUNT2_RX_NUM_BLOCK USB_COUNT2_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ #define USB_COUNT2_RX_NUM_BLOCK_0 (0x01U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ @@ -6096,16 +6096,16 @@ typedef struct #define USB_COUNT2_RX_NUM_BLOCK_3 (0x08U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ #define USB_COUNT2_RX_NUM_BLOCK_4 (0x10U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ -#define USB_COUNT2_RX_BLSIZE_Pos (15U) +#define USB_COUNT2_RX_BLSIZE_Pos (15U) #define USB_COUNT2_RX_BLSIZE_Msk (0x1U << USB_COUNT2_RX_BLSIZE_Pos) /*!< 0x00008000 */ #define USB_COUNT2_RX_BLSIZE USB_COUNT2_RX_BLSIZE_Msk /*!< BLock SIZE */ /***************** Bit definition for USB_COUNT3_RX register ****************/ -#define USB_COUNT3_RX_COUNT3_RX_Pos (0U) +#define USB_COUNT3_RX_COUNT3_RX_Pos (0U) #define USB_COUNT3_RX_COUNT3_RX_Msk (0x3FFU << USB_COUNT3_RX_COUNT3_RX_Pos) /*!< 0x000003FF */ #define USB_COUNT3_RX_COUNT3_RX USB_COUNT3_RX_COUNT3_RX_Msk /*!< Reception Byte Count */ -#define USB_COUNT3_RX_NUM_BLOCK_Pos (10U) +#define USB_COUNT3_RX_NUM_BLOCK_Pos (10U) #define USB_COUNT3_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ #define USB_COUNT3_RX_NUM_BLOCK USB_COUNT3_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ #define USB_COUNT3_RX_NUM_BLOCK_0 (0x01U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ @@ -6114,16 +6114,16 @@ typedef struct #define USB_COUNT3_RX_NUM_BLOCK_3 (0x08U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ #define USB_COUNT3_RX_NUM_BLOCK_4 (0x10U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ -#define USB_COUNT3_RX_BLSIZE_Pos (15U) +#define USB_COUNT3_RX_BLSIZE_Pos (15U) #define USB_COUNT3_RX_BLSIZE_Msk (0x1U << USB_COUNT3_RX_BLSIZE_Pos) /*!< 0x00008000 */ #define USB_COUNT3_RX_BLSIZE USB_COUNT3_RX_BLSIZE_Msk /*!< BLock SIZE */ /***************** Bit definition for USB_COUNT4_RX register ****************/ -#define USB_COUNT4_RX_COUNT4_RX_Pos (0U) +#define USB_COUNT4_RX_COUNT4_RX_Pos (0U) #define USB_COUNT4_RX_COUNT4_RX_Msk (0x3FFU << USB_COUNT4_RX_COUNT4_RX_Pos) /*!< 0x000003FF */ #define USB_COUNT4_RX_COUNT4_RX USB_COUNT4_RX_COUNT4_RX_Msk /*!< Reception Byte Count */ -#define USB_COUNT4_RX_NUM_BLOCK_Pos (10U) +#define USB_COUNT4_RX_NUM_BLOCK_Pos (10U) #define USB_COUNT4_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ #define USB_COUNT4_RX_NUM_BLOCK USB_COUNT4_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ #define USB_COUNT4_RX_NUM_BLOCK_0 (0x01U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ @@ -6132,16 +6132,16 @@ typedef struct #define USB_COUNT4_RX_NUM_BLOCK_3 (0x08U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ #define USB_COUNT4_RX_NUM_BLOCK_4 (0x10U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ -#define USB_COUNT4_RX_BLSIZE_Pos (15U) +#define USB_COUNT4_RX_BLSIZE_Pos (15U) #define USB_COUNT4_RX_BLSIZE_Msk (0x1U << USB_COUNT4_RX_BLSIZE_Pos) /*!< 0x00008000 */ #define USB_COUNT4_RX_BLSIZE USB_COUNT4_RX_BLSIZE_Msk /*!< BLock SIZE */ /***************** Bit definition for USB_COUNT5_RX register ****************/ -#define USB_COUNT5_RX_COUNT5_RX_Pos (0U) +#define USB_COUNT5_RX_COUNT5_RX_Pos (0U) #define USB_COUNT5_RX_COUNT5_RX_Msk (0x3FFU << USB_COUNT5_RX_COUNT5_RX_Pos) /*!< 0x000003FF */ #define USB_COUNT5_RX_COUNT5_RX USB_COUNT5_RX_COUNT5_RX_Msk /*!< Reception Byte Count */ -#define USB_COUNT5_RX_NUM_BLOCK_Pos (10U) +#define USB_COUNT5_RX_NUM_BLOCK_Pos (10U) #define USB_COUNT5_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ #define USB_COUNT5_RX_NUM_BLOCK USB_COUNT5_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ #define USB_COUNT5_RX_NUM_BLOCK_0 (0x01U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ @@ -6150,16 +6150,16 @@ typedef struct #define USB_COUNT5_RX_NUM_BLOCK_3 (0x08U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ #define USB_COUNT5_RX_NUM_BLOCK_4 (0x10U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ -#define USB_COUNT5_RX_BLSIZE_Pos (15U) +#define USB_COUNT5_RX_BLSIZE_Pos (15U) #define USB_COUNT5_RX_BLSIZE_Msk (0x1U << USB_COUNT5_RX_BLSIZE_Pos) /*!< 0x00008000 */ #define USB_COUNT5_RX_BLSIZE USB_COUNT5_RX_BLSIZE_Msk /*!< BLock SIZE */ /***************** Bit definition for USB_COUNT6_RX register ****************/ -#define USB_COUNT6_RX_COUNT6_RX_Pos (0U) +#define USB_COUNT6_RX_COUNT6_RX_Pos (0U) #define USB_COUNT6_RX_COUNT6_RX_Msk (0x3FFU << USB_COUNT6_RX_COUNT6_RX_Pos) /*!< 0x000003FF */ #define USB_COUNT6_RX_COUNT6_RX USB_COUNT6_RX_COUNT6_RX_Msk /*!< Reception Byte Count */ -#define USB_COUNT6_RX_NUM_BLOCK_Pos (10U) +#define USB_COUNT6_RX_NUM_BLOCK_Pos (10U) #define USB_COUNT6_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ #define USB_COUNT6_RX_NUM_BLOCK USB_COUNT6_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ #define USB_COUNT6_RX_NUM_BLOCK_0 (0x01U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ @@ -6168,16 +6168,16 @@ typedef struct #define USB_COUNT6_RX_NUM_BLOCK_3 (0x08U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ #define USB_COUNT6_RX_NUM_BLOCK_4 (0x10U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ -#define USB_COUNT6_RX_BLSIZE_Pos (15U) +#define USB_COUNT6_RX_BLSIZE_Pos (15U) #define USB_COUNT6_RX_BLSIZE_Msk (0x1U << USB_COUNT6_RX_BLSIZE_Pos) /*!< 0x00008000 */ #define USB_COUNT6_RX_BLSIZE USB_COUNT6_RX_BLSIZE_Msk /*!< BLock SIZE */ /***************** Bit definition for USB_COUNT7_RX register ****************/ -#define USB_COUNT7_RX_COUNT7_RX_Pos (0U) +#define USB_COUNT7_RX_COUNT7_RX_Pos (0U) #define USB_COUNT7_RX_COUNT7_RX_Msk (0x3FFU << USB_COUNT7_RX_COUNT7_RX_Pos) /*!< 0x000003FF */ #define USB_COUNT7_RX_COUNT7_RX USB_COUNT7_RX_COUNT7_RX_Msk /*!< Reception Byte Count */ -#define USB_COUNT7_RX_NUM_BLOCK_Pos (10U) +#define USB_COUNT7_RX_NUM_BLOCK_Pos (10U) #define USB_COUNT7_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ #define USB_COUNT7_RX_NUM_BLOCK USB_COUNT7_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ #define USB_COUNT7_RX_NUM_BLOCK_0 (0x01U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ @@ -6186,7 +6186,7 @@ typedef struct #define USB_COUNT7_RX_NUM_BLOCK_3 (0x08U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ #define USB_COUNT7_RX_NUM_BLOCK_4 (0x10U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ -#define USB_COUNT7_RX_BLSIZE_Pos (15U) +#define USB_COUNT7_RX_BLSIZE_Pos (15U) #define USB_COUNT7_RX_BLSIZE_Msk (0x1U << USB_COUNT7_RX_BLSIZE_Pos) /*!< 0x00008000 */ #define USB_COUNT7_RX_BLSIZE USB_COUNT7_RX_BLSIZE_Msk /*!< BLock SIZE */ @@ -6392,3481 +6392,3481 @@ typedef struct /*!< CAN control and status registers */ /******************* Bit definition for CAN_MCR register ********************/ -#define CAN_MCR_INRQ_Pos (0U) +#define CAN_MCR_INRQ_Pos (0U) #define CAN_MCR_INRQ_Msk (0x1U << CAN_MCR_INRQ_Pos) /*!< 0x00000001 */ #define CAN_MCR_INRQ CAN_MCR_INRQ_Msk /*!< Initialization Request */ -#define CAN_MCR_SLEEP_Pos (1U) +#define CAN_MCR_SLEEP_Pos (1U) #define CAN_MCR_SLEEP_Msk (0x1U << CAN_MCR_SLEEP_Pos) /*!< 0x00000002 */ #define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk /*!< Sleep Mode Request */ -#define CAN_MCR_TXFP_Pos (2U) +#define CAN_MCR_TXFP_Pos (2U) #define CAN_MCR_TXFP_Msk (0x1U << CAN_MCR_TXFP_Pos) /*!< 0x00000004 */ #define CAN_MCR_TXFP CAN_MCR_TXFP_Msk /*!< Transmit FIFO Priority */ -#define CAN_MCR_RFLM_Pos (3U) +#define CAN_MCR_RFLM_Pos (3U) #define CAN_MCR_RFLM_Msk (0x1U << CAN_MCR_RFLM_Pos) /*!< 0x00000008 */ #define CAN_MCR_RFLM CAN_MCR_RFLM_Msk /*!< Receive FIFO Locked Mode */ -#define CAN_MCR_NART_Pos (4U) +#define CAN_MCR_NART_Pos (4U) #define CAN_MCR_NART_Msk (0x1U << CAN_MCR_NART_Pos) /*!< 0x00000010 */ #define CAN_MCR_NART CAN_MCR_NART_Msk /*!< No Automatic Retransmission */ -#define CAN_MCR_AWUM_Pos (5U) +#define CAN_MCR_AWUM_Pos (5U) #define CAN_MCR_AWUM_Msk (0x1U << CAN_MCR_AWUM_Pos) /*!< 0x00000020 */ #define CAN_MCR_AWUM CAN_MCR_AWUM_Msk /*!< Automatic Wakeup Mode */ -#define CAN_MCR_ABOM_Pos (6U) +#define CAN_MCR_ABOM_Pos (6U) #define CAN_MCR_ABOM_Msk (0x1U << CAN_MCR_ABOM_Pos) /*!< 0x00000040 */ #define CAN_MCR_ABOM CAN_MCR_ABOM_Msk /*!< Automatic Bus-Off Management */ -#define CAN_MCR_TTCM_Pos (7U) +#define CAN_MCR_TTCM_Pos (7U) #define CAN_MCR_TTCM_Msk (0x1U << CAN_MCR_TTCM_Pos) /*!< 0x00000080 */ #define CAN_MCR_TTCM CAN_MCR_TTCM_Msk /*!< Time Triggered Communication Mode */ -#define CAN_MCR_RESET_Pos (15U) +#define CAN_MCR_RESET_Pos (15U) #define CAN_MCR_RESET_Msk (0x1U << CAN_MCR_RESET_Pos) /*!< 0x00008000 */ #define CAN_MCR_RESET CAN_MCR_RESET_Msk /*!< CAN software master reset */ -#define CAN_MCR_DBF_Pos (16U) +#define CAN_MCR_DBF_Pos (16U) #define CAN_MCR_DBF_Msk (0x1U << CAN_MCR_DBF_Pos) /*!< 0x00010000 */ #define CAN_MCR_DBF CAN_MCR_DBF_Msk /*!< CAN Debug freeze */ /******************* Bit definition for CAN_MSR register ********************/ -#define CAN_MSR_INAK_Pos (0U) +#define CAN_MSR_INAK_Pos (0U) #define CAN_MSR_INAK_Msk (0x1U << CAN_MSR_INAK_Pos) /*!< 0x00000001 */ #define CAN_MSR_INAK CAN_MSR_INAK_Msk /*!< Initialization Acknowledge */ -#define CAN_MSR_SLAK_Pos (1U) +#define CAN_MSR_SLAK_Pos (1U) #define CAN_MSR_SLAK_Msk (0x1U << CAN_MSR_SLAK_Pos) /*!< 0x00000002 */ #define CAN_MSR_SLAK CAN_MSR_SLAK_Msk /*!< Sleep Acknowledge */ -#define CAN_MSR_ERRI_Pos (2U) +#define CAN_MSR_ERRI_Pos (2U) #define CAN_MSR_ERRI_Msk (0x1U << CAN_MSR_ERRI_Pos) /*!< 0x00000004 */ #define CAN_MSR_ERRI CAN_MSR_ERRI_Msk /*!< Error Interrupt */ -#define CAN_MSR_WKUI_Pos (3U) +#define CAN_MSR_WKUI_Pos (3U) #define CAN_MSR_WKUI_Msk (0x1U << CAN_MSR_WKUI_Pos) /*!< 0x00000008 */ #define CAN_MSR_WKUI CAN_MSR_WKUI_Msk /*!< Wakeup Interrupt */ -#define CAN_MSR_SLAKI_Pos (4U) +#define CAN_MSR_SLAKI_Pos (4U) #define CAN_MSR_SLAKI_Msk (0x1U << CAN_MSR_SLAKI_Pos) /*!< 0x00000010 */ #define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk /*!< Sleep Acknowledge Interrupt */ -#define CAN_MSR_TXM_Pos (8U) +#define CAN_MSR_TXM_Pos (8U) #define CAN_MSR_TXM_Msk (0x1U << CAN_MSR_TXM_Pos) /*!< 0x00000100 */ #define CAN_MSR_TXM CAN_MSR_TXM_Msk /*!< Transmit Mode */ -#define CAN_MSR_RXM_Pos (9U) +#define CAN_MSR_RXM_Pos (9U) #define CAN_MSR_RXM_Msk (0x1U << CAN_MSR_RXM_Pos) /*!< 0x00000200 */ #define CAN_MSR_RXM CAN_MSR_RXM_Msk /*!< Receive Mode */ -#define CAN_MSR_SAMP_Pos (10U) +#define CAN_MSR_SAMP_Pos (10U) #define CAN_MSR_SAMP_Msk (0x1U << CAN_MSR_SAMP_Pos) /*!< 0x00000400 */ #define CAN_MSR_SAMP CAN_MSR_SAMP_Msk /*!< Last Sample Point */ -#define CAN_MSR_RX_Pos (11U) +#define CAN_MSR_RX_Pos (11U) #define CAN_MSR_RX_Msk (0x1U << CAN_MSR_RX_Pos) /*!< 0x00000800 */ #define CAN_MSR_RX CAN_MSR_RX_Msk /*!< CAN Rx Signal */ /******************* Bit definition for CAN_TSR register ********************/ -#define CAN_TSR_RQCP0_Pos (0U) +#define CAN_TSR_RQCP0_Pos (0U) #define CAN_TSR_RQCP0_Msk (0x1U << CAN_TSR_RQCP0_Pos) /*!< 0x00000001 */ #define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk /*!< Request Completed Mailbox0 */ -#define CAN_TSR_TXOK0_Pos (1U) +#define CAN_TSR_TXOK0_Pos (1U) #define CAN_TSR_TXOK0_Msk (0x1U << CAN_TSR_TXOK0_Pos) /*!< 0x00000002 */ #define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk /*!< Transmission OK of Mailbox0 */ -#define CAN_TSR_ALST0_Pos (2U) +#define CAN_TSR_ALST0_Pos (2U) #define CAN_TSR_ALST0_Msk (0x1U << CAN_TSR_ALST0_Pos) /*!< 0x00000004 */ #define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk /*!< Arbitration Lost for Mailbox0 */ -#define CAN_TSR_TERR0_Pos (3U) +#define CAN_TSR_TERR0_Pos (3U) #define CAN_TSR_TERR0_Msk (0x1U << CAN_TSR_TERR0_Pos) /*!< 0x00000008 */ #define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk /*!< Transmission Error of Mailbox0 */ -#define CAN_TSR_ABRQ0_Pos (7U) +#define CAN_TSR_ABRQ0_Pos (7U) #define CAN_TSR_ABRQ0_Msk (0x1U << CAN_TSR_ABRQ0_Pos) /*!< 0x00000080 */ #define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk /*!< Abort Request for Mailbox0 */ -#define CAN_TSR_RQCP1_Pos (8U) +#define CAN_TSR_RQCP1_Pos (8U) #define CAN_TSR_RQCP1_Msk (0x1U << CAN_TSR_RQCP1_Pos) /*!< 0x00000100 */ #define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk /*!< Request Completed Mailbox1 */ -#define CAN_TSR_TXOK1_Pos (9U) +#define CAN_TSR_TXOK1_Pos (9U) #define CAN_TSR_TXOK1_Msk (0x1U << CAN_TSR_TXOK1_Pos) /*!< 0x00000200 */ #define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk /*!< Transmission OK of Mailbox1 */ -#define CAN_TSR_ALST1_Pos (10U) +#define CAN_TSR_ALST1_Pos (10U) #define CAN_TSR_ALST1_Msk (0x1U << CAN_TSR_ALST1_Pos) /*!< 0x00000400 */ #define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk /*!< Arbitration Lost for Mailbox1 */ -#define CAN_TSR_TERR1_Pos (11U) +#define CAN_TSR_TERR1_Pos (11U) #define CAN_TSR_TERR1_Msk (0x1U << CAN_TSR_TERR1_Pos) /*!< 0x00000800 */ #define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk /*!< Transmission Error of Mailbox1 */ -#define CAN_TSR_ABRQ1_Pos (15U) +#define CAN_TSR_ABRQ1_Pos (15U) #define CAN_TSR_ABRQ1_Msk (0x1U << CAN_TSR_ABRQ1_Pos) /*!< 0x00008000 */ #define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk /*!< Abort Request for Mailbox 1 */ -#define CAN_TSR_RQCP2_Pos (16U) +#define CAN_TSR_RQCP2_Pos (16U) #define CAN_TSR_RQCP2_Msk (0x1U << CAN_TSR_RQCP2_Pos) /*!< 0x00010000 */ #define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk /*!< Request Completed Mailbox2 */ -#define CAN_TSR_TXOK2_Pos (17U) +#define CAN_TSR_TXOK2_Pos (17U) #define CAN_TSR_TXOK2_Msk (0x1U << CAN_TSR_TXOK2_Pos) /*!< 0x00020000 */ #define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk /*!< Transmission OK of Mailbox 2 */ -#define CAN_TSR_ALST2_Pos (18U) +#define CAN_TSR_ALST2_Pos (18U) #define CAN_TSR_ALST2_Msk (0x1U << CAN_TSR_ALST2_Pos) /*!< 0x00040000 */ #define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk /*!< Arbitration Lost for mailbox 2 */ -#define CAN_TSR_TERR2_Pos (19U) +#define CAN_TSR_TERR2_Pos (19U) #define CAN_TSR_TERR2_Msk (0x1U << CAN_TSR_TERR2_Pos) /*!< 0x00080000 */ #define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk /*!< Transmission Error of Mailbox 2 */ -#define CAN_TSR_ABRQ2_Pos (23U) +#define CAN_TSR_ABRQ2_Pos (23U) #define CAN_TSR_ABRQ2_Msk (0x1U << CAN_TSR_ABRQ2_Pos) /*!< 0x00800000 */ #define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk /*!< Abort Request for Mailbox 2 */ -#define CAN_TSR_CODE_Pos (24U) +#define CAN_TSR_CODE_Pos (24U) #define CAN_TSR_CODE_Msk (0x3U << CAN_TSR_CODE_Pos) /*!< 0x03000000 */ #define CAN_TSR_CODE CAN_TSR_CODE_Msk /*!< Mailbox Code */ -#define CAN_TSR_TME_Pos (26U) +#define CAN_TSR_TME_Pos (26U) #define CAN_TSR_TME_Msk (0x7U << CAN_TSR_TME_Pos) /*!< 0x1C000000 */ #define CAN_TSR_TME CAN_TSR_TME_Msk /*!< TME[2:0] bits */ -#define CAN_TSR_TME0_Pos (26U) +#define CAN_TSR_TME0_Pos (26U) #define CAN_TSR_TME0_Msk (0x1U << CAN_TSR_TME0_Pos) /*!< 0x04000000 */ #define CAN_TSR_TME0 CAN_TSR_TME0_Msk /*!< Transmit Mailbox 0 Empty */ -#define CAN_TSR_TME1_Pos (27U) +#define CAN_TSR_TME1_Pos (27U) #define CAN_TSR_TME1_Msk (0x1U << CAN_TSR_TME1_Pos) /*!< 0x08000000 */ #define CAN_TSR_TME1 CAN_TSR_TME1_Msk /*!< Transmit Mailbox 1 Empty */ -#define CAN_TSR_TME2_Pos (28U) +#define CAN_TSR_TME2_Pos (28U) #define CAN_TSR_TME2_Msk (0x1U << CAN_TSR_TME2_Pos) /*!< 0x10000000 */ #define CAN_TSR_TME2 CAN_TSR_TME2_Msk /*!< Transmit Mailbox 2 Empty */ -#define CAN_TSR_LOW_Pos (29U) +#define CAN_TSR_LOW_Pos (29U) #define CAN_TSR_LOW_Msk (0x7U << CAN_TSR_LOW_Pos) /*!< 0xE0000000 */ #define CAN_TSR_LOW CAN_TSR_LOW_Msk /*!< LOW[2:0] bits */ -#define CAN_TSR_LOW0_Pos (29U) +#define CAN_TSR_LOW0_Pos (29U) #define CAN_TSR_LOW0_Msk (0x1U << CAN_TSR_LOW0_Pos) /*!< 0x20000000 */ #define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk /*!< Lowest Priority Flag for Mailbox 0 */ -#define CAN_TSR_LOW1_Pos (30U) +#define CAN_TSR_LOW1_Pos (30U) #define CAN_TSR_LOW1_Msk (0x1U << CAN_TSR_LOW1_Pos) /*!< 0x40000000 */ #define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk /*!< Lowest Priority Flag for Mailbox 1 */ -#define CAN_TSR_LOW2_Pos (31U) +#define CAN_TSR_LOW2_Pos (31U) #define CAN_TSR_LOW2_Msk (0x1U << CAN_TSR_LOW2_Pos) /*!< 0x80000000 */ #define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk /*!< Lowest Priority Flag for Mailbox 2 */ /******************* Bit definition for CAN_RF0R register *******************/ -#define CAN_RF0R_FMP0_Pos (0U) +#define CAN_RF0R_FMP0_Pos (0U) #define CAN_RF0R_FMP0_Msk (0x3U << CAN_RF0R_FMP0_Pos) /*!< 0x00000003 */ #define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk /*!< FIFO 0 Message Pending */ -#define CAN_RF0R_FULL0_Pos (3U) +#define CAN_RF0R_FULL0_Pos (3U) #define CAN_RF0R_FULL0_Msk (0x1U << CAN_RF0R_FULL0_Pos) /*!< 0x00000008 */ #define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk /*!< FIFO 0 Full */ -#define CAN_RF0R_FOVR0_Pos (4U) +#define CAN_RF0R_FOVR0_Pos (4U) #define CAN_RF0R_FOVR0_Msk (0x1U << CAN_RF0R_FOVR0_Pos) /*!< 0x00000010 */ #define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk /*!< FIFO 0 Overrun */ -#define CAN_RF0R_RFOM0_Pos (5U) +#define CAN_RF0R_RFOM0_Pos (5U) #define CAN_RF0R_RFOM0_Msk (0x1U << CAN_RF0R_RFOM0_Pos) /*!< 0x00000020 */ #define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk /*!< Release FIFO 0 Output Mailbox */ /******************* Bit definition for CAN_RF1R register *******************/ -#define CAN_RF1R_FMP1_Pos (0U) +#define CAN_RF1R_FMP1_Pos (0U) #define CAN_RF1R_FMP1_Msk (0x3U << CAN_RF1R_FMP1_Pos) /*!< 0x00000003 */ #define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk /*!< FIFO 1 Message Pending */ -#define CAN_RF1R_FULL1_Pos (3U) +#define CAN_RF1R_FULL1_Pos (3U) #define CAN_RF1R_FULL1_Msk (0x1U << CAN_RF1R_FULL1_Pos) /*!< 0x00000008 */ #define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk /*!< FIFO 1 Full */ -#define CAN_RF1R_FOVR1_Pos (4U) +#define CAN_RF1R_FOVR1_Pos (4U) #define CAN_RF1R_FOVR1_Msk (0x1U << CAN_RF1R_FOVR1_Pos) /*!< 0x00000010 */ #define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk /*!< FIFO 1 Overrun */ -#define CAN_RF1R_RFOM1_Pos (5U) +#define CAN_RF1R_RFOM1_Pos (5U) #define CAN_RF1R_RFOM1_Msk (0x1U << CAN_RF1R_RFOM1_Pos) /*!< 0x00000020 */ #define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk /*!< Release FIFO 1 Output Mailbox */ /******************** Bit definition for CAN_IER register *******************/ -#define CAN_IER_TMEIE_Pos (0U) +#define CAN_IER_TMEIE_Pos (0U) #define CAN_IER_TMEIE_Msk (0x1U << CAN_IER_TMEIE_Pos) /*!< 0x00000001 */ #define CAN_IER_TMEIE CAN_IER_TMEIE_Msk /*!< Transmit Mailbox Empty Interrupt Enable */ -#define CAN_IER_FMPIE0_Pos (1U) +#define CAN_IER_FMPIE0_Pos (1U) #define CAN_IER_FMPIE0_Msk (0x1U << CAN_IER_FMPIE0_Pos) /*!< 0x00000002 */ #define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk /*!< FIFO Message Pending Interrupt Enable */ -#define CAN_IER_FFIE0_Pos (2U) +#define CAN_IER_FFIE0_Pos (2U) #define CAN_IER_FFIE0_Msk (0x1U << CAN_IER_FFIE0_Pos) /*!< 0x00000004 */ #define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk /*!< FIFO Full Interrupt Enable */ -#define CAN_IER_FOVIE0_Pos (3U) +#define CAN_IER_FOVIE0_Pos (3U) #define CAN_IER_FOVIE0_Msk (0x1U << CAN_IER_FOVIE0_Pos) /*!< 0x00000008 */ #define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk /*!< FIFO Overrun Interrupt Enable */ -#define CAN_IER_FMPIE1_Pos (4U) +#define CAN_IER_FMPIE1_Pos (4U) #define CAN_IER_FMPIE1_Msk (0x1U << CAN_IER_FMPIE1_Pos) /*!< 0x00000010 */ #define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk /*!< FIFO Message Pending Interrupt Enable */ -#define CAN_IER_FFIE1_Pos (5U) +#define CAN_IER_FFIE1_Pos (5U) #define CAN_IER_FFIE1_Msk (0x1U << CAN_IER_FFIE1_Pos) /*!< 0x00000020 */ #define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk /*!< FIFO Full Interrupt Enable */ -#define CAN_IER_FOVIE1_Pos (6U) +#define CAN_IER_FOVIE1_Pos (6U) #define CAN_IER_FOVIE1_Msk (0x1U << CAN_IER_FOVIE1_Pos) /*!< 0x00000040 */ #define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk /*!< FIFO Overrun Interrupt Enable */ -#define CAN_IER_EWGIE_Pos (8U) +#define CAN_IER_EWGIE_Pos (8U) #define CAN_IER_EWGIE_Msk (0x1U << CAN_IER_EWGIE_Pos) /*!< 0x00000100 */ #define CAN_IER_EWGIE CAN_IER_EWGIE_Msk /*!< Error Warning Interrupt Enable */ -#define CAN_IER_EPVIE_Pos (9U) +#define CAN_IER_EPVIE_Pos (9U) #define CAN_IER_EPVIE_Msk (0x1U << CAN_IER_EPVIE_Pos) /*!< 0x00000200 */ #define CAN_IER_EPVIE CAN_IER_EPVIE_Msk /*!< Error Passive Interrupt Enable */ -#define CAN_IER_BOFIE_Pos (10U) +#define CAN_IER_BOFIE_Pos (10U) #define CAN_IER_BOFIE_Msk (0x1U << CAN_IER_BOFIE_Pos) /*!< 0x00000400 */ #define CAN_IER_BOFIE CAN_IER_BOFIE_Msk /*!< Bus-Off Interrupt Enable */ -#define CAN_IER_LECIE_Pos (11U) +#define CAN_IER_LECIE_Pos (11U) #define CAN_IER_LECIE_Msk (0x1U << CAN_IER_LECIE_Pos) /*!< 0x00000800 */ #define CAN_IER_LECIE CAN_IER_LECIE_Msk /*!< Last Error Code Interrupt Enable */ -#define CAN_IER_ERRIE_Pos (15U) +#define CAN_IER_ERRIE_Pos (15U) #define CAN_IER_ERRIE_Msk (0x1U << CAN_IER_ERRIE_Pos) /*!< 0x00008000 */ #define CAN_IER_ERRIE CAN_IER_ERRIE_Msk /*!< Error Interrupt Enable */ -#define CAN_IER_WKUIE_Pos (16U) +#define CAN_IER_WKUIE_Pos (16U) #define CAN_IER_WKUIE_Msk (0x1U << CAN_IER_WKUIE_Pos) /*!< 0x00010000 */ #define CAN_IER_WKUIE CAN_IER_WKUIE_Msk /*!< Wakeup Interrupt Enable */ -#define CAN_IER_SLKIE_Pos (17U) +#define CAN_IER_SLKIE_Pos (17U) #define CAN_IER_SLKIE_Msk (0x1U << CAN_IER_SLKIE_Pos) /*!< 0x00020000 */ #define CAN_IER_SLKIE CAN_IER_SLKIE_Msk /*!< Sleep Interrupt Enable */ /******************** Bit definition for CAN_ESR register *******************/ -#define CAN_ESR_EWGF_Pos (0U) +#define CAN_ESR_EWGF_Pos (0U) #define CAN_ESR_EWGF_Msk (0x1U << CAN_ESR_EWGF_Pos) /*!< 0x00000001 */ #define CAN_ESR_EWGF CAN_ESR_EWGF_Msk /*!< Error Warning Flag */ -#define CAN_ESR_EPVF_Pos (1U) +#define CAN_ESR_EPVF_Pos (1U) #define CAN_ESR_EPVF_Msk (0x1U << CAN_ESR_EPVF_Pos) /*!< 0x00000002 */ #define CAN_ESR_EPVF CAN_ESR_EPVF_Msk /*!< Error Passive Flag */ -#define CAN_ESR_BOFF_Pos (2U) +#define CAN_ESR_BOFF_Pos (2U) #define CAN_ESR_BOFF_Msk (0x1U << CAN_ESR_BOFF_Pos) /*!< 0x00000004 */ #define CAN_ESR_BOFF CAN_ESR_BOFF_Msk /*!< Bus-Off Flag */ -#define CAN_ESR_LEC_Pos (4U) +#define CAN_ESR_LEC_Pos (4U) #define CAN_ESR_LEC_Msk (0x7U << CAN_ESR_LEC_Pos) /*!< 0x00000070 */ #define CAN_ESR_LEC CAN_ESR_LEC_Msk /*!< LEC[2:0] bits (Last Error Code) */ #define CAN_ESR_LEC_0 (0x1U << CAN_ESR_LEC_Pos) /*!< 0x00000010 */ #define CAN_ESR_LEC_1 (0x2U << CAN_ESR_LEC_Pos) /*!< 0x00000020 */ #define CAN_ESR_LEC_2 (0x4U << CAN_ESR_LEC_Pos) /*!< 0x00000040 */ -#define CAN_ESR_TEC_Pos (16U) +#define CAN_ESR_TEC_Pos (16U) #define CAN_ESR_TEC_Msk (0xFFU << CAN_ESR_TEC_Pos) /*!< 0x00FF0000 */ #define CAN_ESR_TEC CAN_ESR_TEC_Msk /*!< Least significant byte of the 9-bit Transmit Error Counter */ -#define CAN_ESR_REC_Pos (24U) +#define CAN_ESR_REC_Pos (24U) #define CAN_ESR_REC_Msk (0xFFU << CAN_ESR_REC_Pos) /*!< 0xFF000000 */ #define CAN_ESR_REC CAN_ESR_REC_Msk /*!< Receive Error Counter */ /******************* Bit definition for CAN_BTR register ********************/ -#define CAN_BTR_BRP_Pos (0U) +#define CAN_BTR_BRP_Pos (0U) #define CAN_BTR_BRP_Msk (0x3FFU << CAN_BTR_BRP_Pos) /*!< 0x000003FF */ #define CAN_BTR_BRP CAN_BTR_BRP_Msk /*!<Baud Rate Prescaler */ -#define CAN_BTR_TS1_Pos (16U) +#define CAN_BTR_TS1_Pos (16U) #define CAN_BTR_TS1_Msk (0xFU << CAN_BTR_TS1_Pos) /*!< 0x000F0000 */ #define CAN_BTR_TS1 CAN_BTR_TS1_Msk /*!<Time Segment 1 */ #define CAN_BTR_TS1_0 (0x1U << CAN_BTR_TS1_Pos) /*!< 0x00010000 */ #define CAN_BTR_TS1_1 (0x2U << CAN_BTR_TS1_Pos) /*!< 0x00020000 */ #define CAN_BTR_TS1_2 (0x4U << CAN_BTR_TS1_Pos) /*!< 0x00040000 */ #define CAN_BTR_TS1_3 (0x8U << CAN_BTR_TS1_Pos) /*!< 0x00080000 */ -#define CAN_BTR_TS2_Pos (20U) +#define CAN_BTR_TS2_Pos (20U) #define CAN_BTR_TS2_Msk (0x7U << CAN_BTR_TS2_Pos) /*!< 0x00700000 */ #define CAN_BTR_TS2 CAN_BTR_TS2_Msk /*!<Time Segment 2 */ #define CAN_BTR_TS2_0 (0x1U << CAN_BTR_TS2_Pos) /*!< 0x00100000 */ #define CAN_BTR_TS2_1 (0x2U << CAN_BTR_TS2_Pos) /*!< 0x00200000 */ #define CAN_BTR_TS2_2 (0x4U << CAN_BTR_TS2_Pos) /*!< 0x00400000 */ -#define CAN_BTR_SJW_Pos (24U) +#define CAN_BTR_SJW_Pos (24U) #define CAN_BTR_SJW_Msk (0x3U << CAN_BTR_SJW_Pos) /*!< 0x03000000 */ #define CAN_BTR_SJW CAN_BTR_SJW_Msk /*!<Resynchronization Jump Width */ #define CAN_BTR_SJW_0 (0x1U << CAN_BTR_SJW_Pos) /*!< 0x01000000 */ #define CAN_BTR_SJW_1 (0x2U << CAN_BTR_SJW_Pos) /*!< 0x02000000 */ -#define CAN_BTR_LBKM_Pos (30U) +#define CAN_BTR_LBKM_Pos (30U) #define CAN_BTR_LBKM_Msk (0x1U << CAN_BTR_LBKM_Pos) /*!< 0x40000000 */ #define CAN_BTR_LBKM CAN_BTR_LBKM_Msk /*!<Loop Back Mode (Debug) */ -#define CAN_BTR_SILM_Pos (31U) +#define CAN_BTR_SILM_Pos (31U) #define CAN_BTR_SILM_Msk (0x1U << CAN_BTR_SILM_Pos) /*!< 0x80000000 */ #define CAN_BTR_SILM CAN_BTR_SILM_Msk /*!<Silent Mode */ /*!< Mailbox registers */ /****************** Bit definition for CAN_TI0R register ********************/ -#define CAN_TI0R_TXRQ_Pos (0U) +#define CAN_TI0R_TXRQ_Pos (0U) #define CAN_TI0R_TXRQ_Msk (0x1U << CAN_TI0R_TXRQ_Pos) /*!< 0x00000001 */ #define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk /*!< Transmit Mailbox Request */ -#define CAN_TI0R_RTR_Pos (1U) +#define CAN_TI0R_RTR_Pos (1U) #define CAN_TI0R_RTR_Msk (0x1U << CAN_TI0R_RTR_Pos) /*!< 0x00000002 */ #define CAN_TI0R_RTR CAN_TI0R_RTR_Msk /*!< Remote Transmission Request */ -#define CAN_TI0R_IDE_Pos (2U) +#define CAN_TI0R_IDE_Pos (2U) #define CAN_TI0R_IDE_Msk (0x1U << CAN_TI0R_IDE_Pos) /*!< 0x00000004 */ #define CAN_TI0R_IDE CAN_TI0R_IDE_Msk /*!< Identifier Extension */ -#define CAN_TI0R_EXID_Pos (3U) +#define CAN_TI0R_EXID_Pos (3U) #define CAN_TI0R_EXID_Msk (0x3FFFFU << CAN_TI0R_EXID_Pos) /*!< 0x001FFFF8 */ #define CAN_TI0R_EXID CAN_TI0R_EXID_Msk /*!< Extended Identifier */ -#define CAN_TI0R_STID_Pos (21U) +#define CAN_TI0R_STID_Pos (21U) #define CAN_TI0R_STID_Msk (0x7FFU << CAN_TI0R_STID_Pos) /*!< 0xFFE00000 */ #define CAN_TI0R_STID CAN_TI0R_STID_Msk /*!< Standard Identifier or Extended Identifier */ /****************** Bit definition for CAN_TDT0R register *******************/ -#define CAN_TDT0R_DLC_Pos (0U) +#define CAN_TDT0R_DLC_Pos (0U) #define CAN_TDT0R_DLC_Msk (0xFU << CAN_TDT0R_DLC_Pos) /*!< 0x0000000F */ #define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk /*!< Data Length Code */ -#define CAN_TDT0R_TGT_Pos (8U) +#define CAN_TDT0R_TGT_Pos (8U) #define CAN_TDT0R_TGT_Msk (0x1U << CAN_TDT0R_TGT_Pos) /*!< 0x00000100 */ #define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk /*!< Transmit Global Time */ -#define CAN_TDT0R_TIME_Pos (16U) +#define CAN_TDT0R_TIME_Pos (16U) #define CAN_TDT0R_TIME_Msk (0xFFFFU << CAN_TDT0R_TIME_Pos) /*!< 0xFFFF0000 */ #define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk /*!< Message Time Stamp */ /****************** Bit definition for CAN_TDL0R register *******************/ -#define CAN_TDL0R_DATA0_Pos (0U) +#define CAN_TDL0R_DATA0_Pos (0U) #define CAN_TDL0R_DATA0_Msk (0xFFU << CAN_TDL0R_DATA0_Pos) /*!< 0x000000FF */ #define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk /*!< Data byte 0 */ -#define CAN_TDL0R_DATA1_Pos (8U) +#define CAN_TDL0R_DATA1_Pos (8U) #define CAN_TDL0R_DATA1_Msk (0xFFU << CAN_TDL0R_DATA1_Pos) /*!< 0x0000FF00 */ #define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk /*!< Data byte 1 */ -#define CAN_TDL0R_DATA2_Pos (16U) +#define CAN_TDL0R_DATA2_Pos (16U) #define CAN_TDL0R_DATA2_Msk (0xFFU << CAN_TDL0R_DATA2_Pos) /*!< 0x00FF0000 */ #define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk /*!< Data byte 2 */ -#define CAN_TDL0R_DATA3_Pos (24U) +#define CAN_TDL0R_DATA3_Pos (24U) #define CAN_TDL0R_DATA3_Msk (0xFFU << CAN_TDL0R_DATA3_Pos) /*!< 0xFF000000 */ #define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk /*!< Data byte 3 */ /****************** Bit definition for CAN_TDH0R register *******************/ -#define CAN_TDH0R_DATA4_Pos (0U) +#define CAN_TDH0R_DATA4_Pos (0U) #define CAN_TDH0R_DATA4_Msk (0xFFU << CAN_TDH0R_DATA4_Pos) /*!< 0x000000FF */ #define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk /*!< Data byte 4 */ -#define CAN_TDH0R_DATA5_Pos (8U) +#define CAN_TDH0R_DATA5_Pos (8U) #define CAN_TDH0R_DATA5_Msk (0xFFU << CAN_TDH0R_DATA5_Pos) /*!< 0x0000FF00 */ #define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk /*!< Data byte 5 */ -#define CAN_TDH0R_DATA6_Pos (16U) +#define CAN_TDH0R_DATA6_Pos (16U) #define CAN_TDH0R_DATA6_Msk (0xFFU << CAN_TDH0R_DATA6_Pos) /*!< 0x00FF0000 */ #define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk /*!< Data byte 6 */ -#define CAN_TDH0R_DATA7_Pos (24U) +#define CAN_TDH0R_DATA7_Pos (24U) #define CAN_TDH0R_DATA7_Msk (0xFFU << CAN_TDH0R_DATA7_Pos) /*!< 0xFF000000 */ #define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk /*!< Data byte 7 */ /******************* Bit definition for CAN_TI1R register *******************/ -#define CAN_TI1R_TXRQ_Pos (0U) +#define CAN_TI1R_TXRQ_Pos (0U) #define CAN_TI1R_TXRQ_Msk (0x1U << CAN_TI1R_TXRQ_Pos) /*!< 0x00000001 */ #define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk /*!< Transmit Mailbox Request */ -#define CAN_TI1R_RTR_Pos (1U) +#define CAN_TI1R_RTR_Pos (1U) #define CAN_TI1R_RTR_Msk (0x1U << CAN_TI1R_RTR_Pos) /*!< 0x00000002 */ #define CAN_TI1R_RTR CAN_TI1R_RTR_Msk /*!< Remote Transmission Request */ -#define CAN_TI1R_IDE_Pos (2U) +#define CAN_TI1R_IDE_Pos (2U) #define CAN_TI1R_IDE_Msk (0x1U << CAN_TI1R_IDE_Pos) /*!< 0x00000004 */ #define CAN_TI1R_IDE CAN_TI1R_IDE_Msk /*!< Identifier Extension */ -#define CAN_TI1R_EXID_Pos (3U) +#define CAN_TI1R_EXID_Pos (3U) #define CAN_TI1R_EXID_Msk (0x3FFFFU << CAN_TI1R_EXID_Pos) /*!< 0x001FFFF8 */ #define CAN_TI1R_EXID CAN_TI1R_EXID_Msk /*!< Extended Identifier */ -#define CAN_TI1R_STID_Pos (21U) +#define CAN_TI1R_STID_Pos (21U) #define CAN_TI1R_STID_Msk (0x7FFU << CAN_TI1R_STID_Pos) /*!< 0xFFE00000 */ #define CAN_TI1R_STID CAN_TI1R_STID_Msk /*!< Standard Identifier or Extended Identifier */ /******************* Bit definition for CAN_TDT1R register ******************/ -#define CAN_TDT1R_DLC_Pos (0U) +#define CAN_TDT1R_DLC_Pos (0U) #define CAN_TDT1R_DLC_Msk (0xFU << CAN_TDT1R_DLC_Pos) /*!< 0x0000000F */ #define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk /*!< Data Length Code */ -#define CAN_TDT1R_TGT_Pos (8U) +#define CAN_TDT1R_TGT_Pos (8U) #define CAN_TDT1R_TGT_Msk (0x1U << CAN_TDT1R_TGT_Pos) /*!< 0x00000100 */ #define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk /*!< Transmit Global Time */ -#define CAN_TDT1R_TIME_Pos (16U) +#define CAN_TDT1R_TIME_Pos (16U) #define CAN_TDT1R_TIME_Msk (0xFFFFU << CAN_TDT1R_TIME_Pos) /*!< 0xFFFF0000 */ #define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk /*!< Message Time Stamp */ /******************* Bit definition for CAN_TDL1R register ******************/ -#define CAN_TDL1R_DATA0_Pos (0U) +#define CAN_TDL1R_DATA0_Pos (0U) #define CAN_TDL1R_DATA0_Msk (0xFFU << CAN_TDL1R_DATA0_Pos) /*!< 0x000000FF */ #define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk /*!< Data byte 0 */ -#define CAN_TDL1R_DATA1_Pos (8U) +#define CAN_TDL1R_DATA1_Pos (8U) #define CAN_TDL1R_DATA1_Msk (0xFFU << CAN_TDL1R_DATA1_Pos) /*!< 0x0000FF00 */ #define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk /*!< Data byte 1 */ -#define CAN_TDL1R_DATA2_Pos (16U) +#define CAN_TDL1R_DATA2_Pos (16U) #define CAN_TDL1R_DATA2_Msk (0xFFU << CAN_TDL1R_DATA2_Pos) /*!< 0x00FF0000 */ #define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk /*!< Data byte 2 */ -#define CAN_TDL1R_DATA3_Pos (24U) +#define CAN_TDL1R_DATA3_Pos (24U) #define CAN_TDL1R_DATA3_Msk (0xFFU << CAN_TDL1R_DATA3_Pos) /*!< 0xFF000000 */ #define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk /*!< Data byte 3 */ /******************* Bit definition for CAN_TDH1R register ******************/ -#define CAN_TDH1R_DATA4_Pos (0U) +#define CAN_TDH1R_DATA4_Pos (0U) #define CAN_TDH1R_DATA4_Msk (0xFFU << CAN_TDH1R_DATA4_Pos) /*!< 0x000000FF */ #define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk /*!< Data byte 4 */ -#define CAN_TDH1R_DATA5_Pos (8U) +#define CAN_TDH1R_DATA5_Pos (8U) #define CAN_TDH1R_DATA5_Msk (0xFFU << CAN_TDH1R_DATA5_Pos) /*!< 0x0000FF00 */ #define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk /*!< Data byte 5 */ -#define CAN_TDH1R_DATA6_Pos (16U) +#define CAN_TDH1R_DATA6_Pos (16U) #define CAN_TDH1R_DATA6_Msk (0xFFU << CAN_TDH1R_DATA6_Pos) /*!< 0x00FF0000 */ #define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk /*!< Data byte 6 */ -#define CAN_TDH1R_DATA7_Pos (24U) +#define CAN_TDH1R_DATA7_Pos (24U) #define CAN_TDH1R_DATA7_Msk (0xFFU << CAN_TDH1R_DATA7_Pos) /*!< 0xFF000000 */ #define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk /*!< Data byte 7 */ /******************* Bit definition for CAN_TI2R register *******************/ -#define CAN_TI2R_TXRQ_Pos (0U) +#define CAN_TI2R_TXRQ_Pos (0U) #define CAN_TI2R_TXRQ_Msk (0x1U << CAN_TI2R_TXRQ_Pos) /*!< 0x00000001 */ #define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk /*!< Transmit Mailbox Request */ -#define CAN_TI2R_RTR_Pos (1U) +#define CAN_TI2R_RTR_Pos (1U) #define CAN_TI2R_RTR_Msk (0x1U << CAN_TI2R_RTR_Pos) /*!< 0x00000002 */ #define CAN_TI2R_RTR CAN_TI2R_RTR_Msk /*!< Remote Transmission Request */ -#define CAN_TI2R_IDE_Pos (2U) +#define CAN_TI2R_IDE_Pos (2U) #define CAN_TI2R_IDE_Msk (0x1U << CAN_TI2R_IDE_Pos) /*!< 0x00000004 */ #define CAN_TI2R_IDE CAN_TI2R_IDE_Msk /*!< Identifier Extension */ -#define CAN_TI2R_EXID_Pos (3U) +#define CAN_TI2R_EXID_Pos (3U) #define CAN_TI2R_EXID_Msk (0x3FFFFU << CAN_TI2R_EXID_Pos) /*!< 0x001FFFF8 */ #define CAN_TI2R_EXID CAN_TI2R_EXID_Msk /*!< Extended identifier */ -#define CAN_TI2R_STID_Pos (21U) +#define CAN_TI2R_STID_Pos (21U) #define CAN_TI2R_STID_Msk (0x7FFU << CAN_TI2R_STID_Pos) /*!< 0xFFE00000 */ #define CAN_TI2R_STID CAN_TI2R_STID_Msk /*!< Standard Identifier or Extended Identifier */ -/******************* Bit definition for CAN_TDT2R register ******************/ -#define CAN_TDT2R_DLC_Pos (0U) +/******************* Bit definition for CAN_TDT2R register ******************/ +#define CAN_TDT2R_DLC_Pos (0U) #define CAN_TDT2R_DLC_Msk (0xFU << CAN_TDT2R_DLC_Pos) /*!< 0x0000000F */ #define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk /*!< Data Length Code */ -#define CAN_TDT2R_TGT_Pos (8U) +#define CAN_TDT2R_TGT_Pos (8U) #define CAN_TDT2R_TGT_Msk (0x1U << CAN_TDT2R_TGT_Pos) /*!< 0x00000100 */ #define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk /*!< Transmit Global Time */ -#define CAN_TDT2R_TIME_Pos (16U) +#define CAN_TDT2R_TIME_Pos (16U) #define CAN_TDT2R_TIME_Msk (0xFFFFU << CAN_TDT2R_TIME_Pos) /*!< 0xFFFF0000 */ #define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk /*!< Message Time Stamp */ /******************* Bit definition for CAN_TDL2R register ******************/ -#define CAN_TDL2R_DATA0_Pos (0U) +#define CAN_TDL2R_DATA0_Pos (0U) #define CAN_TDL2R_DATA0_Msk (0xFFU << CAN_TDL2R_DATA0_Pos) /*!< 0x000000FF */ #define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk /*!< Data byte 0 */ -#define CAN_TDL2R_DATA1_Pos (8U) +#define CAN_TDL2R_DATA1_Pos (8U) #define CAN_TDL2R_DATA1_Msk (0xFFU << CAN_TDL2R_DATA1_Pos) /*!< 0x0000FF00 */ #define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk /*!< Data byte 1 */ -#define CAN_TDL2R_DATA2_Pos (16U) +#define CAN_TDL2R_DATA2_Pos (16U) #define CAN_TDL2R_DATA2_Msk (0xFFU << CAN_TDL2R_DATA2_Pos) /*!< 0x00FF0000 */ #define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk /*!< Data byte 2 */ -#define CAN_TDL2R_DATA3_Pos (24U) +#define CAN_TDL2R_DATA3_Pos (24U) #define CAN_TDL2R_DATA3_Msk (0xFFU << CAN_TDL2R_DATA3_Pos) /*!< 0xFF000000 */ #define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk /*!< Data byte 3 */ /******************* Bit definition for CAN_TDH2R register ******************/ -#define CAN_TDH2R_DATA4_Pos (0U) +#define CAN_TDH2R_DATA4_Pos (0U) #define CAN_TDH2R_DATA4_Msk (0xFFU << CAN_TDH2R_DATA4_Pos) /*!< 0x000000FF */ #define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk /*!< Data byte 4 */ -#define CAN_TDH2R_DATA5_Pos (8U) +#define CAN_TDH2R_DATA5_Pos (8U) #define CAN_TDH2R_DATA5_Msk (0xFFU << CAN_TDH2R_DATA5_Pos) /*!< 0x0000FF00 */ #define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk /*!< Data byte 5 */ -#define CAN_TDH2R_DATA6_Pos (16U) +#define CAN_TDH2R_DATA6_Pos (16U) #define CAN_TDH2R_DATA6_Msk (0xFFU << CAN_TDH2R_DATA6_Pos) /*!< 0x00FF0000 */ #define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk /*!< Data byte 6 */ -#define CAN_TDH2R_DATA7_Pos (24U) +#define CAN_TDH2R_DATA7_Pos (24U) #define CAN_TDH2R_DATA7_Msk (0xFFU << CAN_TDH2R_DATA7_Pos) /*!< 0xFF000000 */ #define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk /*!< Data byte 7 */ /******************* Bit definition for CAN_RI0R register *******************/ -#define CAN_RI0R_RTR_Pos (1U) +#define CAN_RI0R_RTR_Pos (1U) #define CAN_RI0R_RTR_Msk (0x1U << CAN_RI0R_RTR_Pos) /*!< 0x00000002 */ #define CAN_RI0R_RTR CAN_RI0R_RTR_Msk /*!< Remote Transmission Request */ -#define CAN_RI0R_IDE_Pos (2U) +#define CAN_RI0R_IDE_Pos (2U) #define CAN_RI0R_IDE_Msk (0x1U << CAN_RI0R_IDE_Pos) /*!< 0x00000004 */ #define CAN_RI0R_IDE CAN_RI0R_IDE_Msk /*!< Identifier Extension */ -#define CAN_RI0R_EXID_Pos (3U) +#define CAN_RI0R_EXID_Pos (3U) #define CAN_RI0R_EXID_Msk (0x3FFFFU << CAN_RI0R_EXID_Pos) /*!< 0x001FFFF8 */ #define CAN_RI0R_EXID CAN_RI0R_EXID_Msk /*!< Extended Identifier */ -#define CAN_RI0R_STID_Pos (21U) +#define CAN_RI0R_STID_Pos (21U) #define CAN_RI0R_STID_Msk (0x7FFU << CAN_RI0R_STID_Pos) /*!< 0xFFE00000 */ #define CAN_RI0R_STID CAN_RI0R_STID_Msk /*!< Standard Identifier or Extended Identifier */ /******************* Bit definition for CAN_RDT0R register ******************/ -#define CAN_RDT0R_DLC_Pos (0U) +#define CAN_RDT0R_DLC_Pos (0U) #define CAN_RDT0R_DLC_Msk (0xFU << CAN_RDT0R_DLC_Pos) /*!< 0x0000000F */ #define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk /*!< Data Length Code */ -#define CAN_RDT0R_FMI_Pos (8U) +#define CAN_RDT0R_FMI_Pos (8U) #define CAN_RDT0R_FMI_Msk (0xFFU << CAN_RDT0R_FMI_Pos) /*!< 0x0000FF00 */ #define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk /*!< Filter Match Index */ -#define CAN_RDT0R_TIME_Pos (16U) +#define CAN_RDT0R_TIME_Pos (16U) #define CAN_RDT0R_TIME_Msk (0xFFFFU << CAN_RDT0R_TIME_Pos) /*!< 0xFFFF0000 */ #define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk /*!< Message Time Stamp */ /******************* Bit definition for CAN_RDL0R register ******************/ -#define CAN_RDL0R_DATA0_Pos (0U) +#define CAN_RDL0R_DATA0_Pos (0U) #define CAN_RDL0R_DATA0_Msk (0xFFU << CAN_RDL0R_DATA0_Pos) /*!< 0x000000FF */ #define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk /*!< Data byte 0 */ -#define CAN_RDL0R_DATA1_Pos (8U) +#define CAN_RDL0R_DATA1_Pos (8U) #define CAN_RDL0R_DATA1_Msk (0xFFU << CAN_RDL0R_DATA1_Pos) /*!< 0x0000FF00 */ #define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk /*!< Data byte 1 */ -#define CAN_RDL0R_DATA2_Pos (16U) +#define CAN_RDL0R_DATA2_Pos (16U) #define CAN_RDL0R_DATA2_Msk (0xFFU << CAN_RDL0R_DATA2_Pos) /*!< 0x00FF0000 */ #define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk /*!< Data byte 2 */ -#define CAN_RDL0R_DATA3_Pos (24U) +#define CAN_RDL0R_DATA3_Pos (24U) #define CAN_RDL0R_DATA3_Msk (0xFFU << CAN_RDL0R_DATA3_Pos) /*!< 0xFF000000 */ #define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk /*!< Data byte 3 */ /******************* Bit definition for CAN_RDH0R register ******************/ -#define CAN_RDH0R_DATA4_Pos (0U) +#define CAN_RDH0R_DATA4_Pos (0U) #define CAN_RDH0R_DATA4_Msk (0xFFU << CAN_RDH0R_DATA4_Pos) /*!< 0x000000FF */ #define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk /*!< Data byte 4 */ -#define CAN_RDH0R_DATA5_Pos (8U) +#define CAN_RDH0R_DATA5_Pos (8U) #define CAN_RDH0R_DATA5_Msk (0xFFU << CAN_RDH0R_DATA5_Pos) /*!< 0x0000FF00 */ #define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk /*!< Data byte 5 */ -#define CAN_RDH0R_DATA6_Pos (16U) +#define CAN_RDH0R_DATA6_Pos (16U) #define CAN_RDH0R_DATA6_Msk (0xFFU << CAN_RDH0R_DATA6_Pos) /*!< 0x00FF0000 */ #define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk /*!< Data byte 6 */ -#define CAN_RDH0R_DATA7_Pos (24U) +#define CAN_RDH0R_DATA7_Pos (24U) #define CAN_RDH0R_DATA7_Msk (0xFFU << CAN_RDH0R_DATA7_Pos) /*!< 0xFF000000 */ #define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk /*!< Data byte 7 */ /******************* Bit definition for CAN_RI1R register *******************/ -#define CAN_RI1R_RTR_Pos (1U) +#define CAN_RI1R_RTR_Pos (1U) #define CAN_RI1R_RTR_Msk (0x1U << CAN_RI1R_RTR_Pos) /*!< 0x00000002 */ #define CAN_RI1R_RTR CAN_RI1R_RTR_Msk /*!< Remote Transmission Request */ -#define CAN_RI1R_IDE_Pos (2U) +#define CAN_RI1R_IDE_Pos (2U) #define CAN_RI1R_IDE_Msk (0x1U << CAN_RI1R_IDE_Pos) /*!< 0x00000004 */ #define CAN_RI1R_IDE CAN_RI1R_IDE_Msk /*!< Identifier Extension */ -#define CAN_RI1R_EXID_Pos (3U) +#define CAN_RI1R_EXID_Pos (3U) #define CAN_RI1R_EXID_Msk (0x3FFFFU << CAN_RI1R_EXID_Pos) /*!< 0x001FFFF8 */ #define CAN_RI1R_EXID CAN_RI1R_EXID_Msk /*!< Extended identifier */ -#define CAN_RI1R_STID_Pos (21U) +#define CAN_RI1R_STID_Pos (21U) #define CAN_RI1R_STID_Msk (0x7FFU << CAN_RI1R_STID_Pos) /*!< 0xFFE00000 */ #define CAN_RI1R_STID CAN_RI1R_STID_Msk /*!< Standard Identifier or Extended Identifier */ /******************* Bit definition for CAN_RDT1R register ******************/ -#define CAN_RDT1R_DLC_Pos (0U) +#define CAN_RDT1R_DLC_Pos (0U) #define CAN_RDT1R_DLC_Msk (0xFU << CAN_RDT1R_DLC_Pos) /*!< 0x0000000F */ #define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk /*!< Data Length Code */ -#define CAN_RDT1R_FMI_Pos (8U) +#define CAN_RDT1R_FMI_Pos (8U) #define CAN_RDT1R_FMI_Msk (0xFFU << CAN_RDT1R_FMI_Pos) /*!< 0x0000FF00 */ #define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk /*!< Filter Match Index */ -#define CAN_RDT1R_TIME_Pos (16U) +#define CAN_RDT1R_TIME_Pos (16U) #define CAN_RDT1R_TIME_Msk (0xFFFFU << CAN_RDT1R_TIME_Pos) /*!< 0xFFFF0000 */ #define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk /*!< Message Time Stamp */ /******************* Bit definition for CAN_RDL1R register ******************/ -#define CAN_RDL1R_DATA0_Pos (0U) +#define CAN_RDL1R_DATA0_Pos (0U) #define CAN_RDL1R_DATA0_Msk (0xFFU << CAN_RDL1R_DATA0_Pos) /*!< 0x000000FF */ #define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk /*!< Data byte 0 */ -#define CAN_RDL1R_DATA1_Pos (8U) +#define CAN_RDL1R_DATA1_Pos (8U) #define CAN_RDL1R_DATA1_Msk (0xFFU << CAN_RDL1R_DATA1_Pos) /*!< 0x0000FF00 */ #define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk /*!< Data byte 1 */ -#define CAN_RDL1R_DATA2_Pos (16U) +#define CAN_RDL1R_DATA2_Pos (16U) #define CAN_RDL1R_DATA2_Msk (0xFFU << CAN_RDL1R_DATA2_Pos) /*!< 0x00FF0000 */ #define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk /*!< Data byte 2 */ -#define CAN_RDL1R_DATA3_Pos (24U) +#define CAN_RDL1R_DATA3_Pos (24U) #define CAN_RDL1R_DATA3_Msk (0xFFU << CAN_RDL1R_DATA3_Pos) /*!< 0xFF000000 */ #define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk /*!< Data byte 3 */ /******************* Bit definition for CAN_RDH1R register ******************/ -#define CAN_RDH1R_DATA4_Pos (0U) +#define CAN_RDH1R_DATA4_Pos (0U) #define CAN_RDH1R_DATA4_Msk (0xFFU << CAN_RDH1R_DATA4_Pos) /*!< 0x000000FF */ #define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk /*!< Data byte 4 */ -#define CAN_RDH1R_DATA5_Pos (8U) +#define CAN_RDH1R_DATA5_Pos (8U) #define CAN_RDH1R_DATA5_Msk (0xFFU << CAN_RDH1R_DATA5_Pos) /*!< 0x0000FF00 */ #define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk /*!< Data byte 5 */ -#define CAN_RDH1R_DATA6_Pos (16U) +#define CAN_RDH1R_DATA6_Pos (16U) #define CAN_RDH1R_DATA6_Msk (0xFFU << CAN_RDH1R_DATA6_Pos) /*!< 0x00FF0000 */ #define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk /*!< Data byte 6 */ -#define CAN_RDH1R_DATA7_Pos (24U) +#define CAN_RDH1R_DATA7_Pos (24U) #define CAN_RDH1R_DATA7_Msk (0xFFU << CAN_RDH1R_DATA7_Pos) /*!< 0xFF000000 */ #define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk /*!< Data byte 7 */ /*!< CAN filter registers */ /******************* Bit definition for CAN_FMR register ********************/ -#define CAN_FMR_FINIT_Pos (0U) +#define CAN_FMR_FINIT_Pos (0U) #define CAN_FMR_FINIT_Msk (0x1U << CAN_FMR_FINIT_Pos) /*!< 0x00000001 */ #define CAN_FMR_FINIT CAN_FMR_FINIT_Msk /*!< Filter Init Mode */ -#define CAN_FMR_CAN2SB_Pos (8U) +#define CAN_FMR_CAN2SB_Pos (8U) #define CAN_FMR_CAN2SB_Msk (0x3FU << CAN_FMR_CAN2SB_Pos) /*!< 0x00003F00 */ #define CAN_FMR_CAN2SB CAN_FMR_CAN2SB_Msk /*!< CAN2 start bank */ /******************* Bit definition for CAN_FM1R register *******************/ -#define CAN_FM1R_FBM_Pos (0U) +#define CAN_FM1R_FBM_Pos (0U) #define CAN_FM1R_FBM_Msk (0x3FFFU << CAN_FM1R_FBM_Pos) /*!< 0x00003FFF */ #define CAN_FM1R_FBM CAN_FM1R_FBM_Msk /*!< Filter Mode */ -#define CAN_FM1R_FBM0_Pos (0U) +#define CAN_FM1R_FBM0_Pos (0U) #define CAN_FM1R_FBM0_Msk (0x1U << CAN_FM1R_FBM0_Pos) /*!< 0x00000001 */ #define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk /*!< Filter Init Mode for filter 0 */ -#define CAN_FM1R_FBM1_Pos (1U) +#define CAN_FM1R_FBM1_Pos (1U) #define CAN_FM1R_FBM1_Msk (0x1U << CAN_FM1R_FBM1_Pos) /*!< 0x00000002 */ #define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk /*!< Filter Init Mode for filter 1 */ -#define CAN_FM1R_FBM2_Pos (2U) +#define CAN_FM1R_FBM2_Pos (2U) #define CAN_FM1R_FBM2_Msk (0x1U << CAN_FM1R_FBM2_Pos) /*!< 0x00000004 */ #define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk /*!< Filter Init Mode for filter 2 */ -#define CAN_FM1R_FBM3_Pos (3U) +#define CAN_FM1R_FBM3_Pos (3U) #define CAN_FM1R_FBM3_Msk (0x1U << CAN_FM1R_FBM3_Pos) /*!< 0x00000008 */ #define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk /*!< Filter Init Mode for filter 3 */ -#define CAN_FM1R_FBM4_Pos (4U) +#define CAN_FM1R_FBM4_Pos (4U) #define CAN_FM1R_FBM4_Msk (0x1U << CAN_FM1R_FBM4_Pos) /*!< 0x00000010 */ #define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk /*!< Filter Init Mode for filter 4 */ -#define CAN_FM1R_FBM5_Pos (5U) +#define CAN_FM1R_FBM5_Pos (5U) #define CAN_FM1R_FBM5_Msk (0x1U << CAN_FM1R_FBM5_Pos) /*!< 0x00000020 */ #define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk /*!< Filter Init Mode for filter 5 */ -#define CAN_FM1R_FBM6_Pos (6U) +#define CAN_FM1R_FBM6_Pos (6U) #define CAN_FM1R_FBM6_Msk (0x1U << CAN_FM1R_FBM6_Pos) /*!< 0x00000040 */ #define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk /*!< Filter Init Mode for filter 6 */ -#define CAN_FM1R_FBM7_Pos (7U) +#define CAN_FM1R_FBM7_Pos (7U) #define CAN_FM1R_FBM7_Msk (0x1U << CAN_FM1R_FBM7_Pos) /*!< 0x00000080 */ #define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk /*!< Filter Init Mode for filter 7 */ -#define CAN_FM1R_FBM8_Pos (8U) +#define CAN_FM1R_FBM8_Pos (8U) #define CAN_FM1R_FBM8_Msk (0x1U << CAN_FM1R_FBM8_Pos) /*!< 0x00000100 */ #define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk /*!< Filter Init Mode for filter 8 */ -#define CAN_FM1R_FBM9_Pos (9U) +#define CAN_FM1R_FBM9_Pos (9U) #define CAN_FM1R_FBM9_Msk (0x1U << CAN_FM1R_FBM9_Pos) /*!< 0x00000200 */ #define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk /*!< Filter Init Mode for filter 9 */ -#define CAN_FM1R_FBM10_Pos (10U) +#define CAN_FM1R_FBM10_Pos (10U) #define CAN_FM1R_FBM10_Msk (0x1U << CAN_FM1R_FBM10_Pos) /*!< 0x00000400 */ #define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk /*!< Filter Init Mode for filter 10 */ -#define CAN_FM1R_FBM11_Pos (11U) +#define CAN_FM1R_FBM11_Pos (11U) #define CAN_FM1R_FBM11_Msk (0x1U << CAN_FM1R_FBM11_Pos) /*!< 0x00000800 */ #define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk /*!< Filter Init Mode for filter 11 */ -#define CAN_FM1R_FBM12_Pos (12U) +#define CAN_FM1R_FBM12_Pos (12U) #define CAN_FM1R_FBM12_Msk (0x1U << CAN_FM1R_FBM12_Pos) /*!< 0x00001000 */ #define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk /*!< Filter Init Mode for filter 12 */ -#define CAN_FM1R_FBM13_Pos (13U) +#define CAN_FM1R_FBM13_Pos (13U) #define CAN_FM1R_FBM13_Msk (0x1U << CAN_FM1R_FBM13_Pos) /*!< 0x00002000 */ #define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk /*!< Filter Init Mode for filter 13 */ /******************* Bit definition for CAN_FS1R register *******************/ -#define CAN_FS1R_FSC_Pos (0U) +#define CAN_FS1R_FSC_Pos (0U) #define CAN_FS1R_FSC_Msk (0x3FFFU << CAN_FS1R_FSC_Pos) /*!< 0x00003FFF */ #define CAN_FS1R_FSC CAN_FS1R_FSC_Msk /*!< Filter Scale Configuration */ -#define CAN_FS1R_FSC0_Pos (0U) +#define CAN_FS1R_FSC0_Pos (0U) #define CAN_FS1R_FSC0_Msk (0x1U << CAN_FS1R_FSC0_Pos) /*!< 0x00000001 */ #define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk /*!< Filter Scale Configuration for filter 0 */ -#define CAN_FS1R_FSC1_Pos (1U) +#define CAN_FS1R_FSC1_Pos (1U) #define CAN_FS1R_FSC1_Msk (0x1U << CAN_FS1R_FSC1_Pos) /*!< 0x00000002 */ #define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk /*!< Filter Scale Configuration for filter 1 */ -#define CAN_FS1R_FSC2_Pos (2U) +#define CAN_FS1R_FSC2_Pos (2U) #define CAN_FS1R_FSC2_Msk (0x1U << CAN_FS1R_FSC2_Pos) /*!< 0x00000004 */ #define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk /*!< Filter Scale Configuration for filter 2 */ -#define CAN_FS1R_FSC3_Pos (3U) +#define CAN_FS1R_FSC3_Pos (3U) #define CAN_FS1R_FSC3_Msk (0x1U << CAN_FS1R_FSC3_Pos) /*!< 0x00000008 */ #define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk /*!< Filter Scale Configuration for filter 3 */ -#define CAN_FS1R_FSC4_Pos (4U) +#define CAN_FS1R_FSC4_Pos (4U) #define CAN_FS1R_FSC4_Msk (0x1U << CAN_FS1R_FSC4_Pos) /*!< 0x00000010 */ #define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk /*!< Filter Scale Configuration for filter 4 */ -#define CAN_FS1R_FSC5_Pos (5U) +#define CAN_FS1R_FSC5_Pos (5U) #define CAN_FS1R_FSC5_Msk (0x1U << CAN_FS1R_FSC5_Pos) /*!< 0x00000020 */ #define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk /*!< Filter Scale Configuration for filter 5 */ -#define CAN_FS1R_FSC6_Pos (6U) +#define CAN_FS1R_FSC6_Pos (6U) #define CAN_FS1R_FSC6_Msk (0x1U << CAN_FS1R_FSC6_Pos) /*!< 0x00000040 */ #define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk /*!< Filter Scale Configuration for filter 6 */ -#define CAN_FS1R_FSC7_Pos (7U) +#define CAN_FS1R_FSC7_Pos (7U) #define CAN_FS1R_FSC7_Msk (0x1U << CAN_FS1R_FSC7_Pos) /*!< 0x00000080 */ #define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk /*!< Filter Scale Configuration for filter 7 */ -#define CAN_FS1R_FSC8_Pos (8U) +#define CAN_FS1R_FSC8_Pos (8U) #define CAN_FS1R_FSC8_Msk (0x1U << CAN_FS1R_FSC8_Pos) /*!< 0x00000100 */ #define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk /*!< Filter Scale Configuration for filter 8 */ -#define CAN_FS1R_FSC9_Pos (9U) +#define CAN_FS1R_FSC9_Pos (9U) #define CAN_FS1R_FSC9_Msk (0x1U << CAN_FS1R_FSC9_Pos) /*!< 0x00000200 */ #define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk /*!< Filter Scale Configuration for filter 9 */ -#define CAN_FS1R_FSC10_Pos (10U) +#define CAN_FS1R_FSC10_Pos (10U) #define CAN_FS1R_FSC10_Msk (0x1U << CAN_FS1R_FSC10_Pos) /*!< 0x00000400 */ #define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk /*!< Filter Scale Configuration for filter 10 */ -#define CAN_FS1R_FSC11_Pos (11U) +#define CAN_FS1R_FSC11_Pos (11U) #define CAN_FS1R_FSC11_Msk (0x1U << CAN_FS1R_FSC11_Pos) /*!< 0x00000800 */ #define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk /*!< Filter Scale Configuration for filter 11 */ -#define CAN_FS1R_FSC12_Pos (12U) +#define CAN_FS1R_FSC12_Pos (12U) #define CAN_FS1R_FSC12_Msk (0x1U << CAN_FS1R_FSC12_Pos) /*!< 0x00001000 */ #define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk /*!< Filter Scale Configuration for filter 12 */ -#define CAN_FS1R_FSC13_Pos (13U) +#define CAN_FS1R_FSC13_Pos (13U) #define CAN_FS1R_FSC13_Msk (0x1U << CAN_FS1R_FSC13_Pos) /*!< 0x00002000 */ #define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk /*!< Filter Scale Configuration for filter 13 */ /****************** Bit definition for CAN_FFA1R register *******************/ -#define CAN_FFA1R_FFA_Pos (0U) +#define CAN_FFA1R_FFA_Pos (0U) #define CAN_FFA1R_FFA_Msk (0x3FFFU << CAN_FFA1R_FFA_Pos) /*!< 0x00003FFF */ #define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk /*!< Filter FIFO Assignment */ -#define CAN_FFA1R_FFA0_Pos (0U) +#define CAN_FFA1R_FFA0_Pos (0U) #define CAN_FFA1R_FFA0_Msk (0x1U << CAN_FFA1R_FFA0_Pos) /*!< 0x00000001 */ #define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk /*!< Filter FIFO Assignment for filter 0 */ -#define CAN_FFA1R_FFA1_Pos (1U) +#define CAN_FFA1R_FFA1_Pos (1U) #define CAN_FFA1R_FFA1_Msk (0x1U << CAN_FFA1R_FFA1_Pos) /*!< 0x00000002 */ #define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk /*!< Filter FIFO Assignment for filter 1 */ -#define CAN_FFA1R_FFA2_Pos (2U) +#define CAN_FFA1R_FFA2_Pos (2U) #define CAN_FFA1R_FFA2_Msk (0x1U << CAN_FFA1R_FFA2_Pos) /*!< 0x00000004 */ #define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk /*!< Filter FIFO Assignment for filter 2 */ -#define CAN_FFA1R_FFA3_Pos (3U) +#define CAN_FFA1R_FFA3_Pos (3U) #define CAN_FFA1R_FFA3_Msk (0x1U << CAN_FFA1R_FFA3_Pos) /*!< 0x00000008 */ #define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk /*!< Filter FIFO Assignment for filter 3 */ -#define CAN_FFA1R_FFA4_Pos (4U) +#define CAN_FFA1R_FFA4_Pos (4U) #define CAN_FFA1R_FFA4_Msk (0x1U << CAN_FFA1R_FFA4_Pos) /*!< 0x00000010 */ #define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk /*!< Filter FIFO Assignment for filter 4 */ -#define CAN_FFA1R_FFA5_Pos (5U) +#define CAN_FFA1R_FFA5_Pos (5U) #define CAN_FFA1R_FFA5_Msk (0x1U << CAN_FFA1R_FFA5_Pos) /*!< 0x00000020 */ #define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk /*!< Filter FIFO Assignment for filter 5 */ -#define CAN_FFA1R_FFA6_Pos (6U) +#define CAN_FFA1R_FFA6_Pos (6U) #define CAN_FFA1R_FFA6_Msk (0x1U << CAN_FFA1R_FFA6_Pos) /*!< 0x00000040 */ #define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk /*!< Filter FIFO Assignment for filter 6 */ -#define CAN_FFA1R_FFA7_Pos (7U) +#define CAN_FFA1R_FFA7_Pos (7U) #define CAN_FFA1R_FFA7_Msk (0x1U << CAN_FFA1R_FFA7_Pos) /*!< 0x00000080 */ #define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk /*!< Filter FIFO Assignment for filter 7 */ -#define CAN_FFA1R_FFA8_Pos (8U) +#define CAN_FFA1R_FFA8_Pos (8U) #define CAN_FFA1R_FFA8_Msk (0x1U << CAN_FFA1R_FFA8_Pos) /*!< 0x00000100 */ #define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk /*!< Filter FIFO Assignment for filter 8 */ -#define CAN_FFA1R_FFA9_Pos (9U) +#define CAN_FFA1R_FFA9_Pos (9U) #define CAN_FFA1R_FFA9_Msk (0x1U << CAN_FFA1R_FFA9_Pos) /*!< 0x00000200 */ #define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk /*!< Filter FIFO Assignment for filter 9 */ -#define CAN_FFA1R_FFA10_Pos (10U) +#define CAN_FFA1R_FFA10_Pos (10U) #define CAN_FFA1R_FFA10_Msk (0x1U << CAN_FFA1R_FFA10_Pos) /*!< 0x00000400 */ #define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk /*!< Filter FIFO Assignment for filter 10 */ -#define CAN_FFA1R_FFA11_Pos (11U) +#define CAN_FFA1R_FFA11_Pos (11U) #define CAN_FFA1R_FFA11_Msk (0x1U << CAN_FFA1R_FFA11_Pos) /*!< 0x00000800 */ #define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk /*!< Filter FIFO Assignment for filter 11 */ -#define CAN_FFA1R_FFA12_Pos (12U) +#define CAN_FFA1R_FFA12_Pos (12U) #define CAN_FFA1R_FFA12_Msk (0x1U << CAN_FFA1R_FFA12_Pos) /*!< 0x00001000 */ #define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk /*!< Filter FIFO Assignment for filter 12 */ -#define CAN_FFA1R_FFA13_Pos (13U) +#define CAN_FFA1R_FFA13_Pos (13U) #define CAN_FFA1R_FFA13_Msk (0x1U << CAN_FFA1R_FFA13_Pos) /*!< 0x00002000 */ #define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk /*!< Filter FIFO Assignment for filter 13 */ /******************* Bit definition for CAN_FA1R register *******************/ -#define CAN_FA1R_FACT_Pos (0U) +#define CAN_FA1R_FACT_Pos (0U) #define CAN_FA1R_FACT_Msk (0x3FFFU << CAN_FA1R_FACT_Pos) /*!< 0x00003FFF */ #define CAN_FA1R_FACT CAN_FA1R_FACT_Msk /*!< Filter Active */ -#define CAN_FA1R_FACT0_Pos (0U) +#define CAN_FA1R_FACT0_Pos (0U) #define CAN_FA1R_FACT0_Msk (0x1U << CAN_FA1R_FACT0_Pos) /*!< 0x00000001 */ #define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk /*!< Filter 0 Active */ -#define CAN_FA1R_FACT1_Pos (1U) +#define CAN_FA1R_FACT1_Pos (1U) #define CAN_FA1R_FACT1_Msk (0x1U << CAN_FA1R_FACT1_Pos) /*!< 0x00000002 */ #define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk /*!< Filter 1 Active */ -#define CAN_FA1R_FACT2_Pos (2U) +#define CAN_FA1R_FACT2_Pos (2U) #define CAN_FA1R_FACT2_Msk (0x1U << CAN_FA1R_FACT2_Pos) /*!< 0x00000004 */ #define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk /*!< Filter 2 Active */ -#define CAN_FA1R_FACT3_Pos (3U) +#define CAN_FA1R_FACT3_Pos (3U) #define CAN_FA1R_FACT3_Msk (0x1U << CAN_FA1R_FACT3_Pos) /*!< 0x00000008 */ #define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk /*!< Filter 3 Active */ -#define CAN_FA1R_FACT4_Pos (4U) +#define CAN_FA1R_FACT4_Pos (4U) #define CAN_FA1R_FACT4_Msk (0x1U << CAN_FA1R_FACT4_Pos) /*!< 0x00000010 */ #define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk /*!< Filter 4 Active */ -#define CAN_FA1R_FACT5_Pos (5U) +#define CAN_FA1R_FACT5_Pos (5U) #define CAN_FA1R_FACT5_Msk (0x1U << CAN_FA1R_FACT5_Pos) /*!< 0x00000020 */ #define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk /*!< Filter 5 Active */ -#define CAN_FA1R_FACT6_Pos (6U) +#define CAN_FA1R_FACT6_Pos (6U) #define CAN_FA1R_FACT6_Msk (0x1U << CAN_FA1R_FACT6_Pos) /*!< 0x00000040 */ #define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk /*!< Filter 6 Active */ -#define CAN_FA1R_FACT7_Pos (7U) +#define CAN_FA1R_FACT7_Pos (7U) #define CAN_FA1R_FACT7_Msk (0x1U << CAN_FA1R_FACT7_Pos) /*!< 0x00000080 */ #define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk /*!< Filter 7 Active */ -#define CAN_FA1R_FACT8_Pos (8U) +#define CAN_FA1R_FACT8_Pos (8U) #define CAN_FA1R_FACT8_Msk (0x1U << CAN_FA1R_FACT8_Pos) /*!< 0x00000100 */ #define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk /*!< Filter 8 Active */ -#define CAN_FA1R_FACT9_Pos (9U) +#define CAN_FA1R_FACT9_Pos (9U) #define CAN_FA1R_FACT9_Msk (0x1U << CAN_FA1R_FACT9_Pos) /*!< 0x00000200 */ #define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk /*!< Filter 9 Active */ -#define CAN_FA1R_FACT10_Pos (10U) +#define CAN_FA1R_FACT10_Pos (10U) #define CAN_FA1R_FACT10_Msk (0x1U << CAN_FA1R_FACT10_Pos) /*!< 0x00000400 */ #define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk /*!< Filter 10 Active */ -#define CAN_FA1R_FACT11_Pos (11U) +#define CAN_FA1R_FACT11_Pos (11U) #define CAN_FA1R_FACT11_Msk (0x1U << CAN_FA1R_FACT11_Pos) /*!< 0x00000800 */ #define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk /*!< Filter 11 Active */ -#define CAN_FA1R_FACT12_Pos (12U) +#define CAN_FA1R_FACT12_Pos (12U) #define CAN_FA1R_FACT12_Msk (0x1U << CAN_FA1R_FACT12_Pos) /*!< 0x00001000 */ #define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk /*!< Filter 12 Active */ -#define CAN_FA1R_FACT13_Pos (13U) +#define CAN_FA1R_FACT13_Pos (13U) #define CAN_FA1R_FACT13_Msk (0x1U << CAN_FA1R_FACT13_Pos) /*!< 0x00002000 */ #define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk /*!< Filter 13 Active */ /******************* Bit definition for CAN_F0R1 register *******************/ -#define CAN_F0R1_FB0_Pos (0U) +#define CAN_F0R1_FB0_Pos (0U) #define CAN_F0R1_FB0_Msk (0x1U << CAN_F0R1_FB0_Pos) /*!< 0x00000001 */ #define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk /*!< Filter bit 0 */ -#define CAN_F0R1_FB1_Pos (1U) +#define CAN_F0R1_FB1_Pos (1U) #define CAN_F0R1_FB1_Msk (0x1U << CAN_F0R1_FB1_Pos) /*!< 0x00000002 */ #define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk /*!< Filter bit 1 */ -#define CAN_F0R1_FB2_Pos (2U) +#define CAN_F0R1_FB2_Pos (2U) #define CAN_F0R1_FB2_Msk (0x1U << CAN_F0R1_FB2_Pos) /*!< 0x00000004 */ #define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk /*!< Filter bit 2 */ -#define CAN_F0R1_FB3_Pos (3U) +#define CAN_F0R1_FB3_Pos (3U) #define CAN_F0R1_FB3_Msk (0x1U << CAN_F0R1_FB3_Pos) /*!< 0x00000008 */ #define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk /*!< Filter bit 3 */ -#define CAN_F0R1_FB4_Pos (4U) +#define CAN_F0R1_FB4_Pos (4U) #define CAN_F0R1_FB4_Msk (0x1U << CAN_F0R1_FB4_Pos) /*!< 0x00000010 */ #define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk /*!< Filter bit 4 */ -#define CAN_F0R1_FB5_Pos (5U) +#define CAN_F0R1_FB5_Pos (5U) #define CAN_F0R1_FB5_Msk (0x1U << CAN_F0R1_FB5_Pos) /*!< 0x00000020 */ #define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk /*!< Filter bit 5 */ -#define CAN_F0R1_FB6_Pos (6U) +#define CAN_F0R1_FB6_Pos (6U) #define CAN_F0R1_FB6_Msk (0x1U << CAN_F0R1_FB6_Pos) /*!< 0x00000040 */ #define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk /*!< Filter bit 6 */ -#define CAN_F0R1_FB7_Pos (7U) +#define CAN_F0R1_FB7_Pos (7U) #define CAN_F0R1_FB7_Msk (0x1U << CAN_F0R1_FB7_Pos) /*!< 0x00000080 */ #define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk /*!< Filter bit 7 */ -#define CAN_F0R1_FB8_Pos (8U) +#define CAN_F0R1_FB8_Pos (8U) #define CAN_F0R1_FB8_Msk (0x1U << CAN_F0R1_FB8_Pos) /*!< 0x00000100 */ #define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk /*!< Filter bit 8 */ -#define CAN_F0R1_FB9_Pos (9U) +#define CAN_F0R1_FB9_Pos (9U) #define CAN_F0R1_FB9_Msk (0x1U << CAN_F0R1_FB9_Pos) /*!< 0x00000200 */ #define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk /*!< Filter bit 9 */ -#define CAN_F0R1_FB10_Pos (10U) +#define CAN_F0R1_FB10_Pos (10U) #define CAN_F0R1_FB10_Msk (0x1U << CAN_F0R1_FB10_Pos) /*!< 0x00000400 */ #define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk /*!< Filter bit 10 */ -#define CAN_F0R1_FB11_Pos (11U) +#define CAN_F0R1_FB11_Pos (11U) #define CAN_F0R1_FB11_Msk (0x1U << CAN_F0R1_FB11_Pos) /*!< 0x00000800 */ #define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk /*!< Filter bit 11 */ -#define CAN_F0R1_FB12_Pos (12U) +#define CAN_F0R1_FB12_Pos (12U) #define CAN_F0R1_FB12_Msk (0x1U << CAN_F0R1_FB12_Pos) /*!< 0x00001000 */ #define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk /*!< Filter bit 12 */ -#define CAN_F0R1_FB13_Pos (13U) +#define CAN_F0R1_FB13_Pos (13U) #define CAN_F0R1_FB13_Msk (0x1U << CAN_F0R1_FB13_Pos) /*!< 0x00002000 */ #define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk /*!< Filter bit 13 */ -#define CAN_F0R1_FB14_Pos (14U) +#define CAN_F0R1_FB14_Pos (14U) #define CAN_F0R1_FB14_Msk (0x1U << CAN_F0R1_FB14_Pos) /*!< 0x00004000 */ #define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk /*!< Filter bit 14 */ -#define CAN_F0R1_FB15_Pos (15U) +#define CAN_F0R1_FB15_Pos (15U) #define CAN_F0R1_FB15_Msk (0x1U << CAN_F0R1_FB15_Pos) /*!< 0x00008000 */ #define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk /*!< Filter bit 15 */ -#define CAN_F0R1_FB16_Pos (16U) +#define CAN_F0R1_FB16_Pos (16U) #define CAN_F0R1_FB16_Msk (0x1U << CAN_F0R1_FB16_Pos) /*!< 0x00010000 */ #define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk /*!< Filter bit 16 */ -#define CAN_F0R1_FB17_Pos (17U) +#define CAN_F0R1_FB17_Pos (17U) #define CAN_F0R1_FB17_Msk (0x1U << CAN_F0R1_FB17_Pos) /*!< 0x00020000 */ #define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk /*!< Filter bit 17 */ -#define CAN_F0R1_FB18_Pos (18U) +#define CAN_F0R1_FB18_Pos (18U) #define CAN_F0R1_FB18_Msk (0x1U << CAN_F0R1_FB18_Pos) /*!< 0x00040000 */ #define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk /*!< Filter bit 18 */ -#define CAN_F0R1_FB19_Pos (19U) +#define CAN_F0R1_FB19_Pos (19U) #define CAN_F0R1_FB19_Msk (0x1U << CAN_F0R1_FB19_Pos) /*!< 0x00080000 */ #define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk /*!< Filter bit 19 */ -#define CAN_F0R1_FB20_Pos (20U) +#define CAN_F0R1_FB20_Pos (20U) #define CAN_F0R1_FB20_Msk (0x1U << CAN_F0R1_FB20_Pos) /*!< 0x00100000 */ #define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk /*!< Filter bit 20 */ -#define CAN_F0R1_FB21_Pos (21U) +#define CAN_F0R1_FB21_Pos (21U) #define CAN_F0R1_FB21_Msk (0x1U << CAN_F0R1_FB21_Pos) /*!< 0x00200000 */ #define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk /*!< Filter bit 21 */ -#define CAN_F0R1_FB22_Pos (22U) +#define CAN_F0R1_FB22_Pos (22U) #define CAN_F0R1_FB22_Msk (0x1U << CAN_F0R1_FB22_Pos) /*!< 0x00400000 */ #define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk /*!< Filter bit 22 */ -#define CAN_F0R1_FB23_Pos (23U) +#define CAN_F0R1_FB23_Pos (23U) #define CAN_F0R1_FB23_Msk (0x1U << CAN_F0R1_FB23_Pos) /*!< 0x00800000 */ #define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk /*!< Filter bit 23 */ -#define CAN_F0R1_FB24_Pos (24U) +#define CAN_F0R1_FB24_Pos (24U) #define CAN_F0R1_FB24_Msk (0x1U << CAN_F0R1_FB24_Pos) /*!< 0x01000000 */ #define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk /*!< Filter bit 24 */ -#define CAN_F0R1_FB25_Pos (25U) +#define CAN_F0R1_FB25_Pos (25U) #define CAN_F0R1_FB25_Msk (0x1U << CAN_F0R1_FB25_Pos) /*!< 0x02000000 */ #define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk /*!< Filter bit 25 */ -#define CAN_F0R1_FB26_Pos (26U) +#define CAN_F0R1_FB26_Pos (26U) #define CAN_F0R1_FB26_Msk (0x1U << CAN_F0R1_FB26_Pos) /*!< 0x04000000 */ #define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk /*!< Filter bit 26 */ -#define CAN_F0R1_FB27_Pos (27U) +#define CAN_F0R1_FB27_Pos (27U) #define CAN_F0R1_FB27_Msk (0x1U << CAN_F0R1_FB27_Pos) /*!< 0x08000000 */ #define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk /*!< Filter bit 27 */ -#define CAN_F0R1_FB28_Pos (28U) +#define CAN_F0R1_FB28_Pos (28U) #define CAN_F0R1_FB28_Msk (0x1U << CAN_F0R1_FB28_Pos) /*!< 0x10000000 */ #define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk /*!< Filter bit 28 */ -#define CAN_F0R1_FB29_Pos (29U) +#define CAN_F0R1_FB29_Pos (29U) #define CAN_F0R1_FB29_Msk (0x1U << CAN_F0R1_FB29_Pos) /*!< 0x20000000 */ #define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk /*!< Filter bit 29 */ -#define CAN_F0R1_FB30_Pos (30U) +#define CAN_F0R1_FB30_Pos (30U) #define CAN_F0R1_FB30_Msk (0x1U << CAN_F0R1_FB30_Pos) /*!< 0x40000000 */ #define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk /*!< Filter bit 30 */ -#define CAN_F0R1_FB31_Pos (31U) +#define CAN_F0R1_FB31_Pos (31U) #define CAN_F0R1_FB31_Msk (0x1U << CAN_F0R1_FB31_Pos) /*!< 0x80000000 */ #define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk /*!< Filter bit 31 */ /******************* Bit definition for CAN_F1R1 register *******************/ -#define CAN_F1R1_FB0_Pos (0U) +#define CAN_F1R1_FB0_Pos (0U) #define CAN_F1R1_FB0_Msk (0x1U << CAN_F1R1_FB0_Pos) /*!< 0x00000001 */ #define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk /*!< Filter bit 0 */ -#define CAN_F1R1_FB1_Pos (1U) +#define CAN_F1R1_FB1_Pos (1U) #define CAN_F1R1_FB1_Msk (0x1U << CAN_F1R1_FB1_Pos) /*!< 0x00000002 */ #define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk /*!< Filter bit 1 */ -#define CAN_F1R1_FB2_Pos (2U) +#define CAN_F1R1_FB2_Pos (2U) #define CAN_F1R1_FB2_Msk (0x1U << CAN_F1R1_FB2_Pos) /*!< 0x00000004 */ #define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk /*!< Filter bit 2 */ -#define CAN_F1R1_FB3_Pos (3U) +#define CAN_F1R1_FB3_Pos (3U) #define CAN_F1R1_FB3_Msk (0x1U << CAN_F1R1_FB3_Pos) /*!< 0x00000008 */ #define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk /*!< Filter bit 3 */ -#define CAN_F1R1_FB4_Pos (4U) +#define CAN_F1R1_FB4_Pos (4U) #define CAN_F1R1_FB4_Msk (0x1U << CAN_F1R1_FB4_Pos) /*!< 0x00000010 */ #define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk /*!< Filter bit 4 */ -#define CAN_F1R1_FB5_Pos (5U) +#define CAN_F1R1_FB5_Pos (5U) #define CAN_F1R1_FB5_Msk (0x1U << CAN_F1R1_FB5_Pos) /*!< 0x00000020 */ #define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk /*!< Filter bit 5 */ -#define CAN_F1R1_FB6_Pos (6U) +#define CAN_F1R1_FB6_Pos (6U) #define CAN_F1R1_FB6_Msk (0x1U << CAN_F1R1_FB6_Pos) /*!< 0x00000040 */ #define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk /*!< Filter bit 6 */ -#define CAN_F1R1_FB7_Pos (7U) +#define CAN_F1R1_FB7_Pos (7U) #define CAN_F1R1_FB7_Msk (0x1U << CAN_F1R1_FB7_Pos) /*!< 0x00000080 */ #define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk /*!< Filter bit 7 */ -#define CAN_F1R1_FB8_Pos (8U) +#define CAN_F1R1_FB8_Pos (8U) #define CAN_F1R1_FB8_Msk (0x1U << CAN_F1R1_FB8_Pos) /*!< 0x00000100 */ #define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk /*!< Filter bit 8 */ -#define CAN_F1R1_FB9_Pos (9U) +#define CAN_F1R1_FB9_Pos (9U) #define CAN_F1R1_FB9_Msk (0x1U << CAN_F1R1_FB9_Pos) /*!< 0x00000200 */ #define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk /*!< Filter bit 9 */ -#define CAN_F1R1_FB10_Pos (10U) +#define CAN_F1R1_FB10_Pos (10U) #define CAN_F1R1_FB10_Msk (0x1U << CAN_F1R1_FB10_Pos) /*!< 0x00000400 */ #define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk /*!< Filter bit 10 */ -#define CAN_F1R1_FB11_Pos (11U) +#define CAN_F1R1_FB11_Pos (11U) #define CAN_F1R1_FB11_Msk (0x1U << CAN_F1R1_FB11_Pos) /*!< 0x00000800 */ #define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk /*!< Filter bit 11 */ -#define CAN_F1R1_FB12_Pos (12U) +#define CAN_F1R1_FB12_Pos (12U) #define CAN_F1R1_FB12_Msk (0x1U << CAN_F1R1_FB12_Pos) /*!< 0x00001000 */ #define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk /*!< Filter bit 12 */ -#define CAN_F1R1_FB13_Pos (13U) +#define CAN_F1R1_FB13_Pos (13U) #define CAN_F1R1_FB13_Msk (0x1U << CAN_F1R1_FB13_Pos) /*!< 0x00002000 */ #define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk /*!< Filter bit 13 */ -#define CAN_F1R1_FB14_Pos (14U) +#define CAN_F1R1_FB14_Pos (14U) #define CAN_F1R1_FB14_Msk (0x1U << CAN_F1R1_FB14_Pos) /*!< 0x00004000 */ #define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk /*!< Filter bit 14 */ -#define CAN_F1R1_FB15_Pos (15U) +#define CAN_F1R1_FB15_Pos (15U) #define CAN_F1R1_FB15_Msk (0x1U << CAN_F1R1_FB15_Pos) /*!< 0x00008000 */ #define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk /*!< Filter bit 15 */ -#define CAN_F1R1_FB16_Pos (16U) +#define CAN_F1R1_FB16_Pos (16U) #define CAN_F1R1_FB16_Msk (0x1U << CAN_F1R1_FB16_Pos) /*!< 0x00010000 */ #define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk /*!< Filter bit 16 */ -#define CAN_F1R1_FB17_Pos (17U) +#define CAN_F1R1_FB17_Pos (17U) #define CAN_F1R1_FB17_Msk (0x1U << CAN_F1R1_FB17_Pos) /*!< 0x00020000 */ #define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk /*!< Filter bit 17 */ -#define CAN_F1R1_FB18_Pos (18U) +#define CAN_F1R1_FB18_Pos (18U) #define CAN_F1R1_FB18_Msk (0x1U << CAN_F1R1_FB18_Pos) /*!< 0x00040000 */ #define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk /*!< Filter bit 18 */ -#define CAN_F1R1_FB19_Pos (19U) +#define CAN_F1R1_FB19_Pos (19U) #define CAN_F1R1_FB19_Msk (0x1U << CAN_F1R1_FB19_Pos) /*!< 0x00080000 */ #define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk /*!< Filter bit 19 */ -#define CAN_F1R1_FB20_Pos (20U) +#define CAN_F1R1_FB20_Pos (20U) #define CAN_F1R1_FB20_Msk (0x1U << CAN_F1R1_FB20_Pos) /*!< 0x00100000 */ #define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk /*!< Filter bit 20 */ -#define CAN_F1R1_FB21_Pos (21U) +#define CAN_F1R1_FB21_Pos (21U) #define CAN_F1R1_FB21_Msk (0x1U << CAN_F1R1_FB21_Pos) /*!< 0x00200000 */ #define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk /*!< Filter bit 21 */ -#define CAN_F1R1_FB22_Pos (22U) +#define CAN_F1R1_FB22_Pos (22U) #define CAN_F1R1_FB22_Msk (0x1U << CAN_F1R1_FB22_Pos) /*!< 0x00400000 */ #define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk /*!< Filter bit 22 */ -#define CAN_F1R1_FB23_Pos (23U) +#define CAN_F1R1_FB23_Pos (23U) #define CAN_F1R1_FB23_Msk (0x1U << CAN_F1R1_FB23_Pos) /*!< 0x00800000 */ #define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk /*!< Filter bit 23 */ -#define CAN_F1R1_FB24_Pos (24U) +#define CAN_F1R1_FB24_Pos (24U) #define CAN_F1R1_FB24_Msk (0x1U << CAN_F1R1_FB24_Pos) /*!< 0x01000000 */ #define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk /*!< Filter bit 24 */ -#define CAN_F1R1_FB25_Pos (25U) +#define CAN_F1R1_FB25_Pos (25U) #define CAN_F1R1_FB25_Msk (0x1U << CAN_F1R1_FB25_Pos) /*!< 0x02000000 */ #define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk /*!< Filter bit 25 */ -#define CAN_F1R1_FB26_Pos (26U) +#define CAN_F1R1_FB26_Pos (26U) #define CAN_F1R1_FB26_Msk (0x1U << CAN_F1R1_FB26_Pos) /*!< 0x04000000 */ #define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk /*!< Filter bit 26 */ -#define CAN_F1R1_FB27_Pos (27U) +#define CAN_F1R1_FB27_Pos (27U) #define CAN_F1R1_FB27_Msk (0x1U << CAN_F1R1_FB27_Pos) /*!< 0x08000000 */ #define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk /*!< Filter bit 27 */ -#define CAN_F1R1_FB28_Pos (28U) +#define CAN_F1R1_FB28_Pos (28U) #define CAN_F1R1_FB28_Msk (0x1U << CAN_F1R1_FB28_Pos) /*!< 0x10000000 */ #define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk /*!< Filter bit 28 */ -#define CAN_F1R1_FB29_Pos (29U) +#define CAN_F1R1_FB29_Pos (29U) #define CAN_F1R1_FB29_Msk (0x1U << CAN_F1R1_FB29_Pos) /*!< 0x20000000 */ #define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk /*!< Filter bit 29 */ -#define CAN_F1R1_FB30_Pos (30U) +#define CAN_F1R1_FB30_Pos (30U) #define CAN_F1R1_FB30_Msk (0x1U << CAN_F1R1_FB30_Pos) /*!< 0x40000000 */ #define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk /*!< Filter bit 30 */ -#define CAN_F1R1_FB31_Pos (31U) +#define CAN_F1R1_FB31_Pos (31U) #define CAN_F1R1_FB31_Msk (0x1U << CAN_F1R1_FB31_Pos) /*!< 0x80000000 */ #define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk /*!< Filter bit 31 */ /******************* Bit definition for CAN_F2R1 register *******************/ -#define CAN_F2R1_FB0_Pos (0U) +#define CAN_F2R1_FB0_Pos (0U) #define CAN_F2R1_FB0_Msk (0x1U << CAN_F2R1_FB0_Pos) /*!< 0x00000001 */ #define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk /*!< Filter bit 0 */ -#define CAN_F2R1_FB1_Pos (1U) +#define CAN_F2R1_FB1_Pos (1U) #define CAN_F2R1_FB1_Msk (0x1U << CAN_F2R1_FB1_Pos) /*!< 0x00000002 */ #define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk /*!< Filter bit 1 */ -#define CAN_F2R1_FB2_Pos (2U) +#define CAN_F2R1_FB2_Pos (2U) #define CAN_F2R1_FB2_Msk (0x1U << CAN_F2R1_FB2_Pos) /*!< 0x00000004 */ #define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk /*!< Filter bit 2 */ -#define CAN_F2R1_FB3_Pos (3U) +#define CAN_F2R1_FB3_Pos (3U) #define CAN_F2R1_FB3_Msk (0x1U << CAN_F2R1_FB3_Pos) /*!< 0x00000008 */ #define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk /*!< Filter bit 3 */ -#define CAN_F2R1_FB4_Pos (4U) +#define CAN_F2R1_FB4_Pos (4U) #define CAN_F2R1_FB4_Msk (0x1U << CAN_F2R1_FB4_Pos) /*!< 0x00000010 */ #define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk /*!< Filter bit 4 */ -#define CAN_F2R1_FB5_Pos (5U) +#define CAN_F2R1_FB5_Pos (5U) #define CAN_F2R1_FB5_Msk (0x1U << CAN_F2R1_FB5_Pos) /*!< 0x00000020 */ #define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk /*!< Filter bit 5 */ -#define CAN_F2R1_FB6_Pos (6U) +#define CAN_F2R1_FB6_Pos (6U) #define CAN_F2R1_FB6_Msk (0x1U << CAN_F2R1_FB6_Pos) /*!< 0x00000040 */ #define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk /*!< Filter bit 6 */ -#define CAN_F2R1_FB7_Pos (7U) +#define CAN_F2R1_FB7_Pos (7U) #define CAN_F2R1_FB7_Msk (0x1U << CAN_F2R1_FB7_Pos) /*!< 0x00000080 */ #define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk /*!< Filter bit 7 */ -#define CAN_F2R1_FB8_Pos (8U) +#define CAN_F2R1_FB8_Pos (8U) #define CAN_F2R1_FB8_Msk (0x1U << CAN_F2R1_FB8_Pos) /*!< 0x00000100 */ #define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk /*!< Filter bit 8 */ -#define CAN_F2R1_FB9_Pos (9U) +#define CAN_F2R1_FB9_Pos (9U) #define CAN_F2R1_FB9_Msk (0x1U << CAN_F2R1_FB9_Pos) /*!< 0x00000200 */ #define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk /*!< Filter bit 9 */ -#define CAN_F2R1_FB10_Pos (10U) +#define CAN_F2R1_FB10_Pos (10U) #define CAN_F2R1_FB10_Msk (0x1U << CAN_F2R1_FB10_Pos) /*!< 0x00000400 */ #define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk /*!< Filter bit 10 */ -#define CAN_F2R1_FB11_Pos (11U) +#define CAN_F2R1_FB11_Pos (11U) #define CAN_F2R1_FB11_Msk (0x1U << CAN_F2R1_FB11_Pos) /*!< 0x00000800 */ #define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk /*!< Filter bit 11 */ -#define CAN_F2R1_FB12_Pos (12U) +#define CAN_F2R1_FB12_Pos (12U) #define CAN_F2R1_FB12_Msk (0x1U << CAN_F2R1_FB12_Pos) /*!< 0x00001000 */ #define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk /*!< Filter bit 12 */ -#define CAN_F2R1_FB13_Pos (13U) +#define CAN_F2R1_FB13_Pos (13U) #define CAN_F2R1_FB13_Msk (0x1U << CAN_F2R1_FB13_Pos) /*!< 0x00002000 */ #define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk /*!< Filter bit 13 */ -#define CAN_F2R1_FB14_Pos (14U) +#define CAN_F2R1_FB14_Pos (14U) #define CAN_F2R1_FB14_Msk (0x1U << CAN_F2R1_FB14_Pos) /*!< 0x00004000 */ #define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk /*!< Filter bit 14 */ -#define CAN_F2R1_FB15_Pos (15U) +#define CAN_F2R1_FB15_Pos (15U) #define CAN_F2R1_FB15_Msk (0x1U << CAN_F2R1_FB15_Pos) /*!< 0x00008000 */ #define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk /*!< Filter bit 15 */ -#define CAN_F2R1_FB16_Pos (16U) +#define CAN_F2R1_FB16_Pos (16U) #define CAN_F2R1_FB16_Msk (0x1U << CAN_F2R1_FB16_Pos) /*!< 0x00010000 */ #define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk /*!< Filter bit 16 */ -#define CAN_F2R1_FB17_Pos (17U) +#define CAN_F2R1_FB17_Pos (17U) #define CAN_F2R1_FB17_Msk (0x1U << CAN_F2R1_FB17_Pos) /*!< 0x00020000 */ #define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk /*!< Filter bit 17 */ -#define CAN_F2R1_FB18_Pos (18U) +#define CAN_F2R1_FB18_Pos (18U) #define CAN_F2R1_FB18_Msk (0x1U << CAN_F2R1_FB18_Pos) /*!< 0x00040000 */ #define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk /*!< Filter bit 18 */ -#define CAN_F2R1_FB19_Pos (19U) +#define CAN_F2R1_FB19_Pos (19U) #define CAN_F2R1_FB19_Msk (0x1U << CAN_F2R1_FB19_Pos) /*!< 0x00080000 */ #define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk /*!< Filter bit 19 */ -#define CAN_F2R1_FB20_Pos (20U) +#define CAN_F2R1_FB20_Pos (20U) #define CAN_F2R1_FB20_Msk (0x1U << CAN_F2R1_FB20_Pos) /*!< 0x00100000 */ #define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk /*!< Filter bit 20 */ -#define CAN_F2R1_FB21_Pos (21U) +#define CAN_F2R1_FB21_Pos (21U) #define CAN_F2R1_FB21_Msk (0x1U << CAN_F2R1_FB21_Pos) /*!< 0x00200000 */ #define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk /*!< Filter bit 21 */ -#define CAN_F2R1_FB22_Pos (22U) +#define CAN_F2R1_FB22_Pos (22U) #define CAN_F2R1_FB22_Msk (0x1U << CAN_F2R1_FB22_Pos) /*!< 0x00400000 */ #define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk /*!< Filter bit 22 */ -#define CAN_F2R1_FB23_Pos (23U) +#define CAN_F2R1_FB23_Pos (23U) #define CAN_F2R1_FB23_Msk (0x1U << CAN_F2R1_FB23_Pos) /*!< 0x00800000 */ #define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk /*!< Filter bit 23 */ -#define CAN_F2R1_FB24_Pos (24U) +#define CAN_F2R1_FB24_Pos (24U) #define CAN_F2R1_FB24_Msk (0x1U << CAN_F2R1_FB24_Pos) /*!< 0x01000000 */ #define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk /*!< Filter bit 24 */ -#define CAN_F2R1_FB25_Pos (25U) +#define CAN_F2R1_FB25_Pos (25U) #define CAN_F2R1_FB25_Msk (0x1U << CAN_F2R1_FB25_Pos) /*!< 0x02000000 */ #define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk /*!< Filter bit 25 */ -#define CAN_F2R1_FB26_Pos (26U) +#define CAN_F2R1_FB26_Pos (26U) #define CAN_F2R1_FB26_Msk (0x1U << CAN_F2R1_FB26_Pos) /*!< 0x04000000 */ #define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk /*!< Filter bit 26 */ -#define CAN_F2R1_FB27_Pos (27U) +#define CAN_F2R1_FB27_Pos (27U) #define CAN_F2R1_FB27_Msk (0x1U << CAN_F2R1_FB27_Pos) /*!< 0x08000000 */ #define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk /*!< Filter bit 27 */ -#define CAN_F2R1_FB28_Pos (28U) +#define CAN_F2R1_FB28_Pos (28U) #define CAN_F2R1_FB28_Msk (0x1U << CAN_F2R1_FB28_Pos) /*!< 0x10000000 */ #define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk /*!< Filter bit 28 */ -#define CAN_F2R1_FB29_Pos (29U) +#define CAN_F2R1_FB29_Pos (29U) #define CAN_F2R1_FB29_Msk (0x1U << CAN_F2R1_FB29_Pos) /*!< 0x20000000 */ #define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk /*!< Filter bit 29 */ -#define CAN_F2R1_FB30_Pos (30U) +#define CAN_F2R1_FB30_Pos (30U) #define CAN_F2R1_FB30_Msk (0x1U << CAN_F2R1_FB30_Pos) /*!< 0x40000000 */ #define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk /*!< Filter bit 30 */ -#define CAN_F2R1_FB31_Pos (31U) +#define CAN_F2R1_FB31_Pos (31U) #define CAN_F2R1_FB31_Msk (0x1U << CAN_F2R1_FB31_Pos) /*!< 0x80000000 */ #define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk /*!< Filter bit 31 */ /******************* Bit definition for CAN_F3R1 register *******************/ -#define CAN_F3R1_FB0_Pos (0U) +#define CAN_F3R1_FB0_Pos (0U) #define CAN_F3R1_FB0_Msk (0x1U << CAN_F3R1_FB0_Pos) /*!< 0x00000001 */ #define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk /*!< Filter bit 0 */ -#define CAN_F3R1_FB1_Pos (1U) +#define CAN_F3R1_FB1_Pos (1U) #define CAN_F3R1_FB1_Msk (0x1U << CAN_F3R1_FB1_Pos) /*!< 0x00000002 */ #define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk /*!< Filter bit 1 */ -#define CAN_F3R1_FB2_Pos (2U) +#define CAN_F3R1_FB2_Pos (2U) #define CAN_F3R1_FB2_Msk (0x1U << CAN_F3R1_FB2_Pos) /*!< 0x00000004 */ #define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk /*!< Filter bit 2 */ -#define CAN_F3R1_FB3_Pos (3U) +#define CAN_F3R1_FB3_Pos (3U) #define CAN_F3R1_FB3_Msk (0x1U << CAN_F3R1_FB3_Pos) /*!< 0x00000008 */ #define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk /*!< Filter bit 3 */ -#define CAN_F3R1_FB4_Pos (4U) +#define CAN_F3R1_FB4_Pos (4U) #define CAN_F3R1_FB4_Msk (0x1U << CAN_F3R1_FB4_Pos) /*!< 0x00000010 */ #define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk /*!< Filter bit 4 */ -#define CAN_F3R1_FB5_Pos (5U) +#define CAN_F3R1_FB5_Pos (5U) #define CAN_F3R1_FB5_Msk (0x1U << CAN_F3R1_FB5_Pos) /*!< 0x00000020 */ #define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk /*!< Filter bit 5 */ -#define CAN_F3R1_FB6_Pos (6U) +#define CAN_F3R1_FB6_Pos (6U) #define CAN_F3R1_FB6_Msk (0x1U << CAN_F3R1_FB6_Pos) /*!< 0x00000040 */ #define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk /*!< Filter bit 6 */ -#define CAN_F3R1_FB7_Pos (7U) +#define CAN_F3R1_FB7_Pos (7U) #define CAN_F3R1_FB7_Msk (0x1U << CAN_F3R1_FB7_Pos) /*!< 0x00000080 */ #define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk /*!< Filter bit 7 */ -#define CAN_F3R1_FB8_Pos (8U) +#define CAN_F3R1_FB8_Pos (8U) #define CAN_F3R1_FB8_Msk (0x1U << CAN_F3R1_FB8_Pos) /*!< 0x00000100 */ #define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk /*!< Filter bit 8 */ -#define CAN_F3R1_FB9_Pos (9U) +#define CAN_F3R1_FB9_Pos (9U) #define CAN_F3R1_FB9_Msk (0x1U << CAN_F3R1_FB9_Pos) /*!< 0x00000200 */ #define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk /*!< Filter bit 9 */ -#define CAN_F3R1_FB10_Pos (10U) +#define CAN_F3R1_FB10_Pos (10U) #define CAN_F3R1_FB10_Msk (0x1U << CAN_F3R1_FB10_Pos) /*!< 0x00000400 */ #define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk /*!< Filter bit 10 */ -#define CAN_F3R1_FB11_Pos (11U) +#define CAN_F3R1_FB11_Pos (11U) #define CAN_F3R1_FB11_Msk (0x1U << CAN_F3R1_FB11_Pos) /*!< 0x00000800 */ #define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk /*!< Filter bit 11 */ -#define CAN_F3R1_FB12_Pos (12U) +#define CAN_F3R1_FB12_Pos (12U) #define CAN_F3R1_FB12_Msk (0x1U << CAN_F3R1_FB12_Pos) /*!< 0x00001000 */ #define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk /*!< Filter bit 12 */ -#define CAN_F3R1_FB13_Pos (13U) +#define CAN_F3R1_FB13_Pos (13U) #define CAN_F3R1_FB13_Msk (0x1U << CAN_F3R1_FB13_Pos) /*!< 0x00002000 */ #define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk /*!< Filter bit 13 */ -#define CAN_F3R1_FB14_Pos (14U) +#define CAN_F3R1_FB14_Pos (14U) #define CAN_F3R1_FB14_Msk (0x1U << CAN_F3R1_FB14_Pos) /*!< 0x00004000 */ #define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk /*!< Filter bit 14 */ -#define CAN_F3R1_FB15_Pos (15U) +#define CAN_F3R1_FB15_Pos (15U) #define CAN_F3R1_FB15_Msk (0x1U << CAN_F3R1_FB15_Pos) /*!< 0x00008000 */ #define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk /*!< Filter bit 15 */ -#define CAN_F3R1_FB16_Pos (16U) +#define CAN_F3R1_FB16_Pos (16U) #define CAN_F3R1_FB16_Msk (0x1U << CAN_F3R1_FB16_Pos) /*!< 0x00010000 */ #define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk /*!< Filter bit 16 */ -#define CAN_F3R1_FB17_Pos (17U) +#define CAN_F3R1_FB17_Pos (17U) #define CAN_F3R1_FB17_Msk (0x1U << CAN_F3R1_FB17_Pos) /*!< 0x00020000 */ #define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk /*!< Filter bit 17 */ -#define CAN_F3R1_FB18_Pos (18U) +#define CAN_F3R1_FB18_Pos (18U) #define CAN_F3R1_FB18_Msk (0x1U << CAN_F3R1_FB18_Pos) /*!< 0x00040000 */ #define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk /*!< Filter bit 18 */ -#define CAN_F3R1_FB19_Pos (19U) +#define CAN_F3R1_FB19_Pos (19U) #define CAN_F3R1_FB19_Msk (0x1U << CAN_F3R1_FB19_Pos) /*!< 0x00080000 */ #define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk /*!< Filter bit 19 */ -#define CAN_F3R1_FB20_Pos (20U) +#define CAN_F3R1_FB20_Pos (20U) #define CAN_F3R1_FB20_Msk (0x1U << CAN_F3R1_FB20_Pos) /*!< 0x00100000 */ #define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk /*!< Filter bit 20 */ -#define CAN_F3R1_FB21_Pos (21U) +#define CAN_F3R1_FB21_Pos (21U) #define CAN_F3R1_FB21_Msk (0x1U << CAN_F3R1_FB21_Pos) /*!< 0x00200000 */ #define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk /*!< Filter bit 21 */ -#define CAN_F3R1_FB22_Pos (22U) +#define CAN_F3R1_FB22_Pos (22U) #define CAN_F3R1_FB22_Msk (0x1U << CAN_F3R1_FB22_Pos) /*!< 0x00400000 */ #define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk /*!< Filter bit 22 */ -#define CAN_F3R1_FB23_Pos (23U) +#define CAN_F3R1_FB23_Pos (23U) #define CAN_F3R1_FB23_Msk (0x1U << CAN_F3R1_FB23_Pos) /*!< 0x00800000 */ #define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk /*!< Filter bit 23 */ -#define CAN_F3R1_FB24_Pos (24U) +#define CAN_F3R1_FB24_Pos (24U) #define CAN_F3R1_FB24_Msk (0x1U << CAN_F3R1_FB24_Pos) /*!< 0x01000000 */ #define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk /*!< Filter bit 24 */ -#define CAN_F3R1_FB25_Pos (25U) +#define CAN_F3R1_FB25_Pos (25U) #define CAN_F3R1_FB25_Msk (0x1U << CAN_F3R1_FB25_Pos) /*!< 0x02000000 */ #define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk /*!< Filter bit 25 */ -#define CAN_F3R1_FB26_Pos (26U) +#define CAN_F3R1_FB26_Pos (26U) #define CAN_F3R1_FB26_Msk (0x1U << CAN_F3R1_FB26_Pos) /*!< 0x04000000 */ #define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk /*!< Filter bit 26 */ -#define CAN_F3R1_FB27_Pos (27U) +#define CAN_F3R1_FB27_Pos (27U) #define CAN_F3R1_FB27_Msk (0x1U << CAN_F3R1_FB27_Pos) /*!< 0x08000000 */ #define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk /*!< Filter bit 27 */ -#define CAN_F3R1_FB28_Pos (28U) +#define CAN_F3R1_FB28_Pos (28U) #define CAN_F3R1_FB28_Msk (0x1U << CAN_F3R1_FB28_Pos) /*!< 0x10000000 */ #define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk /*!< Filter bit 28 */ -#define CAN_F3R1_FB29_Pos (29U) +#define CAN_F3R1_FB29_Pos (29U) #define CAN_F3R1_FB29_Msk (0x1U << CAN_F3R1_FB29_Pos) /*!< 0x20000000 */ #define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk /*!< Filter bit 29 */ -#define CAN_F3R1_FB30_Pos (30U) +#define CAN_F3R1_FB30_Pos (30U) #define CAN_F3R1_FB30_Msk (0x1U << CAN_F3R1_FB30_Pos) /*!< 0x40000000 */ #define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk /*!< Filter bit 30 */ -#define CAN_F3R1_FB31_Pos (31U) +#define CAN_F3R1_FB31_Pos (31U) #define CAN_F3R1_FB31_Msk (0x1U << CAN_F3R1_FB31_Pos) /*!< 0x80000000 */ #define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk /*!< Filter bit 31 */ /******************* Bit definition for CAN_F4R1 register *******************/ -#define CAN_F4R1_FB0_Pos (0U) +#define CAN_F4R1_FB0_Pos (0U) #define CAN_F4R1_FB0_Msk (0x1U << CAN_F4R1_FB0_Pos) /*!< 0x00000001 */ #define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk /*!< Filter bit 0 */ -#define CAN_F4R1_FB1_Pos (1U) +#define CAN_F4R1_FB1_Pos (1U) #define CAN_F4R1_FB1_Msk (0x1U << CAN_F4R1_FB1_Pos) /*!< 0x00000002 */ #define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk /*!< Filter bit 1 */ -#define CAN_F4R1_FB2_Pos (2U) +#define CAN_F4R1_FB2_Pos (2U) #define CAN_F4R1_FB2_Msk (0x1U << CAN_F4R1_FB2_Pos) /*!< 0x00000004 */ #define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk /*!< Filter bit 2 */ -#define CAN_F4R1_FB3_Pos (3U) +#define CAN_F4R1_FB3_Pos (3U) #define CAN_F4R1_FB3_Msk (0x1U << CAN_F4R1_FB3_Pos) /*!< 0x00000008 */ #define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk /*!< Filter bit 3 */ -#define CAN_F4R1_FB4_Pos (4U) +#define CAN_F4R1_FB4_Pos (4U) #define CAN_F4R1_FB4_Msk (0x1U << CAN_F4R1_FB4_Pos) /*!< 0x00000010 */ #define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk /*!< Filter bit 4 */ -#define CAN_F4R1_FB5_Pos (5U) +#define CAN_F4R1_FB5_Pos (5U) #define CAN_F4R1_FB5_Msk (0x1U << CAN_F4R1_FB5_Pos) /*!< 0x00000020 */ #define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk /*!< Filter bit 5 */ -#define CAN_F4R1_FB6_Pos (6U) +#define CAN_F4R1_FB6_Pos (6U) #define CAN_F4R1_FB6_Msk (0x1U << CAN_F4R1_FB6_Pos) /*!< 0x00000040 */ #define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk /*!< Filter bit 6 */ -#define CAN_F4R1_FB7_Pos (7U) +#define CAN_F4R1_FB7_Pos (7U) #define CAN_F4R1_FB7_Msk (0x1U << CAN_F4R1_FB7_Pos) /*!< 0x00000080 */ #define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk /*!< Filter bit 7 */ -#define CAN_F4R1_FB8_Pos (8U) +#define CAN_F4R1_FB8_Pos (8U) #define CAN_F4R1_FB8_Msk (0x1U << CAN_F4R1_FB8_Pos) /*!< 0x00000100 */ #define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk /*!< Filter bit 8 */ -#define CAN_F4R1_FB9_Pos (9U) +#define CAN_F4R1_FB9_Pos (9U) #define CAN_F4R1_FB9_Msk (0x1U << CAN_F4R1_FB9_Pos) /*!< 0x00000200 */ #define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk /*!< Filter bit 9 */ -#define CAN_F4R1_FB10_Pos (10U) +#define CAN_F4R1_FB10_Pos (10U) #define CAN_F4R1_FB10_Msk (0x1U << CAN_F4R1_FB10_Pos) /*!< 0x00000400 */ #define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk /*!< Filter bit 10 */ -#define CAN_F4R1_FB11_Pos (11U) +#define CAN_F4R1_FB11_Pos (11U) #define CAN_F4R1_FB11_Msk (0x1U << CAN_F4R1_FB11_Pos) /*!< 0x00000800 */ #define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk /*!< Filter bit 11 */ -#define CAN_F4R1_FB12_Pos (12U) +#define CAN_F4R1_FB12_Pos (12U) #define CAN_F4R1_FB12_Msk (0x1U << CAN_F4R1_FB12_Pos) /*!< 0x00001000 */ #define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk /*!< Filter bit 12 */ -#define CAN_F4R1_FB13_Pos (13U) +#define CAN_F4R1_FB13_Pos (13U) #define CAN_F4R1_FB13_Msk (0x1U << CAN_F4R1_FB13_Pos) /*!< 0x00002000 */ #define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk /*!< Filter bit 13 */ -#define CAN_F4R1_FB14_Pos (14U) +#define CAN_F4R1_FB14_Pos (14U) #define CAN_F4R1_FB14_Msk (0x1U << CAN_F4R1_FB14_Pos) /*!< 0x00004000 */ #define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk /*!< Filter bit 14 */ -#define CAN_F4R1_FB15_Pos (15U) +#define CAN_F4R1_FB15_Pos (15U) #define CAN_F4R1_FB15_Msk (0x1U << CAN_F4R1_FB15_Pos) /*!< 0x00008000 */ #define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk /*!< Filter bit 15 */ -#define CAN_F4R1_FB16_Pos (16U) +#define CAN_F4R1_FB16_Pos (16U) #define CAN_F4R1_FB16_Msk (0x1U << CAN_F4R1_FB16_Pos) /*!< 0x00010000 */ #define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk /*!< Filter bit 16 */ -#define CAN_F4R1_FB17_Pos (17U) +#define CAN_F4R1_FB17_Pos (17U) #define CAN_F4R1_FB17_Msk (0x1U << CAN_F4R1_FB17_Pos) /*!< 0x00020000 */ #define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk /*!< Filter bit 17 */ -#define CAN_F4R1_FB18_Pos (18U) +#define CAN_F4R1_FB18_Pos (18U) #define CAN_F4R1_FB18_Msk (0x1U << CAN_F4R1_FB18_Pos) /*!< 0x00040000 */ #define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk /*!< Filter bit 18 */ -#define CAN_F4R1_FB19_Pos (19U) +#define CAN_F4R1_FB19_Pos (19U) #define CAN_F4R1_FB19_Msk (0x1U << CAN_F4R1_FB19_Pos) /*!< 0x00080000 */ #define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk /*!< Filter bit 19 */ -#define CAN_F4R1_FB20_Pos (20U) +#define CAN_F4R1_FB20_Pos (20U) #define CAN_F4R1_FB20_Msk (0x1U << CAN_F4R1_FB20_Pos) /*!< 0x00100000 */ #define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk /*!< Filter bit 20 */ -#define CAN_F4R1_FB21_Pos (21U) +#define CAN_F4R1_FB21_Pos (21U) #define CAN_F4R1_FB21_Msk (0x1U << CAN_F4R1_FB21_Pos) /*!< 0x00200000 */ #define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk /*!< Filter bit 21 */ -#define CAN_F4R1_FB22_Pos (22U) +#define CAN_F4R1_FB22_Pos (22U) #define CAN_F4R1_FB22_Msk (0x1U << CAN_F4R1_FB22_Pos) /*!< 0x00400000 */ #define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk /*!< Filter bit 22 */ -#define CAN_F4R1_FB23_Pos (23U) +#define CAN_F4R1_FB23_Pos (23U) #define CAN_F4R1_FB23_Msk (0x1U << CAN_F4R1_FB23_Pos) /*!< 0x00800000 */ #define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk /*!< Filter bit 23 */ -#define CAN_F4R1_FB24_Pos (24U) +#define CAN_F4R1_FB24_Pos (24U) #define CAN_F4R1_FB24_Msk (0x1U << CAN_F4R1_FB24_Pos) /*!< 0x01000000 */ #define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk /*!< Filter bit 24 */ -#define CAN_F4R1_FB25_Pos (25U) +#define CAN_F4R1_FB25_Pos (25U) #define CAN_F4R1_FB25_Msk (0x1U << CAN_F4R1_FB25_Pos) /*!< 0x02000000 */ #define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk /*!< Filter bit 25 */ -#define CAN_F4R1_FB26_Pos (26U) +#define CAN_F4R1_FB26_Pos (26U) #define CAN_F4R1_FB26_Msk (0x1U << CAN_F4R1_FB26_Pos) /*!< 0x04000000 */ #define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk /*!< Filter bit 26 */ -#define CAN_F4R1_FB27_Pos (27U) +#define CAN_F4R1_FB27_Pos (27U) #define CAN_F4R1_FB27_Msk (0x1U << CAN_F4R1_FB27_Pos) /*!< 0x08000000 */ #define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk /*!< Filter bit 27 */ -#define CAN_F4R1_FB28_Pos (28U) +#define CAN_F4R1_FB28_Pos (28U) #define CAN_F4R1_FB28_Msk (0x1U << CAN_F4R1_FB28_Pos) /*!< 0x10000000 */ #define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk /*!< Filter bit 28 */ -#define CAN_F4R1_FB29_Pos (29U) +#define CAN_F4R1_FB29_Pos (29U) #define CAN_F4R1_FB29_Msk (0x1U << CAN_F4R1_FB29_Pos) /*!< 0x20000000 */ #define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk /*!< Filter bit 29 */ -#define CAN_F4R1_FB30_Pos (30U) +#define CAN_F4R1_FB30_Pos (30U) #define CAN_F4R1_FB30_Msk (0x1U << CAN_F4R1_FB30_Pos) /*!< 0x40000000 */ #define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk /*!< Filter bit 30 */ -#define CAN_F4R1_FB31_Pos (31U) +#define CAN_F4R1_FB31_Pos (31U) #define CAN_F4R1_FB31_Msk (0x1U << CAN_F4R1_FB31_Pos) /*!< 0x80000000 */ #define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk /*!< Filter bit 31 */ /******************* Bit definition for CAN_F5R1 register *******************/ -#define CAN_F5R1_FB0_Pos (0U) +#define CAN_F5R1_FB0_Pos (0U) #define CAN_F5R1_FB0_Msk (0x1U << CAN_F5R1_FB0_Pos) /*!< 0x00000001 */ #define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk /*!< Filter bit 0 */ -#define CAN_F5R1_FB1_Pos (1U) +#define CAN_F5R1_FB1_Pos (1U) #define CAN_F5R1_FB1_Msk (0x1U << CAN_F5R1_FB1_Pos) /*!< 0x00000002 */ #define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk /*!< Filter bit 1 */ -#define CAN_F5R1_FB2_Pos (2U) +#define CAN_F5R1_FB2_Pos (2U) #define CAN_F5R1_FB2_Msk (0x1U << CAN_F5R1_FB2_Pos) /*!< 0x00000004 */ #define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk /*!< Filter bit 2 */ -#define CAN_F5R1_FB3_Pos (3U) +#define CAN_F5R1_FB3_Pos (3U) #define CAN_F5R1_FB3_Msk (0x1U << CAN_F5R1_FB3_Pos) /*!< 0x00000008 */ #define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk /*!< Filter bit 3 */ -#define CAN_F5R1_FB4_Pos (4U) +#define CAN_F5R1_FB4_Pos (4U) #define CAN_F5R1_FB4_Msk (0x1U << CAN_F5R1_FB4_Pos) /*!< 0x00000010 */ #define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk /*!< Filter bit 4 */ -#define CAN_F5R1_FB5_Pos (5U) +#define CAN_F5R1_FB5_Pos (5U) #define CAN_F5R1_FB5_Msk (0x1U << CAN_F5R1_FB5_Pos) /*!< 0x00000020 */ #define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk /*!< Filter bit 5 */ -#define CAN_F5R1_FB6_Pos (6U) +#define CAN_F5R1_FB6_Pos (6U) #define CAN_F5R1_FB6_Msk (0x1U << CAN_F5R1_FB6_Pos) /*!< 0x00000040 */ #define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk /*!< Filter bit 6 */ -#define CAN_F5R1_FB7_Pos (7U) +#define CAN_F5R1_FB7_Pos (7U) #define CAN_F5R1_FB7_Msk (0x1U << CAN_F5R1_FB7_Pos) /*!< 0x00000080 */ #define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk /*!< Filter bit 7 */ -#define CAN_F5R1_FB8_Pos (8U) +#define CAN_F5R1_FB8_Pos (8U) #define CAN_F5R1_FB8_Msk (0x1U << CAN_F5R1_FB8_Pos) /*!< 0x00000100 */ #define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk /*!< Filter bit 8 */ -#define CAN_F5R1_FB9_Pos (9U) +#define CAN_F5R1_FB9_Pos (9U) #define CAN_F5R1_FB9_Msk (0x1U << CAN_F5R1_FB9_Pos) /*!< 0x00000200 */ #define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk /*!< Filter bit 9 */ -#define CAN_F5R1_FB10_Pos (10U) +#define CAN_F5R1_FB10_Pos (10U) #define CAN_F5R1_FB10_Msk (0x1U << CAN_F5R1_FB10_Pos) /*!< 0x00000400 */ #define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk /*!< Filter bit 10 */ -#define CAN_F5R1_FB11_Pos (11U) +#define CAN_F5R1_FB11_Pos (11U) #define CAN_F5R1_FB11_Msk (0x1U << CAN_F5R1_FB11_Pos) /*!< 0x00000800 */ #define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk /*!< Filter bit 11 */ -#define CAN_F5R1_FB12_Pos (12U) +#define CAN_F5R1_FB12_Pos (12U) #define CAN_F5R1_FB12_Msk (0x1U << CAN_F5R1_FB12_Pos) /*!< 0x00001000 */ #define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk /*!< Filter bit 12 */ -#define CAN_F5R1_FB13_Pos (13U) +#define CAN_F5R1_FB13_Pos (13U) #define CAN_F5R1_FB13_Msk (0x1U << CAN_F5R1_FB13_Pos) /*!< 0x00002000 */ #define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk /*!< Filter bit 13 */ -#define CAN_F5R1_FB14_Pos (14U) +#define CAN_F5R1_FB14_Pos (14U) #define CAN_F5R1_FB14_Msk (0x1U << CAN_F5R1_FB14_Pos) /*!< 0x00004000 */ #define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk /*!< Filter bit 14 */ -#define CAN_F5R1_FB15_Pos (15U) +#define CAN_F5R1_FB15_Pos (15U) #define CAN_F5R1_FB15_Msk (0x1U << CAN_F5R1_FB15_Pos) /*!< 0x00008000 */ #define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk /*!< Filter bit 15 */ -#define CAN_F5R1_FB16_Pos (16U) +#define CAN_F5R1_FB16_Pos (16U) #define CAN_F5R1_FB16_Msk (0x1U << CAN_F5R1_FB16_Pos) /*!< 0x00010000 */ #define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk /*!< Filter bit 16 */ -#define CAN_F5R1_FB17_Pos (17U) +#define CAN_F5R1_FB17_Pos (17U) #define CAN_F5R1_FB17_Msk (0x1U << CAN_F5R1_FB17_Pos) /*!< 0x00020000 */ #define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk /*!< Filter bit 17 */ -#define CAN_F5R1_FB18_Pos (18U) +#define CAN_F5R1_FB18_Pos (18U) #define CAN_F5R1_FB18_Msk (0x1U << CAN_F5R1_FB18_Pos) /*!< 0x00040000 */ #define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk /*!< Filter bit 18 */ -#define CAN_F5R1_FB19_Pos (19U) +#define CAN_F5R1_FB19_Pos (19U) #define CAN_F5R1_FB19_Msk (0x1U << CAN_F5R1_FB19_Pos) /*!< 0x00080000 */ #define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk /*!< Filter bit 19 */ -#define CAN_F5R1_FB20_Pos (20U) +#define CAN_F5R1_FB20_Pos (20U) #define CAN_F5R1_FB20_Msk (0x1U << CAN_F5R1_FB20_Pos) /*!< 0x00100000 */ #define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk /*!< Filter bit 20 */ -#define CAN_F5R1_FB21_Pos (21U) +#define CAN_F5R1_FB21_Pos (21U) #define CAN_F5R1_FB21_Msk (0x1U << CAN_F5R1_FB21_Pos) /*!< 0x00200000 */ #define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk /*!< Filter bit 21 */ -#define CAN_F5R1_FB22_Pos (22U) +#define CAN_F5R1_FB22_Pos (22U) #define CAN_F5R1_FB22_Msk (0x1U << CAN_F5R1_FB22_Pos) /*!< 0x00400000 */ #define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk /*!< Filter bit 22 */ -#define CAN_F5R1_FB23_Pos (23U) +#define CAN_F5R1_FB23_Pos (23U) #define CAN_F5R1_FB23_Msk (0x1U << CAN_F5R1_FB23_Pos) /*!< 0x00800000 */ #define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk /*!< Filter bit 23 */ -#define CAN_F5R1_FB24_Pos (24U) +#define CAN_F5R1_FB24_Pos (24U) #define CAN_F5R1_FB24_Msk (0x1U << CAN_F5R1_FB24_Pos) /*!< 0x01000000 */ #define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk /*!< Filter bit 24 */ -#define CAN_F5R1_FB25_Pos (25U) +#define CAN_F5R1_FB25_Pos (25U) #define CAN_F5R1_FB25_Msk (0x1U << CAN_F5R1_FB25_Pos) /*!< 0x02000000 */ #define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk /*!< Filter bit 25 */ -#define CAN_F5R1_FB26_Pos (26U) +#define CAN_F5R1_FB26_Pos (26U) #define CAN_F5R1_FB26_Msk (0x1U << CAN_F5R1_FB26_Pos) /*!< 0x04000000 */ #define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk /*!< Filter bit 26 */ -#define CAN_F5R1_FB27_Pos (27U) +#define CAN_F5R1_FB27_Pos (27U) #define CAN_F5R1_FB27_Msk (0x1U << CAN_F5R1_FB27_Pos) /*!< 0x08000000 */ #define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk /*!< Filter bit 27 */ -#define CAN_F5R1_FB28_Pos (28U) +#define CAN_F5R1_FB28_Pos (28U) #define CAN_F5R1_FB28_Msk (0x1U << CAN_F5R1_FB28_Pos) /*!< 0x10000000 */ #define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk /*!< Filter bit 28 */ -#define CAN_F5R1_FB29_Pos (29U) +#define CAN_F5R1_FB29_Pos (29U) #define CAN_F5R1_FB29_Msk (0x1U << CAN_F5R1_FB29_Pos) /*!< 0x20000000 */ #define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk /*!< Filter bit 29 */ -#define CAN_F5R1_FB30_Pos (30U) +#define CAN_F5R1_FB30_Pos (30U) #define CAN_F5R1_FB30_Msk (0x1U << CAN_F5R1_FB30_Pos) /*!< 0x40000000 */ #define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk /*!< Filter bit 30 */ -#define CAN_F5R1_FB31_Pos (31U) +#define CAN_F5R1_FB31_Pos (31U) #define CAN_F5R1_FB31_Msk (0x1U << CAN_F5R1_FB31_Pos) /*!< 0x80000000 */ #define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk /*!< Filter bit 31 */ /******************* Bit definition for CAN_F6R1 register *******************/ -#define CAN_F6R1_FB0_Pos (0U) +#define CAN_F6R1_FB0_Pos (0U) #define CAN_F6R1_FB0_Msk (0x1U << CAN_F6R1_FB0_Pos) /*!< 0x00000001 */ #define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk /*!< Filter bit 0 */ -#define CAN_F6R1_FB1_Pos (1U) +#define CAN_F6R1_FB1_Pos (1U) #define CAN_F6R1_FB1_Msk (0x1U << CAN_F6R1_FB1_Pos) /*!< 0x00000002 */ #define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk /*!< Filter bit 1 */ -#define CAN_F6R1_FB2_Pos (2U) +#define CAN_F6R1_FB2_Pos (2U) #define CAN_F6R1_FB2_Msk (0x1U << CAN_F6R1_FB2_Pos) /*!< 0x00000004 */ #define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk /*!< Filter bit 2 */ -#define CAN_F6R1_FB3_Pos (3U) +#define CAN_F6R1_FB3_Pos (3U) #define CAN_F6R1_FB3_Msk (0x1U << CAN_F6R1_FB3_Pos) /*!< 0x00000008 */ #define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk /*!< Filter bit 3 */ -#define CAN_F6R1_FB4_Pos (4U) +#define CAN_F6R1_FB4_Pos (4U) #define CAN_F6R1_FB4_Msk (0x1U << CAN_F6R1_FB4_Pos) /*!< 0x00000010 */ #define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk /*!< Filter bit 4 */ -#define CAN_F6R1_FB5_Pos (5U) +#define CAN_F6R1_FB5_Pos (5U) #define CAN_F6R1_FB5_Msk (0x1U << CAN_F6R1_FB5_Pos) /*!< 0x00000020 */ #define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk /*!< Filter bit 5 */ -#define CAN_F6R1_FB6_Pos (6U) +#define CAN_F6R1_FB6_Pos (6U) #define CAN_F6R1_FB6_Msk (0x1U << CAN_F6R1_FB6_Pos) /*!< 0x00000040 */ #define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk /*!< Filter bit 6 */ -#define CAN_F6R1_FB7_Pos (7U) +#define CAN_F6R1_FB7_Pos (7U) #define CAN_F6R1_FB7_Msk (0x1U << CAN_F6R1_FB7_Pos) /*!< 0x00000080 */ #define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk /*!< Filter bit 7 */ -#define CAN_F6R1_FB8_Pos (8U) +#define CAN_F6R1_FB8_Pos (8U) #define CAN_F6R1_FB8_Msk (0x1U << CAN_F6R1_FB8_Pos) /*!< 0x00000100 */ #define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk /*!< Filter bit 8 */ -#define CAN_F6R1_FB9_Pos (9U) +#define CAN_F6R1_FB9_Pos (9U) #define CAN_F6R1_FB9_Msk (0x1U << CAN_F6R1_FB9_Pos) /*!< 0x00000200 */ #define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk /*!< Filter bit 9 */ -#define CAN_F6R1_FB10_Pos (10U) +#define CAN_F6R1_FB10_Pos (10U) #define CAN_F6R1_FB10_Msk (0x1U << CAN_F6R1_FB10_Pos) /*!< 0x00000400 */ #define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk /*!< Filter bit 10 */ -#define CAN_F6R1_FB11_Pos (11U) +#define CAN_F6R1_FB11_Pos (11U) #define CAN_F6R1_FB11_Msk (0x1U << CAN_F6R1_FB11_Pos) /*!< 0x00000800 */ #define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk /*!< Filter bit 11 */ -#define CAN_F6R1_FB12_Pos (12U) +#define CAN_F6R1_FB12_Pos (12U) #define CAN_F6R1_FB12_Msk (0x1U << CAN_F6R1_FB12_Pos) /*!< 0x00001000 */ #define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk /*!< Filter bit 12 */ -#define CAN_F6R1_FB13_Pos (13U) +#define CAN_F6R1_FB13_Pos (13U) #define CAN_F6R1_FB13_Msk (0x1U << CAN_F6R1_FB13_Pos) /*!< 0x00002000 */ #define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk /*!< Filter bit 13 */ -#define CAN_F6R1_FB14_Pos (14U) +#define CAN_F6R1_FB14_Pos (14U) #define CAN_F6R1_FB14_Msk (0x1U << CAN_F6R1_FB14_Pos) /*!< 0x00004000 */ #define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk /*!< Filter bit 14 */ -#define CAN_F6R1_FB15_Pos (15U) +#define CAN_F6R1_FB15_Pos (15U) #define CAN_F6R1_FB15_Msk (0x1U << CAN_F6R1_FB15_Pos) /*!< 0x00008000 */ #define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk /*!< Filter bit 15 */ -#define CAN_F6R1_FB16_Pos (16U) +#define CAN_F6R1_FB16_Pos (16U) #define CAN_F6R1_FB16_Msk (0x1U << CAN_F6R1_FB16_Pos) /*!< 0x00010000 */ #define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk /*!< Filter bit 16 */ -#define CAN_F6R1_FB17_Pos (17U) +#define CAN_F6R1_FB17_Pos (17U) #define CAN_F6R1_FB17_Msk (0x1U << CAN_F6R1_FB17_Pos) /*!< 0x00020000 */ #define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk /*!< Filter bit 17 */ -#define CAN_F6R1_FB18_Pos (18U) +#define CAN_F6R1_FB18_Pos (18U) #define CAN_F6R1_FB18_Msk (0x1U << CAN_F6R1_FB18_Pos) /*!< 0x00040000 */ #define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk /*!< Filter bit 18 */ -#define CAN_F6R1_FB19_Pos (19U) +#define CAN_F6R1_FB19_Pos (19U) #define CAN_F6R1_FB19_Msk (0x1U << CAN_F6R1_FB19_Pos) /*!< 0x00080000 */ #define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk /*!< Filter bit 19 */ -#define CAN_F6R1_FB20_Pos (20U) +#define CAN_F6R1_FB20_Pos (20U) #define CAN_F6R1_FB20_Msk (0x1U << CAN_F6R1_FB20_Pos) /*!< 0x00100000 */ #define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk /*!< Filter bit 20 */ -#define CAN_F6R1_FB21_Pos (21U) +#define CAN_F6R1_FB21_Pos (21U) #define CAN_F6R1_FB21_Msk (0x1U << CAN_F6R1_FB21_Pos) /*!< 0x00200000 */ #define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk /*!< Filter bit 21 */ -#define CAN_F6R1_FB22_Pos (22U) +#define CAN_F6R1_FB22_Pos (22U) #define CAN_F6R1_FB22_Msk (0x1U << CAN_F6R1_FB22_Pos) /*!< 0x00400000 */ #define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk /*!< Filter bit 22 */ -#define CAN_F6R1_FB23_Pos (23U) +#define CAN_F6R1_FB23_Pos (23U) #define CAN_F6R1_FB23_Msk (0x1U << CAN_F6R1_FB23_Pos) /*!< 0x00800000 */ #define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk /*!< Filter bit 23 */ -#define CAN_F6R1_FB24_Pos (24U) +#define CAN_F6R1_FB24_Pos (24U) #define CAN_F6R1_FB24_Msk (0x1U << CAN_F6R1_FB24_Pos) /*!< 0x01000000 */ #define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk /*!< Filter bit 24 */ -#define CAN_F6R1_FB25_Pos (25U) +#define CAN_F6R1_FB25_Pos (25U) #define CAN_F6R1_FB25_Msk (0x1U << CAN_F6R1_FB25_Pos) /*!< 0x02000000 */ #define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk /*!< Filter bit 25 */ -#define CAN_F6R1_FB26_Pos (26U) +#define CAN_F6R1_FB26_Pos (26U) #define CAN_F6R1_FB26_Msk (0x1U << CAN_F6R1_FB26_Pos) /*!< 0x04000000 */ #define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk /*!< Filter bit 26 */ -#define CAN_F6R1_FB27_Pos (27U) +#define CAN_F6R1_FB27_Pos (27U) #define CAN_F6R1_FB27_Msk (0x1U << CAN_F6R1_FB27_Pos) /*!< 0x08000000 */ #define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk /*!< Filter bit 27 */ -#define CAN_F6R1_FB28_Pos (28U) +#define CAN_F6R1_FB28_Pos (28U) #define CAN_F6R1_FB28_Msk (0x1U << CAN_F6R1_FB28_Pos) /*!< 0x10000000 */ #define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk /*!< Filter bit 28 */ -#define CAN_F6R1_FB29_Pos (29U) +#define CAN_F6R1_FB29_Pos (29U) #define CAN_F6R1_FB29_Msk (0x1U << CAN_F6R1_FB29_Pos) /*!< 0x20000000 */ #define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk /*!< Filter bit 29 */ -#define CAN_F6R1_FB30_Pos (30U) +#define CAN_F6R1_FB30_Pos (30U) #define CAN_F6R1_FB30_Msk (0x1U << CAN_F6R1_FB30_Pos) /*!< 0x40000000 */ #define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk /*!< Filter bit 30 */ -#define CAN_F6R1_FB31_Pos (31U) +#define CAN_F6R1_FB31_Pos (31U) #define CAN_F6R1_FB31_Msk (0x1U << CAN_F6R1_FB31_Pos) /*!< 0x80000000 */ #define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk /*!< Filter bit 31 */ /******************* Bit definition for CAN_F7R1 register *******************/ -#define CAN_F7R1_FB0_Pos (0U) +#define CAN_F7R1_FB0_Pos (0U) #define CAN_F7R1_FB0_Msk (0x1U << CAN_F7R1_FB0_Pos) /*!< 0x00000001 */ #define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk /*!< Filter bit 0 */ -#define CAN_F7R1_FB1_Pos (1U) +#define CAN_F7R1_FB1_Pos (1U) #define CAN_F7R1_FB1_Msk (0x1U << CAN_F7R1_FB1_Pos) /*!< 0x00000002 */ #define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk /*!< Filter bit 1 */ -#define CAN_F7R1_FB2_Pos (2U) +#define CAN_F7R1_FB2_Pos (2U) #define CAN_F7R1_FB2_Msk (0x1U << CAN_F7R1_FB2_Pos) /*!< 0x00000004 */ #define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk /*!< Filter bit 2 */ -#define CAN_F7R1_FB3_Pos (3U) +#define CAN_F7R1_FB3_Pos (3U) #define CAN_F7R1_FB3_Msk (0x1U << CAN_F7R1_FB3_Pos) /*!< 0x00000008 */ #define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk /*!< Filter bit 3 */ -#define CAN_F7R1_FB4_Pos (4U) +#define CAN_F7R1_FB4_Pos (4U) #define CAN_F7R1_FB4_Msk (0x1U << CAN_F7R1_FB4_Pos) /*!< 0x00000010 */ #define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk /*!< Filter bit 4 */ -#define CAN_F7R1_FB5_Pos (5U) +#define CAN_F7R1_FB5_Pos (5U) #define CAN_F7R1_FB5_Msk (0x1U << CAN_F7R1_FB5_Pos) /*!< 0x00000020 */ #define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk /*!< Filter bit 5 */ -#define CAN_F7R1_FB6_Pos (6U) +#define CAN_F7R1_FB6_Pos (6U) #define CAN_F7R1_FB6_Msk (0x1U << CAN_F7R1_FB6_Pos) /*!< 0x00000040 */ #define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk /*!< Filter bit 6 */ -#define CAN_F7R1_FB7_Pos (7U) +#define CAN_F7R1_FB7_Pos (7U) #define CAN_F7R1_FB7_Msk (0x1U << CAN_F7R1_FB7_Pos) /*!< 0x00000080 */ #define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk /*!< Filter bit 7 */ -#define CAN_F7R1_FB8_Pos (8U) +#define CAN_F7R1_FB8_Pos (8U) #define CAN_F7R1_FB8_Msk (0x1U << CAN_F7R1_FB8_Pos) /*!< 0x00000100 */ #define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk /*!< Filter bit 8 */ -#define CAN_F7R1_FB9_Pos (9U) +#define CAN_F7R1_FB9_Pos (9U) #define CAN_F7R1_FB9_Msk (0x1U << CAN_F7R1_FB9_Pos) /*!< 0x00000200 */ #define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk /*!< Filter bit 9 */ -#define CAN_F7R1_FB10_Pos (10U) +#define CAN_F7R1_FB10_Pos (10U) #define CAN_F7R1_FB10_Msk (0x1U << CAN_F7R1_FB10_Pos) /*!< 0x00000400 */ #define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk /*!< Filter bit 10 */ -#define CAN_F7R1_FB11_Pos (11U) +#define CAN_F7R1_FB11_Pos (11U) #define CAN_F7R1_FB11_Msk (0x1U << CAN_F7R1_FB11_Pos) /*!< 0x00000800 */ #define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk /*!< Filter bit 11 */ -#define CAN_F7R1_FB12_Pos (12U) +#define CAN_F7R1_FB12_Pos (12U) #define CAN_F7R1_FB12_Msk (0x1U << CAN_F7R1_FB12_Pos) /*!< 0x00001000 */ #define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk /*!< Filter bit 12 */ -#define CAN_F7R1_FB13_Pos (13U) +#define CAN_F7R1_FB13_Pos (13U) #define CAN_F7R1_FB13_Msk (0x1U << CAN_F7R1_FB13_Pos) /*!< 0x00002000 */ #define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk /*!< Filter bit 13 */ -#define CAN_F7R1_FB14_Pos (14U) +#define CAN_F7R1_FB14_Pos (14U) #define CAN_F7R1_FB14_Msk (0x1U << CAN_F7R1_FB14_Pos) /*!< 0x00004000 */ #define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk /*!< Filter bit 14 */ -#define CAN_F7R1_FB15_Pos (15U) +#define CAN_F7R1_FB15_Pos (15U) #define CAN_F7R1_FB15_Msk (0x1U << CAN_F7R1_FB15_Pos) /*!< 0x00008000 */ #define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk /*!< Filter bit 15 */ -#define CAN_F7R1_FB16_Pos (16U) +#define CAN_F7R1_FB16_Pos (16U) #define CAN_F7R1_FB16_Msk (0x1U << CAN_F7R1_FB16_Pos) /*!< 0x00010000 */ #define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk /*!< Filter bit 16 */ -#define CAN_F7R1_FB17_Pos (17U) +#define CAN_F7R1_FB17_Pos (17U) #define CAN_F7R1_FB17_Msk (0x1U << CAN_F7R1_FB17_Pos) /*!< 0x00020000 */ #define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk /*!< Filter bit 17 */ -#define CAN_F7R1_FB18_Pos (18U) +#define CAN_F7R1_FB18_Pos (18U) #define CAN_F7R1_FB18_Msk (0x1U << CAN_F7R1_FB18_Pos) /*!< 0x00040000 */ #define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk /*!< Filter bit 18 */ -#define CAN_F7R1_FB19_Pos (19U) +#define CAN_F7R1_FB19_Pos (19U) #define CAN_F7R1_FB19_Msk (0x1U << CAN_F7R1_FB19_Pos) /*!< 0x00080000 */ #define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk /*!< Filter bit 19 */ -#define CAN_F7R1_FB20_Pos (20U) +#define CAN_F7R1_FB20_Pos (20U) #define CAN_F7R1_FB20_Msk (0x1U << CAN_F7R1_FB20_Pos) /*!< 0x00100000 */ #define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk /*!< Filter bit 20 */ -#define CAN_F7R1_FB21_Pos (21U) +#define CAN_F7R1_FB21_Pos (21U) #define CAN_F7R1_FB21_Msk (0x1U << CAN_F7R1_FB21_Pos) /*!< 0x00200000 */ #define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk /*!< Filter bit 21 */ -#define CAN_F7R1_FB22_Pos (22U) +#define CAN_F7R1_FB22_Pos (22U) #define CAN_F7R1_FB22_Msk (0x1U << CAN_F7R1_FB22_Pos) /*!< 0x00400000 */ #define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk /*!< Filter bit 22 */ -#define CAN_F7R1_FB23_Pos (23U) +#define CAN_F7R1_FB23_Pos (23U) #define CAN_F7R1_FB23_Msk (0x1U << CAN_F7R1_FB23_Pos) /*!< 0x00800000 */ #define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk /*!< Filter bit 23 */ -#define CAN_F7R1_FB24_Pos (24U) +#define CAN_F7R1_FB24_Pos (24U) #define CAN_F7R1_FB24_Msk (0x1U << CAN_F7R1_FB24_Pos) /*!< 0x01000000 */ #define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk /*!< Filter bit 24 */ -#define CAN_F7R1_FB25_Pos (25U) +#define CAN_F7R1_FB25_Pos (25U) #define CAN_F7R1_FB25_Msk (0x1U << CAN_F7R1_FB25_Pos) /*!< 0x02000000 */ #define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk /*!< Filter bit 25 */ -#define CAN_F7R1_FB26_Pos (26U) +#define CAN_F7R1_FB26_Pos (26U) #define CAN_F7R1_FB26_Msk (0x1U << CAN_F7R1_FB26_Pos) /*!< 0x04000000 */ #define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk /*!< Filter bit 26 */ -#define CAN_F7R1_FB27_Pos (27U) +#define CAN_F7R1_FB27_Pos (27U) #define CAN_F7R1_FB27_Msk (0x1U << CAN_F7R1_FB27_Pos) /*!< 0x08000000 */ #define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk /*!< Filter bit 27 */ -#define CAN_F7R1_FB28_Pos (28U) +#define CAN_F7R1_FB28_Pos (28U) #define CAN_F7R1_FB28_Msk (0x1U << CAN_F7R1_FB28_Pos) /*!< 0x10000000 */ #define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk /*!< Filter bit 28 */ -#define CAN_F7R1_FB29_Pos (29U) +#define CAN_F7R1_FB29_Pos (29U) #define CAN_F7R1_FB29_Msk (0x1U << CAN_F7R1_FB29_Pos) /*!< 0x20000000 */ #define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk /*!< Filter bit 29 */ -#define CAN_F7R1_FB30_Pos (30U) +#define CAN_F7R1_FB30_Pos (30U) #define CAN_F7R1_FB30_Msk (0x1U << CAN_F7R1_FB30_Pos) /*!< 0x40000000 */ #define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk /*!< Filter bit 30 */ -#define CAN_F7R1_FB31_Pos (31U) +#define CAN_F7R1_FB31_Pos (31U) #define CAN_F7R1_FB31_Msk (0x1U << CAN_F7R1_FB31_Pos) /*!< 0x80000000 */ #define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk /*!< Filter bit 31 */ /******************* Bit definition for CAN_F8R1 register *******************/ -#define CAN_F8R1_FB0_Pos (0U) +#define CAN_F8R1_FB0_Pos (0U) #define CAN_F8R1_FB0_Msk (0x1U << CAN_F8R1_FB0_Pos) /*!< 0x00000001 */ #define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk /*!< Filter bit 0 */ -#define CAN_F8R1_FB1_Pos (1U) +#define CAN_F8R1_FB1_Pos (1U) #define CAN_F8R1_FB1_Msk (0x1U << CAN_F8R1_FB1_Pos) /*!< 0x00000002 */ #define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk /*!< Filter bit 1 */ -#define CAN_F8R1_FB2_Pos (2U) +#define CAN_F8R1_FB2_Pos (2U) #define CAN_F8R1_FB2_Msk (0x1U << CAN_F8R1_FB2_Pos) /*!< 0x00000004 */ #define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk /*!< Filter bit 2 */ -#define CAN_F8R1_FB3_Pos (3U) +#define CAN_F8R1_FB3_Pos (3U) #define CAN_F8R1_FB3_Msk (0x1U << CAN_F8R1_FB3_Pos) /*!< 0x00000008 */ #define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk /*!< Filter bit 3 */ -#define CAN_F8R1_FB4_Pos (4U) +#define CAN_F8R1_FB4_Pos (4U) #define CAN_F8R1_FB4_Msk (0x1U << CAN_F8R1_FB4_Pos) /*!< 0x00000010 */ #define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk /*!< Filter bit 4 */ -#define CAN_F8R1_FB5_Pos (5U) +#define CAN_F8R1_FB5_Pos (5U) #define CAN_F8R1_FB5_Msk (0x1U << CAN_F8R1_FB5_Pos) /*!< 0x00000020 */ #define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk /*!< Filter bit 5 */ -#define CAN_F8R1_FB6_Pos (6U) +#define CAN_F8R1_FB6_Pos (6U) #define CAN_F8R1_FB6_Msk (0x1U << CAN_F8R1_FB6_Pos) /*!< 0x00000040 */ #define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk /*!< Filter bit 6 */ -#define CAN_F8R1_FB7_Pos (7U) +#define CAN_F8R1_FB7_Pos (7U) #define CAN_F8R1_FB7_Msk (0x1U << CAN_F8R1_FB7_Pos) /*!< 0x00000080 */ #define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk /*!< Filter bit 7 */ -#define CAN_F8R1_FB8_Pos (8U) +#define CAN_F8R1_FB8_Pos (8U) #define CAN_F8R1_FB8_Msk (0x1U << CAN_F8R1_FB8_Pos) /*!< 0x00000100 */ #define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk /*!< Filter bit 8 */ -#define CAN_F8R1_FB9_Pos (9U) +#define CAN_F8R1_FB9_Pos (9U) #define CAN_F8R1_FB9_Msk (0x1U << CAN_F8R1_FB9_Pos) /*!< 0x00000200 */ #define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk /*!< Filter bit 9 */ -#define CAN_F8R1_FB10_Pos (10U) +#define CAN_F8R1_FB10_Pos (10U) #define CAN_F8R1_FB10_Msk (0x1U << CAN_F8R1_FB10_Pos) /*!< 0x00000400 */ #define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk /*!< Filter bit 10 */ -#define CAN_F8R1_FB11_Pos (11U) +#define CAN_F8R1_FB11_Pos (11U) #define CAN_F8R1_FB11_Msk (0x1U << CAN_F8R1_FB11_Pos) /*!< 0x00000800 */ #define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk /*!< Filter bit 11 */ -#define CAN_F8R1_FB12_Pos (12U) +#define CAN_F8R1_FB12_Pos (12U) #define CAN_F8R1_FB12_Msk (0x1U << CAN_F8R1_FB12_Pos) /*!< 0x00001000 */ #define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk /*!< Filter bit 12 */ -#define CAN_F8R1_FB13_Pos (13U) +#define CAN_F8R1_FB13_Pos (13U) #define CAN_F8R1_FB13_Msk (0x1U << CAN_F8R1_FB13_Pos) /*!< 0x00002000 */ #define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk /*!< Filter bit 13 */ -#define CAN_F8R1_FB14_Pos (14U) +#define CAN_F8R1_FB14_Pos (14U) #define CAN_F8R1_FB14_Msk (0x1U << CAN_F8R1_FB14_Pos) /*!< 0x00004000 */ #define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk /*!< Filter bit 14 */ -#define CAN_F8R1_FB15_Pos (15U) +#define CAN_F8R1_FB15_Pos (15U) #define CAN_F8R1_FB15_Msk (0x1U << CAN_F8R1_FB15_Pos) /*!< 0x00008000 */ #define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk /*!< Filter bit 15 */ -#define CAN_F8R1_FB16_Pos (16U) +#define CAN_F8R1_FB16_Pos (16U) #define CAN_F8R1_FB16_Msk (0x1U << CAN_F8R1_FB16_Pos) /*!< 0x00010000 */ #define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk /*!< Filter bit 16 */ -#define CAN_F8R1_FB17_Pos (17U) +#define CAN_F8R1_FB17_Pos (17U) #define CAN_F8R1_FB17_Msk (0x1U << CAN_F8R1_FB17_Pos) /*!< 0x00020000 */ #define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk /*!< Filter bit 17 */ -#define CAN_F8R1_FB18_Pos (18U) +#define CAN_F8R1_FB18_Pos (18U) #define CAN_F8R1_FB18_Msk (0x1U << CAN_F8R1_FB18_Pos) /*!< 0x00040000 */ #define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk /*!< Filter bit 18 */ -#define CAN_F8R1_FB19_Pos (19U) +#define CAN_F8R1_FB19_Pos (19U) #define CAN_F8R1_FB19_Msk (0x1U << CAN_F8R1_FB19_Pos) /*!< 0x00080000 */ #define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk /*!< Filter bit 19 */ -#define CAN_F8R1_FB20_Pos (20U) +#define CAN_F8R1_FB20_Pos (20U) #define CAN_F8R1_FB20_Msk (0x1U << CAN_F8R1_FB20_Pos) /*!< 0x00100000 */ #define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk /*!< Filter bit 20 */ -#define CAN_F8R1_FB21_Pos (21U) +#define CAN_F8R1_FB21_Pos (21U) #define CAN_F8R1_FB21_Msk (0x1U << CAN_F8R1_FB21_Pos) /*!< 0x00200000 */ #define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk /*!< Filter bit 21 */ -#define CAN_F8R1_FB22_Pos (22U) +#define CAN_F8R1_FB22_Pos (22U) #define CAN_F8R1_FB22_Msk (0x1U << CAN_F8R1_FB22_Pos) /*!< 0x00400000 */ #define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk /*!< Filter bit 22 */ -#define CAN_F8R1_FB23_Pos (23U) +#define CAN_F8R1_FB23_Pos (23U) #define CAN_F8R1_FB23_Msk (0x1U << CAN_F8R1_FB23_Pos) /*!< 0x00800000 */ #define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk /*!< Filter bit 23 */ -#define CAN_F8R1_FB24_Pos (24U) +#define CAN_F8R1_FB24_Pos (24U) #define CAN_F8R1_FB24_Msk (0x1U << CAN_F8R1_FB24_Pos) /*!< 0x01000000 */ #define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk /*!< Filter bit 24 */ -#define CAN_F8R1_FB25_Pos (25U) +#define CAN_F8R1_FB25_Pos (25U) #define CAN_F8R1_FB25_Msk (0x1U << CAN_F8R1_FB25_Pos) /*!< 0x02000000 */ #define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk /*!< Filter bit 25 */ -#define CAN_F8R1_FB26_Pos (26U) +#define CAN_F8R1_FB26_Pos (26U) #define CAN_F8R1_FB26_Msk (0x1U << CAN_F8R1_FB26_Pos) /*!< 0x04000000 */ #define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk /*!< Filter bit 26 */ -#define CAN_F8R1_FB27_Pos (27U) +#define CAN_F8R1_FB27_Pos (27U) #define CAN_F8R1_FB27_Msk (0x1U << CAN_F8R1_FB27_Pos) /*!< 0x08000000 */ #define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk /*!< Filter bit 27 */ -#define CAN_F8R1_FB28_Pos (28U) +#define CAN_F8R1_FB28_Pos (28U) #define CAN_F8R1_FB28_Msk (0x1U << CAN_F8R1_FB28_Pos) /*!< 0x10000000 */ #define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk /*!< Filter bit 28 */ -#define CAN_F8R1_FB29_Pos (29U) +#define CAN_F8R1_FB29_Pos (29U) #define CAN_F8R1_FB29_Msk (0x1U << CAN_F8R1_FB29_Pos) /*!< 0x20000000 */ #define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk /*!< Filter bit 29 */ -#define CAN_F8R1_FB30_Pos (30U) +#define CAN_F8R1_FB30_Pos (30U) #define CAN_F8R1_FB30_Msk (0x1U << CAN_F8R1_FB30_Pos) /*!< 0x40000000 */ #define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk /*!< Filter bit 30 */ -#define CAN_F8R1_FB31_Pos (31U) +#define CAN_F8R1_FB31_Pos (31U) #define CAN_F8R1_FB31_Msk (0x1U << CAN_F8R1_FB31_Pos) /*!< 0x80000000 */ #define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk /*!< Filter bit 31 */ /******************* Bit definition for CAN_F9R1 register *******************/ -#define CAN_F9R1_FB0_Pos (0U) +#define CAN_F9R1_FB0_Pos (0U) #define CAN_F9R1_FB0_Msk (0x1U << CAN_F9R1_FB0_Pos) /*!< 0x00000001 */ #define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk /*!< Filter bit 0 */ -#define CAN_F9R1_FB1_Pos (1U) +#define CAN_F9R1_FB1_Pos (1U) #define CAN_F9R1_FB1_Msk (0x1U << CAN_F9R1_FB1_Pos) /*!< 0x00000002 */ #define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk /*!< Filter bit 1 */ -#define CAN_F9R1_FB2_Pos (2U) +#define CAN_F9R1_FB2_Pos (2U) #define CAN_F9R1_FB2_Msk (0x1U << CAN_F9R1_FB2_Pos) /*!< 0x00000004 */ #define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk /*!< Filter bit 2 */ -#define CAN_F9R1_FB3_Pos (3U) +#define CAN_F9R1_FB3_Pos (3U) #define CAN_F9R1_FB3_Msk (0x1U << CAN_F9R1_FB3_Pos) /*!< 0x00000008 */ #define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk /*!< Filter bit 3 */ -#define CAN_F9R1_FB4_Pos (4U) +#define CAN_F9R1_FB4_Pos (4U) #define CAN_F9R1_FB4_Msk (0x1U << CAN_F9R1_FB4_Pos) /*!< 0x00000010 */ #define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk /*!< Filter bit 4 */ -#define CAN_F9R1_FB5_Pos (5U) +#define CAN_F9R1_FB5_Pos (5U) #define CAN_F9R1_FB5_Msk (0x1U << CAN_F9R1_FB5_Pos) /*!< 0x00000020 */ #define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk /*!< Filter bit 5 */ -#define CAN_F9R1_FB6_Pos (6U) +#define CAN_F9R1_FB6_Pos (6U) #define CAN_F9R1_FB6_Msk (0x1U << CAN_F9R1_FB6_Pos) /*!< 0x00000040 */ #define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk /*!< Filter bit 6 */ -#define CAN_F9R1_FB7_Pos (7U) +#define CAN_F9R1_FB7_Pos (7U) #define CAN_F9R1_FB7_Msk (0x1U << CAN_F9R1_FB7_Pos) /*!< 0x00000080 */ #define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk /*!< Filter bit 7 */ -#define CAN_F9R1_FB8_Pos (8U) +#define CAN_F9R1_FB8_Pos (8U) #define CAN_F9R1_FB8_Msk (0x1U << CAN_F9R1_FB8_Pos) /*!< 0x00000100 */ #define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk /*!< Filter bit 8 */ -#define CAN_F9R1_FB9_Pos (9U) +#define CAN_F9R1_FB9_Pos (9U) #define CAN_F9R1_FB9_Msk (0x1U << CAN_F9R1_FB9_Pos) /*!< 0x00000200 */ #define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk /*!< Filter bit 9 */ -#define CAN_F9R1_FB10_Pos (10U) +#define CAN_F9R1_FB10_Pos (10U) #define CAN_F9R1_FB10_Msk (0x1U << CAN_F9R1_FB10_Pos) /*!< 0x00000400 */ #define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk /*!< Filter bit 10 */ -#define CAN_F9R1_FB11_Pos (11U) +#define CAN_F9R1_FB11_Pos (11U) #define CAN_F9R1_FB11_Msk (0x1U << CAN_F9R1_FB11_Pos) /*!< 0x00000800 */ #define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk /*!< Filter bit 11 */ -#define CAN_F9R1_FB12_Pos (12U) +#define CAN_F9R1_FB12_Pos (12U) #define CAN_F9R1_FB12_Msk (0x1U << CAN_F9R1_FB12_Pos) /*!< 0x00001000 */ #define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk /*!< Filter bit 12 */ -#define CAN_F9R1_FB13_Pos (13U) +#define CAN_F9R1_FB13_Pos (13U) #define CAN_F9R1_FB13_Msk (0x1U << CAN_F9R1_FB13_Pos) /*!< 0x00002000 */ #define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk /*!< Filter bit 13 */ -#define CAN_F9R1_FB14_Pos (14U) +#define CAN_F9R1_FB14_Pos (14U) #define CAN_F9R1_FB14_Msk (0x1U << CAN_F9R1_FB14_Pos) /*!< 0x00004000 */ #define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk /*!< Filter bit 14 */ -#define CAN_F9R1_FB15_Pos (15U) +#define CAN_F9R1_FB15_Pos (15U) #define CAN_F9R1_FB15_Msk (0x1U << CAN_F9R1_FB15_Pos) /*!< 0x00008000 */ #define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk /*!< Filter bit 15 */ -#define CAN_F9R1_FB16_Pos (16U) +#define CAN_F9R1_FB16_Pos (16U) #define CAN_F9R1_FB16_Msk (0x1U << CAN_F9R1_FB16_Pos) /*!< 0x00010000 */ #define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk /*!< Filter bit 16 */ -#define CAN_F9R1_FB17_Pos (17U) +#define CAN_F9R1_FB17_Pos (17U) #define CAN_F9R1_FB17_Msk (0x1U << CAN_F9R1_FB17_Pos) /*!< 0x00020000 */ #define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk /*!< Filter bit 17 */ -#define CAN_F9R1_FB18_Pos (18U) +#define CAN_F9R1_FB18_Pos (18U) #define CAN_F9R1_FB18_Msk (0x1U << CAN_F9R1_FB18_Pos) /*!< 0x00040000 */ #define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk /*!< Filter bit 18 */ -#define CAN_F9R1_FB19_Pos (19U) +#define CAN_F9R1_FB19_Pos (19U) #define CAN_F9R1_FB19_Msk (0x1U << CAN_F9R1_FB19_Pos) /*!< 0x00080000 */ #define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk /*!< Filter bit 19 */ -#define CAN_F9R1_FB20_Pos (20U) +#define CAN_F9R1_FB20_Pos (20U) #define CAN_F9R1_FB20_Msk (0x1U << CAN_F9R1_FB20_Pos) /*!< 0x00100000 */ #define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk /*!< Filter bit 20 */ -#define CAN_F9R1_FB21_Pos (21U) +#define CAN_F9R1_FB21_Pos (21U) #define CAN_F9R1_FB21_Msk (0x1U << CAN_F9R1_FB21_Pos) /*!< 0x00200000 */ #define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk /*!< Filter bit 21 */ -#define CAN_F9R1_FB22_Pos (22U) +#define CAN_F9R1_FB22_Pos (22U) #define CAN_F9R1_FB22_Msk (0x1U << CAN_F9R1_FB22_Pos) /*!< 0x00400000 */ #define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk /*!< Filter bit 22 */ -#define CAN_F9R1_FB23_Pos (23U) +#define CAN_F9R1_FB23_Pos (23U) #define CAN_F9R1_FB23_Msk (0x1U << CAN_F9R1_FB23_Pos) /*!< 0x00800000 */ #define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk /*!< Filter bit 23 */ -#define CAN_F9R1_FB24_Pos (24U) +#define CAN_F9R1_FB24_Pos (24U) #define CAN_F9R1_FB24_Msk (0x1U << CAN_F9R1_FB24_Pos) /*!< 0x01000000 */ #define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk /*!< Filter bit 24 */ -#define CAN_F9R1_FB25_Pos (25U) +#define CAN_F9R1_FB25_Pos (25U) #define CAN_F9R1_FB25_Msk (0x1U << CAN_F9R1_FB25_Pos) /*!< 0x02000000 */ #define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk /*!< Filter bit 25 */ -#define CAN_F9R1_FB26_Pos (26U) +#define CAN_F9R1_FB26_Pos (26U) #define CAN_F9R1_FB26_Msk (0x1U << CAN_F9R1_FB26_Pos) /*!< 0x04000000 */ #define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk /*!< Filter bit 26 */ -#define CAN_F9R1_FB27_Pos (27U) +#define CAN_F9R1_FB27_Pos (27U) #define CAN_F9R1_FB27_Msk (0x1U << CAN_F9R1_FB27_Pos) /*!< 0x08000000 */ #define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk /*!< Filter bit 27 */ -#define CAN_F9R1_FB28_Pos (28U) +#define CAN_F9R1_FB28_Pos (28U) #define CAN_F9R1_FB28_Msk (0x1U << CAN_F9R1_FB28_Pos) /*!< 0x10000000 */ #define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk /*!< Filter bit 28 */ -#define CAN_F9R1_FB29_Pos (29U) +#define CAN_F9R1_FB29_Pos (29U) #define CAN_F9R1_FB29_Msk (0x1U << CAN_F9R1_FB29_Pos) /*!< 0x20000000 */ #define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk /*!< Filter bit 29 */ -#define CAN_F9R1_FB30_Pos (30U) +#define CAN_F9R1_FB30_Pos (30U) #define CAN_F9R1_FB30_Msk (0x1U << CAN_F9R1_FB30_Pos) /*!< 0x40000000 */ #define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk /*!< Filter bit 30 */ -#define CAN_F9R1_FB31_Pos (31U) +#define CAN_F9R1_FB31_Pos (31U) #define CAN_F9R1_FB31_Msk (0x1U << CAN_F9R1_FB31_Pos) /*!< 0x80000000 */ #define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk /*!< Filter bit 31 */ /******************* Bit definition for CAN_F10R1 register ******************/ -#define CAN_F10R1_FB0_Pos (0U) +#define CAN_F10R1_FB0_Pos (0U) #define CAN_F10R1_FB0_Msk (0x1U << CAN_F10R1_FB0_Pos) /*!< 0x00000001 */ #define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk /*!< Filter bit 0 */ -#define CAN_F10R1_FB1_Pos (1U) +#define CAN_F10R1_FB1_Pos (1U) #define CAN_F10R1_FB1_Msk (0x1U << CAN_F10R1_FB1_Pos) /*!< 0x00000002 */ #define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk /*!< Filter bit 1 */ -#define CAN_F10R1_FB2_Pos (2U) +#define CAN_F10R1_FB2_Pos (2U) #define CAN_F10R1_FB2_Msk (0x1U << CAN_F10R1_FB2_Pos) /*!< 0x00000004 */ #define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk /*!< Filter bit 2 */ -#define CAN_F10R1_FB3_Pos (3U) +#define CAN_F10R1_FB3_Pos (3U) #define CAN_F10R1_FB3_Msk (0x1U << CAN_F10R1_FB3_Pos) /*!< 0x00000008 */ #define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk /*!< Filter bit 3 */ -#define CAN_F10R1_FB4_Pos (4U) +#define CAN_F10R1_FB4_Pos (4U) #define CAN_F10R1_FB4_Msk (0x1U << CAN_F10R1_FB4_Pos) /*!< 0x00000010 */ #define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk /*!< Filter bit 4 */ -#define CAN_F10R1_FB5_Pos (5U) +#define CAN_F10R1_FB5_Pos (5U) #define CAN_F10R1_FB5_Msk (0x1U << CAN_F10R1_FB5_Pos) /*!< 0x00000020 */ #define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk /*!< Filter bit 5 */ -#define CAN_F10R1_FB6_Pos (6U) +#define CAN_F10R1_FB6_Pos (6U) #define CAN_F10R1_FB6_Msk (0x1U << CAN_F10R1_FB6_Pos) /*!< 0x00000040 */ #define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk /*!< Filter bit 6 */ -#define CAN_F10R1_FB7_Pos (7U) +#define CAN_F10R1_FB7_Pos (7U) #define CAN_F10R1_FB7_Msk (0x1U << CAN_F10R1_FB7_Pos) /*!< 0x00000080 */ #define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk /*!< Filter bit 7 */ -#define CAN_F10R1_FB8_Pos (8U) +#define CAN_F10R1_FB8_Pos (8U) #define CAN_F10R1_FB8_Msk (0x1U << CAN_F10R1_FB8_Pos) /*!< 0x00000100 */ #define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk /*!< Filter bit 8 */ -#define CAN_F10R1_FB9_Pos (9U) +#define CAN_F10R1_FB9_Pos (9U) #define CAN_F10R1_FB9_Msk (0x1U << CAN_F10R1_FB9_Pos) /*!< 0x00000200 */ #define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk /*!< Filter bit 9 */ -#define CAN_F10R1_FB10_Pos (10U) +#define CAN_F10R1_FB10_Pos (10U) #define CAN_F10R1_FB10_Msk (0x1U << CAN_F10R1_FB10_Pos) /*!< 0x00000400 */ #define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk /*!< Filter bit 10 */ -#define CAN_F10R1_FB11_Pos (11U) +#define CAN_F10R1_FB11_Pos (11U) #define CAN_F10R1_FB11_Msk (0x1U << CAN_F10R1_FB11_Pos) /*!< 0x00000800 */ #define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk /*!< Filter bit 11 */ -#define CAN_F10R1_FB12_Pos (12U) +#define CAN_F10R1_FB12_Pos (12U) #define CAN_F10R1_FB12_Msk (0x1U << CAN_F10R1_FB12_Pos) /*!< 0x00001000 */ #define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk /*!< Filter bit 12 */ -#define CAN_F10R1_FB13_Pos (13U) +#define CAN_F10R1_FB13_Pos (13U) #define CAN_F10R1_FB13_Msk (0x1U << CAN_F10R1_FB13_Pos) /*!< 0x00002000 */ #define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk /*!< Filter bit 13 */ -#define CAN_F10R1_FB14_Pos (14U) +#define CAN_F10R1_FB14_Pos (14U) #define CAN_F10R1_FB14_Msk (0x1U << CAN_F10R1_FB14_Pos) /*!< 0x00004000 */ #define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk /*!< Filter bit 14 */ -#define CAN_F10R1_FB15_Pos (15U) +#define CAN_F10R1_FB15_Pos (15U) #define CAN_F10R1_FB15_Msk (0x1U << CAN_F10R1_FB15_Pos) /*!< 0x00008000 */ #define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk /*!< Filter bit 15 */ -#define CAN_F10R1_FB16_Pos (16U) +#define CAN_F10R1_FB16_Pos (16U) #define CAN_F10R1_FB16_Msk (0x1U << CAN_F10R1_FB16_Pos) /*!< 0x00010000 */ #define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk /*!< Filter bit 16 */ -#define CAN_F10R1_FB17_Pos (17U) +#define CAN_F10R1_FB17_Pos (17U) #define CAN_F10R1_FB17_Msk (0x1U << CAN_F10R1_FB17_Pos) /*!< 0x00020000 */ #define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk /*!< Filter bit 17 */ -#define CAN_F10R1_FB18_Pos (18U) +#define CAN_F10R1_FB18_Pos (18U) #define CAN_F10R1_FB18_Msk (0x1U << CAN_F10R1_FB18_Pos) /*!< 0x00040000 */ #define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk /*!< Filter bit 18 */ -#define CAN_F10R1_FB19_Pos (19U) +#define CAN_F10R1_FB19_Pos (19U) #define CAN_F10R1_FB19_Msk (0x1U << CAN_F10R1_FB19_Pos) /*!< 0x00080000 */ #define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk /*!< Filter bit 19 */ -#define CAN_F10R1_FB20_Pos (20U) +#define CAN_F10R1_FB20_Pos (20U) #define CAN_F10R1_FB20_Msk (0x1U << CAN_F10R1_FB20_Pos) /*!< 0x00100000 */ #define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk /*!< Filter bit 20 */ -#define CAN_F10R1_FB21_Pos (21U) +#define CAN_F10R1_FB21_Pos (21U) #define CAN_F10R1_FB21_Msk (0x1U << CAN_F10R1_FB21_Pos) /*!< 0x00200000 */ #define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk /*!< Filter bit 21 */ -#define CAN_F10R1_FB22_Pos (22U) +#define CAN_F10R1_FB22_Pos (22U) #define CAN_F10R1_FB22_Msk (0x1U << CAN_F10R1_FB22_Pos) /*!< 0x00400000 */ #define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk /*!< Filter bit 22 */ -#define CAN_F10R1_FB23_Pos (23U) +#define CAN_F10R1_FB23_Pos (23U) #define CAN_F10R1_FB23_Msk (0x1U << CAN_F10R1_FB23_Pos) /*!< 0x00800000 */ #define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk /*!< Filter bit 23 */ -#define CAN_F10R1_FB24_Pos (24U) +#define CAN_F10R1_FB24_Pos (24U) #define CAN_F10R1_FB24_Msk (0x1U << CAN_F10R1_FB24_Pos) /*!< 0x01000000 */ #define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk /*!< Filter bit 24 */ -#define CAN_F10R1_FB25_Pos (25U) +#define CAN_F10R1_FB25_Pos (25U) #define CAN_F10R1_FB25_Msk (0x1U << CAN_F10R1_FB25_Pos) /*!< 0x02000000 */ #define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk /*!< Filter bit 25 */ -#define CAN_F10R1_FB26_Pos (26U) +#define CAN_F10R1_FB26_Pos (26U) #define CAN_F10R1_FB26_Msk (0x1U << CAN_F10R1_FB26_Pos) /*!< 0x04000000 */ #define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk /*!< Filter bit 26 */ -#define CAN_F10R1_FB27_Pos (27U) +#define CAN_F10R1_FB27_Pos (27U) #define CAN_F10R1_FB27_Msk (0x1U << CAN_F10R1_FB27_Pos) /*!< 0x08000000 */ #define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk /*!< Filter bit 27 */ -#define CAN_F10R1_FB28_Pos (28U) +#define CAN_F10R1_FB28_Pos (28U) #define CAN_F10R1_FB28_Msk (0x1U << CAN_F10R1_FB28_Pos) /*!< 0x10000000 */ #define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk /*!< Filter bit 28 */ -#define CAN_F10R1_FB29_Pos (29U) +#define CAN_F10R1_FB29_Pos (29U) #define CAN_F10R1_FB29_Msk (0x1U << CAN_F10R1_FB29_Pos) /*!< 0x20000000 */ #define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk /*!< Filter bit 29 */ -#define CAN_F10R1_FB30_Pos (30U) +#define CAN_F10R1_FB30_Pos (30U) #define CAN_F10R1_FB30_Msk (0x1U << CAN_F10R1_FB30_Pos) /*!< 0x40000000 */ #define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk /*!< Filter bit 30 */ -#define CAN_F10R1_FB31_Pos (31U) +#define CAN_F10R1_FB31_Pos (31U) #define CAN_F10R1_FB31_Msk (0x1U << CAN_F10R1_FB31_Pos) /*!< 0x80000000 */ #define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk /*!< Filter bit 31 */ /******************* Bit definition for CAN_F11R1 register ******************/ -#define CAN_F11R1_FB0_Pos (0U) +#define CAN_F11R1_FB0_Pos (0U) #define CAN_F11R1_FB0_Msk (0x1U << CAN_F11R1_FB0_Pos) /*!< 0x00000001 */ #define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk /*!< Filter bit 0 */ -#define CAN_F11R1_FB1_Pos (1U) +#define CAN_F11R1_FB1_Pos (1U) #define CAN_F11R1_FB1_Msk (0x1U << CAN_F11R1_FB1_Pos) /*!< 0x00000002 */ #define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk /*!< Filter bit 1 */ -#define CAN_F11R1_FB2_Pos (2U) +#define CAN_F11R1_FB2_Pos (2U) #define CAN_F11R1_FB2_Msk (0x1U << CAN_F11R1_FB2_Pos) /*!< 0x00000004 */ #define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk /*!< Filter bit 2 */ -#define CAN_F11R1_FB3_Pos (3U) +#define CAN_F11R1_FB3_Pos (3U) #define CAN_F11R1_FB3_Msk (0x1U << CAN_F11R1_FB3_Pos) /*!< 0x00000008 */ #define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk /*!< Filter bit 3 */ -#define CAN_F11R1_FB4_Pos (4U) +#define CAN_F11R1_FB4_Pos (4U) #define CAN_F11R1_FB4_Msk (0x1U << CAN_F11R1_FB4_Pos) /*!< 0x00000010 */ #define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk /*!< Filter bit 4 */ -#define CAN_F11R1_FB5_Pos (5U) +#define CAN_F11R1_FB5_Pos (5U) #define CAN_F11R1_FB5_Msk (0x1U << CAN_F11R1_FB5_Pos) /*!< 0x00000020 */ #define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk /*!< Filter bit 5 */ -#define CAN_F11R1_FB6_Pos (6U) +#define CAN_F11R1_FB6_Pos (6U) #define CAN_F11R1_FB6_Msk (0x1U << CAN_F11R1_FB6_Pos) /*!< 0x00000040 */ #define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk /*!< Filter bit 6 */ -#define CAN_F11R1_FB7_Pos (7U) +#define CAN_F11R1_FB7_Pos (7U) #define CAN_F11R1_FB7_Msk (0x1U << CAN_F11R1_FB7_Pos) /*!< 0x00000080 */ #define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk /*!< Filter bit 7 */ -#define CAN_F11R1_FB8_Pos (8U) +#define CAN_F11R1_FB8_Pos (8U) #define CAN_F11R1_FB8_Msk (0x1U << CAN_F11R1_FB8_Pos) /*!< 0x00000100 */ #define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk /*!< Filter bit 8 */ -#define CAN_F11R1_FB9_Pos (9U) +#define CAN_F11R1_FB9_Pos (9U) #define CAN_F11R1_FB9_Msk (0x1U << CAN_F11R1_FB9_Pos) /*!< 0x00000200 */ #define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk /*!< Filter bit 9 */ -#define CAN_F11R1_FB10_Pos (10U) +#define CAN_F11R1_FB10_Pos (10U) #define CAN_F11R1_FB10_Msk (0x1U << CAN_F11R1_FB10_Pos) /*!< 0x00000400 */ #define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk /*!< Filter bit 10 */ -#define CAN_F11R1_FB11_Pos (11U) +#define CAN_F11R1_FB11_Pos (11U) #define CAN_F11R1_FB11_Msk (0x1U << CAN_F11R1_FB11_Pos) /*!< 0x00000800 */ #define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk /*!< Filter bit 11 */ -#define CAN_F11R1_FB12_Pos (12U) +#define CAN_F11R1_FB12_Pos (12U) #define CAN_F11R1_FB12_Msk (0x1U << CAN_F11R1_FB12_Pos) /*!< 0x00001000 */ #define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk /*!< Filter bit 12 */ -#define CAN_F11R1_FB13_Pos (13U) +#define CAN_F11R1_FB13_Pos (13U) #define CAN_F11R1_FB13_Msk (0x1U << CAN_F11R1_FB13_Pos) /*!< 0x00002000 */ #define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk /*!< Filter bit 13 */ -#define CAN_F11R1_FB14_Pos (14U) +#define CAN_F11R1_FB14_Pos (14U) #define CAN_F11R1_FB14_Msk (0x1U << CAN_F11R1_FB14_Pos) /*!< 0x00004000 */ #define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk /*!< Filter bit 14 */ -#define CAN_F11R1_FB15_Pos (15U) +#define CAN_F11R1_FB15_Pos (15U) #define CAN_F11R1_FB15_Msk (0x1U << CAN_F11R1_FB15_Pos) /*!< 0x00008000 */ #define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk /*!< Filter bit 15 */ -#define CAN_F11R1_FB16_Pos (16U) +#define CAN_F11R1_FB16_Pos (16U) #define CAN_F11R1_FB16_Msk (0x1U << CAN_F11R1_FB16_Pos) /*!< 0x00010000 */ #define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk /*!< Filter bit 16 */ -#define CAN_F11R1_FB17_Pos (17U) +#define CAN_F11R1_FB17_Pos (17U) #define CAN_F11R1_FB17_Msk (0x1U << CAN_F11R1_FB17_Pos) /*!< 0x00020000 */ #define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk /*!< Filter bit 17 */ -#define CAN_F11R1_FB18_Pos (18U) +#define CAN_F11R1_FB18_Pos (18U) #define CAN_F11R1_FB18_Msk (0x1U << CAN_F11R1_FB18_Pos) /*!< 0x00040000 */ #define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk /*!< Filter bit 18 */ -#define CAN_F11R1_FB19_Pos (19U) +#define CAN_F11R1_FB19_Pos (19U) #define CAN_F11R1_FB19_Msk (0x1U << CAN_F11R1_FB19_Pos) /*!< 0x00080000 */ #define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk /*!< Filter bit 19 */ -#define CAN_F11R1_FB20_Pos (20U) +#define CAN_F11R1_FB20_Pos (20U) #define CAN_F11R1_FB20_Msk (0x1U << CAN_F11R1_FB20_Pos) /*!< 0x00100000 */ #define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk /*!< Filter bit 20 */ -#define CAN_F11R1_FB21_Pos (21U) +#define CAN_F11R1_FB21_Pos (21U) #define CAN_F11R1_FB21_Msk (0x1U << CAN_F11R1_FB21_Pos) /*!< 0x00200000 */ #define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk /*!< Filter bit 21 */ -#define CAN_F11R1_FB22_Pos (22U) +#define CAN_F11R1_FB22_Pos (22U) #define CAN_F11R1_FB22_Msk (0x1U << CAN_F11R1_FB22_Pos) /*!< 0x00400000 */ #define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk /*!< Filter bit 22 */ -#define CAN_F11R1_FB23_Pos (23U) +#define CAN_F11R1_FB23_Pos (23U) #define CAN_F11R1_FB23_Msk (0x1U << CAN_F11R1_FB23_Pos) /*!< 0x00800000 */ #define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk /*!< Filter bit 23 */ -#define CAN_F11R1_FB24_Pos (24U) +#define CAN_F11R1_FB24_Pos (24U) #define CAN_F11R1_FB24_Msk (0x1U << CAN_F11R1_FB24_Pos) /*!< 0x01000000 */ #define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk /*!< Filter bit 24 */ -#define CAN_F11R1_FB25_Pos (25U) +#define CAN_F11R1_FB25_Pos (25U) #define CAN_F11R1_FB25_Msk (0x1U << CAN_F11R1_FB25_Pos) /*!< 0x02000000 */ #define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk /*!< Filter bit 25 */ -#define CAN_F11R1_FB26_Pos (26U) +#define CAN_F11R1_FB26_Pos (26U) #define CAN_F11R1_FB26_Msk (0x1U << CAN_F11R1_FB26_Pos) /*!< 0x04000000 */ #define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk /*!< Filter bit 26 */ -#define CAN_F11R1_FB27_Pos (27U) +#define CAN_F11R1_FB27_Pos (27U) #define CAN_F11R1_FB27_Msk (0x1U << CAN_F11R1_FB27_Pos) /*!< 0x08000000 */ #define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk /*!< Filter bit 27 */ -#define CAN_F11R1_FB28_Pos (28U) +#define CAN_F11R1_FB28_Pos (28U) #define CAN_F11R1_FB28_Msk (0x1U << CAN_F11R1_FB28_Pos) /*!< 0x10000000 */ #define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk /*!< Filter bit 28 */ -#define CAN_F11R1_FB29_Pos (29U) +#define CAN_F11R1_FB29_Pos (29U) #define CAN_F11R1_FB29_Msk (0x1U << CAN_F11R1_FB29_Pos) /*!< 0x20000000 */ #define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk /*!< Filter bit 29 */ -#define CAN_F11R1_FB30_Pos (30U) +#define CAN_F11R1_FB30_Pos (30U) #define CAN_F11R1_FB30_Msk (0x1U << CAN_F11R1_FB30_Pos) /*!< 0x40000000 */ #define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk /*!< Filter bit 30 */ -#define CAN_F11R1_FB31_Pos (31U) +#define CAN_F11R1_FB31_Pos (31U) #define CAN_F11R1_FB31_Msk (0x1U << CAN_F11R1_FB31_Pos) /*!< 0x80000000 */ #define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk /*!< Filter bit 31 */ /******************* Bit definition for CAN_F12R1 register ******************/ -#define CAN_F12R1_FB0_Pos (0U) +#define CAN_F12R1_FB0_Pos (0U) #define CAN_F12R1_FB0_Msk (0x1U << CAN_F12R1_FB0_Pos) /*!< 0x00000001 */ #define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk /*!< Filter bit 0 */ -#define CAN_F12R1_FB1_Pos (1U) +#define CAN_F12R1_FB1_Pos (1U) #define CAN_F12R1_FB1_Msk (0x1U << CAN_F12R1_FB1_Pos) /*!< 0x00000002 */ #define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk /*!< Filter bit 1 */ -#define CAN_F12R1_FB2_Pos (2U) +#define CAN_F12R1_FB2_Pos (2U) #define CAN_F12R1_FB2_Msk (0x1U << CAN_F12R1_FB2_Pos) /*!< 0x00000004 */ #define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk /*!< Filter bit 2 */ -#define CAN_F12R1_FB3_Pos (3U) +#define CAN_F12R1_FB3_Pos (3U) #define CAN_F12R1_FB3_Msk (0x1U << CAN_F12R1_FB3_Pos) /*!< 0x00000008 */ #define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk /*!< Filter bit 3 */ -#define CAN_F12R1_FB4_Pos (4U) +#define CAN_F12R1_FB4_Pos (4U) #define CAN_F12R1_FB4_Msk (0x1U << CAN_F12R1_FB4_Pos) /*!< 0x00000010 */ #define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk /*!< Filter bit 4 */ -#define CAN_F12R1_FB5_Pos (5U) +#define CAN_F12R1_FB5_Pos (5U) #define CAN_F12R1_FB5_Msk (0x1U << CAN_F12R1_FB5_Pos) /*!< 0x00000020 */ #define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk /*!< Filter bit 5 */ -#define CAN_F12R1_FB6_Pos (6U) +#define CAN_F12R1_FB6_Pos (6U) #define CAN_F12R1_FB6_Msk (0x1U << CAN_F12R1_FB6_Pos) /*!< 0x00000040 */ #define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk /*!< Filter bit 6 */ -#define CAN_F12R1_FB7_Pos (7U) +#define CAN_F12R1_FB7_Pos (7U) #define CAN_F12R1_FB7_Msk (0x1U << CAN_F12R1_FB7_Pos) /*!< 0x00000080 */ #define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk /*!< Filter bit 7 */ -#define CAN_F12R1_FB8_Pos (8U) +#define CAN_F12R1_FB8_Pos (8U) #define CAN_F12R1_FB8_Msk (0x1U << CAN_F12R1_FB8_Pos) /*!< 0x00000100 */ #define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk /*!< Filter bit 8 */ -#define CAN_F12R1_FB9_Pos (9U) +#define CAN_F12R1_FB9_Pos (9U) #define CAN_F12R1_FB9_Msk (0x1U << CAN_F12R1_FB9_Pos) /*!< 0x00000200 */ #define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk /*!< Filter bit 9 */ -#define CAN_F12R1_FB10_Pos (10U) +#define CAN_F12R1_FB10_Pos (10U) #define CAN_F12R1_FB10_Msk (0x1U << CAN_F12R1_FB10_Pos) /*!< 0x00000400 */ #define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk /*!< Filter bit 10 */ -#define CAN_F12R1_FB11_Pos (11U) +#define CAN_F12R1_FB11_Pos (11U) #define CAN_F12R1_FB11_Msk (0x1U << CAN_F12R1_FB11_Pos) /*!< 0x00000800 */ #define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk /*!< Filter bit 11 */ -#define CAN_F12R1_FB12_Pos (12U) +#define CAN_F12R1_FB12_Pos (12U) #define CAN_F12R1_FB12_Msk (0x1U << CAN_F12R1_FB12_Pos) /*!< 0x00001000 */ #define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk /*!< Filter bit 12 */ -#define CAN_F12R1_FB13_Pos (13U) +#define CAN_F12R1_FB13_Pos (13U) #define CAN_F12R1_FB13_Msk (0x1U << CAN_F12R1_FB13_Pos) /*!< 0x00002000 */ #define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk /*!< Filter bit 13 */ -#define CAN_F12R1_FB14_Pos (14U) +#define CAN_F12R1_FB14_Pos (14U) #define CAN_F12R1_FB14_Msk (0x1U << CAN_F12R1_FB14_Pos) /*!< 0x00004000 */ #define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk /*!< Filter bit 14 */ -#define CAN_F12R1_FB15_Pos (15U) +#define CAN_F12R1_FB15_Pos (15U) #define CAN_F12R1_FB15_Msk (0x1U << CAN_F12R1_FB15_Pos) /*!< 0x00008000 */ #define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk /*!< Filter bit 15 */ -#define CAN_F12R1_FB16_Pos (16U) +#define CAN_F12R1_FB16_Pos (16U) #define CAN_F12R1_FB16_Msk (0x1U << CAN_F12R1_FB16_Pos) /*!< 0x00010000 */ #define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk /*!< Filter bit 16 */ -#define CAN_F12R1_FB17_Pos (17U) +#define CAN_F12R1_FB17_Pos (17U) #define CAN_F12R1_FB17_Msk (0x1U << CAN_F12R1_FB17_Pos) /*!< 0x00020000 */ #define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk /*!< Filter bit 17 */ -#define CAN_F12R1_FB18_Pos (18U) +#define CAN_F12R1_FB18_Pos (18U) #define CAN_F12R1_FB18_Msk (0x1U << CAN_F12R1_FB18_Pos) /*!< 0x00040000 */ #define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk /*!< Filter bit 18 */ -#define CAN_F12R1_FB19_Pos (19U) +#define CAN_F12R1_FB19_Pos (19U) #define CAN_F12R1_FB19_Msk (0x1U << CAN_F12R1_FB19_Pos) /*!< 0x00080000 */ #define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk /*!< Filter bit 19 */ -#define CAN_F12R1_FB20_Pos (20U) +#define CAN_F12R1_FB20_Pos (20U) #define CAN_F12R1_FB20_Msk (0x1U << CAN_F12R1_FB20_Pos) /*!< 0x00100000 */ #define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk /*!< Filter bit 20 */ -#define CAN_F12R1_FB21_Pos (21U) +#define CAN_F12R1_FB21_Pos (21U) #define CAN_F12R1_FB21_Msk (0x1U << CAN_F12R1_FB21_Pos) /*!< 0x00200000 */ #define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk /*!< Filter bit 21 */ -#define CAN_F12R1_FB22_Pos (22U) +#define CAN_F12R1_FB22_Pos (22U) #define CAN_F12R1_FB22_Msk (0x1U << CAN_F12R1_FB22_Pos) /*!< 0x00400000 */ #define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk /*!< Filter bit 22 */ -#define CAN_F12R1_FB23_Pos (23U) +#define CAN_F12R1_FB23_Pos (23U) #define CAN_F12R1_FB23_Msk (0x1U << CAN_F12R1_FB23_Pos) /*!< 0x00800000 */ #define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk /*!< Filter bit 23 */ -#define CAN_F12R1_FB24_Pos (24U) +#define CAN_F12R1_FB24_Pos (24U) #define CAN_F12R1_FB24_Msk (0x1U << CAN_F12R1_FB24_Pos) /*!< 0x01000000 */ #define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk /*!< Filter bit 24 */ -#define CAN_F12R1_FB25_Pos (25U) +#define CAN_F12R1_FB25_Pos (25U) #define CAN_F12R1_FB25_Msk (0x1U << CAN_F12R1_FB25_Pos) /*!< 0x02000000 */ #define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk /*!< Filter bit 25 */ -#define CAN_F12R1_FB26_Pos (26U) +#define CAN_F12R1_FB26_Pos (26U) #define CAN_F12R1_FB26_Msk (0x1U << CAN_F12R1_FB26_Pos) /*!< 0x04000000 */ #define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk /*!< Filter bit 26 */ -#define CAN_F12R1_FB27_Pos (27U) +#define CAN_F12R1_FB27_Pos (27U) #define CAN_F12R1_FB27_Msk (0x1U << CAN_F12R1_FB27_Pos) /*!< 0x08000000 */ #define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk /*!< Filter bit 27 */ -#define CAN_F12R1_FB28_Pos (28U) +#define CAN_F12R1_FB28_Pos (28U) #define CAN_F12R1_FB28_Msk (0x1U << CAN_F12R1_FB28_Pos) /*!< 0x10000000 */ #define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk /*!< Filter bit 28 */ -#define CAN_F12R1_FB29_Pos (29U) +#define CAN_F12R1_FB29_Pos (29U) #define CAN_F12R1_FB29_Msk (0x1U << CAN_F12R1_FB29_Pos) /*!< 0x20000000 */ #define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk /*!< Filter bit 29 */ -#define CAN_F12R1_FB30_Pos (30U) +#define CAN_F12R1_FB30_Pos (30U) #define CAN_F12R1_FB30_Msk (0x1U << CAN_F12R1_FB30_Pos) /*!< 0x40000000 */ #define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk /*!< Filter bit 30 */ -#define CAN_F12R1_FB31_Pos (31U) +#define CAN_F12R1_FB31_Pos (31U) #define CAN_F12R1_FB31_Msk (0x1U << CAN_F12R1_FB31_Pos) /*!< 0x80000000 */ #define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk /*!< Filter bit 31 */ /******************* Bit definition for CAN_F13R1 register ******************/ -#define CAN_F13R1_FB0_Pos (0U) +#define CAN_F13R1_FB0_Pos (0U) #define CAN_F13R1_FB0_Msk (0x1U << CAN_F13R1_FB0_Pos) /*!< 0x00000001 */ #define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk /*!< Filter bit 0 */ -#define CAN_F13R1_FB1_Pos (1U) +#define CAN_F13R1_FB1_Pos (1U) #define CAN_F13R1_FB1_Msk (0x1U << CAN_F13R1_FB1_Pos) /*!< 0x00000002 */ #define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk /*!< Filter bit 1 */ -#define CAN_F13R1_FB2_Pos (2U) +#define CAN_F13R1_FB2_Pos (2U) #define CAN_F13R1_FB2_Msk (0x1U << CAN_F13R1_FB2_Pos) /*!< 0x00000004 */ #define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk /*!< Filter bit 2 */ -#define CAN_F13R1_FB3_Pos (3U) +#define CAN_F13R1_FB3_Pos (3U) #define CAN_F13R1_FB3_Msk (0x1U << CAN_F13R1_FB3_Pos) /*!< 0x00000008 */ #define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk /*!< Filter bit 3 */ -#define CAN_F13R1_FB4_Pos (4U) +#define CAN_F13R1_FB4_Pos (4U) #define CAN_F13R1_FB4_Msk (0x1U << CAN_F13R1_FB4_Pos) /*!< 0x00000010 */ #define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk /*!< Filter bit 4 */ -#define CAN_F13R1_FB5_Pos (5U) +#define CAN_F13R1_FB5_Pos (5U) #define CAN_F13R1_FB5_Msk (0x1U << CAN_F13R1_FB5_Pos) /*!< 0x00000020 */ #define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk /*!< Filter bit 5 */ -#define CAN_F13R1_FB6_Pos (6U) +#define CAN_F13R1_FB6_Pos (6U) #define CAN_F13R1_FB6_Msk (0x1U << CAN_F13R1_FB6_Pos) /*!< 0x00000040 */ #define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk /*!< Filter bit 6 */ -#define CAN_F13R1_FB7_Pos (7U) +#define CAN_F13R1_FB7_Pos (7U) #define CAN_F13R1_FB7_Msk (0x1U << CAN_F13R1_FB7_Pos) /*!< 0x00000080 */ #define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk /*!< Filter bit 7 */ -#define CAN_F13R1_FB8_Pos (8U) +#define CAN_F13R1_FB8_Pos (8U) #define CAN_F13R1_FB8_Msk (0x1U << CAN_F13R1_FB8_Pos) /*!< 0x00000100 */ #define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk /*!< Filter bit 8 */ -#define CAN_F13R1_FB9_Pos (9U) +#define CAN_F13R1_FB9_Pos (9U) #define CAN_F13R1_FB9_Msk (0x1U << CAN_F13R1_FB9_Pos) /*!< 0x00000200 */ #define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk /*!< Filter bit 9 */ -#define CAN_F13R1_FB10_Pos (10U) +#define CAN_F13R1_FB10_Pos (10U) #define CAN_F13R1_FB10_Msk (0x1U << CAN_F13R1_FB10_Pos) /*!< 0x00000400 */ #define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk /*!< Filter bit 10 */ -#define CAN_F13R1_FB11_Pos (11U) +#define CAN_F13R1_FB11_Pos (11U) #define CAN_F13R1_FB11_Msk (0x1U << CAN_F13R1_FB11_Pos) /*!< 0x00000800 */ #define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk /*!< Filter bit 11 */ -#define CAN_F13R1_FB12_Pos (12U) +#define CAN_F13R1_FB12_Pos (12U) #define CAN_F13R1_FB12_Msk (0x1U << CAN_F13R1_FB12_Pos) /*!< 0x00001000 */ #define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk /*!< Filter bit 12 */ -#define CAN_F13R1_FB13_Pos (13U) +#define CAN_F13R1_FB13_Pos (13U) #define CAN_F13R1_FB13_Msk (0x1U << CAN_F13R1_FB13_Pos) /*!< 0x00002000 */ #define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk /*!< Filter bit 13 */ -#define CAN_F13R1_FB14_Pos (14U) +#define CAN_F13R1_FB14_Pos (14U) #define CAN_F13R1_FB14_Msk (0x1U << CAN_F13R1_FB14_Pos) /*!< 0x00004000 */ #define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk /*!< Filter bit 14 */ -#define CAN_F13R1_FB15_Pos (15U) +#define CAN_F13R1_FB15_Pos (15U) #define CAN_F13R1_FB15_Msk (0x1U << CAN_F13R1_FB15_Pos) /*!< 0x00008000 */ #define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk /*!< Filter bit 15 */ -#define CAN_F13R1_FB16_Pos (16U) +#define CAN_F13R1_FB16_Pos (16U) #define CAN_F13R1_FB16_Msk (0x1U << CAN_F13R1_FB16_Pos) /*!< 0x00010000 */ #define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk /*!< Filter bit 16 */ -#define CAN_F13R1_FB17_Pos (17U) +#define CAN_F13R1_FB17_Pos (17U) #define CAN_F13R1_FB17_Msk (0x1U << CAN_F13R1_FB17_Pos) /*!< 0x00020000 */ #define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk /*!< Filter bit 17 */ -#define CAN_F13R1_FB18_Pos (18U) +#define CAN_F13R1_FB18_Pos (18U) #define CAN_F13R1_FB18_Msk (0x1U << CAN_F13R1_FB18_Pos) /*!< 0x00040000 */ #define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk /*!< Filter bit 18 */ -#define CAN_F13R1_FB19_Pos (19U) +#define CAN_F13R1_FB19_Pos (19U) #define CAN_F13R1_FB19_Msk (0x1U << CAN_F13R1_FB19_Pos) /*!< 0x00080000 */ #define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk /*!< Filter bit 19 */ -#define CAN_F13R1_FB20_Pos (20U) +#define CAN_F13R1_FB20_Pos (20U) #define CAN_F13R1_FB20_Msk (0x1U << CAN_F13R1_FB20_Pos) /*!< 0x00100000 */ #define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk /*!< Filter bit 20 */ -#define CAN_F13R1_FB21_Pos (21U) +#define CAN_F13R1_FB21_Pos (21U) #define CAN_F13R1_FB21_Msk (0x1U << CAN_F13R1_FB21_Pos) /*!< 0x00200000 */ #define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk /*!< Filter bit 21 */ -#define CAN_F13R1_FB22_Pos (22U) +#define CAN_F13R1_FB22_Pos (22U) #define CAN_F13R1_FB22_Msk (0x1U << CAN_F13R1_FB22_Pos) /*!< 0x00400000 */ #define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk /*!< Filter bit 22 */ -#define CAN_F13R1_FB23_Pos (23U) +#define CAN_F13R1_FB23_Pos (23U) #define CAN_F13R1_FB23_Msk (0x1U << CAN_F13R1_FB23_Pos) /*!< 0x00800000 */ #define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk /*!< Filter bit 23 */ -#define CAN_F13R1_FB24_Pos (24U) +#define CAN_F13R1_FB24_Pos (24U) #define CAN_F13R1_FB24_Msk (0x1U << CAN_F13R1_FB24_Pos) /*!< 0x01000000 */ #define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk /*!< Filter bit 24 */ -#define CAN_F13R1_FB25_Pos (25U) +#define CAN_F13R1_FB25_Pos (25U) #define CAN_F13R1_FB25_Msk (0x1U << CAN_F13R1_FB25_Pos) /*!< 0x02000000 */ #define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk /*!< Filter bit 25 */ -#define CAN_F13R1_FB26_Pos (26U) +#define CAN_F13R1_FB26_Pos (26U) #define CAN_F13R1_FB26_Msk (0x1U << CAN_F13R1_FB26_Pos) /*!< 0x04000000 */ #define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk /*!< Filter bit 26 */ -#define CAN_F13R1_FB27_Pos (27U) +#define CAN_F13R1_FB27_Pos (27U) #define CAN_F13R1_FB27_Msk (0x1U << CAN_F13R1_FB27_Pos) /*!< 0x08000000 */ #define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk /*!< Filter bit 27 */ -#define CAN_F13R1_FB28_Pos (28U) +#define CAN_F13R1_FB28_Pos (28U) #define CAN_F13R1_FB28_Msk (0x1U << CAN_F13R1_FB28_Pos) /*!< 0x10000000 */ #define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk /*!< Filter bit 28 */ -#define CAN_F13R1_FB29_Pos (29U) +#define CAN_F13R1_FB29_Pos (29U) #define CAN_F13R1_FB29_Msk (0x1U << CAN_F13R1_FB29_Pos) /*!< 0x20000000 */ #define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk /*!< Filter bit 29 */ -#define CAN_F13R1_FB30_Pos (30U) +#define CAN_F13R1_FB30_Pos (30U) #define CAN_F13R1_FB30_Msk (0x1U << CAN_F13R1_FB30_Pos) /*!< 0x40000000 */ #define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk /*!< Filter bit 30 */ -#define CAN_F13R1_FB31_Pos (31U) +#define CAN_F13R1_FB31_Pos (31U) #define CAN_F13R1_FB31_Msk (0x1U << CAN_F13R1_FB31_Pos) /*!< 0x80000000 */ #define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk /*!< Filter bit 31 */ /******************* Bit definition for CAN_F0R2 register *******************/ -#define CAN_F0R2_FB0_Pos (0U) +#define CAN_F0R2_FB0_Pos (0U) #define CAN_F0R2_FB0_Msk (0x1U << CAN_F0R2_FB0_Pos) /*!< 0x00000001 */ #define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk /*!< Filter bit 0 */ -#define CAN_F0R2_FB1_Pos (1U) +#define CAN_F0R2_FB1_Pos (1U) #define CAN_F0R2_FB1_Msk (0x1U << CAN_F0R2_FB1_Pos) /*!< 0x00000002 */ #define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk /*!< Filter bit 1 */ -#define CAN_F0R2_FB2_Pos (2U) +#define CAN_F0R2_FB2_Pos (2U) #define CAN_F0R2_FB2_Msk (0x1U << CAN_F0R2_FB2_Pos) /*!< 0x00000004 */ #define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk /*!< Filter bit 2 */ -#define CAN_F0R2_FB3_Pos (3U) +#define CAN_F0R2_FB3_Pos (3U) #define CAN_F0R2_FB3_Msk (0x1U << CAN_F0R2_FB3_Pos) /*!< 0x00000008 */ #define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk /*!< Filter bit 3 */ -#define CAN_F0R2_FB4_Pos (4U) +#define CAN_F0R2_FB4_Pos (4U) #define CAN_F0R2_FB4_Msk (0x1U << CAN_F0R2_FB4_Pos) /*!< 0x00000010 */ #define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk /*!< Filter bit 4 */ -#define CAN_F0R2_FB5_Pos (5U) +#define CAN_F0R2_FB5_Pos (5U) #define CAN_F0R2_FB5_Msk (0x1U << CAN_F0R2_FB5_Pos) /*!< 0x00000020 */ #define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk /*!< Filter bit 5 */ -#define CAN_F0R2_FB6_Pos (6U) +#define CAN_F0R2_FB6_Pos (6U) #define CAN_F0R2_FB6_Msk (0x1U << CAN_F0R2_FB6_Pos) /*!< 0x00000040 */ #define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk /*!< Filter bit 6 */ -#define CAN_F0R2_FB7_Pos (7U) +#define CAN_F0R2_FB7_Pos (7U) #define CAN_F0R2_FB7_Msk (0x1U << CAN_F0R2_FB7_Pos) /*!< 0x00000080 */ #define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk /*!< Filter bit 7 */ -#define CAN_F0R2_FB8_Pos (8U) +#define CAN_F0R2_FB8_Pos (8U) #define CAN_F0R2_FB8_Msk (0x1U << CAN_F0R2_FB8_Pos) /*!< 0x00000100 */ #define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk /*!< Filter bit 8 */ -#define CAN_F0R2_FB9_Pos (9U) +#define CAN_F0R2_FB9_Pos (9U) #define CAN_F0R2_FB9_Msk (0x1U << CAN_F0R2_FB9_Pos) /*!< 0x00000200 */ #define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk /*!< Filter bit 9 */ -#define CAN_F0R2_FB10_Pos (10U) +#define CAN_F0R2_FB10_Pos (10U) #define CAN_F0R2_FB10_Msk (0x1U << CAN_F0R2_FB10_Pos) /*!< 0x00000400 */ #define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk /*!< Filter bit 10 */ -#define CAN_F0R2_FB11_Pos (11U) +#define CAN_F0R2_FB11_Pos (11U) #define CAN_F0R2_FB11_Msk (0x1U << CAN_F0R2_FB11_Pos) /*!< 0x00000800 */ #define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk /*!< Filter bit 11 */ -#define CAN_F0R2_FB12_Pos (12U) +#define CAN_F0R2_FB12_Pos (12U) #define CAN_F0R2_FB12_Msk (0x1U << CAN_F0R2_FB12_Pos) /*!< 0x00001000 */ #define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk /*!< Filter bit 12 */ -#define CAN_F0R2_FB13_Pos (13U) +#define CAN_F0R2_FB13_Pos (13U) #define CAN_F0R2_FB13_Msk (0x1U << CAN_F0R2_FB13_Pos) /*!< 0x00002000 */ #define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk /*!< Filter bit 13 */ -#define CAN_F0R2_FB14_Pos (14U) +#define CAN_F0R2_FB14_Pos (14U) #define CAN_F0R2_FB14_Msk (0x1U << CAN_F0R2_FB14_Pos) /*!< 0x00004000 */ #define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk /*!< Filter bit 14 */ -#define CAN_F0R2_FB15_Pos (15U) +#define CAN_F0R2_FB15_Pos (15U) #define CAN_F0R2_FB15_Msk (0x1U << CAN_F0R2_FB15_Pos) /*!< 0x00008000 */ #define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk /*!< Filter bit 15 */ -#define CAN_F0R2_FB16_Pos (16U) +#define CAN_F0R2_FB16_Pos (16U) #define CAN_F0R2_FB16_Msk (0x1U << CAN_F0R2_FB16_Pos) /*!< 0x00010000 */ #define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk /*!< Filter bit 16 */ -#define CAN_F0R2_FB17_Pos (17U) +#define CAN_F0R2_FB17_Pos (17U) #define CAN_F0R2_FB17_Msk (0x1U << CAN_F0R2_FB17_Pos) /*!< 0x00020000 */ #define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk /*!< Filter bit 17 */ -#define CAN_F0R2_FB18_Pos (18U) +#define CAN_F0R2_FB18_Pos (18U) #define CAN_F0R2_FB18_Msk (0x1U << CAN_F0R2_FB18_Pos) /*!< 0x00040000 */ #define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk /*!< Filter bit 18 */ -#define CAN_F0R2_FB19_Pos (19U) +#define CAN_F0R2_FB19_Pos (19U) #define CAN_F0R2_FB19_Msk (0x1U << CAN_F0R2_FB19_Pos) /*!< 0x00080000 */ #define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk /*!< Filter bit 19 */ -#define CAN_F0R2_FB20_Pos (20U) +#define CAN_F0R2_FB20_Pos (20U) #define CAN_F0R2_FB20_Msk (0x1U << CAN_F0R2_FB20_Pos) /*!< 0x00100000 */ #define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk /*!< Filter bit 20 */ -#define CAN_F0R2_FB21_Pos (21U) +#define CAN_F0R2_FB21_Pos (21U) #define CAN_F0R2_FB21_Msk (0x1U << CAN_F0R2_FB21_Pos) /*!< 0x00200000 */ #define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk /*!< Filter bit 21 */ -#define CAN_F0R2_FB22_Pos (22U) +#define CAN_F0R2_FB22_Pos (22U) #define CAN_F0R2_FB22_Msk (0x1U << CAN_F0R2_FB22_Pos) /*!< 0x00400000 */ #define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk /*!< Filter bit 22 */ -#define CAN_F0R2_FB23_Pos (23U) +#define CAN_F0R2_FB23_Pos (23U) #define CAN_F0R2_FB23_Msk (0x1U << CAN_F0R2_FB23_Pos) /*!< 0x00800000 */ #define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk /*!< Filter bit 23 */ -#define CAN_F0R2_FB24_Pos (24U) +#define CAN_F0R2_FB24_Pos (24U) #define CAN_F0R2_FB24_Msk (0x1U << CAN_F0R2_FB24_Pos) /*!< 0x01000000 */ #define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk /*!< Filter bit 24 */ -#define CAN_F0R2_FB25_Pos (25U) +#define CAN_F0R2_FB25_Pos (25U) #define CAN_F0R2_FB25_Msk (0x1U << CAN_F0R2_FB25_Pos) /*!< 0x02000000 */ #define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk /*!< Filter bit 25 */ -#define CAN_F0R2_FB26_Pos (26U) +#define CAN_F0R2_FB26_Pos (26U) #define CAN_F0R2_FB26_Msk (0x1U << CAN_F0R2_FB26_Pos) /*!< 0x04000000 */ #define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk /*!< Filter bit 26 */ -#define CAN_F0R2_FB27_Pos (27U) +#define CAN_F0R2_FB27_Pos (27U) #define CAN_F0R2_FB27_Msk (0x1U << CAN_F0R2_FB27_Pos) /*!< 0x08000000 */ #define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk /*!< Filter bit 27 */ -#define CAN_F0R2_FB28_Pos (28U) +#define CAN_F0R2_FB28_Pos (28U) #define CAN_F0R2_FB28_Msk (0x1U << CAN_F0R2_FB28_Pos) /*!< 0x10000000 */ #define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk /*!< Filter bit 28 */ -#define CAN_F0R2_FB29_Pos (29U) +#define CAN_F0R2_FB29_Pos (29U) #define CAN_F0R2_FB29_Msk (0x1U << CAN_F0R2_FB29_Pos) /*!< 0x20000000 */ #define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk /*!< Filter bit 29 */ -#define CAN_F0R2_FB30_Pos (30U) +#define CAN_F0R2_FB30_Pos (30U) #define CAN_F0R2_FB30_Msk (0x1U << CAN_F0R2_FB30_Pos) /*!< 0x40000000 */ #define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk /*!< Filter bit 30 */ -#define CAN_F0R2_FB31_Pos (31U) +#define CAN_F0R2_FB31_Pos (31U) #define CAN_F0R2_FB31_Msk (0x1U << CAN_F0R2_FB31_Pos) /*!< 0x80000000 */ #define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk /*!< Filter bit 31 */ /******************* Bit definition for CAN_F1R2 register *******************/ -#define CAN_F1R2_FB0_Pos (0U) +#define CAN_F1R2_FB0_Pos (0U) #define CAN_F1R2_FB0_Msk (0x1U << CAN_F1R2_FB0_Pos) /*!< 0x00000001 */ #define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk /*!< Filter bit 0 */ -#define CAN_F1R2_FB1_Pos (1U) +#define CAN_F1R2_FB1_Pos (1U) #define CAN_F1R2_FB1_Msk (0x1U << CAN_F1R2_FB1_Pos) /*!< 0x00000002 */ #define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk /*!< Filter bit 1 */ -#define CAN_F1R2_FB2_Pos (2U) +#define CAN_F1R2_FB2_Pos (2U) #define CAN_F1R2_FB2_Msk (0x1U << CAN_F1R2_FB2_Pos) /*!< 0x00000004 */ #define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk /*!< Filter bit 2 */ -#define CAN_F1R2_FB3_Pos (3U) +#define CAN_F1R2_FB3_Pos (3U) #define CAN_F1R2_FB3_Msk (0x1U << CAN_F1R2_FB3_Pos) /*!< 0x00000008 */ #define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk /*!< Filter bit 3 */ -#define CAN_F1R2_FB4_Pos (4U) +#define CAN_F1R2_FB4_Pos (4U) #define CAN_F1R2_FB4_Msk (0x1U << CAN_F1R2_FB4_Pos) /*!< 0x00000010 */ #define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk /*!< Filter bit 4 */ -#define CAN_F1R2_FB5_Pos (5U) +#define CAN_F1R2_FB5_Pos (5U) #define CAN_F1R2_FB5_Msk (0x1U << CAN_F1R2_FB5_Pos) /*!< 0x00000020 */ #define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk /*!< Filter bit 5 */ -#define CAN_F1R2_FB6_Pos (6U) +#define CAN_F1R2_FB6_Pos (6U) #define CAN_F1R2_FB6_Msk (0x1U << CAN_F1R2_FB6_Pos) /*!< 0x00000040 */ #define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk /*!< Filter bit 6 */ -#define CAN_F1R2_FB7_Pos (7U) +#define CAN_F1R2_FB7_Pos (7U) #define CAN_F1R2_FB7_Msk (0x1U << CAN_F1R2_FB7_Pos) /*!< 0x00000080 */ #define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk /*!< Filter bit 7 */ -#define CAN_F1R2_FB8_Pos (8U) +#define CAN_F1R2_FB8_Pos (8U) #define CAN_F1R2_FB8_Msk (0x1U << CAN_F1R2_FB8_Pos) /*!< 0x00000100 */ #define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk /*!< Filter bit 8 */ -#define CAN_F1R2_FB9_Pos (9U) +#define CAN_F1R2_FB9_Pos (9U) #define CAN_F1R2_FB9_Msk (0x1U << CAN_F1R2_FB9_Pos) /*!< 0x00000200 */ #define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk /*!< Filter bit 9 */ -#define CAN_F1R2_FB10_Pos (10U) +#define CAN_F1R2_FB10_Pos (10U) #define CAN_F1R2_FB10_Msk (0x1U << CAN_F1R2_FB10_Pos) /*!< 0x00000400 */ #define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk /*!< Filter bit 10 */ -#define CAN_F1R2_FB11_Pos (11U) +#define CAN_F1R2_FB11_Pos (11U) #define CAN_F1R2_FB11_Msk (0x1U << CAN_F1R2_FB11_Pos) /*!< 0x00000800 */ #define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk /*!< Filter bit 11 */ -#define CAN_F1R2_FB12_Pos (12U) +#define CAN_F1R2_FB12_Pos (12U) #define CAN_F1R2_FB12_Msk (0x1U << CAN_F1R2_FB12_Pos) /*!< 0x00001000 */ #define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk /*!< Filter bit 12 */ -#define CAN_F1R2_FB13_Pos (13U) +#define CAN_F1R2_FB13_Pos (13U) #define CAN_F1R2_FB13_Msk (0x1U << CAN_F1R2_FB13_Pos) /*!< 0x00002000 */ #define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk /*!< Filter bit 13 */ -#define CAN_F1R2_FB14_Pos (14U) +#define CAN_F1R2_FB14_Pos (14U) #define CAN_F1R2_FB14_Msk (0x1U << CAN_F1R2_FB14_Pos) /*!< 0x00004000 */ #define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk /*!< Filter bit 14 */ -#define CAN_F1R2_FB15_Pos (15U) +#define CAN_F1R2_FB15_Pos (15U) #define CAN_F1R2_FB15_Msk (0x1U << CAN_F1R2_FB15_Pos) /*!< 0x00008000 */ #define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk /*!< Filter bit 15 */ -#define CAN_F1R2_FB16_Pos (16U) +#define CAN_F1R2_FB16_Pos (16U) #define CAN_F1R2_FB16_Msk (0x1U << CAN_F1R2_FB16_Pos) /*!< 0x00010000 */ #define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk /*!< Filter bit 16 */ -#define CAN_F1R2_FB17_Pos (17U) +#define CAN_F1R2_FB17_Pos (17U) #define CAN_F1R2_FB17_Msk (0x1U << CAN_F1R2_FB17_Pos) /*!< 0x00020000 */ #define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk /*!< Filter bit 17 */ -#define CAN_F1R2_FB18_Pos (18U) +#define CAN_F1R2_FB18_Pos (18U) #define CAN_F1R2_FB18_Msk (0x1U << CAN_F1R2_FB18_Pos) /*!< 0x00040000 */ #define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk /*!< Filter bit 18 */ -#define CAN_F1R2_FB19_Pos (19U) +#define CAN_F1R2_FB19_Pos (19U) #define CAN_F1R2_FB19_Msk (0x1U << CAN_F1R2_FB19_Pos) /*!< 0x00080000 */ #define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk /*!< Filter bit 19 */ -#define CAN_F1R2_FB20_Pos (20U) +#define CAN_F1R2_FB20_Pos (20U) #define CAN_F1R2_FB20_Msk (0x1U << CAN_F1R2_FB20_Pos) /*!< 0x00100000 */ #define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk /*!< Filter bit 20 */ -#define CAN_F1R2_FB21_Pos (21U) +#define CAN_F1R2_FB21_Pos (21U) #define CAN_F1R2_FB21_Msk (0x1U << CAN_F1R2_FB21_Pos) /*!< 0x00200000 */ #define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk /*!< Filter bit 21 */ -#define CAN_F1R2_FB22_Pos (22U) +#define CAN_F1R2_FB22_Pos (22U) #define CAN_F1R2_FB22_Msk (0x1U << CAN_F1R2_FB22_Pos) /*!< 0x00400000 */ #define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk /*!< Filter bit 22 */ -#define CAN_F1R2_FB23_Pos (23U) +#define CAN_F1R2_FB23_Pos (23U) #define CAN_F1R2_FB23_Msk (0x1U << CAN_F1R2_FB23_Pos) /*!< 0x00800000 */ #define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk /*!< Filter bit 23 */ -#define CAN_F1R2_FB24_Pos (24U) +#define CAN_F1R2_FB24_Pos (24U) #define CAN_F1R2_FB24_Msk (0x1U << CAN_F1R2_FB24_Pos) /*!< 0x01000000 */ #define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk /*!< Filter bit 24 */ -#define CAN_F1R2_FB25_Pos (25U) +#define CAN_F1R2_FB25_Pos (25U) #define CAN_F1R2_FB25_Msk (0x1U << CAN_F1R2_FB25_Pos) /*!< 0x02000000 */ #define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk /*!< Filter bit 25 */ -#define CAN_F1R2_FB26_Pos (26U) +#define CAN_F1R2_FB26_Pos (26U) #define CAN_F1R2_FB26_Msk (0x1U << CAN_F1R2_FB26_Pos) /*!< 0x04000000 */ #define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk /*!< Filter bit 26 */ -#define CAN_F1R2_FB27_Pos (27U) +#define CAN_F1R2_FB27_Pos (27U) #define CAN_F1R2_FB27_Msk (0x1U << CAN_F1R2_FB27_Pos) /*!< 0x08000000 */ #define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk /*!< Filter bit 27 */ -#define CAN_F1R2_FB28_Pos (28U) +#define CAN_F1R2_FB28_Pos (28U) #define CAN_F1R2_FB28_Msk (0x1U << CAN_F1R2_FB28_Pos) /*!< 0x10000000 */ #define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk /*!< Filter bit 28 */ -#define CAN_F1R2_FB29_Pos (29U) +#define CAN_F1R2_FB29_Pos (29U) #define CAN_F1R2_FB29_Msk (0x1U << CAN_F1R2_FB29_Pos) /*!< 0x20000000 */ #define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk /*!< Filter bit 29 */ -#define CAN_F1R2_FB30_Pos (30U) +#define CAN_F1R2_FB30_Pos (30U) #define CAN_F1R2_FB30_Msk (0x1U << CAN_F1R2_FB30_Pos) /*!< 0x40000000 */ #define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk /*!< Filter bit 30 */ -#define CAN_F1R2_FB31_Pos (31U) +#define CAN_F1R2_FB31_Pos (31U) #define CAN_F1R2_FB31_Msk (0x1U << CAN_F1R2_FB31_Pos) /*!< 0x80000000 */ #define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk /*!< Filter bit 31 */ /******************* Bit definition for CAN_F2R2 register *******************/ -#define CAN_F2R2_FB0_Pos (0U) +#define CAN_F2R2_FB0_Pos (0U) #define CAN_F2R2_FB0_Msk (0x1U << CAN_F2R2_FB0_Pos) /*!< 0x00000001 */ #define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk /*!< Filter bit 0 */ -#define CAN_F2R2_FB1_Pos (1U) +#define CAN_F2R2_FB1_Pos (1U) #define CAN_F2R2_FB1_Msk (0x1U << CAN_F2R2_FB1_Pos) /*!< 0x00000002 */ #define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk /*!< Filter bit 1 */ -#define CAN_F2R2_FB2_Pos (2U) +#define CAN_F2R2_FB2_Pos (2U) #define CAN_F2R2_FB2_Msk (0x1U << CAN_F2R2_FB2_Pos) /*!< 0x00000004 */ #define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk /*!< Filter bit 2 */ -#define CAN_F2R2_FB3_Pos (3U) +#define CAN_F2R2_FB3_Pos (3U) #define CAN_F2R2_FB3_Msk (0x1U << CAN_F2R2_FB3_Pos) /*!< 0x00000008 */ #define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk /*!< Filter bit 3 */ -#define CAN_F2R2_FB4_Pos (4U) +#define CAN_F2R2_FB4_Pos (4U) #define CAN_F2R2_FB4_Msk (0x1U << CAN_F2R2_FB4_Pos) /*!< 0x00000010 */ #define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk /*!< Filter bit 4 */ -#define CAN_F2R2_FB5_Pos (5U) +#define CAN_F2R2_FB5_Pos (5U) #define CAN_F2R2_FB5_Msk (0x1U << CAN_F2R2_FB5_Pos) /*!< 0x00000020 */ #define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk /*!< Filter bit 5 */ -#define CAN_F2R2_FB6_Pos (6U) +#define CAN_F2R2_FB6_Pos (6U) #define CAN_F2R2_FB6_Msk (0x1U << CAN_F2R2_FB6_Pos) /*!< 0x00000040 */ #define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk /*!< Filter bit 6 */ -#define CAN_F2R2_FB7_Pos (7U) +#define CAN_F2R2_FB7_Pos (7U) #define CAN_F2R2_FB7_Msk (0x1U << CAN_F2R2_FB7_Pos) /*!< 0x00000080 */ #define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk /*!< Filter bit 7 */ -#define CAN_F2R2_FB8_Pos (8U) +#define CAN_F2R2_FB8_Pos (8U) #define CAN_F2R2_FB8_Msk (0x1U << CAN_F2R2_FB8_Pos) /*!< 0x00000100 */ #define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk /*!< Filter bit 8 */ -#define CAN_F2R2_FB9_Pos (9U) +#define CAN_F2R2_FB9_Pos (9U) #define CAN_F2R2_FB9_Msk (0x1U << CAN_F2R2_FB9_Pos) /*!< 0x00000200 */ #define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk /*!< Filter bit 9 */ -#define CAN_F2R2_FB10_Pos (10U) +#define CAN_F2R2_FB10_Pos (10U) #define CAN_F2R2_FB10_Msk (0x1U << CAN_F2R2_FB10_Pos) /*!< 0x00000400 */ #define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk /*!< Filter bit 10 */ -#define CAN_F2R2_FB11_Pos (11U) +#define CAN_F2R2_FB11_Pos (11U) #define CAN_F2R2_FB11_Msk (0x1U << CAN_F2R2_FB11_Pos) /*!< 0x00000800 */ #define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk /*!< Filter bit 11 */ -#define CAN_F2R2_FB12_Pos (12U) +#define CAN_F2R2_FB12_Pos (12U) #define CAN_F2R2_FB12_Msk (0x1U << CAN_F2R2_FB12_Pos) /*!< 0x00001000 */ #define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk /*!< Filter bit 12 */ -#define CAN_F2R2_FB13_Pos (13U) +#define CAN_F2R2_FB13_Pos (13U) #define CAN_F2R2_FB13_Msk (0x1U << CAN_F2R2_FB13_Pos) /*!< 0x00002000 */ #define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk /*!< Filter bit 13 */ -#define CAN_F2R2_FB14_Pos (14U) +#define CAN_F2R2_FB14_Pos (14U) #define CAN_F2R2_FB14_Msk (0x1U << CAN_F2R2_FB14_Pos) /*!< 0x00004000 */ #define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk /*!< Filter bit 14 */ -#define CAN_F2R2_FB15_Pos (15U) +#define CAN_F2R2_FB15_Pos (15U) #define CAN_F2R2_FB15_Msk (0x1U << CAN_F2R2_FB15_Pos) /*!< 0x00008000 */ #define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk /*!< Filter bit 15 */ -#define CAN_F2R2_FB16_Pos (16U) +#define CAN_F2R2_FB16_Pos (16U) #define CAN_F2R2_FB16_Msk (0x1U << CAN_F2R2_FB16_Pos) /*!< 0x00010000 */ #define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk /*!< Filter bit 16 */ -#define CAN_F2R2_FB17_Pos (17U) +#define CAN_F2R2_FB17_Pos (17U) #define CAN_F2R2_FB17_Msk (0x1U << CAN_F2R2_FB17_Pos) /*!< 0x00020000 */ #define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk /*!< Filter bit 17 */ -#define CAN_F2R2_FB18_Pos (18U) +#define CAN_F2R2_FB18_Pos (18U) #define CAN_F2R2_FB18_Msk (0x1U << CAN_F2R2_FB18_Pos) /*!< 0x00040000 */ #define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk /*!< Filter bit 18 */ -#define CAN_F2R2_FB19_Pos (19U) +#define CAN_F2R2_FB19_Pos (19U) #define CAN_F2R2_FB19_Msk (0x1U << CAN_F2R2_FB19_Pos) /*!< 0x00080000 */ #define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk /*!< Filter bit 19 */ -#define CAN_F2R2_FB20_Pos (20U) +#define CAN_F2R2_FB20_Pos (20U) #define CAN_F2R2_FB20_Msk (0x1U << CAN_F2R2_FB20_Pos) /*!< 0x00100000 */ #define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk /*!< Filter bit 20 */ -#define CAN_F2R2_FB21_Pos (21U) +#define CAN_F2R2_FB21_Pos (21U) #define CAN_F2R2_FB21_Msk (0x1U << CAN_F2R2_FB21_Pos) /*!< 0x00200000 */ #define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk /*!< Filter bit 21 */ -#define CAN_F2R2_FB22_Pos (22U) +#define CAN_F2R2_FB22_Pos (22U) #define CAN_F2R2_FB22_Msk (0x1U << CAN_F2R2_FB22_Pos) /*!< 0x00400000 */ #define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk /*!< Filter bit 22 */ -#define CAN_F2R2_FB23_Pos (23U) +#define CAN_F2R2_FB23_Pos (23U) #define CAN_F2R2_FB23_Msk (0x1U << CAN_F2R2_FB23_Pos) /*!< 0x00800000 */ #define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk /*!< Filter bit 23 */ -#define CAN_F2R2_FB24_Pos (24U) +#define CAN_F2R2_FB24_Pos (24U) #define CAN_F2R2_FB24_Msk (0x1U << CAN_F2R2_FB24_Pos) /*!< 0x01000000 */ #define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk /*!< Filter bit 24 */ -#define CAN_F2R2_FB25_Pos (25U) +#define CAN_F2R2_FB25_Pos (25U) #define CAN_F2R2_FB25_Msk (0x1U << CAN_F2R2_FB25_Pos) /*!< 0x02000000 */ #define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk /*!< Filter bit 25 */ -#define CAN_F2R2_FB26_Pos (26U) +#define CAN_F2R2_FB26_Pos (26U) #define CAN_F2R2_FB26_Msk (0x1U << CAN_F2R2_FB26_Pos) /*!< 0x04000000 */ #define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk /*!< Filter bit 26 */ -#define CAN_F2R2_FB27_Pos (27U) +#define CAN_F2R2_FB27_Pos (27U) #define CAN_F2R2_FB27_Msk (0x1U << CAN_F2R2_FB27_Pos) /*!< 0x08000000 */ #define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk /*!< Filter bit 27 */ -#define CAN_F2R2_FB28_Pos (28U) +#define CAN_F2R2_FB28_Pos (28U) #define CAN_F2R2_FB28_Msk (0x1U << CAN_F2R2_FB28_Pos) /*!< 0x10000000 */ #define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk /*!< Filter bit 28 */ -#define CAN_F2R2_FB29_Pos (29U) +#define CAN_F2R2_FB29_Pos (29U) #define CAN_F2R2_FB29_Msk (0x1U << CAN_F2R2_FB29_Pos) /*!< 0x20000000 */ #define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk /*!< Filter bit 29 */ -#define CAN_F2R2_FB30_Pos (30U) +#define CAN_F2R2_FB30_Pos (30U) #define CAN_F2R2_FB30_Msk (0x1U << CAN_F2R2_FB30_Pos) /*!< 0x40000000 */ #define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk /*!< Filter bit 30 */ -#define CAN_F2R2_FB31_Pos (31U) +#define CAN_F2R2_FB31_Pos (31U) #define CAN_F2R2_FB31_Msk (0x1U << CAN_F2R2_FB31_Pos) /*!< 0x80000000 */ #define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk /*!< Filter bit 31 */ /******************* Bit definition for CAN_F3R2 register *******************/ -#define CAN_F3R2_FB0_Pos (0U) +#define CAN_F3R2_FB0_Pos (0U) #define CAN_F3R2_FB0_Msk (0x1U << CAN_F3R2_FB0_Pos) /*!< 0x00000001 */ #define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk /*!< Filter bit 0 */ -#define CAN_F3R2_FB1_Pos (1U) +#define CAN_F3R2_FB1_Pos (1U) #define CAN_F3R2_FB1_Msk (0x1U << CAN_F3R2_FB1_Pos) /*!< 0x00000002 */ #define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk /*!< Filter bit 1 */ -#define CAN_F3R2_FB2_Pos (2U) +#define CAN_F3R2_FB2_Pos (2U) #define CAN_F3R2_FB2_Msk (0x1U << CAN_F3R2_FB2_Pos) /*!< 0x00000004 */ #define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk /*!< Filter bit 2 */ -#define CAN_F3R2_FB3_Pos (3U) +#define CAN_F3R2_FB3_Pos (3U) #define CAN_F3R2_FB3_Msk (0x1U << CAN_F3R2_FB3_Pos) /*!< 0x00000008 */ #define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk /*!< Filter bit 3 */ -#define CAN_F3R2_FB4_Pos (4U) +#define CAN_F3R2_FB4_Pos (4U) #define CAN_F3R2_FB4_Msk (0x1U << CAN_F3R2_FB4_Pos) /*!< 0x00000010 */ #define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk /*!< Filter bit 4 */ -#define CAN_F3R2_FB5_Pos (5U) +#define CAN_F3R2_FB5_Pos (5U) #define CAN_F3R2_FB5_Msk (0x1U << CAN_F3R2_FB5_Pos) /*!< 0x00000020 */ #define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk /*!< Filter bit 5 */ -#define CAN_F3R2_FB6_Pos (6U) +#define CAN_F3R2_FB6_Pos (6U) #define CAN_F3R2_FB6_Msk (0x1U << CAN_F3R2_FB6_Pos) /*!< 0x00000040 */ #define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk /*!< Filter bit 6 */ -#define CAN_F3R2_FB7_Pos (7U) +#define CAN_F3R2_FB7_Pos (7U) #define CAN_F3R2_FB7_Msk (0x1U << CAN_F3R2_FB7_Pos) /*!< 0x00000080 */ #define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk /*!< Filter bit 7 */ -#define CAN_F3R2_FB8_Pos (8U) +#define CAN_F3R2_FB8_Pos (8U) #define CAN_F3R2_FB8_Msk (0x1U << CAN_F3R2_FB8_Pos) /*!< 0x00000100 */ #define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk /*!< Filter bit 8 */ -#define CAN_F3R2_FB9_Pos (9U) +#define CAN_F3R2_FB9_Pos (9U) #define CAN_F3R2_FB9_Msk (0x1U << CAN_F3R2_FB9_Pos) /*!< 0x00000200 */ #define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk /*!< Filter bit 9 */ -#define CAN_F3R2_FB10_Pos (10U) +#define CAN_F3R2_FB10_Pos (10U) #define CAN_F3R2_FB10_Msk (0x1U << CAN_F3R2_FB10_Pos) /*!< 0x00000400 */ #define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk /*!< Filter bit 10 */ -#define CAN_F3R2_FB11_Pos (11U) +#define CAN_F3R2_FB11_Pos (11U) #define CAN_F3R2_FB11_Msk (0x1U << CAN_F3R2_FB11_Pos) /*!< 0x00000800 */ #define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk /*!< Filter bit 11 */ -#define CAN_F3R2_FB12_Pos (12U) +#define CAN_F3R2_FB12_Pos (12U) #define CAN_F3R2_FB12_Msk (0x1U << CAN_F3R2_FB12_Pos) /*!< 0x00001000 */ #define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk /*!< Filter bit 12 */ -#define CAN_F3R2_FB13_Pos (13U) +#define CAN_F3R2_FB13_Pos (13U) #define CAN_F3R2_FB13_Msk (0x1U << CAN_F3R2_FB13_Pos) /*!< 0x00002000 */ #define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk /*!< Filter bit 13 */ -#define CAN_F3R2_FB14_Pos (14U) +#define CAN_F3R2_FB14_Pos (14U) #define CAN_F3R2_FB14_Msk (0x1U << CAN_F3R2_FB14_Pos) /*!< 0x00004000 */ #define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk /*!< Filter bit 14 */ -#define CAN_F3R2_FB15_Pos (15U) +#define CAN_F3R2_FB15_Pos (15U) #define CAN_F3R2_FB15_Msk (0x1U << CAN_F3R2_FB15_Pos) /*!< 0x00008000 */ #define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk /*!< Filter bit 15 */ -#define CAN_F3R2_FB16_Pos (16U) +#define CAN_F3R2_FB16_Pos (16U) #define CAN_F3R2_FB16_Msk (0x1U << CAN_F3R2_FB16_Pos) /*!< 0x00010000 */ #define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk /*!< Filter bit 16 */ -#define CAN_F3R2_FB17_Pos (17U) +#define CAN_F3R2_FB17_Pos (17U) #define CAN_F3R2_FB17_Msk (0x1U << CAN_F3R2_FB17_Pos) /*!< 0x00020000 */ #define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk /*!< Filter bit 17 */ -#define CAN_F3R2_FB18_Pos (18U) +#define CAN_F3R2_FB18_Pos (18U) #define CAN_F3R2_FB18_Msk (0x1U << CAN_F3R2_FB18_Pos) /*!< 0x00040000 */ #define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk /*!< Filter bit 18 */ -#define CAN_F3R2_FB19_Pos (19U) +#define CAN_F3R2_FB19_Pos (19U) #define CAN_F3R2_FB19_Msk (0x1U << CAN_F3R2_FB19_Pos) /*!< 0x00080000 */ #define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk /*!< Filter bit 19 */ -#define CAN_F3R2_FB20_Pos (20U) +#define CAN_F3R2_FB20_Pos (20U) #define CAN_F3R2_FB20_Msk (0x1U << CAN_F3R2_FB20_Pos) /*!< 0x00100000 */ #define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk /*!< Filter bit 20 */ -#define CAN_F3R2_FB21_Pos (21U) +#define CAN_F3R2_FB21_Pos (21U) #define CAN_F3R2_FB21_Msk (0x1U << CAN_F3R2_FB21_Pos) /*!< 0x00200000 */ #define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk /*!< Filter bit 21 */ -#define CAN_F3R2_FB22_Pos (22U) +#define CAN_F3R2_FB22_Pos (22U) #define CAN_F3R2_FB22_Msk (0x1U << CAN_F3R2_FB22_Pos) /*!< 0x00400000 */ #define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk /*!< Filter bit 22 */ -#define CAN_F3R2_FB23_Pos (23U) +#define CAN_F3R2_FB23_Pos (23U) #define CAN_F3R2_FB23_Msk (0x1U << CAN_F3R2_FB23_Pos) /*!< 0x00800000 */ #define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk /*!< Filter bit 23 */ -#define CAN_F3R2_FB24_Pos (24U) +#define CAN_F3R2_FB24_Pos (24U) #define CAN_F3R2_FB24_Msk (0x1U << CAN_F3R2_FB24_Pos) /*!< 0x01000000 */ #define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk /*!< Filter bit 24 */ -#define CAN_F3R2_FB25_Pos (25U) +#define CAN_F3R2_FB25_Pos (25U) #define CAN_F3R2_FB25_Msk (0x1U << CAN_F3R2_FB25_Pos) /*!< 0x02000000 */ #define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk /*!< Filter bit 25 */ -#define CAN_F3R2_FB26_Pos (26U) +#define CAN_F3R2_FB26_Pos (26U) #define CAN_F3R2_FB26_Msk (0x1U << CAN_F3R2_FB26_Pos) /*!< 0x04000000 */ #define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk /*!< Filter bit 26 */ -#define CAN_F3R2_FB27_Pos (27U) +#define CAN_F3R2_FB27_Pos (27U) #define CAN_F3R2_FB27_Msk (0x1U << CAN_F3R2_FB27_Pos) /*!< 0x08000000 */ #define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk /*!< Filter bit 27 */ -#define CAN_F3R2_FB28_Pos (28U) +#define CAN_F3R2_FB28_Pos (28U) #define CAN_F3R2_FB28_Msk (0x1U << CAN_F3R2_FB28_Pos) /*!< 0x10000000 */ #define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk /*!< Filter bit 28 */ -#define CAN_F3R2_FB29_Pos (29U) +#define CAN_F3R2_FB29_Pos (29U) #define CAN_F3R2_FB29_Msk (0x1U << CAN_F3R2_FB29_Pos) /*!< 0x20000000 */ #define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk /*!< Filter bit 29 */ -#define CAN_F3R2_FB30_Pos (30U) +#define CAN_F3R2_FB30_Pos (30U) #define CAN_F3R2_FB30_Msk (0x1U << CAN_F3R2_FB30_Pos) /*!< 0x40000000 */ #define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk /*!< Filter bit 30 */ -#define CAN_F3R2_FB31_Pos (31U) +#define CAN_F3R2_FB31_Pos (31U) #define CAN_F3R2_FB31_Msk (0x1U << CAN_F3R2_FB31_Pos) /*!< 0x80000000 */ #define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk /*!< Filter bit 31 */ /******************* Bit definition for CAN_F4R2 register *******************/ -#define CAN_F4R2_FB0_Pos (0U) +#define CAN_F4R2_FB0_Pos (0U) #define CAN_F4R2_FB0_Msk (0x1U << CAN_F4R2_FB0_Pos) /*!< 0x00000001 */ #define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk /*!< Filter bit 0 */ -#define CAN_F4R2_FB1_Pos (1U) +#define CAN_F4R2_FB1_Pos (1U) #define CAN_F4R2_FB1_Msk (0x1U << CAN_F4R2_FB1_Pos) /*!< 0x00000002 */ #define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk /*!< Filter bit 1 */ -#define CAN_F4R2_FB2_Pos (2U) +#define CAN_F4R2_FB2_Pos (2U) #define CAN_F4R2_FB2_Msk (0x1U << CAN_F4R2_FB2_Pos) /*!< 0x00000004 */ #define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk /*!< Filter bit 2 */ -#define CAN_F4R2_FB3_Pos (3U) +#define CAN_F4R2_FB3_Pos (3U) #define CAN_F4R2_FB3_Msk (0x1U << CAN_F4R2_FB3_Pos) /*!< 0x00000008 */ #define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk /*!< Filter bit 3 */ -#define CAN_F4R2_FB4_Pos (4U) +#define CAN_F4R2_FB4_Pos (4U) #define CAN_F4R2_FB4_Msk (0x1U << CAN_F4R2_FB4_Pos) /*!< 0x00000010 */ #define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk /*!< Filter bit 4 */ -#define CAN_F4R2_FB5_Pos (5U) +#define CAN_F4R2_FB5_Pos (5U) #define CAN_F4R2_FB5_Msk (0x1U << CAN_F4R2_FB5_Pos) /*!< 0x00000020 */ #define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk /*!< Filter bit 5 */ -#define CAN_F4R2_FB6_Pos (6U) +#define CAN_F4R2_FB6_Pos (6U) #define CAN_F4R2_FB6_Msk (0x1U << CAN_F4R2_FB6_Pos) /*!< 0x00000040 */ #define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk /*!< Filter bit 6 */ -#define CAN_F4R2_FB7_Pos (7U) +#define CAN_F4R2_FB7_Pos (7U) #define CAN_F4R2_FB7_Msk (0x1U << CAN_F4R2_FB7_Pos) /*!< 0x00000080 */ #define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk /*!< Filter bit 7 */ -#define CAN_F4R2_FB8_Pos (8U) +#define CAN_F4R2_FB8_Pos (8U) #define CAN_F4R2_FB8_Msk (0x1U << CAN_F4R2_FB8_Pos) /*!< 0x00000100 */ #define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk /*!< Filter bit 8 */ -#define CAN_F4R2_FB9_Pos (9U) +#define CAN_F4R2_FB9_Pos (9U) #define CAN_F4R2_FB9_Msk (0x1U << CAN_F4R2_FB9_Pos) /*!< 0x00000200 */ #define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk /*!< Filter bit 9 */ -#define CAN_F4R2_FB10_Pos (10U) +#define CAN_F4R2_FB10_Pos (10U) #define CAN_F4R2_FB10_Msk (0x1U << CAN_F4R2_FB10_Pos) /*!< 0x00000400 */ #define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk /*!< Filter bit 10 */ -#define CAN_F4R2_FB11_Pos (11U) +#define CAN_F4R2_FB11_Pos (11U) #define CAN_F4R2_FB11_Msk (0x1U << CAN_F4R2_FB11_Pos) /*!< 0x00000800 */ #define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk /*!< Filter bit 11 */ -#define CAN_F4R2_FB12_Pos (12U) +#define CAN_F4R2_FB12_Pos (12U) #define CAN_F4R2_FB12_Msk (0x1U << CAN_F4R2_FB12_Pos) /*!< 0x00001000 */ #define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk /*!< Filter bit 12 */ -#define CAN_F4R2_FB13_Pos (13U) +#define CAN_F4R2_FB13_Pos (13U) #define CAN_F4R2_FB13_Msk (0x1U << CAN_F4R2_FB13_Pos) /*!< 0x00002000 */ #define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk /*!< Filter bit 13 */ -#define CAN_F4R2_FB14_Pos (14U) +#define CAN_F4R2_FB14_Pos (14U) #define CAN_F4R2_FB14_Msk (0x1U << CAN_F4R2_FB14_Pos) /*!< 0x00004000 */ #define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk /*!< Filter bit 14 */ -#define CAN_F4R2_FB15_Pos (15U) +#define CAN_F4R2_FB15_Pos (15U) #define CAN_F4R2_FB15_Msk (0x1U << CAN_F4R2_FB15_Pos) /*!< 0x00008000 */ #define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk /*!< Filter bit 15 */ -#define CAN_F4R2_FB16_Pos (16U) +#define CAN_F4R2_FB16_Pos (16U) #define CAN_F4R2_FB16_Msk (0x1U << CAN_F4R2_FB16_Pos) /*!< 0x00010000 */ #define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk /*!< Filter bit 16 */ -#define CAN_F4R2_FB17_Pos (17U) +#define CAN_F4R2_FB17_Pos (17U) #define CAN_F4R2_FB17_Msk (0x1U << CAN_F4R2_FB17_Pos) /*!< 0x00020000 */ #define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk /*!< Filter bit 17 */ -#define CAN_F4R2_FB18_Pos (18U) +#define CAN_F4R2_FB18_Pos (18U) #define CAN_F4R2_FB18_Msk (0x1U << CAN_F4R2_FB18_Pos) /*!< 0x00040000 */ #define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk /*!< Filter bit 18 */ -#define CAN_F4R2_FB19_Pos (19U) +#define CAN_F4R2_FB19_Pos (19U) #define CAN_F4R2_FB19_Msk (0x1U << CAN_F4R2_FB19_Pos) /*!< 0x00080000 */ #define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk /*!< Filter bit 19 */ -#define CAN_F4R2_FB20_Pos (20U) +#define CAN_F4R2_FB20_Pos (20U) #define CAN_F4R2_FB20_Msk (0x1U << CAN_F4R2_FB20_Pos) /*!< 0x00100000 */ #define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk /*!< Filter bit 20 */ -#define CAN_F4R2_FB21_Pos (21U) +#define CAN_F4R2_FB21_Pos (21U) #define CAN_F4R2_FB21_Msk (0x1U << CAN_F4R2_FB21_Pos) /*!< 0x00200000 */ #define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk /*!< Filter bit 21 */ -#define CAN_F4R2_FB22_Pos (22U) +#define CAN_F4R2_FB22_Pos (22U) #define CAN_F4R2_FB22_Msk (0x1U << CAN_F4R2_FB22_Pos) /*!< 0x00400000 */ #define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk /*!< Filter bit 22 */ -#define CAN_F4R2_FB23_Pos (23U) +#define CAN_F4R2_FB23_Pos (23U) #define CAN_F4R2_FB23_Msk (0x1U << CAN_F4R2_FB23_Pos) /*!< 0x00800000 */ #define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk /*!< Filter bit 23 */ -#define CAN_F4R2_FB24_Pos (24U) +#define CAN_F4R2_FB24_Pos (24U) #define CAN_F4R2_FB24_Msk (0x1U << CAN_F4R2_FB24_Pos) /*!< 0x01000000 */ #define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk /*!< Filter bit 24 */ -#define CAN_F4R2_FB25_Pos (25U) +#define CAN_F4R2_FB25_Pos (25U) #define CAN_F4R2_FB25_Msk (0x1U << CAN_F4R2_FB25_Pos) /*!< 0x02000000 */ #define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk /*!< Filter bit 25 */ -#define CAN_F4R2_FB26_Pos (26U) +#define CAN_F4R2_FB26_Pos (26U) #define CAN_F4R2_FB26_Msk (0x1U << CAN_F4R2_FB26_Pos) /*!< 0x04000000 */ #define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk /*!< Filter bit 26 */ -#define CAN_F4R2_FB27_Pos (27U) +#define CAN_F4R2_FB27_Pos (27U) #define CAN_F4R2_FB27_Msk (0x1U << CAN_F4R2_FB27_Pos) /*!< 0x08000000 */ #define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk /*!< Filter bit 27 */ -#define CAN_F4R2_FB28_Pos (28U) +#define CAN_F4R2_FB28_Pos (28U) #define CAN_F4R2_FB28_Msk (0x1U << CAN_F4R2_FB28_Pos) /*!< 0x10000000 */ #define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk /*!< Filter bit 28 */ -#define CAN_F4R2_FB29_Pos (29U) +#define CAN_F4R2_FB29_Pos (29U) #define CAN_F4R2_FB29_Msk (0x1U << CAN_F4R2_FB29_Pos) /*!< 0x20000000 */ #define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk /*!< Filter bit 29 */ -#define CAN_F4R2_FB30_Pos (30U) +#define CAN_F4R2_FB30_Pos (30U) #define CAN_F4R2_FB30_Msk (0x1U << CAN_F4R2_FB30_Pos) /*!< 0x40000000 */ #define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk /*!< Filter bit 30 */ -#define CAN_F4R2_FB31_Pos (31U) +#define CAN_F4R2_FB31_Pos (31U) #define CAN_F4R2_FB31_Msk (0x1U << CAN_F4R2_FB31_Pos) /*!< 0x80000000 */ #define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk /*!< Filter bit 31 */ /******************* Bit definition for CAN_F5R2 register *******************/ -#define CAN_F5R2_FB0_Pos (0U) +#define CAN_F5R2_FB0_Pos (0U) #define CAN_F5R2_FB0_Msk (0x1U << CAN_F5R2_FB0_Pos) /*!< 0x00000001 */ #define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk /*!< Filter bit 0 */ -#define CAN_F5R2_FB1_Pos (1U) +#define CAN_F5R2_FB1_Pos (1U) #define CAN_F5R2_FB1_Msk (0x1U << CAN_F5R2_FB1_Pos) /*!< 0x00000002 */ #define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk /*!< Filter bit 1 */ -#define CAN_F5R2_FB2_Pos (2U) +#define CAN_F5R2_FB2_Pos (2U) #define CAN_F5R2_FB2_Msk (0x1U << CAN_F5R2_FB2_Pos) /*!< 0x00000004 */ #define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk /*!< Filter bit 2 */ -#define CAN_F5R2_FB3_Pos (3U) +#define CAN_F5R2_FB3_Pos (3U) #define CAN_F5R2_FB3_Msk (0x1U << CAN_F5R2_FB3_Pos) /*!< 0x00000008 */ #define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk /*!< Filter bit 3 */ -#define CAN_F5R2_FB4_Pos (4U) +#define CAN_F5R2_FB4_Pos (4U) #define CAN_F5R2_FB4_Msk (0x1U << CAN_F5R2_FB4_Pos) /*!< 0x00000010 */ #define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk /*!< Filter bit 4 */ -#define CAN_F5R2_FB5_Pos (5U) +#define CAN_F5R2_FB5_Pos (5U) #define CAN_F5R2_FB5_Msk (0x1U << CAN_F5R2_FB5_Pos) /*!< 0x00000020 */ #define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk /*!< Filter bit 5 */ -#define CAN_F5R2_FB6_Pos (6U) +#define CAN_F5R2_FB6_Pos (6U) #define CAN_F5R2_FB6_Msk (0x1U << CAN_F5R2_FB6_Pos) /*!< 0x00000040 */ #define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk /*!< Filter bit 6 */ -#define CAN_F5R2_FB7_Pos (7U) +#define CAN_F5R2_FB7_Pos (7U) #define CAN_F5R2_FB7_Msk (0x1U << CAN_F5R2_FB7_Pos) /*!< 0x00000080 */ #define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk /*!< Filter bit 7 */ -#define CAN_F5R2_FB8_Pos (8U) +#define CAN_F5R2_FB8_Pos (8U) #define CAN_F5R2_FB8_Msk (0x1U << CAN_F5R2_FB8_Pos) /*!< 0x00000100 */ #define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk /*!< Filter bit 8 */ -#define CAN_F5R2_FB9_Pos (9U) +#define CAN_F5R2_FB9_Pos (9U) #define CAN_F5R2_FB9_Msk (0x1U << CAN_F5R2_FB9_Pos) /*!< 0x00000200 */ #define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk /*!< Filter bit 9 */ -#define CAN_F5R2_FB10_Pos (10U) +#define CAN_F5R2_FB10_Pos (10U) #define CAN_F5R2_FB10_Msk (0x1U << CAN_F5R2_FB10_Pos) /*!< 0x00000400 */ #define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk /*!< Filter bit 10 */ -#define CAN_F5R2_FB11_Pos (11U) +#define CAN_F5R2_FB11_Pos (11U) #define CAN_F5R2_FB11_Msk (0x1U << CAN_F5R2_FB11_Pos) /*!< 0x00000800 */ #define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk /*!< Filter bit 11 */ -#define CAN_F5R2_FB12_Pos (12U) +#define CAN_F5R2_FB12_Pos (12U) #define CAN_F5R2_FB12_Msk (0x1U << CAN_F5R2_FB12_Pos) /*!< 0x00001000 */ #define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk /*!< Filter bit 12 */ -#define CAN_F5R2_FB13_Pos (13U) +#define CAN_F5R2_FB13_Pos (13U) #define CAN_F5R2_FB13_Msk (0x1U << CAN_F5R2_FB13_Pos) /*!< 0x00002000 */ #define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk /*!< Filter bit 13 */ -#define CAN_F5R2_FB14_Pos (14U) +#define CAN_F5R2_FB14_Pos (14U) #define CAN_F5R2_FB14_Msk (0x1U << CAN_F5R2_FB14_Pos) /*!< 0x00004000 */ #define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk /*!< Filter bit 14 */ -#define CAN_F5R2_FB15_Pos (15U) +#define CAN_F5R2_FB15_Pos (15U) #define CAN_F5R2_FB15_Msk (0x1U << CAN_F5R2_FB15_Pos) /*!< 0x00008000 */ #define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk /*!< Filter bit 15 */ -#define CAN_F5R2_FB16_Pos (16U) +#define CAN_F5R2_FB16_Pos (16U) #define CAN_F5R2_FB16_Msk (0x1U << CAN_F5R2_FB16_Pos) /*!< 0x00010000 */ #define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk /*!< Filter bit 16 */ -#define CAN_F5R2_FB17_Pos (17U) +#define CAN_F5R2_FB17_Pos (17U) #define CAN_F5R2_FB17_Msk (0x1U << CAN_F5R2_FB17_Pos) /*!< 0x00020000 */ #define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk /*!< Filter bit 17 */ -#define CAN_F5R2_FB18_Pos (18U) +#define CAN_F5R2_FB18_Pos (18U) #define CAN_F5R2_FB18_Msk (0x1U << CAN_F5R2_FB18_Pos) /*!< 0x00040000 */ #define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk /*!< Filter bit 18 */ -#define CAN_F5R2_FB19_Pos (19U) +#define CAN_F5R2_FB19_Pos (19U) #define CAN_F5R2_FB19_Msk (0x1U << CAN_F5R2_FB19_Pos) /*!< 0x00080000 */ #define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk /*!< Filter bit 19 */ -#define CAN_F5R2_FB20_Pos (20U) +#define CAN_F5R2_FB20_Pos (20U) #define CAN_F5R2_FB20_Msk (0x1U << CAN_F5R2_FB20_Pos) /*!< 0x00100000 */ #define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk /*!< Filter bit 20 */ -#define CAN_F5R2_FB21_Pos (21U) +#define CAN_F5R2_FB21_Pos (21U) #define CAN_F5R2_FB21_Msk (0x1U << CAN_F5R2_FB21_Pos) /*!< 0x00200000 */ #define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk /*!< Filter bit 21 */ -#define CAN_F5R2_FB22_Pos (22U) +#define CAN_F5R2_FB22_Pos (22U) #define CAN_F5R2_FB22_Msk (0x1U << CAN_F5R2_FB22_Pos) /*!< 0x00400000 */ #define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk /*!< Filter bit 22 */ -#define CAN_F5R2_FB23_Pos (23U) +#define CAN_F5R2_FB23_Pos (23U) #define CAN_F5R2_FB23_Msk (0x1U << CAN_F5R2_FB23_Pos) /*!< 0x00800000 */ #define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk /*!< Filter bit 23 */ -#define CAN_F5R2_FB24_Pos (24U) +#define CAN_F5R2_FB24_Pos (24U) #define CAN_F5R2_FB24_Msk (0x1U << CAN_F5R2_FB24_Pos) /*!< 0x01000000 */ #define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk /*!< Filter bit 24 */ -#define CAN_F5R2_FB25_Pos (25U) +#define CAN_F5R2_FB25_Pos (25U) #define CAN_F5R2_FB25_Msk (0x1U << CAN_F5R2_FB25_Pos) /*!< 0x02000000 */ #define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk /*!< Filter bit 25 */ -#define CAN_F5R2_FB26_Pos (26U) +#define CAN_F5R2_FB26_Pos (26U) #define CAN_F5R2_FB26_Msk (0x1U << CAN_F5R2_FB26_Pos) /*!< 0x04000000 */ #define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk /*!< Filter bit 26 */ -#define CAN_F5R2_FB27_Pos (27U) +#define CAN_F5R2_FB27_Pos (27U) #define CAN_F5R2_FB27_Msk (0x1U << CAN_F5R2_FB27_Pos) /*!< 0x08000000 */ #define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk /*!< Filter bit 27 */ -#define CAN_F5R2_FB28_Pos (28U) +#define CAN_F5R2_FB28_Pos (28U) #define CAN_F5R2_FB28_Msk (0x1U << CAN_F5R2_FB28_Pos) /*!< 0x10000000 */ #define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk /*!< Filter bit 28 */ -#define CAN_F5R2_FB29_Pos (29U) +#define CAN_F5R2_FB29_Pos (29U) #define CAN_F5R2_FB29_Msk (0x1U << CAN_F5R2_FB29_Pos) /*!< 0x20000000 */ #define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk /*!< Filter bit 29 */ -#define CAN_F5R2_FB30_Pos (30U) +#define CAN_F5R2_FB30_Pos (30U) #define CAN_F5R2_FB30_Msk (0x1U << CAN_F5R2_FB30_Pos) /*!< 0x40000000 */ #define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk /*!< Filter bit 30 */ -#define CAN_F5R2_FB31_Pos (31U) +#define CAN_F5R2_FB31_Pos (31U) #define CAN_F5R2_FB31_Msk (0x1U << CAN_F5R2_FB31_Pos) /*!< 0x80000000 */ #define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk /*!< Filter bit 31 */ /******************* Bit definition for CAN_F6R2 register *******************/ -#define CAN_F6R2_FB0_Pos (0U) +#define CAN_F6R2_FB0_Pos (0U) #define CAN_F6R2_FB0_Msk (0x1U << CAN_F6R2_FB0_Pos) /*!< 0x00000001 */ #define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk /*!< Filter bit 0 */ -#define CAN_F6R2_FB1_Pos (1U) +#define CAN_F6R2_FB1_Pos (1U) #define CAN_F6R2_FB1_Msk (0x1U << CAN_F6R2_FB1_Pos) /*!< 0x00000002 */ #define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk /*!< Filter bit 1 */ -#define CAN_F6R2_FB2_Pos (2U) +#define CAN_F6R2_FB2_Pos (2U) #define CAN_F6R2_FB2_Msk (0x1U << CAN_F6R2_FB2_Pos) /*!< 0x00000004 */ #define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk /*!< Filter bit 2 */ -#define CAN_F6R2_FB3_Pos (3U) +#define CAN_F6R2_FB3_Pos (3U) #define CAN_F6R2_FB3_Msk (0x1U << CAN_F6R2_FB3_Pos) /*!< 0x00000008 */ #define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk /*!< Filter bit 3 */ -#define CAN_F6R2_FB4_Pos (4U) +#define CAN_F6R2_FB4_Pos (4U) #define CAN_F6R2_FB4_Msk (0x1U << CAN_F6R2_FB4_Pos) /*!< 0x00000010 */ #define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk /*!< Filter bit 4 */ -#define CAN_F6R2_FB5_Pos (5U) +#define CAN_F6R2_FB5_Pos (5U) #define CAN_F6R2_FB5_Msk (0x1U << CAN_F6R2_FB5_Pos) /*!< 0x00000020 */ #define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk /*!< Filter bit 5 */ -#define CAN_F6R2_FB6_Pos (6U) +#define CAN_F6R2_FB6_Pos (6U) #define CAN_F6R2_FB6_Msk (0x1U << CAN_F6R2_FB6_Pos) /*!< 0x00000040 */ #define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk /*!< Filter bit 6 */ -#define CAN_F6R2_FB7_Pos (7U) +#define CAN_F6R2_FB7_Pos (7U) #define CAN_F6R2_FB7_Msk (0x1U << CAN_F6R2_FB7_Pos) /*!< 0x00000080 */ #define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk /*!< Filter bit 7 */ -#define CAN_F6R2_FB8_Pos (8U) +#define CAN_F6R2_FB8_Pos (8U) #define CAN_F6R2_FB8_Msk (0x1U << CAN_F6R2_FB8_Pos) /*!< 0x00000100 */ #define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk /*!< Filter bit 8 */ -#define CAN_F6R2_FB9_Pos (9U) +#define CAN_F6R2_FB9_Pos (9U) #define CAN_F6R2_FB9_Msk (0x1U << CAN_F6R2_FB9_Pos) /*!< 0x00000200 */ #define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk /*!< Filter bit 9 */ -#define CAN_F6R2_FB10_Pos (10U) +#define CAN_F6R2_FB10_Pos (10U) #define CAN_F6R2_FB10_Msk (0x1U << CAN_F6R2_FB10_Pos) /*!< 0x00000400 */ #define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk /*!< Filter bit 10 */ -#define CAN_F6R2_FB11_Pos (11U) +#define CAN_F6R2_FB11_Pos (11U) #define CAN_F6R2_FB11_Msk (0x1U << CAN_F6R2_FB11_Pos) /*!< 0x00000800 */ #define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk /*!< Filter bit 11 */ -#define CAN_F6R2_FB12_Pos (12U) +#define CAN_F6R2_FB12_Pos (12U) #define CAN_F6R2_FB12_Msk (0x1U << CAN_F6R2_FB12_Pos) /*!< 0x00001000 */ #define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk /*!< Filter bit 12 */ -#define CAN_F6R2_FB13_Pos (13U) +#define CAN_F6R2_FB13_Pos (13U) #define CAN_F6R2_FB13_Msk (0x1U << CAN_F6R2_FB13_Pos) /*!< 0x00002000 */ #define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk /*!< Filter bit 13 */ -#define CAN_F6R2_FB14_Pos (14U) +#define CAN_F6R2_FB14_Pos (14U) #define CAN_F6R2_FB14_Msk (0x1U << CAN_F6R2_FB14_Pos) /*!< 0x00004000 */ #define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk /*!< Filter bit 14 */ -#define CAN_F6R2_FB15_Pos (15U) +#define CAN_F6R2_FB15_Pos (15U) #define CAN_F6R2_FB15_Msk (0x1U << CAN_F6R2_FB15_Pos) /*!< 0x00008000 */ #define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk /*!< Filter bit 15 */ -#define CAN_F6R2_FB16_Pos (16U) +#define CAN_F6R2_FB16_Pos (16U) #define CAN_F6R2_FB16_Msk (0x1U << CAN_F6R2_FB16_Pos) /*!< 0x00010000 */ #define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk /*!< Filter bit 16 */ -#define CAN_F6R2_FB17_Pos (17U) +#define CAN_F6R2_FB17_Pos (17U) #define CAN_F6R2_FB17_Msk (0x1U << CAN_F6R2_FB17_Pos) /*!< 0x00020000 */ #define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk /*!< Filter bit 17 */ -#define CAN_F6R2_FB18_Pos (18U) +#define CAN_F6R2_FB18_Pos (18U) #define CAN_F6R2_FB18_Msk (0x1U << CAN_F6R2_FB18_Pos) /*!< 0x00040000 */ #define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk /*!< Filter bit 18 */ -#define CAN_F6R2_FB19_Pos (19U) +#define CAN_F6R2_FB19_Pos (19U) #define CAN_F6R2_FB19_Msk (0x1U << CAN_F6R2_FB19_Pos) /*!< 0x00080000 */ #define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk /*!< Filter bit 19 */ -#define CAN_F6R2_FB20_Pos (20U) +#define CAN_F6R2_FB20_Pos (20U) #define CAN_F6R2_FB20_Msk (0x1U << CAN_F6R2_FB20_Pos) /*!< 0x00100000 */ #define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk /*!< Filter bit 20 */ -#define CAN_F6R2_FB21_Pos (21U) +#define CAN_F6R2_FB21_Pos (21U) #define CAN_F6R2_FB21_Msk (0x1U << CAN_F6R2_FB21_Pos) /*!< 0x00200000 */ #define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk /*!< Filter bit 21 */ -#define CAN_F6R2_FB22_Pos (22U) +#define CAN_F6R2_FB22_Pos (22U) #define CAN_F6R2_FB22_Msk (0x1U << CAN_F6R2_FB22_Pos) /*!< 0x00400000 */ #define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk /*!< Filter bit 22 */ -#define CAN_F6R2_FB23_Pos (23U) +#define CAN_F6R2_FB23_Pos (23U) #define CAN_F6R2_FB23_Msk (0x1U << CAN_F6R2_FB23_Pos) /*!< 0x00800000 */ #define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk /*!< Filter bit 23 */ -#define CAN_F6R2_FB24_Pos (24U) +#define CAN_F6R2_FB24_Pos (24U) #define CAN_F6R2_FB24_Msk (0x1U << CAN_F6R2_FB24_Pos) /*!< 0x01000000 */ #define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk /*!< Filter bit 24 */ -#define CAN_F6R2_FB25_Pos (25U) +#define CAN_F6R2_FB25_Pos (25U) #define CAN_F6R2_FB25_Msk (0x1U << CAN_F6R2_FB25_Pos) /*!< 0x02000000 */ #define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk /*!< Filter bit 25 */ -#define CAN_F6R2_FB26_Pos (26U) +#define CAN_F6R2_FB26_Pos (26U) #define CAN_F6R2_FB26_Msk (0x1U << CAN_F6R2_FB26_Pos) /*!< 0x04000000 */ #define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk /*!< Filter bit 26 */ -#define CAN_F6R2_FB27_Pos (27U) +#define CAN_F6R2_FB27_Pos (27U) #define CAN_F6R2_FB27_Msk (0x1U << CAN_F6R2_FB27_Pos) /*!< 0x08000000 */ #define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk /*!< Filter bit 27 */ -#define CAN_F6R2_FB28_Pos (28U) +#define CAN_F6R2_FB28_Pos (28U) #define CAN_F6R2_FB28_Msk (0x1U << CAN_F6R2_FB28_Pos) /*!< 0x10000000 */ #define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk /*!< Filter bit 28 */ -#define CAN_F6R2_FB29_Pos (29U) +#define CAN_F6R2_FB29_Pos (29U) #define CAN_F6R2_FB29_Msk (0x1U << CAN_F6R2_FB29_Pos) /*!< 0x20000000 */ #define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk /*!< Filter bit 29 */ -#define CAN_F6R2_FB30_Pos (30U) +#define CAN_F6R2_FB30_Pos (30U) #define CAN_F6R2_FB30_Msk (0x1U << CAN_F6R2_FB30_Pos) /*!< 0x40000000 */ #define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk /*!< Filter bit 30 */ -#define CAN_F6R2_FB31_Pos (31U) +#define CAN_F6R2_FB31_Pos (31U) #define CAN_F6R2_FB31_Msk (0x1U << CAN_F6R2_FB31_Pos) /*!< 0x80000000 */ #define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk /*!< Filter bit 31 */ /******************* Bit definition for CAN_F7R2 register *******************/ -#define CAN_F7R2_FB0_Pos (0U) +#define CAN_F7R2_FB0_Pos (0U) #define CAN_F7R2_FB0_Msk (0x1U << CAN_F7R2_FB0_Pos) /*!< 0x00000001 */ #define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk /*!< Filter bit 0 */ -#define CAN_F7R2_FB1_Pos (1U) +#define CAN_F7R2_FB1_Pos (1U) #define CAN_F7R2_FB1_Msk (0x1U << CAN_F7R2_FB1_Pos) /*!< 0x00000002 */ #define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk /*!< Filter bit 1 */ -#define CAN_F7R2_FB2_Pos (2U) +#define CAN_F7R2_FB2_Pos (2U) #define CAN_F7R2_FB2_Msk (0x1U << CAN_F7R2_FB2_Pos) /*!< 0x00000004 */ #define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk /*!< Filter bit 2 */ -#define CAN_F7R2_FB3_Pos (3U) +#define CAN_F7R2_FB3_Pos (3U) #define CAN_F7R2_FB3_Msk (0x1U << CAN_F7R2_FB3_Pos) /*!< 0x00000008 */ #define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk /*!< Filter bit 3 */ -#define CAN_F7R2_FB4_Pos (4U) +#define CAN_F7R2_FB4_Pos (4U) #define CAN_F7R2_FB4_Msk (0x1U << CAN_F7R2_FB4_Pos) /*!< 0x00000010 */ #define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk /*!< Filter bit 4 */ -#define CAN_F7R2_FB5_Pos (5U) +#define CAN_F7R2_FB5_Pos (5U) #define CAN_F7R2_FB5_Msk (0x1U << CAN_F7R2_FB5_Pos) /*!< 0x00000020 */ #define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk /*!< Filter bit 5 */ -#define CAN_F7R2_FB6_Pos (6U) +#define CAN_F7R2_FB6_Pos (6U) #define CAN_F7R2_FB6_Msk (0x1U << CAN_F7R2_FB6_Pos) /*!< 0x00000040 */ #define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk /*!< Filter bit 6 */ -#define CAN_F7R2_FB7_Pos (7U) +#define CAN_F7R2_FB7_Pos (7U) #define CAN_F7R2_FB7_Msk (0x1U << CAN_F7R2_FB7_Pos) /*!< 0x00000080 */ #define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk /*!< Filter bit 7 */ -#define CAN_F7R2_FB8_Pos (8U) +#define CAN_F7R2_FB8_Pos (8U) #define CAN_F7R2_FB8_Msk (0x1U << CAN_F7R2_FB8_Pos) /*!< 0x00000100 */ #define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk /*!< Filter bit 8 */ -#define CAN_F7R2_FB9_Pos (9U) +#define CAN_F7R2_FB9_Pos (9U) #define CAN_F7R2_FB9_Msk (0x1U << CAN_F7R2_FB9_Pos) /*!< 0x00000200 */ #define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk /*!< Filter bit 9 */ -#define CAN_F7R2_FB10_Pos (10U) +#define CAN_F7R2_FB10_Pos (10U) #define CAN_F7R2_FB10_Msk (0x1U << CAN_F7R2_FB10_Pos) /*!< 0x00000400 */ #define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk /*!< Filter bit 10 */ -#define CAN_F7R2_FB11_Pos (11U) +#define CAN_F7R2_FB11_Pos (11U) #define CAN_F7R2_FB11_Msk (0x1U << CAN_F7R2_FB11_Pos) /*!< 0x00000800 */ #define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk /*!< Filter bit 11 */ -#define CAN_F7R2_FB12_Pos (12U) +#define CAN_F7R2_FB12_Pos (12U) #define CAN_F7R2_FB12_Msk (0x1U << CAN_F7R2_FB12_Pos) /*!< 0x00001000 */ #define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk /*!< Filter bit 12 */ -#define CAN_F7R2_FB13_Pos (13U) +#define CAN_F7R2_FB13_Pos (13U) #define CAN_F7R2_FB13_Msk (0x1U << CAN_F7R2_FB13_Pos) /*!< 0x00002000 */ #define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk /*!< Filter bit 13 */ -#define CAN_F7R2_FB14_Pos (14U) +#define CAN_F7R2_FB14_Pos (14U) #define CAN_F7R2_FB14_Msk (0x1U << CAN_F7R2_FB14_Pos) /*!< 0x00004000 */ #define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk /*!< Filter bit 14 */ -#define CAN_F7R2_FB15_Pos (15U) +#define CAN_F7R2_FB15_Pos (15U) #define CAN_F7R2_FB15_Msk (0x1U << CAN_F7R2_FB15_Pos) /*!< 0x00008000 */ #define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk /*!< Filter bit 15 */ -#define CAN_F7R2_FB16_Pos (16U) +#define CAN_F7R2_FB16_Pos (16U) #define CAN_F7R2_FB16_Msk (0x1U << CAN_F7R2_FB16_Pos) /*!< 0x00010000 */ #define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk /*!< Filter bit 16 */ -#define CAN_F7R2_FB17_Pos (17U) +#define CAN_F7R2_FB17_Pos (17U) #define CAN_F7R2_FB17_Msk (0x1U << CAN_F7R2_FB17_Pos) /*!< 0x00020000 */ #define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk /*!< Filter bit 17 */ -#define CAN_F7R2_FB18_Pos (18U) +#define CAN_F7R2_FB18_Pos (18U) #define CAN_F7R2_FB18_Msk (0x1U << CAN_F7R2_FB18_Pos) /*!< 0x00040000 */ #define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk /*!< Filter bit 18 */ -#define CAN_F7R2_FB19_Pos (19U) +#define CAN_F7R2_FB19_Pos (19U) #define CAN_F7R2_FB19_Msk (0x1U << CAN_F7R2_FB19_Pos) /*!< 0x00080000 */ #define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk /*!< Filter bit 19 */ -#define CAN_F7R2_FB20_Pos (20U) +#define CAN_F7R2_FB20_Pos (20U) #define CAN_F7R2_FB20_Msk (0x1U << CAN_F7R2_FB20_Pos) /*!< 0x00100000 */ #define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk /*!< Filter bit 20 */ -#define CAN_F7R2_FB21_Pos (21U) +#define CAN_F7R2_FB21_Pos (21U) #define CAN_F7R2_FB21_Msk (0x1U << CAN_F7R2_FB21_Pos) /*!< 0x00200000 */ #define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk /*!< Filter bit 21 */ -#define CAN_F7R2_FB22_Pos (22U) +#define CAN_F7R2_FB22_Pos (22U) #define CAN_F7R2_FB22_Msk (0x1U << CAN_F7R2_FB22_Pos) /*!< 0x00400000 */ #define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk /*!< Filter bit 22 */ -#define CAN_F7R2_FB23_Pos (23U) +#define CAN_F7R2_FB23_Pos (23U) #define CAN_F7R2_FB23_Msk (0x1U << CAN_F7R2_FB23_Pos) /*!< 0x00800000 */ #define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk /*!< Filter bit 23 */ -#define CAN_F7R2_FB24_Pos (24U) +#define CAN_F7R2_FB24_Pos (24U) #define CAN_F7R2_FB24_Msk (0x1U << CAN_F7R2_FB24_Pos) /*!< 0x01000000 */ #define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk /*!< Filter bit 24 */ -#define CAN_F7R2_FB25_Pos (25U) +#define CAN_F7R2_FB25_Pos (25U) #define CAN_F7R2_FB25_Msk (0x1U << CAN_F7R2_FB25_Pos) /*!< 0x02000000 */ #define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk /*!< Filter bit 25 */ -#define CAN_F7R2_FB26_Pos (26U) +#define CAN_F7R2_FB26_Pos (26U) #define CAN_F7R2_FB26_Msk (0x1U << CAN_F7R2_FB26_Pos) /*!< 0x04000000 */ #define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk /*!< Filter bit 26 */ -#define CAN_F7R2_FB27_Pos (27U) +#define CAN_F7R2_FB27_Pos (27U) #define CAN_F7R2_FB27_Msk (0x1U << CAN_F7R2_FB27_Pos) /*!< 0x08000000 */ #define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk /*!< Filter bit 27 */ -#define CAN_F7R2_FB28_Pos (28U) +#define CAN_F7R2_FB28_Pos (28U) #define CAN_F7R2_FB28_Msk (0x1U << CAN_F7R2_FB28_Pos) /*!< 0x10000000 */ #define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk /*!< Filter bit 28 */ -#define CAN_F7R2_FB29_Pos (29U) +#define CAN_F7R2_FB29_Pos (29U) #define CAN_F7R2_FB29_Msk (0x1U << CAN_F7R2_FB29_Pos) /*!< 0x20000000 */ #define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk /*!< Filter bit 29 */ -#define CAN_F7R2_FB30_Pos (30U) +#define CAN_F7R2_FB30_Pos (30U) #define CAN_F7R2_FB30_Msk (0x1U << CAN_F7R2_FB30_Pos) /*!< 0x40000000 */ #define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk /*!< Filter bit 30 */ -#define CAN_F7R2_FB31_Pos (31U) +#define CAN_F7R2_FB31_Pos (31U) #define CAN_F7R2_FB31_Msk (0x1U << CAN_F7R2_FB31_Pos) /*!< 0x80000000 */ #define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk /*!< Filter bit 31 */ /******************* Bit definition for CAN_F8R2 register *******************/ -#define CAN_F8R2_FB0_Pos (0U) +#define CAN_F8R2_FB0_Pos (0U) #define CAN_F8R2_FB0_Msk (0x1U << CAN_F8R2_FB0_Pos) /*!< 0x00000001 */ #define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk /*!< Filter bit 0 */ -#define CAN_F8R2_FB1_Pos (1U) +#define CAN_F8R2_FB1_Pos (1U) #define CAN_F8R2_FB1_Msk (0x1U << CAN_F8R2_FB1_Pos) /*!< 0x00000002 */ #define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk /*!< Filter bit 1 */ -#define CAN_F8R2_FB2_Pos (2U) +#define CAN_F8R2_FB2_Pos (2U) #define CAN_F8R2_FB2_Msk (0x1U << CAN_F8R2_FB2_Pos) /*!< 0x00000004 */ #define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk /*!< Filter bit 2 */ -#define CAN_F8R2_FB3_Pos (3U) +#define CAN_F8R2_FB3_Pos (3U) #define CAN_F8R2_FB3_Msk (0x1U << CAN_F8R2_FB3_Pos) /*!< 0x00000008 */ #define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk /*!< Filter bit 3 */ -#define CAN_F8R2_FB4_Pos (4U) +#define CAN_F8R2_FB4_Pos (4U) #define CAN_F8R2_FB4_Msk (0x1U << CAN_F8R2_FB4_Pos) /*!< 0x00000010 */ #define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk /*!< Filter bit 4 */ -#define CAN_F8R2_FB5_Pos (5U) +#define CAN_F8R2_FB5_Pos (5U) #define CAN_F8R2_FB5_Msk (0x1U << CAN_F8R2_FB5_Pos) /*!< 0x00000020 */ #define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk /*!< Filter bit 5 */ -#define CAN_F8R2_FB6_Pos (6U) +#define CAN_F8R2_FB6_Pos (6U) #define CAN_F8R2_FB6_Msk (0x1U << CAN_F8R2_FB6_Pos) /*!< 0x00000040 */ #define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk /*!< Filter bit 6 */ -#define CAN_F8R2_FB7_Pos (7U) +#define CAN_F8R2_FB7_Pos (7U) #define CAN_F8R2_FB7_Msk (0x1U << CAN_F8R2_FB7_Pos) /*!< 0x00000080 */ #define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk /*!< Filter bit 7 */ -#define CAN_F8R2_FB8_Pos (8U) +#define CAN_F8R2_FB8_Pos (8U) #define CAN_F8R2_FB8_Msk (0x1U << CAN_F8R2_FB8_Pos) /*!< 0x00000100 */ #define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk /*!< Filter bit 8 */ -#define CAN_F8R2_FB9_Pos (9U) +#define CAN_F8R2_FB9_Pos (9U) #define CAN_F8R2_FB9_Msk (0x1U << CAN_F8R2_FB9_Pos) /*!< 0x00000200 */ #define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk /*!< Filter bit 9 */ -#define CAN_F8R2_FB10_Pos (10U) +#define CAN_F8R2_FB10_Pos (10U) #define CAN_F8R2_FB10_Msk (0x1U << CAN_F8R2_FB10_Pos) /*!< 0x00000400 */ #define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk /*!< Filter bit 10 */ -#define CAN_F8R2_FB11_Pos (11U) +#define CAN_F8R2_FB11_Pos (11U) #define CAN_F8R2_FB11_Msk (0x1U << CAN_F8R2_FB11_Pos) /*!< 0x00000800 */ #define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk /*!< Filter bit 11 */ -#define CAN_F8R2_FB12_Pos (12U) +#define CAN_F8R2_FB12_Pos (12U) #define CAN_F8R2_FB12_Msk (0x1U << CAN_F8R2_FB12_Pos) /*!< 0x00001000 */ #define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk /*!< Filter bit 12 */ -#define CAN_F8R2_FB13_Pos (13U) +#define CAN_F8R2_FB13_Pos (13U) #define CAN_F8R2_FB13_Msk (0x1U << CAN_F8R2_FB13_Pos) /*!< 0x00002000 */ #define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk /*!< Filter bit 13 */ -#define CAN_F8R2_FB14_Pos (14U) +#define CAN_F8R2_FB14_Pos (14U) #define CAN_F8R2_FB14_Msk (0x1U << CAN_F8R2_FB14_Pos) /*!< 0x00004000 */ #define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk /*!< Filter bit 14 */ -#define CAN_F8R2_FB15_Pos (15U) +#define CAN_F8R2_FB15_Pos (15U) #define CAN_F8R2_FB15_Msk (0x1U << CAN_F8R2_FB15_Pos) /*!< 0x00008000 */ #define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk /*!< Filter bit 15 */ -#define CAN_F8R2_FB16_Pos (16U) +#define CAN_F8R2_FB16_Pos (16U) #define CAN_F8R2_FB16_Msk (0x1U << CAN_F8R2_FB16_Pos) /*!< 0x00010000 */ #define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk /*!< Filter bit 16 */ -#define CAN_F8R2_FB17_Pos (17U) +#define CAN_F8R2_FB17_Pos (17U) #define CAN_F8R2_FB17_Msk (0x1U << CAN_F8R2_FB17_Pos) /*!< 0x00020000 */ #define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk /*!< Filter bit 17 */ -#define CAN_F8R2_FB18_Pos (18U) +#define CAN_F8R2_FB18_Pos (18U) #define CAN_F8R2_FB18_Msk (0x1U << CAN_F8R2_FB18_Pos) /*!< 0x00040000 */ #define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk /*!< Filter bit 18 */ -#define CAN_F8R2_FB19_Pos (19U) +#define CAN_F8R2_FB19_Pos (19U) #define CAN_F8R2_FB19_Msk (0x1U << CAN_F8R2_FB19_Pos) /*!< 0x00080000 */ #define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk /*!< Filter bit 19 */ -#define CAN_F8R2_FB20_Pos (20U) +#define CAN_F8R2_FB20_Pos (20U) #define CAN_F8R2_FB20_Msk (0x1U << CAN_F8R2_FB20_Pos) /*!< 0x00100000 */ #define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk /*!< Filter bit 20 */ -#define CAN_F8R2_FB21_Pos (21U) +#define CAN_F8R2_FB21_Pos (21U) #define CAN_F8R2_FB21_Msk (0x1U << CAN_F8R2_FB21_Pos) /*!< 0x00200000 */ #define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk /*!< Filter bit 21 */ -#define CAN_F8R2_FB22_Pos (22U) +#define CAN_F8R2_FB22_Pos (22U) #define CAN_F8R2_FB22_Msk (0x1U << CAN_F8R2_FB22_Pos) /*!< 0x00400000 */ #define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk /*!< Filter bit 22 */ -#define CAN_F8R2_FB23_Pos (23U) +#define CAN_F8R2_FB23_Pos (23U) #define CAN_F8R2_FB23_Msk (0x1U << CAN_F8R2_FB23_Pos) /*!< 0x00800000 */ #define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk /*!< Filter bit 23 */ -#define CAN_F8R2_FB24_Pos (24U) +#define CAN_F8R2_FB24_Pos (24U) #define CAN_F8R2_FB24_Msk (0x1U << CAN_F8R2_FB24_Pos) /*!< 0x01000000 */ #define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk /*!< Filter bit 24 */ -#define CAN_F8R2_FB25_Pos (25U) +#define CAN_F8R2_FB25_Pos (25U) #define CAN_F8R2_FB25_Msk (0x1U << CAN_F8R2_FB25_Pos) /*!< 0x02000000 */ #define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk /*!< Filter bit 25 */ -#define CAN_F8R2_FB26_Pos (26U) +#define CAN_F8R2_FB26_Pos (26U) #define CAN_F8R2_FB26_Msk (0x1U << CAN_F8R2_FB26_Pos) /*!< 0x04000000 */ #define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk /*!< Filter bit 26 */ -#define CAN_F8R2_FB27_Pos (27U) +#define CAN_F8R2_FB27_Pos (27U) #define CAN_F8R2_FB27_Msk (0x1U << CAN_F8R2_FB27_Pos) /*!< 0x08000000 */ #define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk /*!< Filter bit 27 */ -#define CAN_F8R2_FB28_Pos (28U) +#define CAN_F8R2_FB28_Pos (28U) #define CAN_F8R2_FB28_Msk (0x1U << CAN_F8R2_FB28_Pos) /*!< 0x10000000 */ #define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk /*!< Filter bit 28 */ -#define CAN_F8R2_FB29_Pos (29U) +#define CAN_F8R2_FB29_Pos (29U) #define CAN_F8R2_FB29_Msk (0x1U << CAN_F8R2_FB29_Pos) /*!< 0x20000000 */ #define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk /*!< Filter bit 29 */ -#define CAN_F8R2_FB30_Pos (30U) +#define CAN_F8R2_FB30_Pos (30U) #define CAN_F8R2_FB30_Msk (0x1U << CAN_F8R2_FB30_Pos) /*!< 0x40000000 */ #define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk /*!< Filter bit 30 */ -#define CAN_F8R2_FB31_Pos (31U) +#define CAN_F8R2_FB31_Pos (31U) #define CAN_F8R2_FB31_Msk (0x1U << CAN_F8R2_FB31_Pos) /*!< 0x80000000 */ #define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk /*!< Filter bit 31 */ /******************* Bit definition for CAN_F9R2 register *******************/ -#define CAN_F9R2_FB0_Pos (0U) +#define CAN_F9R2_FB0_Pos (0U) #define CAN_F9R2_FB0_Msk (0x1U << CAN_F9R2_FB0_Pos) /*!< 0x00000001 */ #define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk /*!< Filter bit 0 */ -#define CAN_F9R2_FB1_Pos (1U) +#define CAN_F9R2_FB1_Pos (1U) #define CAN_F9R2_FB1_Msk (0x1U << CAN_F9R2_FB1_Pos) /*!< 0x00000002 */ #define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk /*!< Filter bit 1 */ -#define CAN_F9R2_FB2_Pos (2U) +#define CAN_F9R2_FB2_Pos (2U) #define CAN_F9R2_FB2_Msk (0x1U << CAN_F9R2_FB2_Pos) /*!< 0x00000004 */ #define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk /*!< Filter bit 2 */ -#define CAN_F9R2_FB3_Pos (3U) +#define CAN_F9R2_FB3_Pos (3U) #define CAN_F9R2_FB3_Msk (0x1U << CAN_F9R2_FB3_Pos) /*!< 0x00000008 */ #define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk /*!< Filter bit 3 */ -#define CAN_F9R2_FB4_Pos (4U) +#define CAN_F9R2_FB4_Pos (4U) #define CAN_F9R2_FB4_Msk (0x1U << CAN_F9R2_FB4_Pos) /*!< 0x00000010 */ #define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk /*!< Filter bit 4 */ -#define CAN_F9R2_FB5_Pos (5U) +#define CAN_F9R2_FB5_Pos (5U) #define CAN_F9R2_FB5_Msk (0x1U << CAN_F9R2_FB5_Pos) /*!< 0x00000020 */ #define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk /*!< Filter bit 5 */ -#define CAN_F9R2_FB6_Pos (6U) +#define CAN_F9R2_FB6_Pos (6U) #define CAN_F9R2_FB6_Msk (0x1U << CAN_F9R2_FB6_Pos) /*!< 0x00000040 */ #define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk /*!< Filter bit 6 */ -#define CAN_F9R2_FB7_Pos (7U) +#define CAN_F9R2_FB7_Pos (7U) #define CAN_F9R2_FB7_Msk (0x1U << CAN_F9R2_FB7_Pos) /*!< 0x00000080 */ #define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk /*!< Filter bit 7 */ -#define CAN_F9R2_FB8_Pos (8U) +#define CAN_F9R2_FB8_Pos (8U) #define CAN_F9R2_FB8_Msk (0x1U << CAN_F9R2_FB8_Pos) /*!< 0x00000100 */ #define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk /*!< Filter bit 8 */ -#define CAN_F9R2_FB9_Pos (9U) +#define CAN_F9R2_FB9_Pos (9U) #define CAN_F9R2_FB9_Msk (0x1U << CAN_F9R2_FB9_Pos) /*!< 0x00000200 */ #define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk /*!< Filter bit 9 */ -#define CAN_F9R2_FB10_Pos (10U) +#define CAN_F9R2_FB10_Pos (10U) #define CAN_F9R2_FB10_Msk (0x1U << CAN_F9R2_FB10_Pos) /*!< 0x00000400 */ #define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk /*!< Filter bit 10 */ -#define CAN_F9R2_FB11_Pos (11U) +#define CAN_F9R2_FB11_Pos (11U) #define CAN_F9R2_FB11_Msk (0x1U << CAN_F9R2_FB11_Pos) /*!< 0x00000800 */ #define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk /*!< Filter bit 11 */ -#define CAN_F9R2_FB12_Pos (12U) +#define CAN_F9R2_FB12_Pos (12U) #define CAN_F9R2_FB12_Msk (0x1U << CAN_F9R2_FB12_Pos) /*!< 0x00001000 */ #define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk /*!< Filter bit 12 */ -#define CAN_F9R2_FB13_Pos (13U) +#define CAN_F9R2_FB13_Pos (13U) #define CAN_F9R2_FB13_Msk (0x1U << CAN_F9R2_FB13_Pos) /*!< 0x00002000 */ #define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk /*!< Filter bit 13 */ -#define CAN_F9R2_FB14_Pos (14U) +#define CAN_F9R2_FB14_Pos (14U) #define CAN_F9R2_FB14_Msk (0x1U << CAN_F9R2_FB14_Pos) /*!< 0x00004000 */ #define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk /*!< Filter bit 14 */ -#define CAN_F9R2_FB15_Pos (15U) +#define CAN_F9R2_FB15_Pos (15U) #define CAN_F9R2_FB15_Msk (0x1U << CAN_F9R2_FB15_Pos) /*!< 0x00008000 */ #define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk /*!< Filter bit 15 */ -#define CAN_F9R2_FB16_Pos (16U) +#define CAN_F9R2_FB16_Pos (16U) #define CAN_F9R2_FB16_Msk (0x1U << CAN_F9R2_FB16_Pos) /*!< 0x00010000 */ #define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk /*!< Filter bit 16 */ -#define CAN_F9R2_FB17_Pos (17U) +#define CAN_F9R2_FB17_Pos (17U) #define CAN_F9R2_FB17_Msk (0x1U << CAN_F9R2_FB17_Pos) /*!< 0x00020000 */ #define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk /*!< Filter bit 17 */ -#define CAN_F9R2_FB18_Pos (18U) +#define CAN_F9R2_FB18_Pos (18U) #define CAN_F9R2_FB18_Msk (0x1U << CAN_F9R2_FB18_Pos) /*!< 0x00040000 */ #define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk /*!< Filter bit 18 */ -#define CAN_F9R2_FB19_Pos (19U) +#define CAN_F9R2_FB19_Pos (19U) #define CAN_F9R2_FB19_Msk (0x1U << CAN_F9R2_FB19_Pos) /*!< 0x00080000 */ #define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk /*!< Filter bit 19 */ -#define CAN_F9R2_FB20_Pos (20U) +#define CAN_F9R2_FB20_Pos (20U) #define CAN_F9R2_FB20_Msk (0x1U << CAN_F9R2_FB20_Pos) /*!< 0x00100000 */ #define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk /*!< Filter bit 20 */ -#define CAN_F9R2_FB21_Pos (21U) +#define CAN_F9R2_FB21_Pos (21U) #define CAN_F9R2_FB21_Msk (0x1U << CAN_F9R2_FB21_Pos) /*!< 0x00200000 */ #define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk /*!< Filter bit 21 */ -#define CAN_F9R2_FB22_Pos (22U) +#define CAN_F9R2_FB22_Pos (22U) #define CAN_F9R2_FB22_Msk (0x1U << CAN_F9R2_FB22_Pos) /*!< 0x00400000 */ #define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk /*!< Filter bit 22 */ -#define CAN_F9R2_FB23_Pos (23U) +#define CAN_F9R2_FB23_Pos (23U) #define CAN_F9R2_FB23_Msk (0x1U << CAN_F9R2_FB23_Pos) /*!< 0x00800000 */ #define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk /*!< Filter bit 23 */ -#define CAN_F9R2_FB24_Pos (24U) +#define CAN_F9R2_FB24_Pos (24U) #define CAN_F9R2_FB24_Msk (0x1U << CAN_F9R2_FB24_Pos) /*!< 0x01000000 */ #define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk /*!< Filter bit 24 */ -#define CAN_F9R2_FB25_Pos (25U) +#define CAN_F9R2_FB25_Pos (25U) #define CAN_F9R2_FB25_Msk (0x1U << CAN_F9R2_FB25_Pos) /*!< 0x02000000 */ #define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk /*!< Filter bit 25 */ -#define CAN_F9R2_FB26_Pos (26U) +#define CAN_F9R2_FB26_Pos (26U) #define CAN_F9R2_FB26_Msk (0x1U << CAN_F9R2_FB26_Pos) /*!< 0x04000000 */ #define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk /*!< Filter bit 26 */ -#define CAN_F9R2_FB27_Pos (27U) +#define CAN_F9R2_FB27_Pos (27U) #define CAN_F9R2_FB27_Msk (0x1U << CAN_F9R2_FB27_Pos) /*!< 0x08000000 */ #define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk /*!< Filter bit 27 */ -#define CAN_F9R2_FB28_Pos (28U) +#define CAN_F9R2_FB28_Pos (28U) #define CAN_F9R2_FB28_Msk (0x1U << CAN_F9R2_FB28_Pos) /*!< 0x10000000 */ #define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk /*!< Filter bit 28 */ -#define CAN_F9R2_FB29_Pos (29U) +#define CAN_F9R2_FB29_Pos (29U) #define CAN_F9R2_FB29_Msk (0x1U << CAN_F9R2_FB29_Pos) /*!< 0x20000000 */ #define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk /*!< Filter bit 29 */ -#define CAN_F9R2_FB30_Pos (30U) +#define CAN_F9R2_FB30_Pos (30U) #define CAN_F9R2_FB30_Msk (0x1U << CAN_F9R2_FB30_Pos) /*!< 0x40000000 */ #define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk /*!< Filter bit 30 */ -#define CAN_F9R2_FB31_Pos (31U) +#define CAN_F9R2_FB31_Pos (31U) #define CAN_F9R2_FB31_Msk (0x1U << CAN_F9R2_FB31_Pos) /*!< 0x80000000 */ #define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk /*!< Filter bit 31 */ /******************* Bit definition for CAN_F10R2 register ******************/ -#define CAN_F10R2_FB0_Pos (0U) +#define CAN_F10R2_FB0_Pos (0U) #define CAN_F10R2_FB0_Msk (0x1U << CAN_F10R2_FB0_Pos) /*!< 0x00000001 */ #define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk /*!< Filter bit 0 */ -#define CAN_F10R2_FB1_Pos (1U) +#define CAN_F10R2_FB1_Pos (1U) #define CAN_F10R2_FB1_Msk (0x1U << CAN_F10R2_FB1_Pos) /*!< 0x00000002 */ #define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk /*!< Filter bit 1 */ -#define CAN_F10R2_FB2_Pos (2U) +#define CAN_F10R2_FB2_Pos (2U) #define CAN_F10R2_FB2_Msk (0x1U << CAN_F10R2_FB2_Pos) /*!< 0x00000004 */ #define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk /*!< Filter bit 2 */ -#define CAN_F10R2_FB3_Pos (3U) +#define CAN_F10R2_FB3_Pos (3U) #define CAN_F10R2_FB3_Msk (0x1U << CAN_F10R2_FB3_Pos) /*!< 0x00000008 */ #define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk /*!< Filter bit 3 */ -#define CAN_F10R2_FB4_Pos (4U) +#define CAN_F10R2_FB4_Pos (4U) #define CAN_F10R2_FB4_Msk (0x1U << CAN_F10R2_FB4_Pos) /*!< 0x00000010 */ #define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk /*!< Filter bit 4 */ -#define CAN_F10R2_FB5_Pos (5U) +#define CAN_F10R2_FB5_Pos (5U) #define CAN_F10R2_FB5_Msk (0x1U << CAN_F10R2_FB5_Pos) /*!< 0x00000020 */ #define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk /*!< Filter bit 5 */ -#define CAN_F10R2_FB6_Pos (6U) +#define CAN_F10R2_FB6_Pos (6U) #define CAN_F10R2_FB6_Msk (0x1U << CAN_F10R2_FB6_Pos) /*!< 0x00000040 */ #define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk /*!< Filter bit 6 */ -#define CAN_F10R2_FB7_Pos (7U) +#define CAN_F10R2_FB7_Pos (7U) #define CAN_F10R2_FB7_Msk (0x1U << CAN_F10R2_FB7_Pos) /*!< 0x00000080 */ #define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk /*!< Filter bit 7 */ -#define CAN_F10R2_FB8_Pos (8U) +#define CAN_F10R2_FB8_Pos (8U) #define CAN_F10R2_FB8_Msk (0x1U << CAN_F10R2_FB8_Pos) /*!< 0x00000100 */ #define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk /*!< Filter bit 8 */ -#define CAN_F10R2_FB9_Pos (9U) +#define CAN_F10R2_FB9_Pos (9U) #define CAN_F10R2_FB9_Msk (0x1U << CAN_F10R2_FB9_Pos) /*!< 0x00000200 */ #define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk /*!< Filter bit 9 */ -#define CAN_F10R2_FB10_Pos (10U) +#define CAN_F10R2_FB10_Pos (10U) #define CAN_F10R2_FB10_Msk (0x1U << CAN_F10R2_FB10_Pos) /*!< 0x00000400 */ #define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk /*!< Filter bit 10 */ -#define CAN_F10R2_FB11_Pos (11U) +#define CAN_F10R2_FB11_Pos (11U) #define CAN_F10R2_FB11_Msk (0x1U << CAN_F10R2_FB11_Pos) /*!< 0x00000800 */ #define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk /*!< Filter bit 11 */ -#define CAN_F10R2_FB12_Pos (12U) +#define CAN_F10R2_FB12_Pos (12U) #define CAN_F10R2_FB12_Msk (0x1U << CAN_F10R2_FB12_Pos) /*!< 0x00001000 */ #define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk /*!< Filter bit 12 */ -#define CAN_F10R2_FB13_Pos (13U) +#define CAN_F10R2_FB13_Pos (13U) #define CAN_F10R2_FB13_Msk (0x1U << CAN_F10R2_FB13_Pos) /*!< 0x00002000 */ #define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk /*!< Filter bit 13 */ -#define CAN_F10R2_FB14_Pos (14U) +#define CAN_F10R2_FB14_Pos (14U) #define CAN_F10R2_FB14_Msk (0x1U << CAN_F10R2_FB14_Pos) /*!< 0x00004000 */ #define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk /*!< Filter bit 14 */ -#define CAN_F10R2_FB15_Pos (15U) +#define CAN_F10R2_FB15_Pos (15U) #define CAN_F10R2_FB15_Msk (0x1U << CAN_F10R2_FB15_Pos) /*!< 0x00008000 */ #define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk /*!< Filter bit 15 */ -#define CAN_F10R2_FB16_Pos (16U) +#define CAN_F10R2_FB16_Pos (16U) #define CAN_F10R2_FB16_Msk (0x1U << CAN_F10R2_FB16_Pos) /*!< 0x00010000 */ #define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk /*!< Filter bit 16 */ -#define CAN_F10R2_FB17_Pos (17U) +#define CAN_F10R2_FB17_Pos (17U) #define CAN_F10R2_FB17_Msk (0x1U << CAN_F10R2_FB17_Pos) /*!< 0x00020000 */ #define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk /*!< Filter bit 17 */ -#define CAN_F10R2_FB18_Pos (18U) +#define CAN_F10R2_FB18_Pos (18U) #define CAN_F10R2_FB18_Msk (0x1U << CAN_F10R2_FB18_Pos) /*!< 0x00040000 */ #define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk /*!< Filter bit 18 */ -#define CAN_F10R2_FB19_Pos (19U) +#define CAN_F10R2_FB19_Pos (19U) #define CAN_F10R2_FB19_Msk (0x1U << CAN_F10R2_FB19_Pos) /*!< 0x00080000 */ #define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk /*!< Filter bit 19 */ -#define CAN_F10R2_FB20_Pos (20U) +#define CAN_F10R2_FB20_Pos (20U) #define CAN_F10R2_FB20_Msk (0x1U << CAN_F10R2_FB20_Pos) /*!< 0x00100000 */ #define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk /*!< Filter bit 20 */ -#define CAN_F10R2_FB21_Pos (21U) +#define CAN_F10R2_FB21_Pos (21U) #define CAN_F10R2_FB21_Msk (0x1U << CAN_F10R2_FB21_Pos) /*!< 0x00200000 */ #define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk /*!< Filter bit 21 */ -#define CAN_F10R2_FB22_Pos (22U) +#define CAN_F10R2_FB22_Pos (22U) #define CAN_F10R2_FB22_Msk (0x1U << CAN_F10R2_FB22_Pos) /*!< 0x00400000 */ #define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk /*!< Filter bit 22 */ -#define CAN_F10R2_FB23_Pos (23U) +#define CAN_F10R2_FB23_Pos (23U) #define CAN_F10R2_FB23_Msk (0x1U << CAN_F10R2_FB23_Pos) /*!< 0x00800000 */ #define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk /*!< Filter bit 23 */ -#define CAN_F10R2_FB24_Pos (24U) +#define CAN_F10R2_FB24_Pos (24U) #define CAN_F10R2_FB24_Msk (0x1U << CAN_F10R2_FB24_Pos) /*!< 0x01000000 */ #define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk /*!< Filter bit 24 */ -#define CAN_F10R2_FB25_Pos (25U) +#define CAN_F10R2_FB25_Pos (25U) #define CAN_F10R2_FB25_Msk (0x1U << CAN_F10R2_FB25_Pos) /*!< 0x02000000 */ #define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk /*!< Filter bit 25 */ -#define CAN_F10R2_FB26_Pos (26U) +#define CAN_F10R2_FB26_Pos (26U) #define CAN_F10R2_FB26_Msk (0x1U << CAN_F10R2_FB26_Pos) /*!< 0x04000000 */ #define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk /*!< Filter bit 26 */ -#define CAN_F10R2_FB27_Pos (27U) +#define CAN_F10R2_FB27_Pos (27U) #define CAN_F10R2_FB27_Msk (0x1U << CAN_F10R2_FB27_Pos) /*!< 0x08000000 */ #define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk /*!< Filter bit 27 */ -#define CAN_F10R2_FB28_Pos (28U) +#define CAN_F10R2_FB28_Pos (28U) #define CAN_F10R2_FB28_Msk (0x1U << CAN_F10R2_FB28_Pos) /*!< 0x10000000 */ #define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk /*!< Filter bit 28 */ -#define CAN_F10R2_FB29_Pos (29U) +#define CAN_F10R2_FB29_Pos (29U) #define CAN_F10R2_FB29_Msk (0x1U << CAN_F10R2_FB29_Pos) /*!< 0x20000000 */ #define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk /*!< Filter bit 29 */ -#define CAN_F10R2_FB30_Pos (30U) +#define CAN_F10R2_FB30_Pos (30U) #define CAN_F10R2_FB30_Msk (0x1U << CAN_F10R2_FB30_Pos) /*!< 0x40000000 */ #define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk /*!< Filter bit 30 */ -#define CAN_F10R2_FB31_Pos (31U) +#define CAN_F10R2_FB31_Pos (31U) #define CAN_F10R2_FB31_Msk (0x1U << CAN_F10R2_FB31_Pos) /*!< 0x80000000 */ #define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk /*!< Filter bit 31 */ /******************* Bit definition for CAN_F11R2 register ******************/ -#define CAN_F11R2_FB0_Pos (0U) +#define CAN_F11R2_FB0_Pos (0U) #define CAN_F11R2_FB0_Msk (0x1U << CAN_F11R2_FB0_Pos) /*!< 0x00000001 */ #define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk /*!< Filter bit 0 */ -#define CAN_F11R2_FB1_Pos (1U) +#define CAN_F11R2_FB1_Pos (1U) #define CAN_F11R2_FB1_Msk (0x1U << CAN_F11R2_FB1_Pos) /*!< 0x00000002 */ #define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk /*!< Filter bit 1 */ -#define CAN_F11R2_FB2_Pos (2U) +#define CAN_F11R2_FB2_Pos (2U) #define CAN_F11R2_FB2_Msk (0x1U << CAN_F11R2_FB2_Pos) /*!< 0x00000004 */ #define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk /*!< Filter bit 2 */ -#define CAN_F11R2_FB3_Pos (3U) +#define CAN_F11R2_FB3_Pos (3U) #define CAN_F11R2_FB3_Msk (0x1U << CAN_F11R2_FB3_Pos) /*!< 0x00000008 */ #define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk /*!< Filter bit 3 */ -#define CAN_F11R2_FB4_Pos (4U) +#define CAN_F11R2_FB4_Pos (4U) #define CAN_F11R2_FB4_Msk (0x1U << CAN_F11R2_FB4_Pos) /*!< 0x00000010 */ #define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk /*!< Filter bit 4 */ -#define CAN_F11R2_FB5_Pos (5U) +#define CAN_F11R2_FB5_Pos (5U) #define CAN_F11R2_FB5_Msk (0x1U << CAN_F11R2_FB5_Pos) /*!< 0x00000020 */ #define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk /*!< Filter bit 5 */ -#define CAN_F11R2_FB6_Pos (6U) +#define CAN_F11R2_FB6_Pos (6U) #define CAN_F11R2_FB6_Msk (0x1U << CAN_F11R2_FB6_Pos) /*!< 0x00000040 */ #define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk /*!< Filter bit 6 */ -#define CAN_F11R2_FB7_Pos (7U) +#define CAN_F11R2_FB7_Pos (7U) #define CAN_F11R2_FB7_Msk (0x1U << CAN_F11R2_FB7_Pos) /*!< 0x00000080 */ #define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk /*!< Filter bit 7 */ -#define CAN_F11R2_FB8_Pos (8U) +#define CAN_F11R2_FB8_Pos (8U) #define CAN_F11R2_FB8_Msk (0x1U << CAN_F11R2_FB8_Pos) /*!< 0x00000100 */ #define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk /*!< Filter bit 8 */ -#define CAN_F11R2_FB9_Pos (9U) +#define CAN_F11R2_FB9_Pos (9U) #define CAN_F11R2_FB9_Msk (0x1U << CAN_F11R2_FB9_Pos) /*!< 0x00000200 */ #define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk /*!< Filter bit 9 */ -#define CAN_F11R2_FB10_Pos (10U) +#define CAN_F11R2_FB10_Pos (10U) #define CAN_F11R2_FB10_Msk (0x1U << CAN_F11R2_FB10_Pos) /*!< 0x00000400 */ #define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk /*!< Filter bit 10 */ -#define CAN_F11R2_FB11_Pos (11U) +#define CAN_F11R2_FB11_Pos (11U) #define CAN_F11R2_FB11_Msk (0x1U << CAN_F11R2_FB11_Pos) /*!< 0x00000800 */ #define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk /*!< Filter bit 11 */ -#define CAN_F11R2_FB12_Pos (12U) +#define CAN_F11R2_FB12_Pos (12U) #define CAN_F11R2_FB12_Msk (0x1U << CAN_F11R2_FB12_Pos) /*!< 0x00001000 */ #define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk /*!< Filter bit 12 */ -#define CAN_F11R2_FB13_Pos (13U) +#define CAN_F11R2_FB13_Pos (13U) #define CAN_F11R2_FB13_Msk (0x1U << CAN_F11R2_FB13_Pos) /*!< 0x00002000 */ #define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk /*!< Filter bit 13 */ -#define CAN_F11R2_FB14_Pos (14U) +#define CAN_F11R2_FB14_Pos (14U) #define CAN_F11R2_FB14_Msk (0x1U << CAN_F11R2_FB14_Pos) /*!< 0x00004000 */ #define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk /*!< Filter bit 14 */ -#define CAN_F11R2_FB15_Pos (15U) +#define CAN_F11R2_FB15_Pos (15U) #define CAN_F11R2_FB15_Msk (0x1U << CAN_F11R2_FB15_Pos) /*!< 0x00008000 */ #define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk /*!< Filter bit 15 */ -#define CAN_F11R2_FB16_Pos (16U) +#define CAN_F11R2_FB16_Pos (16U) #define CAN_F11R2_FB16_Msk (0x1U << CAN_F11R2_FB16_Pos) /*!< 0x00010000 */ #define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk /*!< Filter bit 16 */ -#define CAN_F11R2_FB17_Pos (17U) +#define CAN_F11R2_FB17_Pos (17U) #define CAN_F11R2_FB17_Msk (0x1U << CAN_F11R2_FB17_Pos) /*!< 0x00020000 */ #define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk /*!< Filter bit 17 */ -#define CAN_F11R2_FB18_Pos (18U) +#define CAN_F11R2_FB18_Pos (18U) #define CAN_F11R2_FB18_Msk (0x1U << CAN_F11R2_FB18_Pos) /*!< 0x00040000 */ #define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk /*!< Filter bit 18 */ -#define CAN_F11R2_FB19_Pos (19U) +#define CAN_F11R2_FB19_Pos (19U) #define CAN_F11R2_FB19_Msk (0x1U << CAN_F11R2_FB19_Pos) /*!< 0x00080000 */ #define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk /*!< Filter bit 19 */ -#define CAN_F11R2_FB20_Pos (20U) +#define CAN_F11R2_FB20_Pos (20U) #define CAN_F11R2_FB20_Msk (0x1U << CAN_F11R2_FB20_Pos) /*!< 0x00100000 */ #define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk /*!< Filter bit 20 */ -#define CAN_F11R2_FB21_Pos (21U) +#define CAN_F11R2_FB21_Pos (21U) #define CAN_F11R2_FB21_Msk (0x1U << CAN_F11R2_FB21_Pos) /*!< 0x00200000 */ #define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk /*!< Filter bit 21 */ -#define CAN_F11R2_FB22_Pos (22U) +#define CAN_F11R2_FB22_Pos (22U) #define CAN_F11R2_FB22_Msk (0x1U << CAN_F11R2_FB22_Pos) /*!< 0x00400000 */ #define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk /*!< Filter bit 22 */ -#define CAN_F11R2_FB23_Pos (23U) +#define CAN_F11R2_FB23_Pos (23U) #define CAN_F11R2_FB23_Msk (0x1U << CAN_F11R2_FB23_Pos) /*!< 0x00800000 */ #define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk /*!< Filter bit 23 */ -#define CAN_F11R2_FB24_Pos (24U) +#define CAN_F11R2_FB24_Pos (24U) #define CAN_F11R2_FB24_Msk (0x1U << CAN_F11R2_FB24_Pos) /*!< 0x01000000 */ #define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk /*!< Filter bit 24 */ -#define CAN_F11R2_FB25_Pos (25U) +#define CAN_F11R2_FB25_Pos (25U) #define CAN_F11R2_FB25_Msk (0x1U << CAN_F11R2_FB25_Pos) /*!< 0x02000000 */ #define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk /*!< Filter bit 25 */ -#define CAN_F11R2_FB26_Pos (26U) +#define CAN_F11R2_FB26_Pos (26U) #define CAN_F11R2_FB26_Msk (0x1U << CAN_F11R2_FB26_Pos) /*!< 0x04000000 */ #define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk /*!< Filter bit 26 */ -#define CAN_F11R2_FB27_Pos (27U) +#define CAN_F11R2_FB27_Pos (27U) #define CAN_F11R2_FB27_Msk (0x1U << CAN_F11R2_FB27_Pos) /*!< 0x08000000 */ #define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk /*!< Filter bit 27 */ -#define CAN_F11R2_FB28_Pos (28U) +#define CAN_F11R2_FB28_Pos (28U) #define CAN_F11R2_FB28_Msk (0x1U << CAN_F11R2_FB28_Pos) /*!< 0x10000000 */ #define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk /*!< Filter bit 28 */ -#define CAN_F11R2_FB29_Pos (29U) +#define CAN_F11R2_FB29_Pos (29U) #define CAN_F11R2_FB29_Msk (0x1U << CAN_F11R2_FB29_Pos) /*!< 0x20000000 */ #define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk /*!< Filter bit 29 */ -#define CAN_F11R2_FB30_Pos (30U) +#define CAN_F11R2_FB30_Pos (30U) #define CAN_F11R2_FB30_Msk (0x1U << CAN_F11R2_FB30_Pos) /*!< 0x40000000 */ #define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk /*!< Filter bit 30 */ -#define CAN_F11R2_FB31_Pos (31U) +#define CAN_F11R2_FB31_Pos (31U) #define CAN_F11R2_FB31_Msk (0x1U << CAN_F11R2_FB31_Pos) /*!< 0x80000000 */ #define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk /*!< Filter bit 31 */ /******************* Bit definition for CAN_F12R2 register ******************/ -#define CAN_F12R2_FB0_Pos (0U) +#define CAN_F12R2_FB0_Pos (0U) #define CAN_F12R2_FB0_Msk (0x1U << CAN_F12R2_FB0_Pos) /*!< 0x00000001 */ #define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk /*!< Filter bit 0 */ -#define CAN_F12R2_FB1_Pos (1U) +#define CAN_F12R2_FB1_Pos (1U) #define CAN_F12R2_FB1_Msk (0x1U << CAN_F12R2_FB1_Pos) /*!< 0x00000002 */ #define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk /*!< Filter bit 1 */ -#define CAN_F12R2_FB2_Pos (2U) +#define CAN_F12R2_FB2_Pos (2U) #define CAN_F12R2_FB2_Msk (0x1U << CAN_F12R2_FB2_Pos) /*!< 0x00000004 */ #define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk /*!< Filter bit 2 */ -#define CAN_F12R2_FB3_Pos (3U) +#define CAN_F12R2_FB3_Pos (3U) #define CAN_F12R2_FB3_Msk (0x1U << CAN_F12R2_FB3_Pos) /*!< 0x00000008 */ #define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk /*!< Filter bit 3 */ -#define CAN_F12R2_FB4_Pos (4U) +#define CAN_F12R2_FB4_Pos (4U) #define CAN_F12R2_FB4_Msk (0x1U << CAN_F12R2_FB4_Pos) /*!< 0x00000010 */ #define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk /*!< Filter bit 4 */ -#define CAN_F12R2_FB5_Pos (5U) +#define CAN_F12R2_FB5_Pos (5U) #define CAN_F12R2_FB5_Msk (0x1U << CAN_F12R2_FB5_Pos) /*!< 0x00000020 */ #define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk /*!< Filter bit 5 */ -#define CAN_F12R2_FB6_Pos (6U) +#define CAN_F12R2_FB6_Pos (6U) #define CAN_F12R2_FB6_Msk (0x1U << CAN_F12R2_FB6_Pos) /*!< 0x00000040 */ #define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk /*!< Filter bit 6 */ -#define CAN_F12R2_FB7_Pos (7U) +#define CAN_F12R2_FB7_Pos (7U) #define CAN_F12R2_FB7_Msk (0x1U << CAN_F12R2_FB7_Pos) /*!< 0x00000080 */ #define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk /*!< Filter bit 7 */ -#define CAN_F12R2_FB8_Pos (8U) +#define CAN_F12R2_FB8_Pos (8U) #define CAN_F12R2_FB8_Msk (0x1U << CAN_F12R2_FB8_Pos) /*!< 0x00000100 */ #define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk /*!< Filter bit 8 */ -#define CAN_F12R2_FB9_Pos (9U) +#define CAN_F12R2_FB9_Pos (9U) #define CAN_F12R2_FB9_Msk (0x1U << CAN_F12R2_FB9_Pos) /*!< 0x00000200 */ #define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk /*!< Filter bit 9 */ -#define CAN_F12R2_FB10_Pos (10U) +#define CAN_F12R2_FB10_Pos (10U) #define CAN_F12R2_FB10_Msk (0x1U << CAN_F12R2_FB10_Pos) /*!< 0x00000400 */ #define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk /*!< Filter bit 10 */ -#define CAN_F12R2_FB11_Pos (11U) +#define CAN_F12R2_FB11_Pos (11U) #define CAN_F12R2_FB11_Msk (0x1U << CAN_F12R2_FB11_Pos) /*!< 0x00000800 */ #define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk /*!< Filter bit 11 */ -#define CAN_F12R2_FB12_Pos (12U) +#define CAN_F12R2_FB12_Pos (12U) #define CAN_F12R2_FB12_Msk (0x1U << CAN_F12R2_FB12_Pos) /*!< 0x00001000 */ #define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk /*!< Filter bit 12 */ -#define CAN_F12R2_FB13_Pos (13U) +#define CAN_F12R2_FB13_Pos (13U) #define CAN_F12R2_FB13_Msk (0x1U << CAN_F12R2_FB13_Pos) /*!< 0x00002000 */ #define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk /*!< Filter bit 13 */ -#define CAN_F12R2_FB14_Pos (14U) +#define CAN_F12R2_FB14_Pos (14U) #define CAN_F12R2_FB14_Msk (0x1U << CAN_F12R2_FB14_Pos) /*!< 0x00004000 */ #define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk /*!< Filter bit 14 */ -#define CAN_F12R2_FB15_Pos (15U) +#define CAN_F12R2_FB15_Pos (15U) #define CAN_F12R2_FB15_Msk (0x1U << CAN_F12R2_FB15_Pos) /*!< 0x00008000 */ #define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk /*!< Filter bit 15 */ -#define CAN_F12R2_FB16_Pos (16U) +#define CAN_F12R2_FB16_Pos (16U) #define CAN_F12R2_FB16_Msk (0x1U << CAN_F12R2_FB16_Pos) /*!< 0x00010000 */ #define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk /*!< Filter bit 16 */ -#define CAN_F12R2_FB17_Pos (17U) +#define CAN_F12R2_FB17_Pos (17U) #define CAN_F12R2_FB17_Msk (0x1U << CAN_F12R2_FB17_Pos) /*!< 0x00020000 */ #define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk /*!< Filter bit 17 */ -#define CAN_F12R2_FB18_Pos (18U) +#define CAN_F12R2_FB18_Pos (18U) #define CAN_F12R2_FB18_Msk (0x1U << CAN_F12R2_FB18_Pos) /*!< 0x00040000 */ #define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk /*!< Filter bit 18 */ -#define CAN_F12R2_FB19_Pos (19U) +#define CAN_F12R2_FB19_Pos (19U) #define CAN_F12R2_FB19_Msk (0x1U << CAN_F12R2_FB19_Pos) /*!< 0x00080000 */ #define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk /*!< Filter bit 19 */ -#define CAN_F12R2_FB20_Pos (20U) +#define CAN_F12R2_FB20_Pos (20U) #define CAN_F12R2_FB20_Msk (0x1U << CAN_F12R2_FB20_Pos) /*!< 0x00100000 */ #define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk /*!< Filter bit 20 */ -#define CAN_F12R2_FB21_Pos (21U) +#define CAN_F12R2_FB21_Pos (21U) #define CAN_F12R2_FB21_Msk (0x1U << CAN_F12R2_FB21_Pos) /*!< 0x00200000 */ #define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk /*!< Filter bit 21 */ -#define CAN_F12R2_FB22_Pos (22U) +#define CAN_F12R2_FB22_Pos (22U) #define CAN_F12R2_FB22_Msk (0x1U << CAN_F12R2_FB22_Pos) /*!< 0x00400000 */ #define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk /*!< Filter bit 22 */ -#define CAN_F12R2_FB23_Pos (23U) +#define CAN_F12R2_FB23_Pos (23U) #define CAN_F12R2_FB23_Msk (0x1U << CAN_F12R2_FB23_Pos) /*!< 0x00800000 */ #define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk /*!< Filter bit 23 */ -#define CAN_F12R2_FB24_Pos (24U) +#define CAN_F12R2_FB24_Pos (24U) #define CAN_F12R2_FB24_Msk (0x1U << CAN_F12R2_FB24_Pos) /*!< 0x01000000 */ #define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk /*!< Filter bit 24 */ -#define CAN_F12R2_FB25_Pos (25U) +#define CAN_F12R2_FB25_Pos (25U) #define CAN_F12R2_FB25_Msk (0x1U << CAN_F12R2_FB25_Pos) /*!< 0x02000000 */ #define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk /*!< Filter bit 25 */ -#define CAN_F12R2_FB26_Pos (26U) +#define CAN_F12R2_FB26_Pos (26U) #define CAN_F12R2_FB26_Msk (0x1U << CAN_F12R2_FB26_Pos) /*!< 0x04000000 */ #define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk /*!< Filter bit 26 */ -#define CAN_F12R2_FB27_Pos (27U) +#define CAN_F12R2_FB27_Pos (27U) #define CAN_F12R2_FB27_Msk (0x1U << CAN_F12R2_FB27_Pos) /*!< 0x08000000 */ #define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk /*!< Filter bit 27 */ -#define CAN_F12R2_FB28_Pos (28U) +#define CAN_F12R2_FB28_Pos (28U) #define CAN_F12R2_FB28_Msk (0x1U << CAN_F12R2_FB28_Pos) /*!< 0x10000000 */ #define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk /*!< Filter bit 28 */ -#define CAN_F12R2_FB29_Pos (29U) +#define CAN_F12R2_FB29_Pos (29U) #define CAN_F12R2_FB29_Msk (0x1U << CAN_F12R2_FB29_Pos) /*!< 0x20000000 */ #define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk /*!< Filter bit 29 */ -#define CAN_F12R2_FB30_Pos (30U) +#define CAN_F12R2_FB30_Pos (30U) #define CAN_F12R2_FB30_Msk (0x1U << CAN_F12R2_FB30_Pos) /*!< 0x40000000 */ #define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk /*!< Filter bit 30 */ -#define CAN_F12R2_FB31_Pos (31U) +#define CAN_F12R2_FB31_Pos (31U) #define CAN_F12R2_FB31_Msk (0x1U << CAN_F12R2_FB31_Pos) /*!< 0x80000000 */ #define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk /*!< Filter bit 31 */ /******************* Bit definition for CAN_F13R2 register ******************/ -#define CAN_F13R2_FB0_Pos (0U) +#define CAN_F13R2_FB0_Pos (0U) #define CAN_F13R2_FB0_Msk (0x1U << CAN_F13R2_FB0_Pos) /*!< 0x00000001 */ #define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk /*!< Filter bit 0 */ -#define CAN_F13R2_FB1_Pos (1U) +#define CAN_F13R2_FB1_Pos (1U) #define CAN_F13R2_FB1_Msk (0x1U << CAN_F13R2_FB1_Pos) /*!< 0x00000002 */ #define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk /*!< Filter bit 1 */ -#define CAN_F13R2_FB2_Pos (2U) +#define CAN_F13R2_FB2_Pos (2U) #define CAN_F13R2_FB2_Msk (0x1U << CAN_F13R2_FB2_Pos) /*!< 0x00000004 */ #define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk /*!< Filter bit 2 */ -#define CAN_F13R2_FB3_Pos (3U) +#define CAN_F13R2_FB3_Pos (3U) #define CAN_F13R2_FB3_Msk (0x1U << CAN_F13R2_FB3_Pos) /*!< 0x00000008 */ #define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk /*!< Filter bit 3 */ -#define CAN_F13R2_FB4_Pos (4U) +#define CAN_F13R2_FB4_Pos (4U) #define CAN_F13R2_FB4_Msk (0x1U << CAN_F13R2_FB4_Pos) /*!< 0x00000010 */ #define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk /*!< Filter bit 4 */ -#define CAN_F13R2_FB5_Pos (5U) +#define CAN_F13R2_FB5_Pos (5U) #define CAN_F13R2_FB5_Msk (0x1U << CAN_F13R2_FB5_Pos) /*!< 0x00000020 */ #define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk /*!< Filter bit 5 */ -#define CAN_F13R2_FB6_Pos (6U) +#define CAN_F13R2_FB6_Pos (6U) #define CAN_F13R2_FB6_Msk (0x1U << CAN_F13R2_FB6_Pos) /*!< 0x00000040 */ #define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk /*!< Filter bit 6 */ -#define CAN_F13R2_FB7_Pos (7U) +#define CAN_F13R2_FB7_Pos (7U) #define CAN_F13R2_FB7_Msk (0x1U << CAN_F13R2_FB7_Pos) /*!< 0x00000080 */ #define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk /*!< Filter bit 7 */ -#define CAN_F13R2_FB8_Pos (8U) +#define CAN_F13R2_FB8_Pos (8U) #define CAN_F13R2_FB8_Msk (0x1U << CAN_F13R2_FB8_Pos) /*!< 0x00000100 */ #define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk /*!< Filter bit 8 */ -#define CAN_F13R2_FB9_Pos (9U) +#define CAN_F13R2_FB9_Pos (9U) #define CAN_F13R2_FB9_Msk (0x1U << CAN_F13R2_FB9_Pos) /*!< 0x00000200 */ #define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk /*!< Filter bit 9 */ -#define CAN_F13R2_FB10_Pos (10U) +#define CAN_F13R2_FB10_Pos (10U) #define CAN_F13R2_FB10_Msk (0x1U << CAN_F13R2_FB10_Pos) /*!< 0x00000400 */ #define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk /*!< Filter bit 10 */ -#define CAN_F13R2_FB11_Pos (11U) +#define CAN_F13R2_FB11_Pos (11U) #define CAN_F13R2_FB11_Msk (0x1U << CAN_F13R2_FB11_Pos) /*!< 0x00000800 */ #define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk /*!< Filter bit 11 */ -#define CAN_F13R2_FB12_Pos (12U) +#define CAN_F13R2_FB12_Pos (12U) #define CAN_F13R2_FB12_Msk (0x1U << CAN_F13R2_FB12_Pos) /*!< 0x00001000 */ #define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk /*!< Filter bit 12 */ -#define CAN_F13R2_FB13_Pos (13U) +#define CAN_F13R2_FB13_Pos (13U) #define CAN_F13R2_FB13_Msk (0x1U << CAN_F13R2_FB13_Pos) /*!< 0x00002000 */ #define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk /*!< Filter bit 13 */ -#define CAN_F13R2_FB14_Pos (14U) +#define CAN_F13R2_FB14_Pos (14U) #define CAN_F13R2_FB14_Msk (0x1U << CAN_F13R2_FB14_Pos) /*!< 0x00004000 */ #define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk /*!< Filter bit 14 */ -#define CAN_F13R2_FB15_Pos (15U) +#define CAN_F13R2_FB15_Pos (15U) #define CAN_F13R2_FB15_Msk (0x1U << CAN_F13R2_FB15_Pos) /*!< 0x00008000 */ #define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk /*!< Filter bit 15 */ -#define CAN_F13R2_FB16_Pos (16U) +#define CAN_F13R2_FB16_Pos (16U) #define CAN_F13R2_FB16_Msk (0x1U << CAN_F13R2_FB16_Pos) /*!< 0x00010000 */ #define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk /*!< Filter bit 16 */ -#define CAN_F13R2_FB17_Pos (17U) +#define CAN_F13R2_FB17_Pos (17U) #define CAN_F13R2_FB17_Msk (0x1U << CAN_F13R2_FB17_Pos) /*!< 0x00020000 */ #define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk /*!< Filter bit 17 */ -#define CAN_F13R2_FB18_Pos (18U) +#define CAN_F13R2_FB18_Pos (18U) #define CAN_F13R2_FB18_Msk (0x1U << CAN_F13R2_FB18_Pos) /*!< 0x00040000 */ #define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk /*!< Filter bit 18 */ -#define CAN_F13R2_FB19_Pos (19U) +#define CAN_F13R2_FB19_Pos (19U) #define CAN_F13R2_FB19_Msk (0x1U << CAN_F13R2_FB19_Pos) /*!< 0x00080000 */ #define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk /*!< Filter bit 19 */ -#define CAN_F13R2_FB20_Pos (20U) +#define CAN_F13R2_FB20_Pos (20U) #define CAN_F13R2_FB20_Msk (0x1U << CAN_F13R2_FB20_Pos) /*!< 0x00100000 */ #define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk /*!< Filter bit 20 */ -#define CAN_F13R2_FB21_Pos (21U) +#define CAN_F13R2_FB21_Pos (21U) #define CAN_F13R2_FB21_Msk (0x1U << CAN_F13R2_FB21_Pos) /*!< 0x00200000 */ #define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk /*!< Filter bit 21 */ -#define CAN_F13R2_FB22_Pos (22U) +#define CAN_F13R2_FB22_Pos (22U) #define CAN_F13R2_FB22_Msk (0x1U << CAN_F13R2_FB22_Pos) /*!< 0x00400000 */ #define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk /*!< Filter bit 22 */ -#define CAN_F13R2_FB23_Pos (23U) +#define CAN_F13R2_FB23_Pos (23U) #define CAN_F13R2_FB23_Msk (0x1U << CAN_F13R2_FB23_Pos) /*!< 0x00800000 */ #define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk /*!< Filter bit 23 */ -#define CAN_F13R2_FB24_Pos (24U) +#define CAN_F13R2_FB24_Pos (24U) #define CAN_F13R2_FB24_Msk (0x1U << CAN_F13R2_FB24_Pos) /*!< 0x01000000 */ #define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk /*!< Filter bit 24 */ -#define CAN_F13R2_FB25_Pos (25U) +#define CAN_F13R2_FB25_Pos (25U) #define CAN_F13R2_FB25_Msk (0x1U << CAN_F13R2_FB25_Pos) /*!< 0x02000000 */ #define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk /*!< Filter bit 25 */ -#define CAN_F13R2_FB26_Pos (26U) +#define CAN_F13R2_FB26_Pos (26U) #define CAN_F13R2_FB26_Msk (0x1U << CAN_F13R2_FB26_Pos) /*!< 0x04000000 */ #define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk /*!< Filter bit 26 */ -#define CAN_F13R2_FB27_Pos (27U) +#define CAN_F13R2_FB27_Pos (27U) #define CAN_F13R2_FB27_Msk (0x1U << CAN_F13R2_FB27_Pos) /*!< 0x08000000 */ #define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk /*!< Filter bit 27 */ -#define CAN_F13R2_FB28_Pos (28U) +#define CAN_F13R2_FB28_Pos (28U) #define CAN_F13R2_FB28_Msk (0x1U << CAN_F13R2_FB28_Pos) /*!< 0x10000000 */ #define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk /*!< Filter bit 28 */ -#define CAN_F13R2_FB29_Pos (29U) +#define CAN_F13R2_FB29_Pos (29U) #define CAN_F13R2_FB29_Msk (0x1U << CAN_F13R2_FB29_Pos) /*!< 0x20000000 */ #define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk /*!< Filter bit 29 */ -#define CAN_F13R2_FB30_Pos (30U) +#define CAN_F13R2_FB30_Pos (30U) #define CAN_F13R2_FB30_Msk (0x1U << CAN_F13R2_FB30_Pos) /*!< 0x40000000 */ #define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk /*!< Filter bit 30 */ -#define CAN_F13R2_FB31_Pos (31U) +#define CAN_F13R2_FB31_Pos (31U) #define CAN_F13R2_FB31_Msk (0x1U << CAN_F13R2_FB31_Pos) /*!< 0x80000000 */ #define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk /*!< Filter bit 31 */ @@ -9877,122 +9877,122 @@ typedef struct /******************************************************************************/ /******************* Bit definition for SPI_CR1 register ********************/ -#define SPI_CR1_CPHA_Pos (0U) +#define SPI_CR1_CPHA_Pos (0U) #define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */ #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */ -#define SPI_CR1_CPOL_Pos (1U) +#define SPI_CR1_CPOL_Pos (1U) #define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */ #define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!< Clock Polarity */ -#define SPI_CR1_MSTR_Pos (2U) +#define SPI_CR1_MSTR_Pos (2U) #define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */ #define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!< Master Selection */ -#define SPI_CR1_BR_Pos (3U) +#define SPI_CR1_BR_Pos (3U) #define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */ #define SPI_CR1_BR SPI_CR1_BR_Msk /*!< BR[2:0] bits (Baud Rate Control) */ #define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */ #define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */ #define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */ -#define SPI_CR1_SPE_Pos (6U) +#define SPI_CR1_SPE_Pos (6U) #define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */ #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */ -#define SPI_CR1_LSBFIRST_Pos (7U) +#define SPI_CR1_LSBFIRST_Pos (7U) #define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */ #define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!< Frame Format */ -#define SPI_CR1_SSI_Pos (8U) +#define SPI_CR1_SSI_Pos (8U) #define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */ #define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!< Internal slave select */ -#define SPI_CR1_SSM_Pos (9U) +#define SPI_CR1_SSM_Pos (9U) #define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */ #define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!< Software slave management */ -#define SPI_CR1_RXONLY_Pos (10U) +#define SPI_CR1_RXONLY_Pos (10U) #define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */ #define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!< Receive only */ -#define SPI_CR1_DFF_Pos (11U) +#define SPI_CR1_DFF_Pos (11U) #define SPI_CR1_DFF_Msk (0x1U << SPI_CR1_DFF_Pos) /*!< 0x00000800 */ #define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!< Data Frame Format */ -#define SPI_CR1_CRCNEXT_Pos (12U) +#define SPI_CR1_CRCNEXT_Pos (12U) #define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */ #define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!< Transmit CRC next */ -#define SPI_CR1_CRCEN_Pos (13U) +#define SPI_CR1_CRCEN_Pos (13U) #define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */ #define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!< Hardware CRC calculation enable */ -#define SPI_CR1_BIDIOE_Pos (14U) +#define SPI_CR1_BIDIOE_Pos (14U) #define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */ #define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!< Output enable in bidirectional mode */ -#define SPI_CR1_BIDIMODE_Pos (15U) +#define SPI_CR1_BIDIMODE_Pos (15U) #define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */ #define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!< Bidirectional data mode enable */ /******************* Bit definition for SPI_CR2 register ********************/ -#define SPI_CR2_RXDMAEN_Pos (0U) +#define SPI_CR2_RXDMAEN_Pos (0U) #define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */ #define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */ -#define SPI_CR2_TXDMAEN_Pos (1U) +#define SPI_CR2_TXDMAEN_Pos (1U) #define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */ #define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */ -#define SPI_CR2_SSOE_Pos (2U) +#define SPI_CR2_SSOE_Pos (2U) #define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */ #define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */ -#define SPI_CR2_ERRIE_Pos (5U) +#define SPI_CR2_ERRIE_Pos (5U) #define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */ #define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */ -#define SPI_CR2_RXNEIE_Pos (6U) +#define SPI_CR2_RXNEIE_Pos (6U) #define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */ #define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */ -#define SPI_CR2_TXEIE_Pos (7U) +#define SPI_CR2_TXEIE_Pos (7U) #define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */ #define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */ /******************** Bit definition for SPI_SR register ********************/ -#define SPI_SR_RXNE_Pos (0U) +#define SPI_SR_RXNE_Pos (0U) #define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */ #define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */ -#define SPI_SR_TXE_Pos (1U) +#define SPI_SR_TXE_Pos (1U) #define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */ #define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */ -#define SPI_SR_CHSIDE_Pos (2U) +#define SPI_SR_CHSIDE_Pos (2U) #define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */ #define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */ -#define SPI_SR_UDR_Pos (3U) +#define SPI_SR_UDR_Pos (3U) #define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */ #define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */ -#define SPI_SR_CRCERR_Pos (4U) +#define SPI_SR_CRCERR_Pos (4U) #define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */ #define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */ -#define SPI_SR_MODF_Pos (5U) +#define SPI_SR_MODF_Pos (5U) #define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */ #define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */ -#define SPI_SR_OVR_Pos (6U) +#define SPI_SR_OVR_Pos (6U) #define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */ #define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */ -#define SPI_SR_BSY_Pos (7U) +#define SPI_SR_BSY_Pos (7U) #define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */ #define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */ /******************** Bit definition for SPI_DR register ********************/ -#define SPI_DR_DR_Pos (0U) +#define SPI_DR_DR_Pos (0U) #define SPI_DR_DR_Msk (0xFFFFU << SPI_DR_DR_Pos) /*!< 0x0000FFFF */ #define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */ /******************* Bit definition for SPI_CRCPR register ******************/ -#define SPI_CRCPR_CRCPOLY_Pos (0U) +#define SPI_CRCPR_CRCPOLY_Pos (0U) #define SPI_CRCPR_CRCPOLY_Msk (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */ #define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!< CRC polynomial register */ /****************** Bit definition for SPI_RXCRCR register ******************/ -#define SPI_RXCRCR_RXCRC_Pos (0U) +#define SPI_RXCRCR_RXCRC_Pos (0U) #define SPI_RXCRCR_RXCRC_Msk (0xFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */ #define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!< Rx CRC Register */ /****************** Bit definition for SPI_TXCRCR register ******************/ -#define SPI_TXCRCR_TXCRC_Pos (0U) +#define SPI_TXCRCR_TXCRC_Pos (0U) #define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */ #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */ /****************** Bit definition for SPI_I2SCFGR register *****************/ -#define SPI_I2SCFGR_I2SMOD_Pos (11U) +#define SPI_I2SCFGR_I2SMOD_Pos (11U) #define SPI_I2SCFGR_I2SMOD_Msk (0x1U << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */ #define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!< I2S mode selection */ @@ -10004,51 +10004,51 @@ typedef struct /******************************************************************************/ /******************* Bit definition for I2C_CR1 register ********************/ -#define I2C_CR1_PE_Pos (0U) +#define I2C_CR1_PE_Pos (0U) #define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */ #define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral Enable */ -#define I2C_CR1_SMBUS_Pos (1U) +#define I2C_CR1_SMBUS_Pos (1U) #define I2C_CR1_SMBUS_Msk (0x1U << I2C_CR1_SMBUS_Pos) /*!< 0x00000002 */ #define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk /*!< SMBus Mode */ -#define I2C_CR1_SMBTYPE_Pos (3U) +#define I2C_CR1_SMBTYPE_Pos (3U) #define I2C_CR1_SMBTYPE_Msk (0x1U << I2C_CR1_SMBTYPE_Pos) /*!< 0x00000008 */ #define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk /*!< SMBus Type */ -#define I2C_CR1_ENARP_Pos (4U) +#define I2C_CR1_ENARP_Pos (4U) #define I2C_CR1_ENARP_Msk (0x1U << I2C_CR1_ENARP_Pos) /*!< 0x00000010 */ #define I2C_CR1_ENARP I2C_CR1_ENARP_Msk /*!< ARP Enable */ -#define I2C_CR1_ENPEC_Pos (5U) +#define I2C_CR1_ENPEC_Pos (5U) #define I2C_CR1_ENPEC_Msk (0x1U << I2C_CR1_ENPEC_Pos) /*!< 0x00000020 */ #define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk /*!< PEC Enable */ -#define I2C_CR1_ENGC_Pos (6U) +#define I2C_CR1_ENGC_Pos (6U) #define I2C_CR1_ENGC_Msk (0x1U << I2C_CR1_ENGC_Pos) /*!< 0x00000040 */ #define I2C_CR1_ENGC I2C_CR1_ENGC_Msk /*!< General Call Enable */ -#define I2C_CR1_NOSTRETCH_Pos (7U) +#define I2C_CR1_NOSTRETCH_Pos (7U) #define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00000080 */ #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock Stretching Disable (Slave mode) */ -#define I2C_CR1_START_Pos (8U) +#define I2C_CR1_START_Pos (8U) #define I2C_CR1_START_Msk (0x1U << I2C_CR1_START_Pos) /*!< 0x00000100 */ #define I2C_CR1_START I2C_CR1_START_Msk /*!< Start Generation */ -#define I2C_CR1_STOP_Pos (9U) +#define I2C_CR1_STOP_Pos (9U) #define I2C_CR1_STOP_Msk (0x1U << I2C_CR1_STOP_Pos) /*!< 0x00000200 */ #define I2C_CR1_STOP I2C_CR1_STOP_Msk /*!< Stop Generation */ -#define I2C_CR1_ACK_Pos (10U) +#define I2C_CR1_ACK_Pos (10U) #define I2C_CR1_ACK_Msk (0x1U << I2C_CR1_ACK_Pos) /*!< 0x00000400 */ #define I2C_CR1_ACK I2C_CR1_ACK_Msk /*!< Acknowledge Enable */ -#define I2C_CR1_POS_Pos (11U) +#define I2C_CR1_POS_Pos (11U) #define I2C_CR1_POS_Msk (0x1U << I2C_CR1_POS_Pos) /*!< 0x00000800 */ #define I2C_CR1_POS I2C_CR1_POS_Msk /*!< Acknowledge/PEC Position (for data reception) */ -#define I2C_CR1_PEC_Pos (12U) +#define I2C_CR1_PEC_Pos (12U) #define I2C_CR1_PEC_Msk (0x1U << I2C_CR1_PEC_Pos) /*!< 0x00001000 */ #define I2C_CR1_PEC I2C_CR1_PEC_Msk /*!< Packet Error Checking */ -#define I2C_CR1_ALERT_Pos (13U) +#define I2C_CR1_ALERT_Pos (13U) #define I2C_CR1_ALERT_Msk (0x1U << I2C_CR1_ALERT_Pos) /*!< 0x00002000 */ #define I2C_CR1_ALERT I2C_CR1_ALERT_Msk /*!< SMBus Alert */ -#define I2C_CR1_SWRST_Pos (15U) +#define I2C_CR1_SWRST_Pos (15U) #define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /*!< 0x00008000 */ #define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software Reset */ /******************* Bit definition for I2C_CR2 register ********************/ -#define I2C_CR2_FREQ_Pos (0U) +#define I2C_CR2_FREQ_Pos (0U) #define I2C_CR2_FREQ_Msk (0x3FU << I2C_CR2_FREQ_Pos) /*!< 0x0000003F */ #define I2C_CR2_FREQ I2C_CR2_FREQ_Msk /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */ #define I2C_CR2_FREQ_0 (0x01U << I2C_CR2_FREQ_Pos) /*!< 0x00000001 */ @@ -10058,19 +10058,19 @@ typedef struct #define I2C_CR2_FREQ_4 (0x10U << I2C_CR2_FREQ_Pos) /*!< 0x00000010 */ #define I2C_CR2_FREQ_5 (0x20U << I2C_CR2_FREQ_Pos) /*!< 0x00000020 */ -#define I2C_CR2_ITERREN_Pos (8U) +#define I2C_CR2_ITERREN_Pos (8U) #define I2C_CR2_ITERREN_Msk (0x1U << I2C_CR2_ITERREN_Pos) /*!< 0x00000100 */ #define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk /*!< Error Interrupt Enable */ -#define I2C_CR2_ITEVTEN_Pos (9U) +#define I2C_CR2_ITEVTEN_Pos (9U) #define I2C_CR2_ITEVTEN_Msk (0x1U << I2C_CR2_ITEVTEN_Pos) /*!< 0x00000200 */ #define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk /*!< Event Interrupt Enable */ -#define I2C_CR2_ITBUFEN_Pos (10U) +#define I2C_CR2_ITBUFEN_Pos (10U) #define I2C_CR2_ITBUFEN_Msk (0x1U << I2C_CR2_ITBUFEN_Pos) /*!< 0x00000400 */ #define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk /*!< Buffer Interrupt Enable */ -#define I2C_CR2_DMAEN_Pos (11U) +#define I2C_CR2_DMAEN_Pos (11U) #define I2C_CR2_DMAEN_Msk (0x1U << I2C_CR2_DMAEN_Pos) /*!< 0x00000800 */ #define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk /*!< DMA Requests Enable */ -#define I2C_CR2_LAST_Pos (12U) +#define I2C_CR2_LAST_Pos (12U) #define I2C_CR2_LAST_Msk (0x1U << I2C_CR2_LAST_Pos) /*!< 0x00001000 */ #define I2C_CR2_LAST I2C_CR2_LAST_Msk /*!< DMA Last Transfer */ @@ -10078,132 +10078,132 @@ typedef struct #define I2C_OAR1_ADD1_7 ((uint32_t)0x000000FE) /*!< Interface Address */ #define I2C_OAR1_ADD8_9 ((uint32_t)0x00000300) /*!< Interface Address */ -#define I2C_OAR1_ADD0_Pos (0U) +#define I2C_OAR1_ADD0_Pos (0U) #define I2C_OAR1_ADD0_Msk (0x1U << I2C_OAR1_ADD0_Pos) /*!< 0x00000001 */ #define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk /*!< Bit 0 */ -#define I2C_OAR1_ADD1_Pos (1U) +#define I2C_OAR1_ADD1_Pos (1U) #define I2C_OAR1_ADD1_Msk (0x1U << I2C_OAR1_ADD1_Pos) /*!< 0x00000002 */ #define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk /*!< Bit 1 */ -#define I2C_OAR1_ADD2_Pos (2U) +#define I2C_OAR1_ADD2_Pos (2U) #define I2C_OAR1_ADD2_Msk (0x1U << I2C_OAR1_ADD2_Pos) /*!< 0x00000004 */ #define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk /*!< Bit 2 */ -#define I2C_OAR1_ADD3_Pos (3U) +#define I2C_OAR1_ADD3_Pos (3U) #define I2C_OAR1_ADD3_Msk (0x1U << I2C_OAR1_ADD3_Pos) /*!< 0x00000008 */ #define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk /*!< Bit 3 */ -#define I2C_OAR1_ADD4_Pos (4U) +#define I2C_OAR1_ADD4_Pos (4U) #define I2C_OAR1_ADD4_Msk (0x1U << I2C_OAR1_ADD4_Pos) /*!< 0x00000010 */ #define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk /*!< Bit 4 */ -#define I2C_OAR1_ADD5_Pos (5U) +#define I2C_OAR1_ADD5_Pos (5U) #define I2C_OAR1_ADD5_Msk (0x1U << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */ #define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk /*!< Bit 5 */ -#define I2C_OAR1_ADD6_Pos (6U) +#define I2C_OAR1_ADD6_Pos (6U) #define I2C_OAR1_ADD6_Msk (0x1U << I2C_OAR1_ADD6_Pos) /*!< 0x00000040 */ #define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk /*!< Bit 6 */ -#define I2C_OAR1_ADD7_Pos (7U) +#define I2C_OAR1_ADD7_Pos (7U) #define I2C_OAR1_ADD7_Msk (0x1U << I2C_OAR1_ADD7_Pos) /*!< 0x00000080 */ #define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk /*!< Bit 7 */ -#define I2C_OAR1_ADD8_Pos (8U) +#define I2C_OAR1_ADD8_Pos (8U) #define I2C_OAR1_ADD8_Msk (0x1U << I2C_OAR1_ADD8_Pos) /*!< 0x00000100 */ #define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk /*!< Bit 8 */ -#define I2C_OAR1_ADD9_Pos (9U) +#define I2C_OAR1_ADD9_Pos (9U) #define I2C_OAR1_ADD9_Msk (0x1U << I2C_OAR1_ADD9_Pos) /*!< 0x00000200 */ #define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk /*!< Bit 9 */ -#define I2C_OAR1_ADDMODE_Pos (15U) +#define I2C_OAR1_ADDMODE_Pos (15U) #define I2C_OAR1_ADDMODE_Msk (0x1U << I2C_OAR1_ADDMODE_Pos) /*!< 0x00008000 */ #define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk /*!< Addressing Mode (Slave mode) */ /******************* Bit definition for I2C_OAR2 register *******************/ -#define I2C_OAR2_ENDUAL_Pos (0U) +#define I2C_OAR2_ENDUAL_Pos (0U) #define I2C_OAR2_ENDUAL_Msk (0x1U << I2C_OAR2_ENDUAL_Pos) /*!< 0x00000001 */ #define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk /*!< Dual addressing mode enable */ -#define I2C_OAR2_ADD2_Pos (1U) +#define I2C_OAR2_ADD2_Pos (1U) #define I2C_OAR2_ADD2_Msk (0x7FU << I2C_OAR2_ADD2_Pos) /*!< 0x000000FE */ #define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /*!< Interface address */ /******************* Bit definition for I2C_SR1 register ********************/ -#define I2C_SR1_SB_Pos (0U) +#define I2C_SR1_SB_Pos (0U) #define I2C_SR1_SB_Msk (0x1U << I2C_SR1_SB_Pos) /*!< 0x00000001 */ #define I2C_SR1_SB I2C_SR1_SB_Msk /*!< Start Bit (Master mode) */ -#define I2C_SR1_ADDR_Pos (1U) +#define I2C_SR1_ADDR_Pos (1U) #define I2C_SR1_ADDR_Msk (0x1U << I2C_SR1_ADDR_Pos) /*!< 0x00000002 */ #define I2C_SR1_ADDR I2C_SR1_ADDR_Msk /*!< Address sent (master mode)/matched (slave mode) */ -#define I2C_SR1_BTF_Pos (2U) +#define I2C_SR1_BTF_Pos (2U) #define I2C_SR1_BTF_Msk (0x1U << I2C_SR1_BTF_Pos) /*!< 0x00000004 */ #define I2C_SR1_BTF I2C_SR1_BTF_Msk /*!< Byte Transfer Finished */ -#define I2C_SR1_ADD10_Pos (3U) +#define I2C_SR1_ADD10_Pos (3U) #define I2C_SR1_ADD10_Msk (0x1U << I2C_SR1_ADD10_Pos) /*!< 0x00000008 */ #define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk /*!< 10-bit header sent (Master mode) */ -#define I2C_SR1_STOPF_Pos (4U) +#define I2C_SR1_STOPF_Pos (4U) #define I2C_SR1_STOPF_Msk (0x1U << I2C_SR1_STOPF_Pos) /*!< 0x00000010 */ #define I2C_SR1_STOPF I2C_SR1_STOPF_Msk /*!< Stop detection (Slave mode) */ -#define I2C_SR1_RXNE_Pos (6U) +#define I2C_SR1_RXNE_Pos (6U) #define I2C_SR1_RXNE_Msk (0x1U << I2C_SR1_RXNE_Pos) /*!< 0x00000040 */ #define I2C_SR1_RXNE I2C_SR1_RXNE_Msk /*!< Data Register not Empty (receivers) */ -#define I2C_SR1_TXE_Pos (7U) +#define I2C_SR1_TXE_Pos (7U) #define I2C_SR1_TXE_Msk (0x1U << I2C_SR1_TXE_Pos) /*!< 0x00000080 */ #define I2C_SR1_TXE I2C_SR1_TXE_Msk /*!< Data Register Empty (transmitters) */ -#define I2C_SR1_BERR_Pos (8U) +#define I2C_SR1_BERR_Pos (8U) #define I2C_SR1_BERR_Msk (0x1U << I2C_SR1_BERR_Pos) /*!< 0x00000100 */ #define I2C_SR1_BERR I2C_SR1_BERR_Msk /*!< Bus Error */ -#define I2C_SR1_ARLO_Pos (9U) +#define I2C_SR1_ARLO_Pos (9U) #define I2C_SR1_ARLO_Msk (0x1U << I2C_SR1_ARLO_Pos) /*!< 0x00000200 */ #define I2C_SR1_ARLO I2C_SR1_ARLO_Msk /*!< Arbitration Lost (master mode) */ -#define I2C_SR1_AF_Pos (10U) +#define I2C_SR1_AF_Pos (10U) #define I2C_SR1_AF_Msk (0x1U << I2C_SR1_AF_Pos) /*!< 0x00000400 */ #define I2C_SR1_AF I2C_SR1_AF_Msk /*!< Acknowledge Failure */ -#define I2C_SR1_OVR_Pos (11U) +#define I2C_SR1_OVR_Pos (11U) #define I2C_SR1_OVR_Msk (0x1U << I2C_SR1_OVR_Pos) /*!< 0x00000800 */ #define I2C_SR1_OVR I2C_SR1_OVR_Msk /*!< Overrun/Underrun */ -#define I2C_SR1_PECERR_Pos (12U) +#define I2C_SR1_PECERR_Pos (12U) #define I2C_SR1_PECERR_Msk (0x1U << I2C_SR1_PECERR_Pos) /*!< 0x00001000 */ #define I2C_SR1_PECERR I2C_SR1_PECERR_Msk /*!< PEC Error in reception */ -#define I2C_SR1_TIMEOUT_Pos (14U) +#define I2C_SR1_TIMEOUT_Pos (14U) #define I2C_SR1_TIMEOUT_Msk (0x1U << I2C_SR1_TIMEOUT_Pos) /*!< 0x00004000 */ #define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk /*!< Timeout or Tlow Error */ -#define I2C_SR1_SMBALERT_Pos (15U) +#define I2C_SR1_SMBALERT_Pos (15U) #define I2C_SR1_SMBALERT_Msk (0x1U << I2C_SR1_SMBALERT_Pos) /*!< 0x00008000 */ #define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk /*!< SMBus Alert */ /******************* Bit definition for I2C_SR2 register ********************/ -#define I2C_SR2_MSL_Pos (0U) +#define I2C_SR2_MSL_Pos (0U) #define I2C_SR2_MSL_Msk (0x1U << I2C_SR2_MSL_Pos) /*!< 0x00000001 */ #define I2C_SR2_MSL I2C_SR2_MSL_Msk /*!< Master/Slave */ -#define I2C_SR2_BUSY_Pos (1U) +#define I2C_SR2_BUSY_Pos (1U) #define I2C_SR2_BUSY_Msk (0x1U << I2C_SR2_BUSY_Pos) /*!< 0x00000002 */ #define I2C_SR2_BUSY I2C_SR2_BUSY_Msk /*!< Bus Busy */ -#define I2C_SR2_TRA_Pos (2U) +#define I2C_SR2_TRA_Pos (2U) #define I2C_SR2_TRA_Msk (0x1U << I2C_SR2_TRA_Pos) /*!< 0x00000004 */ #define I2C_SR2_TRA I2C_SR2_TRA_Msk /*!< Transmitter/Receiver */ -#define I2C_SR2_GENCALL_Pos (4U) +#define I2C_SR2_GENCALL_Pos (4U) #define I2C_SR2_GENCALL_Msk (0x1U << I2C_SR2_GENCALL_Pos) /*!< 0x00000010 */ #define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk /*!< General Call Address (Slave mode) */ -#define I2C_SR2_SMBDEFAULT_Pos (5U) +#define I2C_SR2_SMBDEFAULT_Pos (5U) #define I2C_SR2_SMBDEFAULT_Msk (0x1U << I2C_SR2_SMBDEFAULT_Pos) /*!< 0x00000020 */ #define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk /*!< SMBus Device Default Address (Slave mode) */ -#define I2C_SR2_SMBHOST_Pos (6U) +#define I2C_SR2_SMBHOST_Pos (6U) #define I2C_SR2_SMBHOST_Msk (0x1U << I2C_SR2_SMBHOST_Pos) /*!< 0x00000040 */ #define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk /*!< SMBus Host Header (Slave mode) */ -#define I2C_SR2_DUALF_Pos (7U) +#define I2C_SR2_DUALF_Pos (7U) #define I2C_SR2_DUALF_Msk (0x1U << I2C_SR2_DUALF_Pos) /*!< 0x00000080 */ #define I2C_SR2_DUALF I2C_SR2_DUALF_Msk /*!< Dual Flag (Slave mode) */ -#define I2C_SR2_PEC_Pos (8U) +#define I2C_SR2_PEC_Pos (8U) #define I2C_SR2_PEC_Msk (0xFFU << I2C_SR2_PEC_Pos) /*!< 0x0000FF00 */ #define I2C_SR2_PEC I2C_SR2_PEC_Msk /*!< Packet Error Checking Register */ /******************* Bit definition for I2C_CCR register ********************/ -#define I2C_CCR_CCR_Pos (0U) +#define I2C_CCR_CCR_Pos (0U) #define I2C_CCR_CCR_Msk (0xFFFU << I2C_CCR_CCR_Pos) /*!< 0x00000FFF */ #define I2C_CCR_CCR I2C_CCR_CCR_Msk /*!< Clock Control Register in Fast/Standard mode (Master mode) */ -#define I2C_CCR_DUTY_Pos (14U) +#define I2C_CCR_DUTY_Pos (14U) #define I2C_CCR_DUTY_Msk (0x1U << I2C_CCR_DUTY_Pos) /*!< 0x00004000 */ #define I2C_CCR_DUTY I2C_CCR_DUTY_Msk /*!< Fast Mode Duty Cycle */ -#define I2C_CCR_FS_Pos (15U) +#define I2C_CCR_FS_Pos (15U) #define I2C_CCR_FS_Msk (0x1U << I2C_CCR_FS_Pos) /*!< 0x00008000 */ #define I2C_CCR_FS I2C_CCR_FS_Msk /*!< I2C Master Mode Selection */ /****************** Bit definition for I2C_TRISE register *******************/ -#define I2C_TRISE_TRISE_Pos (0U) +#define I2C_TRISE_TRISE_Pos (0U) #define I2C_TRISE_TRISE_Msk (0x3FU << I2C_TRISE_TRISE_Pos) /*!< 0x0000003F */ #define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */ @@ -10214,164 +10214,164 @@ typedef struct /******************************************************************************/ /******************* Bit definition for USART_SR register *******************/ -#define USART_SR_PE_Pos (0U) +#define USART_SR_PE_Pos (0U) #define USART_SR_PE_Msk (0x1U << USART_SR_PE_Pos) /*!< 0x00000001 */ #define USART_SR_PE USART_SR_PE_Msk /*!< Parity Error */ -#define USART_SR_FE_Pos (1U) +#define USART_SR_FE_Pos (1U) #define USART_SR_FE_Msk (0x1U << USART_SR_FE_Pos) /*!< 0x00000002 */ #define USART_SR_FE USART_SR_FE_Msk /*!< Framing Error */ -#define USART_SR_NE_Pos (2U) +#define USART_SR_NE_Pos (2U) #define USART_SR_NE_Msk (0x1U << USART_SR_NE_Pos) /*!< 0x00000004 */ #define USART_SR_NE USART_SR_NE_Msk /*!< Noise Error Flag */ -#define USART_SR_ORE_Pos (3U) +#define USART_SR_ORE_Pos (3U) #define USART_SR_ORE_Msk (0x1U << USART_SR_ORE_Pos) /*!< 0x00000008 */ #define USART_SR_ORE USART_SR_ORE_Msk /*!< OverRun Error */ -#define USART_SR_IDLE_Pos (4U) +#define USART_SR_IDLE_Pos (4U) #define USART_SR_IDLE_Msk (0x1U << USART_SR_IDLE_Pos) /*!< 0x00000010 */ #define USART_SR_IDLE USART_SR_IDLE_Msk /*!< IDLE line detected */ -#define USART_SR_RXNE_Pos (5U) +#define USART_SR_RXNE_Pos (5U) #define USART_SR_RXNE_Msk (0x1U << USART_SR_RXNE_Pos) /*!< 0x00000020 */ #define USART_SR_RXNE USART_SR_RXNE_Msk /*!< Read Data Register Not Empty */ -#define USART_SR_TC_Pos (6U) +#define USART_SR_TC_Pos (6U) #define USART_SR_TC_Msk (0x1U << USART_SR_TC_Pos) /*!< 0x00000040 */ #define USART_SR_TC USART_SR_TC_Msk /*!< Transmission Complete */ -#define USART_SR_TXE_Pos (7U) +#define USART_SR_TXE_Pos (7U) #define USART_SR_TXE_Msk (0x1U << USART_SR_TXE_Pos) /*!< 0x00000080 */ #define USART_SR_TXE USART_SR_TXE_Msk /*!< Transmit Data Register Empty */ -#define USART_SR_LBD_Pos (8U) +#define USART_SR_LBD_Pos (8U) #define USART_SR_LBD_Msk (0x1U << USART_SR_LBD_Pos) /*!< 0x00000100 */ #define USART_SR_LBD USART_SR_LBD_Msk /*!< LIN Break Detection Flag */ -#define USART_SR_CTS_Pos (9U) +#define USART_SR_CTS_Pos (9U) #define USART_SR_CTS_Msk (0x1U << USART_SR_CTS_Pos) /*!< 0x00000200 */ #define USART_SR_CTS USART_SR_CTS_Msk /*!< CTS Flag */ /******************* Bit definition for USART_DR register *******************/ -#define USART_DR_DR_Pos (0U) +#define USART_DR_DR_Pos (0U) #define USART_DR_DR_Msk (0x1FFU << USART_DR_DR_Pos) /*!< 0x000001FF */ #define USART_DR_DR USART_DR_DR_Msk /*!< Data value */ /****************** Bit definition for USART_BRR register *******************/ -#define USART_BRR_DIV_Fraction_Pos (0U) +#define USART_BRR_DIV_Fraction_Pos (0U) #define USART_BRR_DIV_Fraction_Msk (0xFU << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */ #define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!< Fraction of USARTDIV */ -#define USART_BRR_DIV_Mantissa_Pos (4U) +#define USART_BRR_DIV_Mantissa_Pos (4U) #define USART_BRR_DIV_Mantissa_Msk (0xFFFU << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */ #define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!< Mantissa of USARTDIV */ /****************** Bit definition for USART_CR1 register *******************/ -#define USART_CR1_SBK_Pos (0U) +#define USART_CR1_SBK_Pos (0U) #define USART_CR1_SBK_Msk (0x1U << USART_CR1_SBK_Pos) /*!< 0x00000001 */ #define USART_CR1_SBK USART_CR1_SBK_Msk /*!< Send Break */ -#define USART_CR1_RWU_Pos (1U) +#define USART_CR1_RWU_Pos (1U) #define USART_CR1_RWU_Msk (0x1U << USART_CR1_RWU_Pos) /*!< 0x00000002 */ #define USART_CR1_RWU USART_CR1_RWU_Msk /*!< Receiver wakeup */ -#define USART_CR1_RE_Pos (2U) +#define USART_CR1_RE_Pos (2U) #define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */ #define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */ -#define USART_CR1_TE_Pos (3U) +#define USART_CR1_TE_Pos (3U) #define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */ #define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */ -#define USART_CR1_IDLEIE_Pos (4U) +#define USART_CR1_IDLEIE_Pos (4U) #define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */ #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */ -#define USART_CR1_RXNEIE_Pos (5U) +#define USART_CR1_RXNEIE_Pos (5U) #define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */ #define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */ -#define USART_CR1_TCIE_Pos (6U) +#define USART_CR1_TCIE_Pos (6U) #define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */ #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */ -#define USART_CR1_TXEIE_Pos (7U) +#define USART_CR1_TXEIE_Pos (7U) #define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */ #define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< PE Interrupt Enable */ -#define USART_CR1_PEIE_Pos (8U) +#define USART_CR1_PEIE_Pos (8U) #define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */ #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */ -#define USART_CR1_PS_Pos (9U) +#define USART_CR1_PS_Pos (9U) #define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */ #define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */ -#define USART_CR1_PCE_Pos (10U) +#define USART_CR1_PCE_Pos (10U) #define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */ #define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */ -#define USART_CR1_WAKE_Pos (11U) +#define USART_CR1_WAKE_Pos (11U) #define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */ #define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Wakeup method */ -#define USART_CR1_M_Pos (12U) +#define USART_CR1_M_Pos (12U) #define USART_CR1_M_Msk (0x1U << USART_CR1_M_Pos) /*!< 0x00001000 */ #define USART_CR1_M USART_CR1_M_Msk /*!< Word length */ -#define USART_CR1_UE_Pos (13U) +#define USART_CR1_UE_Pos (13U) #define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00002000 */ #define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */ /****************** Bit definition for USART_CR2 register *******************/ -#define USART_CR2_ADD_Pos (0U) +#define USART_CR2_ADD_Pos (0U) #define USART_CR2_ADD_Msk (0xFU << USART_CR2_ADD_Pos) /*!< 0x0000000F */ #define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */ -#define USART_CR2_LBDL_Pos (5U) +#define USART_CR2_LBDL_Pos (5U) #define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /*!< 0x00000020 */ #define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */ -#define USART_CR2_LBDIE_Pos (6U) +#define USART_CR2_LBDIE_Pos (6U) #define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */ #define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */ -#define USART_CR2_LBCL_Pos (8U) +#define USART_CR2_LBCL_Pos (8U) #define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */ #define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */ -#define USART_CR2_CPHA_Pos (9U) +#define USART_CR2_CPHA_Pos (9U) #define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */ #define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */ -#define USART_CR2_CPOL_Pos (10U) +#define USART_CR2_CPOL_Pos (10U) #define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */ #define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */ -#define USART_CR2_CLKEN_Pos (11U) +#define USART_CR2_CLKEN_Pos (11U) #define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */ #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */ -#define USART_CR2_STOP_Pos (12U) +#define USART_CR2_STOP_Pos (12U) #define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */ #define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */ #define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x00001000 */ #define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x00002000 */ -#define USART_CR2_LINEN_Pos (14U) +#define USART_CR2_LINEN_Pos (14U) #define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /*!< 0x00004000 */ #define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */ /****************** Bit definition for USART_CR3 register *******************/ -#define USART_CR3_EIE_Pos (0U) +#define USART_CR3_EIE_Pos (0U) #define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */ #define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */ -#define USART_CR3_IREN_Pos (1U) +#define USART_CR3_IREN_Pos (1U) #define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /*!< 0x00000002 */ #define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */ -#define USART_CR3_IRLP_Pos (2U) +#define USART_CR3_IRLP_Pos (2U) #define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /*!< 0x00000004 */ #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */ -#define USART_CR3_HDSEL_Pos (3U) +#define USART_CR3_HDSEL_Pos (3U) #define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */ #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */ -#define USART_CR3_NACK_Pos (4U) +#define USART_CR3_NACK_Pos (4U) #define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /*!< 0x00000010 */ #define USART_CR3_NACK USART_CR3_NACK_Msk /*!< Smartcard NACK enable */ -#define USART_CR3_SCEN_Pos (5U) +#define USART_CR3_SCEN_Pos (5U) #define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /*!< 0x00000020 */ #define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< Smartcard mode enable */ -#define USART_CR3_DMAR_Pos (6U) +#define USART_CR3_DMAR_Pos (6U) #define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */ #define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */ -#define USART_CR3_DMAT_Pos (7U) +#define USART_CR3_DMAT_Pos (7U) #define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */ #define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */ -#define USART_CR3_RTSE_Pos (8U) +#define USART_CR3_RTSE_Pos (8U) #define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */ #define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */ -#define USART_CR3_CTSE_Pos (9U) +#define USART_CR3_CTSE_Pos (9U) #define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */ #define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */ -#define USART_CR3_CTSIE_Pos (10U) +#define USART_CR3_CTSIE_Pos (10U) #define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */ #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */ /****************** Bit definition for USART_GTPR register ******************/ -#define USART_GTPR_PSC_Pos (0U) +#define USART_GTPR_PSC_Pos (0U) #define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */ #define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */ #define USART_GTPR_PSC_0 (0x01U << USART_GTPR_PSC_Pos) /*!< 0x00000001 */ @@ -10383,7 +10383,7 @@ typedef struct #define USART_GTPR_PSC_6 (0x40U << USART_GTPR_PSC_Pos) /*!< 0x00000040 */ #define USART_GTPR_PSC_7 (0x80U << USART_GTPR_PSC_Pos) /*!< 0x00000080 */ -#define USART_GTPR_GT_Pos (8U) +#define USART_GTPR_GT_Pos (8U) #define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */ #define USART_GTPR_GT USART_GTPR_GT_Msk /*!< Guard time value */ @@ -10394,11 +10394,11 @@ typedef struct /******************************************************************************/ /**************** Bit definition for DBGMCU_IDCODE register *****************/ -#define DBGMCU_IDCODE_DEV_ID_Pos (0U) +#define DBGMCU_IDCODE_DEV_ID_Pos (0U) #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */ #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device Identifier */ -#define DBGMCU_IDCODE_REV_ID_Pos (16U) +#define DBGMCU_IDCODE_REV_ID_Pos (16U) #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */ #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< REV_ID[15:0] bits (Revision Identifier) */ #define DBGMCU_IDCODE_REV_ID_0 (0x0001U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */ @@ -10419,44 +10419,44 @@ typedef struct #define DBGMCU_IDCODE_REV_ID_15 (0x8000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */ /****************** Bit definition for DBGMCU_CR register *******************/ -#define DBGMCU_CR_DBG_SLEEP_Pos (0U) +#define DBGMCU_CR_DBG_SLEEP_Pos (0U) #define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */ #define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk /*!< Debug Sleep Mode */ -#define DBGMCU_CR_DBG_STOP_Pos (1U) +#define DBGMCU_CR_DBG_STOP_Pos (1U) #define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */ #define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Debug Stop Mode */ -#define DBGMCU_CR_DBG_STANDBY_Pos (2U) +#define DBGMCU_CR_DBG_STANDBY_Pos (2U) #define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */ #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug Standby mode */ -#define DBGMCU_CR_TRACE_IOEN_Pos (5U) +#define DBGMCU_CR_TRACE_IOEN_Pos (5U) #define DBGMCU_CR_TRACE_IOEN_Msk (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */ #define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk /*!< Trace Pin Assignment Control */ -#define DBGMCU_CR_TRACE_MODE_Pos (6U) +#define DBGMCU_CR_TRACE_MODE_Pos (6U) #define DBGMCU_CR_TRACE_MODE_Msk (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */ #define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */ #define DBGMCU_CR_TRACE_MODE_0 (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */ #define DBGMCU_CR_TRACE_MODE_1 (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */ -#define DBGMCU_CR_DBG_IWDG_STOP_Pos (8U) +#define DBGMCU_CR_DBG_IWDG_STOP_Pos (8U) #define DBGMCU_CR_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_CR_DBG_IWDG_STOP_Pos) /*!< 0x00000100 */ #define DBGMCU_CR_DBG_IWDG_STOP DBGMCU_CR_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */ -#define DBGMCU_CR_DBG_WWDG_STOP_Pos (9U) +#define DBGMCU_CR_DBG_WWDG_STOP_Pos (9U) #define DBGMCU_CR_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_CR_DBG_WWDG_STOP_Pos) /*!< 0x00000200 */ #define DBGMCU_CR_DBG_WWDG_STOP DBGMCU_CR_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */ -#define DBGMCU_CR_DBG_TIM1_STOP_Pos (10U) +#define DBGMCU_CR_DBG_TIM1_STOP_Pos (10U) #define DBGMCU_CR_DBG_TIM1_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM1_STOP_Pos) /*!< 0x00000400 */ #define DBGMCU_CR_DBG_TIM1_STOP DBGMCU_CR_DBG_TIM1_STOP_Msk /*!< TIM1 counter stopped when core is halted */ -#define DBGMCU_CR_DBG_TIM2_STOP_Pos (11U) +#define DBGMCU_CR_DBG_TIM2_STOP_Pos (11U) #define DBGMCU_CR_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM2_STOP_Pos) /*!< 0x00000800 */ #define DBGMCU_CR_DBG_TIM2_STOP DBGMCU_CR_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */ -#define DBGMCU_CR_DBG_TIM3_STOP_Pos (12U) +#define DBGMCU_CR_DBG_TIM3_STOP_Pos (12U) #define DBGMCU_CR_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM3_STOP_Pos) /*!< 0x00001000 */ #define DBGMCU_CR_DBG_TIM3_STOP DBGMCU_CR_DBG_TIM3_STOP_Msk /*!< TIM3 counter stopped when core is halted */ -#define DBGMCU_CR_DBG_CAN1_STOP_Pos (14U) +#define DBGMCU_CR_DBG_CAN1_STOP_Pos (14U) #define DBGMCU_CR_DBG_CAN1_STOP_Msk (0x1U << DBGMCU_CR_DBG_CAN1_STOP_Pos) /*!< 0x00004000 */ #define DBGMCU_CR_DBG_CAN1_STOP DBGMCU_CR_DBG_CAN1_STOP_Msk /*!< Debug CAN1 stopped when Core is halted */ -#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Pos (15U) +#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Pos (15U) #define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00008000 */ #define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */ @@ -10466,40 +10466,40 @@ typedef struct /* */ /******************************************************************************/ /******************* Bit definition for FLASH_ACR register ******************/ -#define FLASH_ACR_LATENCY_Pos (0U) +#define FLASH_ACR_LATENCY_Pos (0U) #define FLASH_ACR_LATENCY_Msk (0x7U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000007 */ #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< LATENCY[2:0] bits (Latency) */ #define FLASH_ACR_LATENCY_0 (0x1U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */ #define FLASH_ACR_LATENCY_1 (0x2U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000002 */ #define FLASH_ACR_LATENCY_2 (0x4U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000004 */ -#define FLASH_ACR_HLFCYA_Pos (3U) +#define FLASH_ACR_HLFCYA_Pos (3U) #define FLASH_ACR_HLFCYA_Msk (0x1U << FLASH_ACR_HLFCYA_Pos) /*!< 0x00000008 */ #define FLASH_ACR_HLFCYA FLASH_ACR_HLFCYA_Msk /*!< Flash Half Cycle Access Enable */ -#define FLASH_ACR_PRFTBE_Pos (4U) +#define FLASH_ACR_PRFTBE_Pos (4U) #define FLASH_ACR_PRFTBE_Msk (0x1U << FLASH_ACR_PRFTBE_Pos) /*!< 0x00000010 */ #define FLASH_ACR_PRFTBE FLASH_ACR_PRFTBE_Msk /*!< Prefetch Buffer Enable */ -#define FLASH_ACR_PRFTBS_Pos (5U) +#define FLASH_ACR_PRFTBS_Pos (5U) #define FLASH_ACR_PRFTBS_Msk (0x1U << FLASH_ACR_PRFTBS_Pos) /*!< 0x00000020 */ #define FLASH_ACR_PRFTBS FLASH_ACR_PRFTBS_Msk /*!< Prefetch Buffer Status */ /****************** Bit definition for FLASH_KEYR register ******************/ -#define FLASH_KEYR_FKEYR_Pos (0U) +#define FLASH_KEYR_FKEYR_Pos (0U) #define FLASH_KEYR_FKEYR_Msk (0xFFFFFFFFU << FLASH_KEYR_FKEYR_Pos) /*!< 0xFFFFFFFF */ #define FLASH_KEYR_FKEYR FLASH_KEYR_FKEYR_Msk /*!< FPEC Key */ -#define RDP_KEY_Pos (0U) +#define RDP_KEY_Pos (0U) #define RDP_KEY_Msk (0xA5U << RDP_KEY_Pos) /*!< 0x000000A5 */ #define RDP_KEY RDP_KEY_Msk /*!< RDP Key */ -#define FLASH_KEY1_Pos (0U) +#define FLASH_KEY1_Pos (0U) #define FLASH_KEY1_Msk (0x45670123U << FLASH_KEY1_Pos) /*!< 0x45670123 */ #define FLASH_KEY1 FLASH_KEY1_Msk /*!< FPEC Key1 */ -#define FLASH_KEY2_Pos (0U) +#define FLASH_KEY2_Pos (0U) #define FLASH_KEY2_Msk (0xCDEF89ABU << FLASH_KEY2_Pos) /*!< 0xCDEF89AB */ #define FLASH_KEY2 FLASH_KEY2_Msk /*!< FPEC Key2 */ /***************** Bit definition for FLASH_OPTKEYR register ****************/ -#define FLASH_OPTKEYR_OPTKEYR_Pos (0U) +#define FLASH_OPTKEYR_OPTKEYR_Pos (0U) #define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFU << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */ #define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /*!< Option Byte Key */ @@ -10507,127 +10507,127 @@ typedef struct #define FLASH_OPTKEY2 FLASH_KEY2 /*!< Option Byte Key2 */ /****************** Bit definition for FLASH_SR register ********************/ -#define FLASH_SR_BSY_Pos (0U) +#define FLASH_SR_BSY_Pos (0U) #define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00000001 */ #define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy */ -#define FLASH_SR_PGERR_Pos (2U) +#define FLASH_SR_PGERR_Pos (2U) #define FLASH_SR_PGERR_Msk (0x1U << FLASH_SR_PGERR_Pos) /*!< 0x00000004 */ #define FLASH_SR_PGERR FLASH_SR_PGERR_Msk /*!< Programming Error */ -#define FLASH_SR_WRPRTERR_Pos (4U) +#define FLASH_SR_WRPRTERR_Pos (4U) #define FLASH_SR_WRPRTERR_Msk (0x1U << FLASH_SR_WRPRTERR_Pos) /*!< 0x00000010 */ #define FLASH_SR_WRPRTERR FLASH_SR_WRPRTERR_Msk /*!< Write Protection Error */ -#define FLASH_SR_EOP_Pos (5U) +#define FLASH_SR_EOP_Pos (5U) #define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000020 */ #define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End of operation */ /******************* Bit definition for FLASH_CR register *******************/ -#define FLASH_CR_PG_Pos (0U) +#define FLASH_CR_PG_Pos (0U) #define FLASH_CR_PG_Msk (0x1U << FLASH_CR_PG_Pos) /*!< 0x00000001 */ #define FLASH_CR_PG FLASH_CR_PG_Msk /*!< Programming */ -#define FLASH_CR_PER_Pos (1U) +#define FLASH_CR_PER_Pos (1U) #define FLASH_CR_PER_Msk (0x1U << FLASH_CR_PER_Pos) /*!< 0x00000002 */ #define FLASH_CR_PER FLASH_CR_PER_Msk /*!< Page Erase */ -#define FLASH_CR_MER_Pos (2U) +#define FLASH_CR_MER_Pos (2U) #define FLASH_CR_MER_Msk (0x1U << FLASH_CR_MER_Pos) /*!< 0x00000004 */ #define FLASH_CR_MER FLASH_CR_MER_Msk /*!< Mass Erase */ -#define FLASH_CR_OPTPG_Pos (4U) +#define FLASH_CR_OPTPG_Pos (4U) #define FLASH_CR_OPTPG_Msk (0x1U << FLASH_CR_OPTPG_Pos) /*!< 0x00000010 */ #define FLASH_CR_OPTPG FLASH_CR_OPTPG_Msk /*!< Option Byte Programming */ -#define FLASH_CR_OPTER_Pos (5U) +#define FLASH_CR_OPTER_Pos (5U) #define FLASH_CR_OPTER_Msk (0x1U << FLASH_CR_OPTER_Pos) /*!< 0x00000020 */ #define FLASH_CR_OPTER FLASH_CR_OPTER_Msk /*!< Option Byte Erase */ -#define FLASH_CR_STRT_Pos (6U) +#define FLASH_CR_STRT_Pos (6U) #define FLASH_CR_STRT_Msk (0x1U << FLASH_CR_STRT_Pos) /*!< 0x00000040 */ #define FLASH_CR_STRT FLASH_CR_STRT_Msk /*!< Start */ -#define FLASH_CR_LOCK_Pos (7U) +#define FLASH_CR_LOCK_Pos (7U) #define FLASH_CR_LOCK_Msk (0x1U << FLASH_CR_LOCK_Pos) /*!< 0x00000080 */ #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /*!< Lock */ -#define FLASH_CR_OPTWRE_Pos (9U) +#define FLASH_CR_OPTWRE_Pos (9U) #define FLASH_CR_OPTWRE_Msk (0x1U << FLASH_CR_OPTWRE_Pos) /*!< 0x00000200 */ #define FLASH_CR_OPTWRE FLASH_CR_OPTWRE_Msk /*!< Option Bytes Write Enable */ -#define FLASH_CR_ERRIE_Pos (10U) +#define FLASH_CR_ERRIE_Pos (10U) #define FLASH_CR_ERRIE_Msk (0x1U << FLASH_CR_ERRIE_Pos) /*!< 0x00000400 */ #define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk /*!< Error Interrupt Enable */ -#define FLASH_CR_EOPIE_Pos (12U) +#define FLASH_CR_EOPIE_Pos (12U) #define FLASH_CR_EOPIE_Msk (0x1U << FLASH_CR_EOPIE_Pos) /*!< 0x00001000 */ #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /*!< End of operation interrupt enable */ /******************* Bit definition for FLASH_AR register *******************/ -#define FLASH_AR_FAR_Pos (0U) +#define FLASH_AR_FAR_Pos (0U) #define FLASH_AR_FAR_Msk (0xFFFFFFFFU << FLASH_AR_FAR_Pos) /*!< 0xFFFFFFFF */ #define FLASH_AR_FAR FLASH_AR_FAR_Msk /*!< Flash Address */ /****************** Bit definition for FLASH_OBR register *******************/ -#define FLASH_OBR_OPTERR_Pos (0U) +#define FLASH_OBR_OPTERR_Pos (0U) #define FLASH_OBR_OPTERR_Msk (0x1U << FLASH_OBR_OPTERR_Pos) /*!< 0x00000001 */ #define FLASH_OBR_OPTERR FLASH_OBR_OPTERR_Msk /*!< Option Byte Error */ -#define FLASH_OBR_RDPRT_Pos (1U) +#define FLASH_OBR_RDPRT_Pos (1U) #define FLASH_OBR_RDPRT_Msk (0x1U << FLASH_OBR_RDPRT_Pos) /*!< 0x00000002 */ #define FLASH_OBR_RDPRT FLASH_OBR_RDPRT_Msk /*!< Read protection */ -#define FLASH_OBR_IWDG_SW_Pos (2U) +#define FLASH_OBR_IWDG_SW_Pos (2U) #define FLASH_OBR_IWDG_SW_Msk (0x1U << FLASH_OBR_IWDG_SW_Pos) /*!< 0x00000004 */ #define FLASH_OBR_IWDG_SW FLASH_OBR_IWDG_SW_Msk /*!< IWDG SW */ -#define FLASH_OBR_nRST_STOP_Pos (3U) +#define FLASH_OBR_nRST_STOP_Pos (3U) #define FLASH_OBR_nRST_STOP_Msk (0x1U << FLASH_OBR_nRST_STOP_Pos) /*!< 0x00000008 */ #define FLASH_OBR_nRST_STOP FLASH_OBR_nRST_STOP_Msk /*!< nRST_STOP */ -#define FLASH_OBR_nRST_STDBY_Pos (4U) +#define FLASH_OBR_nRST_STDBY_Pos (4U) #define FLASH_OBR_nRST_STDBY_Msk (0x1U << FLASH_OBR_nRST_STDBY_Pos) /*!< 0x00000010 */ #define FLASH_OBR_nRST_STDBY FLASH_OBR_nRST_STDBY_Msk /*!< nRST_STDBY */ -#define FLASH_OBR_USER_Pos (2U) +#define FLASH_OBR_USER_Pos (2U) #define FLASH_OBR_USER_Msk (0x7U << FLASH_OBR_USER_Pos) /*!< 0x0000001C */ #define FLASH_OBR_USER FLASH_OBR_USER_Msk /*!< User Option Bytes */ -#define FLASH_OBR_DATA0_Pos (10U) +#define FLASH_OBR_DATA0_Pos (10U) #define FLASH_OBR_DATA0_Msk (0xFFU << FLASH_OBR_DATA0_Pos) /*!< 0x0003FC00 */ #define FLASH_OBR_DATA0 FLASH_OBR_DATA0_Msk /*!< Data0 */ -#define FLASH_OBR_DATA1_Pos (18U) +#define FLASH_OBR_DATA1_Pos (18U) #define FLASH_OBR_DATA1_Msk (0xFFU << FLASH_OBR_DATA1_Pos) /*!< 0x03FC0000 */ #define FLASH_OBR_DATA1 FLASH_OBR_DATA1_Msk /*!< Data1 */ /****************** Bit definition for FLASH_WRPR register ******************/ -#define FLASH_WRPR_WRP_Pos (0U) +#define FLASH_WRPR_WRP_Pos (0U) #define FLASH_WRPR_WRP_Msk (0xFFFFFFFFU << FLASH_WRPR_WRP_Pos) /*!< 0xFFFFFFFF */ #define FLASH_WRPR_WRP FLASH_WRPR_WRP_Msk /*!< Write Protect */ /*----------------------------------------------------------------------------*/ /****************** Bit definition for FLASH_RDP register *******************/ -#define FLASH_RDP_RDP_Pos (0U) +#define FLASH_RDP_RDP_Pos (0U) #define FLASH_RDP_RDP_Msk (0xFFU << FLASH_RDP_RDP_Pos) /*!< 0x000000FF */ #define FLASH_RDP_RDP FLASH_RDP_RDP_Msk /*!< Read protection option byte */ -#define FLASH_RDP_nRDP_Pos (8U) +#define FLASH_RDP_nRDP_Pos (8U) #define FLASH_RDP_nRDP_Msk (0xFFU << FLASH_RDP_nRDP_Pos) /*!< 0x0000FF00 */ #define FLASH_RDP_nRDP FLASH_RDP_nRDP_Msk /*!< Read protection complemented option byte */ /****************** Bit definition for FLASH_USER register ******************/ -#define FLASH_USER_USER_Pos (16U) +#define FLASH_USER_USER_Pos (16U) #define FLASH_USER_USER_Msk (0xFFU << FLASH_USER_USER_Pos) /*!< 0x00FF0000 */ #define FLASH_USER_USER FLASH_USER_USER_Msk /*!< User option byte */ -#define FLASH_USER_nUSER_Pos (24U) +#define FLASH_USER_nUSER_Pos (24U) #define FLASH_USER_nUSER_Msk (0xFFU << FLASH_USER_nUSER_Pos) /*!< 0xFF000000 */ #define FLASH_USER_nUSER FLASH_USER_nUSER_Msk /*!< User complemented option byte */ /****************** Bit definition for FLASH_Data0 register *****************/ -#define FLASH_DATA0_DATA0_Pos (0U) +#define FLASH_DATA0_DATA0_Pos (0U) #define FLASH_DATA0_DATA0_Msk (0xFFU << FLASH_DATA0_DATA0_Pos) /*!< 0x000000FF */ #define FLASH_DATA0_DATA0 FLASH_DATA0_DATA0_Msk /*!< User data storage option byte */ -#define FLASH_DATA0_nDATA0_Pos (8U) +#define FLASH_DATA0_nDATA0_Pos (8U) #define FLASH_DATA0_nDATA0_Msk (0xFFU << FLASH_DATA0_nDATA0_Pos) /*!< 0x0000FF00 */ #define FLASH_DATA0_nDATA0 FLASH_DATA0_nDATA0_Msk /*!< User data storage complemented option byte */ /****************** Bit definition for FLASH_Data1 register *****************/ -#define FLASH_DATA1_DATA1_Pos (16U) +#define FLASH_DATA1_DATA1_Pos (16U) #define FLASH_DATA1_DATA1_Msk (0xFFU << FLASH_DATA1_DATA1_Pos) /*!< 0x00FF0000 */ #define FLASH_DATA1_DATA1 FLASH_DATA1_DATA1_Msk /*!< User data storage option byte */ -#define FLASH_DATA1_nDATA1_Pos (24U) +#define FLASH_DATA1_nDATA1_Pos (24U) #define FLASH_DATA1_nDATA1_Msk (0xFFU << FLASH_DATA1_nDATA1_Pos) /*!< 0xFF000000 */ #define FLASH_DATA1_nDATA1 FLASH_DATA1_nDATA1_Msk /*!< User data storage complemented option byte */ /****************** Bit definition for FLASH_WRP0 register ******************/ -#define FLASH_WRP0_WRP0_Pos (0U) +#define FLASH_WRP0_WRP0_Pos (0U) #define FLASH_WRP0_WRP0_Msk (0xFFU << FLASH_WRP0_WRP0_Pos) /*!< 0x000000FF */ #define FLASH_WRP0_WRP0 FLASH_WRP0_WRP0_Msk /*!< Flash memory write protection option bytes */ -#define FLASH_WRP0_nWRP0_Pos (8U) +#define FLASH_WRP0_nWRP0_Pos (8U) #define FLASH_WRP0_nWRP0_Msk (0xFFU << FLASH_WRP0_nWRP0_Pos) /*!< 0x0000FF00 */ #define FLASH_WRP0_nWRP0 FLASH_WRP0_nWRP0_Msk /*!< Flash memory write protection complemented option bytes */ @@ -10639,7 +10639,7 @@ typedef struct /** * @} -*/ +*/ /** @addtogroup Exported_macro * @{ @@ -10655,7 +10655,7 @@ typedef struct #define IS_ADC_DMA_CAPABILITY_INSTANCE(INSTANCE) ((INSTANCE) == ADC1) -/****************************** CAN Instances *********************************/ +/****************************** CAN Instances *********************************/ #define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN1) /****************************** CRC Instances *********************************/ @@ -10671,7 +10671,7 @@ typedef struct ((INSTANCE) == DMA1_Channel5) || \ ((INSTANCE) == DMA1_Channel6) || \ ((INSTANCE) == DMA1_Channel7)) - + /******************************* GPIO Instances *******************************/ #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \ ((INSTANCE) == GPIOB) || \ @@ -10815,19 +10815,19 @@ typedef struct (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3)) - + #define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\ (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3)) - + #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\ ((INSTANCE) == TIM1) /****************************** END TIM Instances *****************************/ -/******************** USART Instances : Synchronous mode **********************/ +/******************** USART Instances : Synchronous mode **********************/ #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ ((INSTANCE) == USART2)) @@ -10843,7 +10843,7 @@ typedef struct #define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ ((INSTANCE) == USART2) ) -/****************** UART Instances : Hardware Flow control ********************/ +/****************** UART Instances : Hardware Flow control ********************/ #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ ((INSTANCE) == USART2) ) @@ -10877,12 +10877,12 @@ typedef struct /** * @} -*/ +*/ /******************************************************************************/ /* For a painless codes migration between the STM32F1xx device product */ /* lines, the aliases defined below are put in place to overcome the */ /* differences in the interrupt handlers and IRQn definitions. */ -/* No need to update developed interrupt code when moving across */ +/* No need to update developed interrupt code when moving across */ /* product lines within the same STM32F1 Family */ /******************************************************************************/ @@ -10936,9 +10936,9 @@ typedef struct #ifdef __cplusplus } #endif /* __cplusplus */ - + #endif /* __STM32F103x6_H */ - - - + + + /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stm32cubemx/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h b/stm32cubemx/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h index 5cd8880..7bd9429 100644 --- a/stm32cubemx/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h +++ b/stm32cubemx/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h @@ -4,17 +4,17 @@ * @author MCD Application Team * @version V4.1.0 * @date 29-April-2016 - * @brief CMSIS STM32F1xx Device Peripheral Access Layer Header File. + * @brief CMSIS STM32F1xx Device Peripheral Access Layer Header File. * * The file is the unique include file that the application programmer * is using in the C source code, usually in main.c. This file contains: * - Configuration section that allows to select: * - The STM32F1xx device used in the target application - * - To use or not the peripheral’s drivers in application code(i.e. - * code will be based on direct access to peripheral’s registers - * rather than drivers API), this option is controlled by + * - To use or not the peripheral’s drivers in application code(i.e. + * code will be based on direct access to peripheral’s registers + * rather than drivers API), this option is controlled by * "#define USE_HAL_DRIVER" - * + * ****************************************************************************** * @attention * @@ -52,14 +52,14 @@ /** @addtogroup stm32f1xx * @{ */ - + #ifndef __STM32F1XX_H #define __STM32F1XX_H #ifdef __cplusplus extern "C" { #endif /* __cplusplus */ - + /** @addtogroup Library_configuration_section * @{ */ @@ -71,8 +71,8 @@ #define STM32F1 #endif /* STM32F1 */ -/* Uncomment the line below according to the target STM32L device used in your - application +/* Uncomment the line below according to the target STM32L device used in your + application */ #if !defined (STM32F100xB) && !defined (STM32F100xE) && !defined (STM32F101x6) && \ @@ -82,7 +82,7 @@ /* #define STM32F100xE */ /*!< STM32F100RC, STM32F100VC, STM32F100ZC, STM32F100RD, STM32F100VD, STM32F100ZD, STM32F100RE, STM32F100VE and STM32F100ZE */ /* #define STM32F101x6 */ /*!< STM32F101C4, STM32F101R4, STM32F101T4, STM32F101C6, STM32F101R6 and STM32F101T6 Devices */ /* #define STM32F101xB */ /*!< STM32F101C8, STM32F101R8, STM32F101T8, STM32F101V8, STM32F101CB, STM32F101RB, STM32F101TB and STM32F101VB */ - /* #define STM32F101xE */ /*!< STM32F101RC, STM32F101VC, STM32F101ZC, STM32F101RD, STM32F101VD, STM32F101ZD, STM32F101RE, STM32F101VE and STM32F101ZE */ + /* #define STM32F101xE */ /*!< STM32F101RC, STM32F101VC, STM32F101ZC, STM32F101RD, STM32F101VD, STM32F101ZD, STM32F101RE, STM32F101VE and STM32F101ZE */ /* #define STM32F101xG */ /*!< STM32F101RF, STM32F101VF, STM32F101ZF, STM32F101RG, STM32F101VG and STM32F101ZG */ /* #define STM32F102x6 */ /*!< STM32F102C4, STM32F102R4, STM32F102C6 and STM32F102R6 */ /* #define STM32F102xB */ /*!< STM32F102C8, STM32F102R8, STM32F102CB and STM32F102RB */ @@ -91,18 +91,18 @@ /* #define STM32F103xE */ /*!< STM32F103RC, STM32F103VC, STM32F103ZC, STM32F103RD, STM32F103VD, STM32F103ZD, STM32F103RE, STM32F103VE and STM32F103ZE */ /* #define STM32F103xG */ /*!< STM32F103RF, STM32F103VF, STM32F103ZF, STM32F103RG, STM32F103VG and STM32F103ZG */ /* #define STM32F105xC */ /*!< STM32F105R8, STM32F105V8, STM32F105RB, STM32F105VB, STM32F105RC and STM32F105VC */ - /* #define STM32F107xC */ /*!< STM32F107RB, STM32F107VB, STM32F107RC and STM32F107VC */ + /* #define STM32F107xC */ /*!< STM32F107RB, STM32F107VB, STM32F107RC and STM32F107VC */ #endif /* Tip: To avoid modifying this file each time you need to switch between these devices, you can define the device in your toolchain compiler preprocessor. */ - + #if !defined (USE_HAL_DRIVER) /** * @brief Comment the line below if you will not use the peripherals drivers. - In this case, these drivers will not be included and the application code will - be based on direct access to peripherals registers + In this case, these drivers will not be included and the application code will + be based on direct access to peripherals registers */ /*#define USE_HAL_DRIVER */ #endif /* USE_HAL_DRIVER */ @@ -110,10 +110,10 @@ /** * @brief CMSIS Device version number */ -#define __STM32F1_CMSIS_VERSION_MAIN (0x04) /*!< [31:24] main version */ +#define __STM32F1_CMSIS_VERSION_MAIN (0x04) /*!< [31:24] main version */ #define __STM32F1_CMSIS_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */ #define __STM32F1_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ -#define __STM32F1_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __STM32F1_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32F1_CMSIS_VERSION ((__STM32F1_CMSIS_VERSION_MAIN << 24)\ |(__STM32F1_CMSIS_VERSION_SUB1 << 16)\ |(__STM32F1_CMSIS_VERSION_SUB2 << 8 )\ @@ -165,23 +165,23 @@ /** @addtogroup Exported_types * @{ - */ -typedef enum + */ +typedef enum { - RESET = 0, + RESET = 0, SET = !RESET } FlagStatus, ITStatus; -typedef enum +typedef enum { - DISABLE = 0, + DISABLE = 0, ENABLE = !DISABLE } FunctionalState; #define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) -typedef enum +typedef enum { - ERROR = 0, + ERROR = 0, SUCCESS = !ERROR } ErrorStatus; @@ -207,7 +207,7 @@ typedef enum #define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) -#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) +#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) /** @@ -231,7 +231,7 @@ typedef enum /** * @} */ - + diff --git a/stm32cubemx/Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h b/stm32cubemx/Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h index 996b3f1..7d23de6 100644 --- a/stm32cubemx/Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h +++ b/stm32cubemx/Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h @@ -41,8 +41,8 @@ /** @addtogroup stm32f10x_system * @{ - */ - + */ + /** * @brief Define to prevent recursive inclusion */ @@ -51,7 +51,7 @@ #ifdef __cplusplus extern "C" { -#endif +#endif /** @addtogroup STM32F10x_System_Includes * @{ @@ -93,7 +93,7 @@ extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */ /** @addtogroup STM32F10x_System_Exported_Functions * @{ */ - + extern void SystemInit(void); extern void SystemCoreClockUpdate(void); /** @@ -109,8 +109,8 @@ extern void SystemCoreClockUpdate(void); /** * @} */ - + /** * @} - */ + */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stm32cubemx/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/system_stm32f1xx.c b/stm32cubemx/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/system_stm32f1xx.c index 0ca6174..9d07f89 100644 --- a/stm32cubemx/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/system_stm32f1xx.c +++ b/stm32cubemx/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/system_stm32f1xx.c @@ -5,19 +5,19 @@ * @version V4.1.0 * @date 29-April-2016 * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. - * - * 1. This file provides two functions and one global variable to be called from + * + * 1. This file provides two functions and one global variable to be called from * user application: * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier - * factors, AHB/APBx prescalers and Flash settings). - * This function is called at startup just after reset and + * factors, AHB/APBx prescalers and Flash settings). + * This function is called at startup just after reset and * before branch to main program. This call is made inside * the "startup_stm32f1xx_xx.s" file. * * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used - * by the user application to setup the SysTick + * by the user application to setup the SysTick * timer or configure other parameters. - * + * * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must * be called whenever the core clock is changed * during program execution. @@ -27,11 +27,11 @@ * configure the system clock before to branch to main program. * * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depending on - * the product used), refer to "HSE_VALUE". + * the product used), refer to "HSE_VALUE". * When HSE is used as system clock source, directly or through PLL, and you * are using different crystal you have to adapt the HSE value to your own * configuration. - * + * ****************************************************************************** * @attention * @@ -68,8 +68,8 @@ /** @addtogroup stm32f1xx_system * @{ - */ - + */ + /** @addtogroup STM32F1xx_System_Private_Includes * @{ */ @@ -92,7 +92,7 @@ * @{ */ -#if !defined (HSE_VALUE) +#if !defined (HSE_VALUE) #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz. This value can be provided and adapted by the user application. */ #endif /* HSE_VALUE */ @@ -102,15 +102,15 @@ This value can be provided and adapted by the user application. */ #endif /* HSI_VALUE */ -/*!< Uncomment the following line if you need to use external SRAM */ +/*!< Uncomment the following line if you need to use external SRAM */ #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG) /* #define DATA_IN_ExtSRAM */ #endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */ /*!< Uncomment the following line if you need to relocate your vector Table in - Internal SRAM. */ + Internal SRAM. */ /* #define VECT_TAB_SRAM */ -#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field. +#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field. This value must be a multiple of 0x200. */ @@ -152,7 +152,7 @@ const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG) #ifdef DATA_IN_ExtSRAM - static void SystemInit_ExtMemCtl(void); + static void SystemInit_ExtMemCtl(void); #endif /* DATA_IN_ExtSRAM */ #endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */ @@ -166,7 +166,7 @@ const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; /** * @brief Setup the microcontroller system - * Initialize the Embedded Flash Interface, the PLL and update the + * Initialize the Embedded Flash Interface, the PLL and update the * SystemCoreClock variable. * @note This function should be used only after reset. * @param None @@ -183,8 +183,8 @@ void SystemInit (void) RCC->CFGR &= (uint32_t)0xF8FF0000; #else RCC->CFGR &= (uint32_t)0xF0FF0000; -#endif /* STM32F105xC */ - +#endif /* STM32F105xC */ + /* Reset HSEON, CSSON and PLLON bits */ RCC->CR &= (uint32_t)0xFEF6FFFF; @@ -208,23 +208,23 @@ void SystemInit (void) RCC->CIR = 0x009F0000; /* Reset CFGR2 register */ - RCC->CFGR2 = 0x00000000; + RCC->CFGR2 = 0x00000000; #else /* Disable all interrupts and clear pending bits */ RCC->CIR = 0x009F0000; #endif /* STM32F105xC */ - + #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG) #ifdef DATA_IN_ExtSRAM - SystemInit_ExtMemCtl(); + SystemInit_ExtMemCtl(); #endif /* DATA_IN_ExtSRAM */ -#endif +#endif #ifdef VECT_TAB_SRAM SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ #else SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ -#endif +#endif } /** @@ -232,31 +232,31 @@ void SystemInit (void) * The SystemCoreClock variable contains the core clock (HCLK), it can * be used by the user application to setup the SysTick timer or configure * other parameters. - * + * * @note Each time the core clock (HCLK) changes, this function must be called * to update SystemCoreClock variable value. Otherwise, any configuration - * based on this variable will be incorrect. - * - * @note - The system frequency computed by this function is not the real - * frequency in the chip. It is calculated based on the predefined + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined * constant and the selected clock source: - * + * * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) - * + * * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) - * - * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) * or HSI_VALUE(*) multiplied by the PLL factors. - * + * * (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value * 8 MHz) but the real value may vary depending on the variations - * in voltage and temperature. - * + * in voltage and temperature. + * * (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value * 8 MHz or 25 MHz, depending on the product used), user has to ensure * that HSE_VALUE is same as the real frequency of the crystal used. * Otherwise, this function may have wrong result. - * + * * - The result of this function could be not correct when using fractional * value for HSE crystal. * @param None @@ -273,10 +273,10 @@ void SystemCoreClockUpdate (void) #if defined(STM32F100xB) || defined(STM32F100xE) uint32_t prediv1factor = 0; #endif /* STM32F100xB or STM32F100xE */ - + /* Get SYSCLK source -------------------------------------------------------*/ tmp = RCC->CFGR & RCC_CFGR_SWS; - + switch (tmp) { case 0x00: /* HSI used as system clock */ @@ -290,10 +290,10 @@ void SystemCoreClockUpdate (void) /* Get PLL clock source and multiplication factor ----------------------*/ pllmull = RCC->CFGR & RCC_CFGR_PLLMULL; pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; - -#if !defined(STM32F105xC) && !defined(STM32F107xC) + +#if !defined(STM32F105xC) && !defined(STM32F107xC) pllmull = ( pllmull >> 18) + 2; - + if (pllsource == 0x00) { /* HSI oscillator clock divided by 2 selected as PLL clock entry */ @@ -304,7 +304,7 @@ void SystemCoreClockUpdate (void) #if defined(STM32F100xB) || defined(STM32F100xE) prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; /* HSE oscillator clock selected as PREDIV1 clock entry */ - SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; + SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; #else /* HSE selected as PLL clock entry */ if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET) @@ -319,16 +319,16 @@ void SystemCoreClockUpdate (void) } #else pllmull = pllmull >> 18; - + if (pllmull != 0x0D) { pllmull += 2; } else { /* PLL multiplication factor = PLL input clock * 6.5 */ - pllmull = 13 / 2; + pllmull = 13 / 2; } - + if (pllsource == 0x00) { /* HSI oscillator clock divided by 2 selected as PLL clock entry */ @@ -336,61 +336,61 @@ void SystemCoreClockUpdate (void) } else {/* PREDIV1 selected as PLL clock entry */ - + /* Get PREDIV1 clock source and division factor */ prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC; prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; - + if (prediv1source == 0) - { + { /* HSE oscillator clock selected as PREDIV1 clock entry */ - SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; + SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; } else {/* PLL2 clock selected as PREDIV1 clock entry */ - + /* Get PREDIV2 division factor and PLL2 multiplication factor */ prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1; - pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; - SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull; + pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; + SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull; } } -#endif /* STM32F105xC */ +#endif /* STM32F105xC */ break; default: SystemCoreClock = HSI_VALUE; break; } - + /* Compute HCLK clock frequency ----------------*/ /* Get HCLK prescaler */ tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; /* HCLK clock frequency */ - SystemCoreClock >>= tmp; + SystemCoreClock >>= tmp; } #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG) /** - * @brief Setup the external memory controller. Called in startup_stm32f1xx.s + * @brief Setup the external memory controller. Called in startup_stm32f1xx.s * before jump to __main * @param None * @retval None - */ + */ #ifdef DATA_IN_ExtSRAM /** - * @brief Setup the external memory controller. + * @brief Setup the external memory controller. * Called in startup_stm32f1xx_xx.s/.c before jump to main. * This function configures the external SRAM mounted on STM3210E-EVAL * board (STM32 High density devices). This SRAM will be used as program * data memory (including heap and stack). * @param None * @retval None - */ -void SystemInit_ExtMemCtl(void) + */ +void SystemInit_ExtMemCtl(void) { __IO uint32_t tmpreg; - /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is + /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is required, then adjust the Register Addresses */ /* Enable FSMC clock */ @@ -398,36 +398,36 @@ void SystemInit_ExtMemCtl(void) /* Delay after an RCC peripheral clock enabling */ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN); - + /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */ RCC->APB2ENR = 0x000001E0; - + /* Delay after an RCC peripheral clock enabling */ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN); (void)(tmpreg); - + /* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/ /*---------------- SRAM Address lines configuration -------------------------*/ -/*---------------- NOE and NWE configuration --------------------------------*/ +/*---------------- NOE and NWE configuration --------------------------------*/ /*---------------- NE3 configuration ----------------------------------------*/ /*---------------- NBL0, NBL1 configuration ---------------------------------*/ - - GPIOD->CRL = 0x44BB44BB; + + GPIOD->CRL = 0x44BB44BB; GPIOD->CRH = 0xBBBBBBBB; - GPIOE->CRL = 0xB44444BB; + GPIOE->CRL = 0xB44444BB; GPIOE->CRH = 0xBBBBBBBB; - GPIOF->CRL = 0x44BBBBBB; + GPIOF->CRL = 0x44BBBBBB; GPIOF->CRH = 0xBBBB4444; - GPIOG->CRL = 0x44BBBBBB; + GPIOG->CRL = 0x44BBBBBB; GPIOG->CRH = 0x444B4B44; - -/*---------------- FSMC Configuration ---------------------------------------*/ + +/*---------------- FSMC Configuration ---------------------------------------*/ /*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/ - + FSMC_Bank1->BTCR[4] = 0x00001091; FSMC_Bank1->BTCR[5] = 0x00110212; } @@ -441,8 +441,8 @@ void SystemInit_ExtMemCtl(void) /** * @} */ - + /** * @} - */ + */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h index 9325273..8b2bd1c 100644 --- a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +++ b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h @@ -4,7 +4,7 @@ * @author MCD Application Team * @version V1.0.4 * @date 29-April-2016 - * @brief This file contains aliases definition for the STM32Cube HAL constants + * @brief This file contains aliases definition for the STM32Cube HAL constants * macros and functions maintained for legacy purpose. ****************************************************************************** * @attention @@ -60,7 +60,7 @@ /** * @} */ - + /** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose * @{ */ @@ -92,10 +92,10 @@ #define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4 #define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6 #define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8 -#define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO -#define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2 -#define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO -#define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4 +#define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO +#define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2 +#define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO +#define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4 #define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO #define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11 #define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1 @@ -111,21 +111,21 @@ #define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC #define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL #define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL -#define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1 +#define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1 /** * @} */ - + /** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose * @{ - */ - -#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG + */ + +#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG /** * @} - */ - + */ + /** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose * @{ */ @@ -150,7 +150,7 @@ #define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1 #define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2 #define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3 - + #define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT #define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT #define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT @@ -214,7 +214,7 @@ /** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose * @{ */ - + #define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE #define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE @@ -231,7 +231,7 @@ #define DAC2_CHANNEL_1 DAC_CHANNEL_1 #define DAC_WAVE_NONE ((uint32_t)0x00000000U) #define DAC_WAVE_NOISE ((uint32_t)DAC_CR_WAVE1_0) -#define DAC_WAVE_TRIANGLE ((uint32_t)DAC_CR_WAVE1_1) +#define DAC_WAVE_TRIANGLE ((uint32_t)DAC_CR_WAVE1_1) #define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE #define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE #define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE @@ -243,28 +243,28 @@ /** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose * @{ */ -#define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2 -#define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4 -#define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5 -#define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4 -#define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2 +#define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2 +#define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4 +#define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5 +#define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4 +#define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2 #define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32 #define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6 -#define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7 -#define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67 -#define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67 -#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32 -#define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76 -#define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6 -#define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7 -#define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6 - -#define IS_HAL_REMAPDMA IS_DMA_REMAP +#define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7 +#define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67 +#define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67 +#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32 +#define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76 +#define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6 +#define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7 +#define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6 + +#define IS_HAL_REMAPDMA IS_DMA_REMAP #define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE #define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE - - - + + + /** * @} */ @@ -272,7 +272,7 @@ /** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose * @{ */ - + #define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE #define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD #define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD @@ -347,11 +347,11 @@ /** * @} */ - + /** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose * @{ */ - + #define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6 @@ -364,7 +364,7 @@ /** * @} */ - + /** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose * @{ @@ -387,7 +387,7 @@ /** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose * @{ */ - + #define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef #define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef /** @@ -420,17 +420,17 @@ #define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1 #if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) -#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW -#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM -#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH -#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH +#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW +#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM +#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH +#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH #endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 */ -#if defined(STM32L1) - #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW - #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM - #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH - #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH +#if defined(STM32L1) + #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW + #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM + #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH + #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH #endif /* STM32L1 */ #if defined(STM32F0) || defined(STM32F3) || defined(STM32F1) @@ -456,7 +456,7 @@ #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7 #define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7 - + #define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER #define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER #define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD @@ -529,7 +529,7 @@ #define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION #define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS #define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS -#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS /* The following 3 definition have also been present in a temporary version of lptim.h */ /* They need to be renamed also to the right name, just in case */ @@ -559,7 +559,7 @@ /** * @} */ - + /** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose * @{ */ @@ -583,11 +583,11 @@ #define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1 #define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2 #define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3 - + #define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0 #define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1 #define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2 -#define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3 +#define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3 #define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 #define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 @@ -596,14 +596,14 @@ #define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 #define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0 -#define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1 +#define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1 #define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1 - -#define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO -#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 -#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 - + +#define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO +#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 +#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 + /** * @} */ @@ -612,7 +612,7 @@ * @{ */ #define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS -#if defined(STM32F7) +#if defined(STM32F7) #define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL #endif /** @@ -624,18 +624,18 @@ */ /* Compact Flash-ATA registers description */ -#define CF_DATA ATA_DATA -#define CF_SECTOR_COUNT ATA_SECTOR_COUNT -#define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER -#define CF_CYLINDER_LOW ATA_CYLINDER_LOW -#define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH -#define CF_CARD_HEAD ATA_CARD_HEAD -#define CF_STATUS_CMD ATA_STATUS_CMD +#define CF_DATA ATA_DATA +#define CF_SECTOR_COUNT ATA_SECTOR_COUNT +#define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER +#define CF_CYLINDER_LOW ATA_CYLINDER_LOW +#define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH +#define CF_CARD_HEAD ATA_CARD_HEAD +#define CF_STATUS_CMD ATA_STATUS_CMD #define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE -#define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA +#define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA /* Compact Flash-ATA commands */ -#define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD +#define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD #define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD #define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD #define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD @@ -648,11 +648,11 @@ /** * @} */ - + /** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose * @{ */ - + #define FORMAT_BIN RTC_FORMAT_BIN #define FORMAT_BCD RTC_FORMAT_BCD @@ -662,17 +662,17 @@ #define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE #define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE -#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE -#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE +#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE +#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE #define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE -#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE -#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE +#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE +#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE #define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE -#define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT -#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT +#define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT +#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT #define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT -#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1 +#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1 #define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1 #define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2 @@ -680,15 +680,15 @@ #define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1 #define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1 -#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT -#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 +#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT +#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 #define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 /** * @} */ - + /** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose * @{ */ @@ -709,7 +709,7 @@ * @} */ - + /** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose * @{ */ @@ -727,7 +727,7 @@ /** * @} */ - + /** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose * @{ */ @@ -743,13 +743,13 @@ /** * @} */ - + /** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose * @{ */ #define CCER_CCxE_MASK TIM_CCER_CCxE_MASK #define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK - + #define TIM_DMABase_CR1 TIM_DMABASE_CR1 #define TIM_DMABase_CR2 TIM_DMABASE_CR2 #define TIM_DMABase_SMCR TIM_DMABASE_SMCR @@ -848,7 +848,7 @@ * @} */ - + /** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose * @{ */ @@ -888,7 +888,7 @@ /** * @} */ - + /** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose * @{ */ @@ -902,18 +902,18 @@ #define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK #define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK -#define ETH_MMCCR ((uint32_t)0x00000100U) -#define ETH_MMCRIR ((uint32_t)0x00000104U) -#define ETH_MMCTIR ((uint32_t)0x00000108U) -#define ETH_MMCRIMR ((uint32_t)0x0000010CU) -#define ETH_MMCTIMR ((uint32_t)0x00000110U) -#define ETH_MMCTGFSCCR ((uint32_t)0x0000014CU) -#define ETH_MMCTGFMSCCR ((uint32_t)0x00000150U) -#define ETH_MMCTGFCR ((uint32_t)0x00000168U) -#define ETH_MMCRFCECR ((uint32_t)0x00000194U) -#define ETH_MMCRFAECR ((uint32_t)0x00000198U) +#define ETH_MMCCR ((uint32_t)0x00000100U) +#define ETH_MMCRIR ((uint32_t)0x00000104U) +#define ETH_MMCTIR ((uint32_t)0x00000108U) +#define ETH_MMCRIMR ((uint32_t)0x0000010CU) +#define ETH_MMCTIMR ((uint32_t)0x00000110U) +#define ETH_MMCTGFSCCR ((uint32_t)0x0000014CU) +#define ETH_MMCTGFMSCCR ((uint32_t)0x00000150U) +#define ETH_MMCTGFCR ((uint32_t)0x00000168U) +#define ETH_MMCRFCECR ((uint32_t)0x00000194U) +#define ETH_MMCRFAECR ((uint32_t)0x00000198U) #define ETH_MMCRGUFCR ((uint32_t)0x000001C4U) - + #define ETH_MAC_TXFIFO_FULL ((uint32_t)0x02000000) /* Tx FIFO full */ #define ETH_MAC_TXFIFONOT_EMPTY ((uint32_t)0x01000000) /* Tx FIFO not empty */ #define ETH_MAC_TXFIFO_WRITE_ACTIVE ((uint32_t)0x00400000) /* Tx FIFO write active */ @@ -948,7 +948,7 @@ /** * @} */ - + /** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose * @{ */ @@ -963,39 +963,39 @@ /** * @} - */ - + */ + #if defined(STM32L4xx) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) ||\ defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) /** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose * @{ */ #define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888 -#define DMA2D_RGB888 DMA2D_OUTPUT_RGB888 -#define DMA2D_RGB565 DMA2D_OUTPUT_RGB565 +#define DMA2D_RGB888 DMA2D_OUTPUT_RGB888 +#define DMA2D_RGB565 DMA2D_OUTPUT_RGB565 #define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555 #define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444 #define CM_ARGB8888 DMA2D_INPUT_ARGB8888 -#define CM_RGB888 DMA2D_INPUT_RGB888 -#define CM_RGB565 DMA2D_INPUT_RGB565 +#define CM_RGB888 DMA2D_INPUT_RGB888 +#define CM_RGB565 DMA2D_INPUT_RGB565 #define CM_ARGB1555 DMA2D_INPUT_ARGB1555 #define CM_ARGB4444 DMA2D_INPUT_ARGB4444 -#define CM_L8 DMA2D_INPUT_L8 -#define CM_AL44 DMA2D_INPUT_AL44 -#define CM_AL88 DMA2D_INPUT_AL88 -#define CM_L4 DMA2D_INPUT_L4 -#define CM_A8 DMA2D_INPUT_A8 -#define CM_A4 DMA2D_INPUT_A4 +#define CM_L8 DMA2D_INPUT_L8 +#define CM_AL44 DMA2D_INPUT_AL44 +#define CM_AL88 DMA2D_INPUT_AL88 +#define CM_L4 DMA2D_INPUT_L4 +#define CM_A8 DMA2D_INPUT_A8 +#define CM_A4 DMA2D_INPUT_A4 /** * @} - */ + */ #endif /* STM32L4xx || STM32F7*/ /** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose * @{ */ - + /** * @} */ @@ -1008,11 +1008,11 @@ #define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback /** * @} - */ + */ /** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose * @{ - */ + */ #define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef #define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef #define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish @@ -1022,12 +1022,12 @@ /*HASH Algorithm Selection*/ -#define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1 +#define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1 #define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224 #define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256 #define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5 -#define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH +#define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH #define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC #define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY @@ -1035,7 +1035,7 @@ /** * @} */ - + /** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose * @{ */ @@ -1129,17 +1129,17 @@ #define BRE_BitNumber BRE_BIT_NUMBER #define PWR_MODE_EVT PWR_PVD_MODE_NORMAL - + /** * @} - */ - + */ + /** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose * @{ */ #define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT -#define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback -#define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback +#define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback +#define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback /** * @} */ @@ -1150,7 +1150,7 @@ #define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo /** * @} - */ + */ /** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose * @{ @@ -1162,28 +1162,28 @@ /** * @} */ - + /** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose * @{ - */ + */ #define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback /** * @} */ - + /** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose * @{ - */ + */ #define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback /** * @} - */ - - + */ + + /** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose * @{ */ - + /** * @} */ @@ -1198,8 +1198,8 @@ #define AES_FLAG_CCF CRYP_FLAG_CCF /** * @} - */ - + */ + /** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose * @{ */ @@ -1208,7 +1208,7 @@ #define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH #define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM #define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC -#define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM +#define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM #define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC #define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI #define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK @@ -1227,7 +1227,7 @@ * @} */ - + /** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose * @{ */ @@ -1324,7 +1324,7 @@ /** * @} */ - + /** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose * @{ */ @@ -1397,7 +1397,7 @@ #define COMP_START __HAL_COMP_ENABLE #define COMP_STOP __HAL_COMP_DISABLE #define COMP_LOCK __HAL_COMP_LOCK - + #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ @@ -1584,7 +1584,7 @@ #define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \ ((WAVE) == DAC_WAVE_NOISE)|| \ ((WAVE) == DAC_WAVE_TRIANGLE)) - + /** * @} */ @@ -1603,11 +1603,11 @@ /** * @} */ - + /** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose * @{ */ - + #define __HAL_I2C_RESET_CR2 I2C_RESET_CR2 #define __HAL_I2C_GENERATE_START I2C_GENERATE_START #define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE @@ -1626,11 +1626,11 @@ /** * @} */ - + /** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose * @{ */ - + #define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE #define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT @@ -1641,7 +1641,7 @@ /** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose * @{ */ - + #define __IRDA_DISABLE __HAL_IRDA_DISABLE #define __IRDA_ENABLE __HAL_IRDA_ENABLE @@ -1650,7 +1650,7 @@ #define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE #define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION -#define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE +#define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE /** @@ -1679,8 +1679,8 @@ /** * @} */ - - + + /** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose * @{ */ @@ -1745,7 +1745,7 @@ #if defined (STM32F4) #define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT() #define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT() -#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG() +#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG() #define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG() #define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT() #else @@ -1753,17 +1753,17 @@ #define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT #define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT #define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT -#define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG +#define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG #endif /* STM32F4 */ -/** +/** * @} - */ - - + */ + + /** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose * @{ */ - + #define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI #define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI @@ -1780,8 +1780,8 @@ #define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE #define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET #define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET -#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE -#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE +#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE +#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE #define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE #define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE #define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET @@ -2219,13 +2219,13 @@ #define __USART4_CLK_DISABLE __HAL_RCC_USART4_CLK_DISABLE #define __USART4_CLK_ENABLE __HAL_RCC_USART4_CLK_ENABLE #define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_USART4_CLK_SLEEP_ENABLE -#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_USART4_CLK_SLEEP_DISABLE +#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_USART4_CLK_SLEEP_DISABLE #define __USART4_FORCE_RESET __HAL_RCC_USART4_FORCE_RESET #define __USART4_RELEASE_RESET __HAL_RCC_USART4_RELEASE_RESET #define __USART5_CLK_DISABLE __HAL_RCC_USART5_CLK_DISABLE #define __USART5_CLK_ENABLE __HAL_RCC_USART5_CLK_ENABLE #define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_USART5_CLK_SLEEP_ENABLE -#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_USART5_CLK_SLEEP_DISABLE +#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_USART5_CLK_SLEEP_DISABLE #define __USART5_FORCE_RESET __HAL_RCC_USART5_FORCE_RESET #define __USART5_RELEASE_RESET __HAL_RCC_USART5_RELEASE_RESET #define __USART7_CLK_DISABLE __HAL_RCC_USART7_CLK_DISABLE @@ -2278,111 +2278,111 @@ #define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE #define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE #define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE -#define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE +#define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE #define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE -#define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE +#define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE #define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE -#define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE +#define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE #define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE -#define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE +#define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE #define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE #define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE #define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE -#define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE +#define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE #define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE #define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET #define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET #define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE #define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE -#define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE +#define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE #define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE #define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE #define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET #define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET #define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE -#define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE +#define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE #define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE #define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE #define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET #define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET #define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE -#define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE +#define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE #define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE #define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE #define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET #define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET -#define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE +#define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE #define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE -#define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE +#define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE #define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE -#define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE +#define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE #define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE -#define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE +#define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE #define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE -#define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE +#define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE #define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE -#define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE +#define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE #define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE -#define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE +#define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE #define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE #define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE #define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE -#define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE +#define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE #define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE -#define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE +#define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE #define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE #define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE #define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET #define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET #define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE -#define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE +#define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE #define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE #define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE #define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET #define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET #define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE -#define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE +#define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE #define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE #define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE #define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET #define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET #define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE -#define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE +#define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE #define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE #define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE #define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET #define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET #define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE -#define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE +#define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE #define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE #define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE #define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET #define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE -#define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE +#define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE #define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE -#define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE +#define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE #define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE #define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE #define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET #define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET #define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE -#define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE +#define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE #define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE #define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE #define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET #define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET #define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE -#define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE +#define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE #define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE #define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE #define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET #define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET #define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE -#define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE +#define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE #define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE #define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE #define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET -#define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET +#define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET #define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE #define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE #define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE @@ -2390,29 +2390,29 @@ #define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED #define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED #define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET -#define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET +#define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET #define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE -#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE +#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE #define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED -#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED -#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET -#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE +#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED +#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET +#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE #define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE -#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE +#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE #define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE -#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE +#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE #define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE -#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE +#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE #define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE -#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE +#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE #define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET #define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET #define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE -#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE +#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE #define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET #define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET #define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE -#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE +#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE #define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE #define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE #define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET @@ -2638,7 +2638,7 @@ #define RCC_IT_HSI14 RCC_IT_HSI14RDY #if defined(STM32L0) -#define RCC_IT_LSECSS RCC_IT_CSSLSE +#define RCC_IT_LSECSS RCC_IT_CSSLSE #define RCC_IT_CSS RCC_IT_CSSHSE #endif @@ -2769,16 +2769,16 @@ /** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose * @{ */ -#define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit) +#define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit) /** * @} */ - + /** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose * @{ */ - + #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG #define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT #define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT @@ -2815,7 +2815,7 @@ #define IS_ALARM_MASK IS_RTC_ALARM_MASK #define IS_TAMPER IS_RTC_TAMPER #define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE -#define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER +#define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER #define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT #define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE #define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION @@ -2842,24 +2842,24 @@ #if defined(STM32F4) #define SD_SDMMC_DISABLED SD_SDIO_DISABLED -#define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY -#define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED -#define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION -#define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND -#define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT -#define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED -#define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE -#define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE -#define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE -#define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL -#define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT -#define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT -#define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG -#define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG -#define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT -#define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT -#define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS -#define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT +#define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY +#define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED +#define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION +#define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND +#define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT +#define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED +#define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE +#define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE +#define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE +#define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL +#define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT +#define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT +#define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG +#define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG +#define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT +#define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT +#define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS +#define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT #define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND /* alias CMSIS */ #define SDMMC1_IRQn SDIO_IRQn @@ -2868,8 +2868,8 @@ #if defined(STM32F7) || defined(STM32L4) #define SD_SDIO_DISABLED SD_SDMMC_DISABLED -#define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY -#define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED +#define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY +#define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED #define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION #define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND #define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT @@ -2909,7 +2909,7 @@ #define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE #define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE -#define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE +#define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE /** * @} @@ -2941,7 +2941,7 @@ /** * @} */ - + /** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose * @{ */ @@ -2953,8 +2953,8 @@ #define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD -#define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE -#define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE +#define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE +#define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE /** * @} @@ -3059,7 +3059,7 @@ /** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose * @{ */ - + #define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT #define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT #define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG @@ -3068,7 +3068,7 @@ #define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER #define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER -#define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE +#define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE #define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE #define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE /** @@ -3108,7 +3108,7 @@ /** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose * @{ */ - + /** * @} */ diff --git a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h index c2f16d6..3b949f7 100644 --- a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h +++ b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h @@ -4,7 +4,7 @@ * @author MCD Application Team * @version V1.0.4 * @date 29-April-2016 - * @brief This file contains all the functions prototypes for the HAL + * @brief This file contains all the functions prototypes for the HAL * module driver. ****************************************************************************** * @attention @@ -34,7 +34,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F1xx_HAL_H @@ -53,7 +53,7 @@ /** @addtogroup HAL * @{ - */ + */ /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ @@ -65,33 +65,33 @@ */ /** @defgroup DBGMCU_Freeze_Unfreeze Freeze Unfreeze Peripherals in Debug mode - * @brief Freeze/Unfreeze Peripherals in Debug mode + * @brief Freeze/Unfreeze Peripherals in Debug mode * Note: On devices STM32F10xx8 and STM32F10xxB, * STM32F101xC/D/E and STM32F103xC/D/E, * STM32F101xF/G and STM32F103xF/G * STM32F10xx4 and STM32F10xx6 - * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in + * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in * debug mode (not accessible by the user software in normal mode). * Refer to errata sheet of these devices for more details. * @{ */ - + /* Peripherals on APB1 */ /** - * @brief TIM2 Peripherals Debug mode + * @brief TIM2 Peripherals Debug mode */ #define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM2_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM2_STOP) /** - * @brief TIM3 Peripherals Debug mode + * @brief TIM3 Peripherals Debug mode */ #define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM3_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM3_STOP) #if defined (DBGMCU_CR_DBG_TIM4_STOP) /** - * @brief TIM4 Peripherals Debug mode + * @brief TIM4 Peripherals Debug mode */ #define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM4_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM4_STOP) @@ -99,7 +99,7 @@ #if defined (DBGMCU_CR_DBG_TIM5_STOP) /** - * @brief TIM5 Peripherals Debug mode + * @brief TIM5 Peripherals Debug mode */ #define __HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM5_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM5() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM5_STOP) @@ -107,7 +107,7 @@ #if defined (DBGMCU_CR_DBG_TIM6_STOP) /** - * @brief TIM6 Peripherals Debug mode + * @brief TIM6 Peripherals Debug mode */ #define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM6_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM6_STOP) @@ -115,7 +115,7 @@ #if defined (DBGMCU_CR_DBG_TIM7_STOP) /** - * @brief TIM7 Peripherals Debug mode + * @brief TIM7 Peripherals Debug mode */ #define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM7_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM7_STOP) @@ -123,7 +123,7 @@ #if defined (DBGMCU_CR_DBG_TIM12_STOP) /** - * @brief TIM12 Peripherals Debug mode + * @brief TIM12 Peripherals Debug mode */ #define __HAL_DBGMCU_FREEZE_TIM12() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM12_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM12() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM12_STOP) @@ -131,7 +131,7 @@ #if defined (DBGMCU_CR_DBG_TIM13_STOP) /** - * @brief TIM13 Peripherals Debug mode + * @brief TIM13 Peripherals Debug mode */ #define __HAL_DBGMCU_FREEZE_TIM13() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM13_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM13() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM13_STOP) @@ -139,33 +139,33 @@ #if defined (DBGMCU_CR_DBG_TIM14_STOP) /** - * @brief TIM14 Peripherals Debug mode + * @brief TIM14 Peripherals Debug mode */ #define __HAL_DBGMCU_FREEZE_TIM14() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM14_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM14() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM14_STOP) #endif /** - * @brief WWDG Peripherals Debug mode + * @brief WWDG Peripherals Debug mode */ #define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_WWDG_STOP) #define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_WWDG_STOP) /** - * @brief IWDG Peripherals Debug mode + * @brief IWDG Peripherals Debug mode */ #define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_IWDG_STOP) #define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_IWDG_STOP) /** - * @brief I2C1 Peripherals Debug mode + * @brief I2C1 Peripherals Debug mode */ #define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT) #define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT) #if defined (DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT) /** - * @brief I2C2 Peripherals Debug mode + * @brief I2C2 Peripherals Debug mode */ #define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT) #define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT) @@ -173,7 +173,7 @@ #if defined (DBGMCU_CR_DBG_CAN1_STOP) /** - * @brief CAN1 Peripherals Debug mode + * @brief CAN1 Peripherals Debug mode */ #define __HAL_DBGMCU_FREEZE_CAN1() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN1_STOP) #define __HAL_DBGMCU_UNFREEZE_CAN1() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN1_STOP) @@ -181,16 +181,16 @@ #if defined (DBGMCU_CR_DBG_CAN2_STOP) /** - * @brief CAN2 Peripherals Debug mode + * @brief CAN2 Peripherals Debug mode */ #define __HAL_DBGMCU_FREEZE_CAN2() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN2_STOP) #define __HAL_DBGMCU_UNFREEZE_CAN2() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN2_STOP) -#endif - +#endif + /* Peripherals on APB2 */ #if defined (DBGMCU_CR_DBG_TIM1_STOP) /** - * @brief TIM1 Peripherals Debug mode + * @brief TIM1 Peripherals Debug mode */ #define __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM1_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM1_STOP) @@ -198,7 +198,7 @@ #if defined (DBGMCU_CR_DBG_TIM8_STOP) /** - * @brief TIM8 Peripherals Debug mode + * @brief TIM8 Peripherals Debug mode */ #define __HAL_DBGMCU_FREEZE_TIM8() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM8_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM8() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM8_STOP) @@ -206,7 +206,7 @@ #if defined (DBGMCU_CR_DBG_TIM9_STOP) /** - * @brief TIM9 Peripherals Debug mode + * @brief TIM9 Peripherals Debug mode */ #define __HAL_DBGMCU_FREEZE_TIM9() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM9_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM9() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM9_STOP) @@ -214,7 +214,7 @@ #if defined (DBGMCU_CR_DBG_TIM10_STOP) /** - * @brief TIM10 Peripherals Debug mode + * @brief TIM10 Peripherals Debug mode */ #define __HAL_DBGMCU_FREEZE_TIM10() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM10_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM10() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM10_STOP) @@ -222,7 +222,7 @@ #if defined (DBGMCU_CR_DBG_TIM11_STOP) /** - * @brief TIM11 Peripherals Debug mode + * @brief TIM11 Peripherals Debug mode */ #define __HAL_DBGMCU_FREEZE_TIM11() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM11_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM11() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM11_STOP) @@ -231,7 +231,7 @@ #if defined (DBGMCU_CR_DBG_TIM15_STOP) /** - * @brief TIM15 Peripherals Debug mode + * @brief TIM15 Peripherals Debug mode */ #define __HAL_DBGMCU_FREEZE_TIM15() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM15_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM15() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM15_STOP) @@ -239,7 +239,7 @@ #if defined (DBGMCU_CR_DBG_TIM16_STOP) /** - * @brief TIM16 Peripherals Debug mode + * @brief TIM16 Peripherals Debug mode */ #define __HAL_DBGMCU_FREEZE_TIM16() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM16_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM16_STOP) @@ -247,7 +247,7 @@ #if defined (DBGMCU_CR_DBG_TIM17_STOP) /** - * @brief TIM17 Peripherals Debug mode + * @brief TIM17 Peripherals Debug mode */ #define __HAL_DBGMCU_FREEZE_TIM17() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM17_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM17() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM17_STOP) @@ -313,12 +313,12 @@ void HAL_DBGMCU_DisableDBGStandbyMode(void); /** * @} - */ + */ /** * @} - */ - + */ + #ifdef __cplusplus } #endif diff --git a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h index 30788b0..d2ee169 100644 --- a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h +++ b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h @@ -33,7 +33,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F1xx_HAL_CORTEX_H @@ -52,7 +52,7 @@ /** @addtogroup CORTEX * @{ - */ + */ /* Exported types ------------------------------------------------------------*/ /** @defgroup CORTEX_Exported_Types Cortex Exported Types * @{ @@ -60,31 +60,31 @@ #if (__MPU_PRESENT == 1) /** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition - * @brief MPU Region initialization structure + * @brief MPU Region initialization structure * @{ */ typedef struct { - uint8_t Enable; /*!< Specifies the status of the region. + uint8_t Enable; /*!< Specifies the status of the region. This parameter can be a value of @ref CORTEX_MPU_Region_Enable */ - uint8_t Number; /*!< Specifies the number of the region to protect. + uint8_t Number; /*!< Specifies the number of the region to protect. This parameter can be a value of @ref CORTEX_MPU_Region_Number */ uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */ - uint8_t Size; /*!< Specifies the size of the region to protect. + uint8_t Size; /*!< Specifies the size of the region to protect. This parameter can be a value of @ref CORTEX_MPU_Region_Size */ - uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable. - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ + uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ uint8_t TypeExtField; /*!< Specifies the TEX field level. - This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */ - uint8_t AccessPermission; /*!< Specifies the region access permission type. + This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */ + uint8_t AccessPermission; /*!< Specifies the region access permission type. This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */ - uint8_t DisableExec; /*!< Specifies the instruction access status. + uint8_t DisableExec; /*!< Specifies the instruction access status. This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */ - uint8_t IsShareable; /*!< Specifies the shareability status of the protected region. + uint8_t IsShareable; /*!< Specifies the shareability status of the protected region. This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */ - uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected. + uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected. This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */ - uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region. + uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region. This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */ }MPU_Region_InitTypeDef; /** @@ -102,7 +102,7 @@ typedef struct */ -/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group +/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group * @{ */ @@ -134,7 +134,7 @@ typedef struct /** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control * @{ */ -#define MPU_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000) +#define MPU_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000) #define MPU_HARDFAULT_NMI ((uint32_t)0x00000002) #define MPU_PRIVILEGED_DEFAULT ((uint32_t)0x00000004) #define MPU_HFNMI_PRIVDEF ((uint32_t)0x00000006) @@ -202,44 +202,44 @@ typedef struct */ #define MPU_REGION_SIZE_32B ((uint8_t)0x04) #define MPU_REGION_SIZE_64B ((uint8_t)0x05) -#define MPU_REGION_SIZE_128B ((uint8_t)0x06) -#define MPU_REGION_SIZE_256B ((uint8_t)0x07) -#define MPU_REGION_SIZE_512B ((uint8_t)0x08) -#define MPU_REGION_SIZE_1KB ((uint8_t)0x09) +#define MPU_REGION_SIZE_128B ((uint8_t)0x06) +#define MPU_REGION_SIZE_256B ((uint8_t)0x07) +#define MPU_REGION_SIZE_512B ((uint8_t)0x08) +#define MPU_REGION_SIZE_1KB ((uint8_t)0x09) #define MPU_REGION_SIZE_2KB ((uint8_t)0x0A) -#define MPU_REGION_SIZE_4KB ((uint8_t)0x0B) -#define MPU_REGION_SIZE_8KB ((uint8_t)0x0C) -#define MPU_REGION_SIZE_16KB ((uint8_t)0x0D) -#define MPU_REGION_SIZE_32KB ((uint8_t)0x0E) -#define MPU_REGION_SIZE_64KB ((uint8_t)0x0F) +#define MPU_REGION_SIZE_4KB ((uint8_t)0x0B) +#define MPU_REGION_SIZE_8KB ((uint8_t)0x0C) +#define MPU_REGION_SIZE_16KB ((uint8_t)0x0D) +#define MPU_REGION_SIZE_32KB ((uint8_t)0x0E) +#define MPU_REGION_SIZE_64KB ((uint8_t)0x0F) #define MPU_REGION_SIZE_128KB ((uint8_t)0x10) #define MPU_REGION_SIZE_256KB ((uint8_t)0x11) #define MPU_REGION_SIZE_512KB ((uint8_t)0x12) -#define MPU_REGION_SIZE_1MB ((uint8_t)0x13) -#define MPU_REGION_SIZE_2MB ((uint8_t)0x14) -#define MPU_REGION_SIZE_4MB ((uint8_t)0x15) -#define MPU_REGION_SIZE_8MB ((uint8_t)0x16) +#define MPU_REGION_SIZE_1MB ((uint8_t)0x13) +#define MPU_REGION_SIZE_2MB ((uint8_t)0x14) +#define MPU_REGION_SIZE_4MB ((uint8_t)0x15) +#define MPU_REGION_SIZE_8MB ((uint8_t)0x16) #define MPU_REGION_SIZE_16MB ((uint8_t)0x17) #define MPU_REGION_SIZE_32MB ((uint8_t)0x18) #define MPU_REGION_SIZE_64MB ((uint8_t)0x19) #define MPU_REGION_SIZE_128MB ((uint8_t)0x1A) #define MPU_REGION_SIZE_256MB ((uint8_t)0x1B) #define MPU_REGION_SIZE_512MB ((uint8_t)0x1C) -#define MPU_REGION_SIZE_1GB ((uint8_t)0x1D) -#define MPU_REGION_SIZE_2GB ((uint8_t)0x1E) +#define MPU_REGION_SIZE_1GB ((uint8_t)0x1D) +#define MPU_REGION_SIZE_2GB ((uint8_t)0x1E) #define MPU_REGION_SIZE_4GB ((uint8_t)0x1F) -/** +/** * @} */ - -/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes + +/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes * @{ */ -#define MPU_REGION_NO_ACCESS ((uint8_t)0x00) -#define MPU_REGION_PRIV_RW ((uint8_t)0x01) -#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02) -#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03) -#define MPU_REGION_PRIV_RO ((uint8_t)0x05) +#define MPU_REGION_NO_ACCESS ((uint8_t)0x00) +#define MPU_REGION_PRIV_RW ((uint8_t)0x01) +#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02) +#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03) +#define MPU_REGION_PRIV_RO ((uint8_t)0x05) #define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06) /** * @} @@ -248,11 +248,11 @@ typedef struct /** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number * @{ */ -#define MPU_REGION_NUMBER0 ((uint8_t)0x00) -#define MPU_REGION_NUMBER1 ((uint8_t)0x01) -#define MPU_REGION_NUMBER2 ((uint8_t)0x02) -#define MPU_REGION_NUMBER3 ((uint8_t)0x03) -#define MPU_REGION_NUMBER4 ((uint8_t)0x04) +#define MPU_REGION_NUMBER0 ((uint8_t)0x00) +#define MPU_REGION_NUMBER1 ((uint8_t)0x01) +#define MPU_REGION_NUMBER2 ((uint8_t)0x02) +#define MPU_REGION_NUMBER3 ((uint8_t)0x03) +#define MPU_REGION_NUMBER4 ((uint8_t)0x04) #define MPU_REGION_NUMBER5 ((uint8_t)0x05) #define MPU_REGION_NUMBER6 ((uint8_t)0x06) #define MPU_REGION_NUMBER7 ((uint8_t)0x07) @@ -264,14 +264,14 @@ typedef struct /** * @} */ - + /* Private macro -------------------------------------------------------------*/ /** @defgroup CORTEX_Private_Macros CORTEX Private Macros * @{ - */ + */ -/** @defgroup CORTEX_Preemption_Priority_Group_Macro CORTEX Preemption Priority Group +/** @defgroup CORTEX_Preemption_Priority_Group_Macro CORTEX Preemption Priority Group * @{ */ #define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \ @@ -281,7 +281,7 @@ typedef struct ((GROUP) == NVIC_PRIORITYGROUP_4)) #define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) - + #define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) #define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x00) @@ -292,7 +292,7 @@ typedef struct /** @defgroup CORTEX_SysTick_clock_source_Macro_Private CORTEX SysTick clock source * @{ - */ + */ #define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \ ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8)) /** @@ -377,7 +377,7 @@ typedef struct /** @addtogroup CORTEX_Exported_Functions_Group1 * @{ - */ + */ /* Initialization and de-initialization functions *****************************/ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup); void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority); @@ -391,7 +391,7 @@ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); /** @addtogroup CORTEX_Exported_Functions_Group2 * @{ - */ + */ /* Peripheral Control functions ***********************************************/ #if (__MPU_PRESENT == 1) void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init); @@ -412,10 +412,10 @@ void HAL_SYSTICK_Callback(void); /** * @} */ - -/* Private functions ---------------------------------------------------------*/ + +/* Private functions ---------------------------------------------------------*/ /** @defgroup CORTEX_Private_Functions CORTEX Private Functions - * @brief CORTEX private functions + * @brief CORTEX private functions * @{ */ @@ -428,15 +428,15 @@ __STATIC_INLINE void HAL_MPU_Disable(void) { /* Disable fault exceptions */ SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; - + /* Disable the MPU */ MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; } /** * @brief Enables the MPU - * @param MPU_Control: Specifies the control mode of the MPU during hard fault, - * NMI, FAULTMASK and privileged accessto the default memory + * @param MPU_Control: Specifies the control mode of the MPU during hard fault, + * NMI, FAULTMASK and privileged accessto the default memory * This parameter can be one of the following values: * @arg MPU_HFNMI_PRIVDEF_NONE * @arg MPU_HARDFAULT_NMI @@ -448,7 +448,7 @@ __STATIC_INLINE void HAL_MPU_Enable(uint32_t MPU_Control) { /* Enable the MPU */ MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; - + /* Enable fault exceptions */ SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; } @@ -460,17 +460,17 @@ __STATIC_INLINE void HAL_MPU_Enable(uint32_t MPU_Control) /** * @} - */ + */ /** * @} */ - + #ifdef __cplusplus } #endif #endif /* __STM32F1xx_HAL_CORTEX_H */ - + /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h index b0f1693..8600be2 100644 --- a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h +++ b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h @@ -4,8 +4,8 @@ * @author MCD Application Team * @version V1.0.4 * @date 29-April-2016 - * @brief This file contains HAL common defines, enumeration, macros and - * structures definitions. + * @brief This file contains HAL common defines, enumeration, macros and + * structures definitions. ****************************************************************************** * @attention * @@ -51,10 +51,10 @@ /* Exported types ------------------------------------------------------------*/ -/** - * @brief HAL Status structures definition - */ -typedef enum +/** + * @brief HAL Status structures definition + */ +typedef enum { HAL_OK = 0x00, HAL_ERROR = 0x01, @@ -62,13 +62,13 @@ typedef enum HAL_TIMEOUT = 0x03 } HAL_StatusTypeDef; -/** - * @brief HAL Lock structures definition +/** + * @brief HAL Lock structures definition */ -typedef enum +typedef enum { HAL_UNLOCKED = 0x00, - HAL_LOCKED = 0x01 + HAL_LOCKED = 0x01 } HAL_LockTypeDef; /* Exported macro ------------------------------------------------------------*/ @@ -88,11 +88,11 @@ typedef enum /** @brief Reset the Handle's State field. * @param __HANDLE__: specifies the Peripheral Handle. - * @note This macro can be used for the following purpose: + * @note This macro can be used for the following purpose: * - When the Handle is declared as local variable; before passing it as parameter - * to HAL_PPP_Init() for the first time, it is mandatory to use this macro + * to HAL_PPP_Init() for the first time, it is mandatory to use this macro * to set to 0 the Handle's "State" field. - * Otherwise, "State" field may have any random value and the first time the function + * Otherwise, "State" field may have any random value and the first time the function * HAL_PPP_Init() is called, the low level hardware initialization will be missed * (i.e. HAL_PPP_MspInit() will not be executed). * - When there is a need to reconfigure the low level hardware: instead of calling @@ -139,62 +139,62 @@ typedef enum #ifndef __ALIGN_END #define __ALIGN_END __attribute__ ((aligned (4))) #endif /* __ALIGN_END */ - #ifndef __ALIGN_BEGIN + #ifndef __ALIGN_BEGIN #define __ALIGN_BEGIN #endif /* __ALIGN_BEGIN */ #else #ifndef __ALIGN_END #define __ALIGN_END #endif /* __ALIGN_END */ - #ifndef __ALIGN_BEGIN + #ifndef __ALIGN_BEGIN #if defined (__CC_ARM) /* ARM Compiler */ - #define __ALIGN_BEGIN __align(4) + #define __ALIGN_BEGIN __align(4) #elif defined (__ICCARM__) /* IAR Compiler */ - #define __ALIGN_BEGIN + #define __ALIGN_BEGIN #endif /* __CC_ARM */ #endif /* __ALIGN_BEGIN */ #endif /* __GNUC__ */ -/** +/** * @brief __RAM_FUNC definition - */ + */ #if defined ( __CC_ARM ) /* ARM Compiler ------------ - RAM functions are defined using the toolchain options. + RAM functions are defined using the toolchain options. Functions that are executed in RAM should reside in a separate source module. - Using the 'Options for File' dialog you can simply change the 'Code / Const' + Using the 'Options for File' dialog you can simply change the 'Code / Const' area of a module to a memory space in physical RAM. Available memory areas are declared in the 'Target' tab of the 'Options for Target' - dialog. + dialog. */ -#define __RAM_FUNC HAL_StatusTypeDef +#define __RAM_FUNC HAL_StatusTypeDef #elif defined ( __ICCARM__ ) /* ICCARM Compiler --------------- - RAM functions are defined using a specific toolchain keyword "__ramfunc". + RAM functions are defined using a specific toolchain keyword "__ramfunc". */ #define __RAM_FUNC __ramfunc HAL_StatusTypeDef #elif defined ( __GNUC__ ) /* GNU Compiler ------------ - RAM functions are defined using a specific toolchain attribute + RAM functions are defined using a specific toolchain attribute "__attribute__((section(".RamFunc")))". */ #define __RAM_FUNC HAL_StatusTypeDef __attribute__((section(".RamFunc"))) #endif -/** +/** * @brief __NOINLINE definition - */ + */ #if defined ( __CC_ARM ) || defined ( __GNUC__ ) -/* ARM & GNUCompiler - ---------------- +/* ARM & GNUCompiler + ---------------- */ -#define __NOINLINE __attribute__ ( (noinline) ) +#define __NOINLINE __attribute__ ( (noinline) ) #elif defined ( __ICCARM__ ) /* ICCARM Compiler diff --git a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h index 5d344b2..d26fd60 100644 --- a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h +++ b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h @@ -33,7 +33,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F1xx_HAL_DMA_H @@ -52,56 +52,56 @@ /** @addtogroup DMA * @{ - */ + */ /* Exported types ------------------------------------------------------------*/ /** @defgroup DMA_Exported_Types DMA Exported Types * @{ */ - -/** + +/** * @brief DMA Configuration Structure definition */ typedef struct { - uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, + uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, from memory to memory or from peripheral to memory. This parameter can be a value of @ref DMA_Data_transfer_direction */ uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not. This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ - + uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not. This parameter can be a value of @ref DMA_Memory_incremented_mode */ - + uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width. This parameter can be a value of @ref DMA_Peripheral_data_size */ uint32_t MemDataAlignment; /*!< Specifies the Memory data width. This parameter can be a value of @ref DMA_Memory_data_size */ - + uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx. This parameter can be a value of @ref DMA_mode @note The circular buffer mode cannot be used if the memory-to-memory - data transfer is configured on the selected Channel */ + data transfer is configured on the selected Channel */ uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx. This parameter can be a value of @ref DMA_Priority_level */ } DMA_InitTypeDef; -/** +/** * @brief DMA Configuration enumeration values definition - */ -typedef enum + */ +typedef enum { DMA_MODE = 0, /*!< Control related DMA mode Parameter in DMA_InitTypeDef */ DMA_PRIORITY = 1, /*!< Control related priority level Parameter in DMA_InitTypeDef */ - + } DMA_ControlTypeDef; /** - * @brief HAL DMA State structures definition + * @brief HAL DMA State structures definition */ typedef enum { @@ -113,7 +113,7 @@ typedef enum HAL_DMA_STATE_ERROR = 0x04, /*!< DMA error state */ }HAL_DMA_StateTypeDef; -/** +/** * @brief HAL DMA Error Code structure definition */ typedef enum @@ -122,29 +122,29 @@ typedef enum HAL_DMA_HALF_TRANSFER = 0x01, /*!< Half Transfer */ }HAL_DMA_LevelCompleteTypeDef; -/** +/** * @brief DMA handle Structure definition */ typedef struct __DMA_HandleTypeDef { DMA_Channel_TypeDef *Instance; /*!< Register base address */ - - DMA_InitTypeDef Init; /*!< DMA communication parameters */ - - HAL_LockTypeDef Lock; /*!< DMA locking object */ - + + DMA_InitTypeDef Init; /*!< DMA communication parameters */ + + HAL_LockTypeDef Lock; /*!< DMA locking object */ + HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ - - void *Parent; /*!< Parent object state */ - + + void *Parent; /*!< Parent object state */ + void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */ - + void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */ - + void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */ - + __IO uint32_t ErrorCode; /*!< DMA Error code */ -} DMA_HandleTypeDef; +} DMA_HandleTypeDef; /** * @} */ @@ -168,7 +168,7 @@ typedef struct __DMA_HandleTypeDef /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction * @{ - */ + */ #define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000) /*!< Peripheral to memory direction */ #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */ #define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_CCR_MEM2MEM) /*!< Memory to memory direction */ @@ -179,16 +179,16 @@ typedef struct __DMA_HandleTypeDef /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode * @{ - */ + */ #define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */ #define DMA_PINC_DISABLE ((uint32_t)0x00000000) /*!< Peripheral increment mode Disable */ /** * @} - */ + */ /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode * @{ - */ + */ #define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */ #define DMA_MINC_DISABLE ((uint32_t)0x00000000) /*!< Memory increment mode Disable */ /** @@ -197,16 +197,16 @@ typedef struct __DMA_HandleTypeDef /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size * @{ - */ + */ #define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Peripheral data alignment: Byte */ #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */ #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment: Word */ /** * @} - */ + */ /** @defgroup DMA_Memory_data_size DMA Memory data size - * @{ + * @{ */ #define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Memory data alignment: Byte */ #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment: HalfWord */ @@ -217,7 +217,7 @@ typedef struct __DMA_HandleTypeDef /** @defgroup DMA_mode DMA mode * @{ - */ + */ #define DMA_NORMAL ((uint32_t)0x00000000) /*!< Normal mode */ #define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular mode */ /** @@ -233,7 +233,7 @@ typedef struct __DMA_HandleTypeDef #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */ /** * @} - */ + */ /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions @@ -248,7 +248,7 @@ typedef struct __DMA_HandleTypeDef /** @defgroup DMA_flag_definitions DMA flag definitions * @{ - */ + */ #define DMA_FLAG_GL1 ((uint32_t)0x00000001) #define DMA_FLAG_TC1 ((uint32_t)0x00000002) #define DMA_FLAG_HT1 ((uint32_t)0x00000004) @@ -284,7 +284,7 @@ typedef struct __DMA_HandleTypeDef /** * @} */ - + /* Exported macro ------------------------------------------------------------*/ /** @defgroup DMA_Exported_Macros DMA Exported Macros @@ -317,7 +317,7 @@ typedef struct __DMA_HandleTypeDef /** * @brief Enables the specified DMA Channel interrupts. * @param __HANDLE__: DMA handle - * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. + * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. * This parameter can be any combination of the following values: * @arg DMA_IT_TC: Transfer complete interrupt mask * @arg DMA_IT_HT: Half transfer complete interrupt mask @@ -329,7 +329,7 @@ typedef struct __DMA_HandleTypeDef /** * @brief Disables the specified DMA Channel interrupts. * @param __HANDLE__: DMA handle - * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. + * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. * This parameter can be any combination of the following values: * @arg DMA_IT_TC: Transfer complete interrupt mask * @arg DMA_IT_HT: Half transfer complete interrupt mask @@ -353,7 +353,7 @@ typedef struct __DMA_HandleTypeDef /** * @brief Returns the number of remaining data units in the current DMAy Channelx transfer. * @param __HANDLE__: DMA handle - * + * * @retval The number of remaining data units in the current DMA Channel transfer. */ #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR) @@ -363,14 +363,14 @@ typedef struct __DMA_HandleTypeDef */ /* Include DMA HAL Extension module */ -#include "stm32f1xx_hal_dma_ex.h" +#include "stm32f1xx_hal_dma_ex.h" /* Exported functions --------------------------------------------------------*/ /** @addtogroup DMA_Exported_Functions DMA Exported Functions * @{ */ -/** @addtogroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions +/** @addtogroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions * @{ */ /* Initialization and de-initialization functions *****************************/ @@ -380,7 +380,7 @@ HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma); * @} */ -/** @addtogroup DMA_Exported_Functions_Group2 Input and Output operation functions +/** @addtogroup DMA_Exported_Functions_Group2 Input and Output operation functions * @{ */ /* IO operation functions *****************************************************/ @@ -409,16 +409,16 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); /* Private Constants -------------------------------------------------------------*/ /** @defgroup DMA_Private_Constants DMA Private Constants - * @brief DMA private defines and constants + * @brief DMA private defines and constants * @{ */ /** * @} - */ + */ /* Private macros ------------------------------------------------------------*/ /** @defgroup DMA_Private_Macros DMA Private Macros - * @brief DMA private macros + * @brief DMA private macros * @{ */ @@ -426,7 +426,7 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ - ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) + ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ ((STATE) == DMA_PINC_DISABLE)) @@ -443,20 +443,20 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); ((SIZE) == DMA_MDATAALIGN_WORD )) #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ - ((MODE) == DMA_CIRCULAR)) + ((MODE) == DMA_CIRCULAR)) #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \ ((PRIORITY) == DMA_PRIORITY_HIGH) || \ - ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) + ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) /** * @} - */ + */ /* Private functions ---------------------------------------------------------*/ /** @defgroup DMA_Private_Functions DMA Private Functions - * @brief DMA private functions + * @brief DMA private functions * @{ */ /** @@ -465,7 +465,7 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); /** * @} - */ + */ /** * @} diff --git a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h index 05d2d3a..ca3af14 100644 --- a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h +++ b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h @@ -52,9 +52,9 @@ /** @defgroup DMAEx DMAEx * @{ - */ + */ -/* Exported types ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ /* Exported macro ------------------------------------------------------------*/ /** @defgroup DMAEx_Exported_Macros DMA Extended Exported Macros @@ -90,7 +90,7 @@ * @brief Returns the current DMA Channel half transfer complete flag. * @param __HANDLE__: DMA handle * @retval The specified half transfer complete flag index. - */ + */ #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ @@ -132,7 +132,7 @@ * @arg DMA_FLAG_TCx: Transfer complete flag * @arg DMA_FLAG_HTx: Half transfer complete flag * @arg DMA_FLAG_TEx: Transfer error flag - * Where x can be 1_7 or 1_5 (depending on DMA1 or DMA2) to select the DMA Channel flag. + * Where x can be 1_7 or 1_5 (depending on DMA1 or DMA2) to select the DMA Channel flag. * @retval The state of FLAG (SET or RESET). */ #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\ @@ -147,7 +147,7 @@ * @arg DMA_FLAG_TCx: Transfer complete flag * @arg DMA_FLAG_HTx: Half transfer complete flag * @arg DMA_FLAG_TEx: Transfer error flag - * Where x can be 1_7 or 1_5 (depending on DMA1 or DMA2) to select the DMA Channel flag. + * Where x can be 1_7 or 1_5 (depending on DMA1 or DMA2) to select the DMA Channel flag. * @retval None */ #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \ @@ -181,7 +181,7 @@ * @brief Returns the current DMA Channel half transfer complete flag. * @param __HANDLE__: DMA handle * @retval The specified half transfer complete flag index. - */ + */ #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ @@ -213,7 +213,7 @@ * @arg DMA_FLAG_TCx: Transfer complete flag * @arg DMA_FLAG_HTx: Half transfer complete flag * @arg DMA_FLAG_TEx: Transfer error flag - * Where x can be 1_7 to select the DMA Channel flag. + * Where x can be 1_7 to select the DMA Channel flag. * @retval The state of FLAG (SET or RESET). */ @@ -227,7 +227,7 @@ * @arg DMA_FLAG_TCx: Transfer complete flag * @arg DMA_FLAG_HTx: Half transfer complete flag * @arg DMA_FLAG_TEx: Transfer error flag - * Where x can be 1_7 to select the DMA Channel flag. + * Where x can be 1_7 to select the DMA Channel flag. * @retval None */ #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__)) @@ -237,7 +237,7 @@ */ #endif - + /** * @} */ diff --git a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h index 1135f81..5f46d66 100644 --- a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h +++ b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h @@ -32,7 +32,7 @@ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - ****************************************************************************** + ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ @@ -45,7 +45,7 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32f1xx_hal_def.h" - + /** @addtogroup STM32F1xx_HAL_Driver * @{ */ @@ -53,7 +53,7 @@ /** @addtogroup FLASH * @{ */ - + /** @addtogroup FLASH_Private_Constants * @{ */ @@ -68,7 +68,7 @@ #define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_HALFWORD) || \ ((VALUE) == FLASH_TYPEPROGRAM_WORD) || \ - ((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD)) + ((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD)) #if defined(FLASH_ACR_LATENCY) #define IS_FLASH_LATENCY(__LATENCY__) (((__LATENCY__) == FLASH_LATENCY_0) || \ @@ -80,20 +80,20 @@ #endif /* FLASH_ACR_LATENCY */ /** * @} - */ + */ -/* Exported types ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ /** @defgroup FLASH_Exported_Types FLASH Exported Types * @{ - */ + */ /** * @brief FLASH Procedure structure definition */ -typedef enum +typedef enum { - FLASH_PROC_NONE = 0, + FLASH_PROC_NONE = 0, FLASH_PROC_PAGEERASE = 1, FLASH_PROC_MASSERASE = 2, FLASH_PROC_PROGRAMHALFWORD = 3, @@ -101,13 +101,13 @@ typedef enum FLASH_PROC_PROGRAMDOUBLEWORD = 5 } FLASH_ProcedureTypeDef; -/** - * @brief FLASH handle Structure definition +/** + * @brief FLASH handle Structure definition */ typedef struct { __IO FLASH_ProcedureTypeDef ProcedureOnGoing; /*!< Internal variable to indicate which procedure is ongoing or not in IT context */ - + __IO uint32_t DataRemaining; /*!< Internal variable to save the remaining pages to erase or half-word to program in IT context */ __IO uint32_t Address; /*!< Internal variable to save address selected for program or erase */ @@ -116,7 +116,7 @@ typedef struct HAL_LockTypeDef Lock; /*!< FLASH locking object */ - __IO uint32_t ErrorCode; /*!< FLASH error code + __IO uint32_t ErrorCode; /*!< FLASH error code This parameter can be a value of @ref FLASH_Error_Codes */ } FLASH_ProcessTypeDef; @@ -127,7 +127,7 @@ typedef struct /* Exported constants --------------------------------------------------------*/ /** @defgroup FLASH_Exported_Constants FLASH Exported Constants * @{ - */ + */ /** @defgroup FLASH_Error_Codes FLASH Error Codes * @{ @@ -144,7 +144,7 @@ typedef struct /** @defgroup FLASH_Type_Program FLASH Type Program * @{ - */ + */ #define FLASH_TYPEPROGRAM_HALFWORD ((uint32_t)0x01) /*!<Program a half-word (16-bit) at a specified address.*/ #define FLASH_TYPEPROGRAM_WORD ((uint32_t)0x02) /*!<Program a word (32-bit) at a specified address.*/ #define FLASH_TYPEPROGRAM_DOUBLEWORD ((uint32_t)0x03) /*!<Program a double word (64-bit) at a specified address*/ @@ -178,15 +178,15 @@ typedef struct #endif /* FLASH_ACR_LATENCY */ /** * @} - */ - + */ + /* Exported macro ------------------------------------------------------------*/ /** @defgroup FLASH_Exported_Macros FLASH Exported Macros - * @brief macros to control FLASH features + * @brief macros to control FLASH features * @{ */ - + /** @defgroup FLASH_Half_Cycle FLASH Half Cycle * @brief macros to handle FLASH half cycle * @{ @@ -216,22 +216,22 @@ typedef struct /** @defgroup FLASH_EM_Latency FLASH Latency * @brief macros to handle FLASH Latency * @{ - */ - + */ + /** * @brief Set the FLASH Latency. - * @param __LATENCY__ FLASH Latency + * @param __LATENCY__ FLASH Latency * The value of this parameter depend on device used within the same series * @retval None - */ + */ #define __HAL_FLASH_SET_LATENCY(__LATENCY__) (FLASH->ACR = (FLASH->ACR&(~FLASH_ACR_LATENCY)) | (__LATENCY__)) /** * @brief Get the FLASH Latency. - * @retval FLASH Latency + * @retval FLASH Latency * The value of this parameter depend on device used within the same series - */ + */ #define __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)) /** @@ -242,11 +242,11 @@ typedef struct /** @defgroup FLASH_Prefetch FLASH Prefetch * @brief macros to handle FLASH Prefetch buffer * @{ - */ + */ /** * @brief Enable the FLASH prefetch buffer. * @retval None - */ + */ #define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() (FLASH->ACR |= FLASH_ACR_PRFTBE) /** @@ -258,19 +258,19 @@ typedef struct /** * @} */ - + /** * @} - */ + */ /* Include FLASH HAL Extended module */ -#include "stm32f1xx_hal_flash_ex.h" +#include "stm32f1xx_hal_flash_ex.h" /* Exported functions --------------------------------------------------------*/ /** @addtogroup FLASH_Exported_Functions * @{ */ - + /** @addtogroup FLASH_Exported_Functions_Group1 * @{ */ @@ -280,7 +280,7 @@ HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, u /* FLASH IRQ handler function */ void HAL_FLASH_IRQHandler(void); -/* Callbacks in non blocking modes */ +/* Callbacks in non blocking modes */ void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue); void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue); diff --git a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h index 933a95e..41375db 100644 --- a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h +++ b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h @@ -52,7 +52,7 @@ /** @addtogroup FLASHEx * @{ - */ + */ /** @addtogroup FLASHEx_Private_Constants * @{ @@ -64,7 +64,7 @@ /** * @} - */ + */ /** @addtogroup FLASHEx_Private_Macros * @{ @@ -74,11 +74,11 @@ #define IS_OPTIONBYTE(VALUE) (((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_DATA))) -#define IS_WRPSTATE(VALUE) (((VALUE) == OB_WRPSTATE_DISABLE) || ((VALUE) == OB_WRPSTATE_ENABLE)) +#define IS_WRPSTATE(VALUE) (((VALUE) == OB_WRPSTATE_DISABLE) || ((VALUE) == OB_WRPSTATE_ENABLE)) #define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) || ((LEVEL) == OB_RDP_LEVEL_1)) -#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == OB_DATA_ADDRESS_DATA0) || ((ADDRESS) == OB_DATA_ADDRESS_DATA1)) +#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == OB_DATA_ADDRESS_DATA0) || ((ADDRESS) == OB_DATA_ADDRESS_DATA1)) #define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW)) @@ -175,12 +175,12 @@ /** * @} - */ + */ -/* Exported types ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ /** @defgroup FLASHEx_Exported_Types FLASHEx Exported Types * @{ - */ + */ /** * @brief FLASH Erase structure definition @@ -189,17 +189,17 @@ typedef struct { uint32_t TypeErase; /*!< TypeErase: Mass erase or page erase. This parameter can be a value of @ref FLASHEx_Type_Erase */ - + uint32_t Banks; /*!< Select banks to erase when Mass erase is enabled. - This parameter must be a value of @ref FLASHEx_Banks */ - + This parameter must be a value of @ref FLASHEx_Banks */ + uint32_t PageAddress; /*!< PageAdress: Initial FLASH page address to erase when mass erase is disabled - This parameter must be a number between Min_Data = 0x08000000 and Max_Data = FLASH_BANKx_END + This parameter must be a number between Min_Data = 0x08000000 and Max_Data = FLASH_BANKx_END (x = 1 or 2 depending on devices)*/ - + uint32_t NbPages; /*!< NbPages: Number of pagess to be erased. This parameter must be a value between Min_Data = 1 and Max_Data = (max number of pages - value of initial page)*/ - + } FLASH_EraseInitTypeDef; /** @@ -217,26 +217,26 @@ typedef struct This parameter can be a value of @ref FLASHEx_OB_Write_Protection */ uint32_t Banks; /*!< Select banks for WRP activation/deactivation of all sectors. - This parameter must be a value of @ref FLASHEx_Banks */ - + This parameter must be a value of @ref FLASHEx_Banks */ + uint8_t RDPLevel; /*!< RDPLevel: Set the read protection level.. This parameter can be a value of @ref FLASHEx_OB_Read_Protection */ #if defined(FLASH_BANK2_END) - uint8_t USERConfig; /*!< USERConfig: Program the FLASH User Option Byte: + uint8_t USERConfig; /*!< USERConfig: Program the FLASH User Option Byte: IWDG / STOP / STDBY / BOOT1 - This parameter can be a combination of @ref FLASHEx_OB_IWatchdog, @ref FLASHEx_OB_nRST_STOP, + This parameter can be a combination of @ref FLASHEx_OB_IWatchdog, @ref FLASHEx_OB_nRST_STOP, @ref FLASHEx_OB_nRST_STDBY, @ref FLASHEx_OB_BOOT1 */ #else - uint8_t USERConfig; /*!< USERConfig: Program the FLASH User Option Byte: + uint8_t USERConfig; /*!< USERConfig: Program the FLASH User Option Byte: IWDG / STOP / STDBY - This parameter can be a combination of @ref FLASHEx_OB_IWatchdog, @ref FLASHEx_OB_nRST_STOP, + This parameter can be a combination of @ref FLASHEx_OB_IWatchdog, @ref FLASHEx_OB_nRST_STOP, @ref FLASHEx_OB_nRST_STDBY */ #endif /* FLASH_BANK2_END */ uint32_t DATAAddress; /*!< DATAAddress: Address of the option byte DATA to be programmed This parameter can be a value of @ref FLASHEx_OB_Data_Address */ - + uint8_t DATAData; /*!< DATAData: Data to be stored in the option byte DATA This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ } FLASH_OBProgramInitTypeDef; @@ -248,15 +248,15 @@ typedef struct /* Exported constants --------------------------------------------------------*/ /** @defgroup FLASHEx_Exported_Constants FLASHEx Exported Constants * @{ - */ + */ /** @defgroup FLASHEx_Constants FLASH Constants * @{ - */ + */ /** @defgroup FLASHEx_Page_Size Page Size * @{ - */ + */ #if (defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6) || defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB)) #define FLASH_PAGE_SIZE ((uint32_t)0x400) #endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */ @@ -265,7 +265,7 @@ typedef struct #if (defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)) #define FLASH_PAGE_SIZE ((uint32_t)0x800) #endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */ - /* STM32F101xG || STM32F103xG */ + /* STM32F101xG || STM32F103xG */ /* STM32F105xC || STM32F107xC */ /** @@ -274,7 +274,7 @@ typedef struct /** @defgroup FLASHEx_Type_Erase Type Erase * @{ - */ + */ #define FLASH_TYPEERASE_PAGES ((uint32_t)0x00) /*!<Pages erase only*/ #define FLASH_TYPEERASE_MASSERASE ((uint32_t)0x02) /*!<Flash mass erase activation*/ @@ -303,7 +303,7 @@ typedef struct /** @defgroup FLASHEx_OptionByte_Constants Option Byte Constants * @{ - */ + */ /** @defgroup FLASHEx_OB_Type Option Bytes Type * @{ @@ -319,7 +319,7 @@ typedef struct /** @defgroup FLASHEx_OB_WRP_State Option Byte WRP State * @{ - */ + */ #define OB_WRPSTATE_DISABLE ((uint32_t)0x00) /*!<Disable the write protection of the desired pages*/ #define OB_WRPSTATE_ENABLE ((uint32_t)0x01) /*!<Enable the write protection of the desired pagess*/ @@ -344,7 +344,7 @@ typedef struct #define OB_WRP_PAGES28TO31 ((uint32_t)0x00000080) /*!< Write protection of page 28 to 31 */ #endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */ /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */ - + /* STM32 Medium-density devices */ #if defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB) #define OB_WRP_PAGES32TO35 ((uint32_t)0x00000100) /*!< Write protection of page 32 to 35 */ @@ -413,11 +413,11 @@ typedef struct #define OB_WRP_PAGES62TO255 ((uint32_t)0x80000000) /*!< Write protection of page 62 TO 255 */ #define OB_WRP_PAGES62TO511 ((uint32_t)0x80000000) /*!< Write protection of page 62 TO 511 */ #endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */ - /* STM32F101xG || STM32F103xG */ + /* STM32F101xG || STM32F103xG */ /* STM32F105xC || STM32F107xC */ #define OB_WRP_ALLPAGES ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Pages */ - + /* Low Density */ #if defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6) #define OB_WRP_PAGES0TO31MASK ((uint32_t)0x000000FF) @@ -430,9 +430,9 @@ typedef struct #define OB_WRP_PAGES64TO95MASK ((uint32_t)0x00FF0000) #define OB_WRP_PAGES96TO127MASK ((uint32_t)0xFF000000) #endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB*/ - + /* High Density */ -#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE) +#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE) #define OB_WRP_PAGES0TO15MASK ((uint32_t)0x000000FF) #define OB_WRP_PAGES16TO31MASK ((uint32_t)0x0000FF00) #define OB_WRP_PAGES32TO47MASK ((uint32_t)0x00FF0000) @@ -440,13 +440,13 @@ typedef struct #endif /* STM32F100xE || STM32F101xE || STM32F103xE */ /* XL Density */ -#if defined(STM32F101xG) || defined(STM32F103xG) +#if defined(STM32F101xG) || defined(STM32F103xG) #define OB_WRP_PAGES0TO15MASK ((uint32_t)0x000000FF) #define OB_WRP_PAGES16TO31MASK ((uint32_t)0x0000FF00) #define OB_WRP_PAGES32TO47MASK ((uint32_t)0x00FF0000) #define OB_WRP_PAGES48TO511MASK ((uint32_t)0xFF000000) #endif /* STM32F101xG || STM32F103xG */ - + /* Connectivity line devices */ #if defined(STM32F105xC) || defined(STM32F107xC) #define OB_WRP_PAGES0TO15MASK ((uint32_t)0x000000FF) @@ -467,10 +467,10 @@ typedef struct /** * @} */ - + /** @defgroup FLASHEx_OB_IWatchdog Option Byte IWatchdog * @{ - */ + */ #define OB_IWDG_SW ((uint16_t)0x0001) /*!< Software IWDG selected */ #define OB_IWDG_HW ((uint16_t)0x0000) /*!< Hardware IWDG selected */ /** @@ -479,16 +479,16 @@ typedef struct /** @defgroup FLASHEx_OB_nRST_STOP Option Byte nRST STOP * @{ - */ + */ #define OB_STOP_NO_RST ((uint16_t)0x0002) /*!< No reset generated when entering in STOP */ #define OB_STOP_RST ((uint16_t)0x0000) /*!< Reset generated when entering in STOP */ /** * @} - */ + */ /** @defgroup FLASHEx_OB_nRST_STDBY Option Byte nRST STDBY * @{ - */ + */ #define OB_STDBY_NO_RST ((uint16_t)0x0004) /*!< No reset generated when entering in STANDBY */ #define OB_STDBY_RST ((uint16_t)0x0000) /*!< Reset generated when entering in STANDBY */ /** @@ -521,31 +521,31 @@ typedef struct /** @addtogroup FLASHEx_Constants * @{ - */ + */ /** @defgroup FLASH_Flag_definition Flag definition * @brief Flag definition * @{ */ #if defined(FLASH_BANK2_END) - #define FLASH_FLAG_BSY FLASH_FLAG_BSY_BANK1 /*!< FLASH Bank1 Busy flag */ + #define FLASH_FLAG_BSY FLASH_FLAG_BSY_BANK1 /*!< FLASH Bank1 Busy flag */ #define FLASH_FLAG_PGERR FLASH_FLAG_PGERR_BANK1 /*!< FLASH Bank1 Programming error flag */ #define FLASH_FLAG_WRPERR FLASH_FLAG_WRPERR_BANK1 /*!< FLASH Bank1 Write protected error flag */ #define FLASH_FLAG_EOP FLASH_FLAG_EOP_BANK1 /*!< FLASH Bank1 End of Operation flag */ - #define FLASH_FLAG_BSY_BANK1 FLASH_SR_BSY /*!< FLASH Bank1 Busy flag */ + #define FLASH_FLAG_BSY_BANK1 FLASH_SR_BSY /*!< FLASH Bank1 Busy flag */ #define FLASH_FLAG_PGERR_BANK1 FLASH_SR_PGERR /*!< FLASH Bank1 Programming error flag */ #define FLASH_FLAG_WRPERR_BANK1 FLASH_SR_WRPRTERR /*!< FLASH Bank1 Write protected error flag */ #define FLASH_FLAG_EOP_BANK1 FLASH_SR_EOP /*!< FLASH Bank1 End of Operation flag */ - - #define FLASH_FLAG_BSY_BANK2 (FLASH_SR2_BSY << 16) /*!< FLASH Bank2 Busy flag */ + + #define FLASH_FLAG_BSY_BANK2 (FLASH_SR2_BSY << 16) /*!< FLASH Bank2 Busy flag */ #define FLASH_FLAG_PGERR_BANK2 (FLASH_SR2_PGERR << 16) /*!< FLASH Bank2 Programming error flag */ #define FLASH_FLAG_WRPERR_BANK2 (FLASH_SR2_WRPRTERR << 16) /*!< FLASH Bank2 Write protected error flag */ #define FLASH_FLAG_EOP_BANK2 (FLASH_SR2_EOP << 16) /*!< FLASH Bank2 End of Operation flag */ -#else +#else - #define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */ + #define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */ #define FLASH_FLAG_PGERR FLASH_SR_PGERR /*!< FLASH Programming error flag */ #define FLASH_FLAG_WRPERR FLASH_SR_WRPRTERR /*!< FLASH Write protected error flag */ #define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of Operation flag */ @@ -555,7 +555,7 @@ typedef struct /** * @} */ - + /** @defgroup FLASH_Interrupt_definition Interrupt definition * @brief FLASH Interrupt definition * @{ @@ -578,12 +578,12 @@ typedef struct #endif /** * @} - */ + */ /** * @} */ - + /** * @} @@ -597,19 +597,19 @@ typedef struct /** @defgroup FLASH_Interrupt Interrupt * @brief macros to handle FLASH interrupts * @{ - */ + */ #if defined(FLASH_BANK2_END) /** * @brief Enable the specified FLASH interrupt. - * @param __INTERRUPT__ FLASH interrupt + * @param __INTERRUPT__ FLASH interrupt * This parameter can be any combination of the following values: * @arg @ref FLASH_IT_EOP_BANK1 End of FLASH Operation Interrupt on bank1 * @arg @ref FLASH_IT_ERR_BANK1 Error Interrupt on bank1 * @arg @ref FLASH_IT_EOP_BANK2 End of FLASH Operation Interrupt on bank2 * @arg @ref FLASH_IT_ERR_BANK2 Error Interrupt on bank2 * @retval none - */ + */ #define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) do { \ /* Enable Bank1 IT */ \ SET_BIT(FLASH->CR, ((__INTERRUPT__) & 0x0000FFFF)); \ @@ -619,14 +619,14 @@ typedef struct /** * @brief Disable the specified FLASH interrupt. - * @param __INTERRUPT__ FLASH interrupt + * @param __INTERRUPT__ FLASH interrupt * This parameter can be any combination of the following values: * @arg @ref FLASH_IT_EOP_BANK1 End of FLASH Operation Interrupt on bank1 * @arg @ref FLASH_IT_ERR_BANK1 Error Interrupt on bank1 * @arg @ref FLASH_IT_EOP_BANK2 End of FLASH Operation Interrupt on bank2 * @arg @ref FLASH_IT_ERR_BANK2 Error Interrupt on bank2 * @retval none - */ + */ #define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) do { \ /* Disable Bank1 IT */ \ CLEAR_BIT(FLASH->CR, ((__INTERRUPT__) & 0x0000FFFF)); \ @@ -635,7 +635,7 @@ typedef struct } while(0) /** - * @brief Get the specified FLASH flag status. + * @brief Get the specified FLASH flag status. * @param __FLAG__ specifies the FLASH flag to check. * This parameter can be one of the following values: * @arg @ref FLASH_FLAG_EOP_BANK1 FLASH End of Operation flag on bank1 @@ -692,30 +692,30 @@ typedef struct #else /** * @brief Enable the specified FLASH interrupt. - * @param __INTERRUPT__ FLASH interrupt + * @param __INTERRUPT__ FLASH interrupt * This parameter can be any combination of the following values: * @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt - * @arg @ref FLASH_IT_ERR Error Interrupt + * @arg @ref FLASH_IT_ERR Error Interrupt * @retval none - */ + */ #define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) (FLASH->CR |= (__INTERRUPT__)) /** * @brief Disable the specified FLASH interrupt. - * @param __INTERRUPT__ FLASH interrupt + * @param __INTERRUPT__ FLASH interrupt * This parameter can be any combination of the following values: * @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt - * @arg @ref FLASH_IT_ERR Error Interrupt + * @arg @ref FLASH_IT_ERR Error Interrupt * @retval none - */ + */ #define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) (FLASH->CR &= ~(__INTERRUPT__)) /** - * @brief Get the specified FLASH flag status. + * @brief Get the specified FLASH flag status. * @param __FLAG__ specifies the FLASH flag to check. * This parameter can be one of the following values: - * @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag - * @arg @ref FLASH_FLAG_WRPERR FLASH Write protected error flag + * @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag + * @arg @ref FLASH_FLAG_WRPERR FLASH Write protected error flag * @arg @ref FLASH_FLAG_PGERR FLASH Programming error flag * @arg @ref FLASH_FLAG_BSY FLASH Busy flag * @arg @ref FLASH_FLAG_OPTVERR Loaded OB and its complement do not match @@ -728,9 +728,9 @@ typedef struct * @brief Clear the specified FLASH flag. * @param __FLAG__ specifies the FLASH flags to clear. * This parameter can be any combination of the following values: - * @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag - * @arg @ref FLASH_FLAG_WRPERR FLASH Write protected error flag - * @arg @ref FLASH_FLAG_PGERR FLASH Programming error flag + * @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag + * @arg @ref FLASH_FLAG_WRPERR FLASH Write protected error flag + * @arg @ref FLASH_FLAG_PGERR FLASH Programming error flag * @arg @ref FLASH_FLAG_OPTVERR Loaded OB and its complement do not match * @retval none */ diff --git a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h index 22cd019..e585410 100644 --- a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h +++ b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h @@ -33,7 +33,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F1xx_HAL_GPIO_H @@ -52,16 +52,16 @@ /** @addtogroup GPIO * @{ - */ + */ /* Exported types ------------------------------------------------------------*/ /** @defgroup GPIO_Exported_Types GPIO Exported Types * @{ - */ + */ -/** - * @brief GPIO Init structure definition - */ +/** + * @brief GPIO Init structure definition + */ typedef struct { uint32_t Pin; /*!< Specifies the GPIO pins to be configured. @@ -69,19 +69,19 @@ typedef struct uint32_t Mode; /*!< Specifies the operating mode for the selected pins. This parameter can be a value of @ref GPIO_mode_define */ - + uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins. This parameter can be a value of @ref GPIO_pull_define */ - + uint32_t Speed; /*!< Specifies the speed for the selected pins. This parameter can be a value of @ref GPIO_speed_define */ }GPIO_InitTypeDef; - -/** - * @brief GPIO Bit SET and Bit RESET enumeration + +/** + * @brief GPIO Bit SET and Bit RESET enumeration */ typedef enum -{ +{ GPIO_PIN_RESET = 0, GPIO_PIN_SET }GPIO_PinState; @@ -95,11 +95,11 @@ typedef enum /** @defgroup GPIO_Exported_Constants GPIO Exported Constants * @{ - */ + */ /** @defgroup GPIO_pins_define GPIO pins define * @{ - */ + */ #define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */ #define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */ #define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */ @@ -121,19 +121,19 @@ typedef enum #define GPIO_PIN_MASK ((uint32_t)0x0000FFFF) /* PIN mask for assert test */ /** * @} - */ + */ + - /** @defgroup GPIO_mode_define GPIO mode define - * @brief GPIO Configuration Mode + * @brief GPIO Configuration Mode * Elements values convention: 0xX0yz00YZ * - X : GPIO mode or EXTI Mode - * - y : External IT or Event trigger detection + * - y : External IT or Event trigger detection * - z : IO configuration on External IT or Event * - Y : Output type (Push Pull or Open Drain) * - Z : IO Direction mode (Input, Output, Alternate or Analog) * @{ - */ + */ #define GPIO_MODE_INPUT ((uint32_t)0x00000000) /*!< Input Floating Mode */ #define GPIO_MODE_OUTPUT_PP ((uint32_t)0x00000001) /*!< Output Push Pull Mode */ #define GPIO_MODE_OUTPUT_OD ((uint32_t)0x00000011) /*!< Output Open Drain Mode */ @@ -142,11 +142,11 @@ typedef enum #define GPIO_MODE_AF_INPUT GPIO_MODE_INPUT /*!< Alternate Function Input Mode */ #define GPIO_MODE_ANALOG ((uint32_t)0x00000003) /*!< Analog Mode */ - + #define GPIO_MODE_IT_RISING ((uint32_t)0x10110000) /*!< External Interrupt Mode with Rising edge trigger detection */ #define GPIO_MODE_IT_FALLING ((uint32_t)0x10210000) /*!< External Interrupt Mode with Falling edge trigger detection */ #define GPIO_MODE_IT_RISING_FALLING ((uint32_t)0x10310000) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ - + #define GPIO_MODE_EVT_RISING ((uint32_t)0x10120000) /*!< External Event Mode with Rising edge trigger detection */ #define GPIO_MODE_EVT_FALLING ((uint32_t)0x10220000) /*!< External Event Mode with Falling edge trigger detection */ #define GPIO_MODE_EVT_RISING_FALLING ((uint32_t)0x10320000) /*!< External Event Mode with Rising/Falling edge trigger detection */ @@ -154,12 +154,12 @@ typedef enum /** * @} */ - - + + /** @defgroup GPIO_speed_define GPIO speed define * @brief GPIO Output Maximum frequency * @{ - */ + */ #define GPIO_SPEED_FREQ_LOW (GPIO_CRL_MODE0_1) /*!< Low speed */ #define GPIO_SPEED_FREQ_MEDIUM (GPIO_CRL_MODE0_0) /*!< Medium speed */ #define GPIO_SPEED_FREQ_HIGH (GPIO_CRL_MODE0) /*!< High speed */ @@ -172,7 +172,7 @@ typedef enum /** @defgroup GPIO_pull_define GPIO pull define * @brief GPIO Pull-Up or Pull-Down Activation * @{ - */ + */ #define GPIO_NOPULL ((uint32_t)0x00000000) /*!< No Pull-up or Pull-down activation */ #define GPIO_PULLUP ((uint32_t)0x00000001) /*!< Pull-up activation */ #define GPIO_PULLDOWN ((uint32_t)0x00000002) /*!< Pull-down activation */ @@ -180,7 +180,7 @@ typedef enum /** * @} */ - + /** * @} */ @@ -197,7 +197,7 @@ typedef enum #define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \ ((PULL) == GPIO_PULLDOWN)) - + #define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_FREQ_LOW) || \ ((SPEED) == GPIO_SPEED_FREQ_MEDIUM) || ((SPEED) == GPIO_SPEED_FREQ_HIGH)) @@ -230,8 +230,8 @@ typedef enum * This parameter can be GPIO_PIN_x where x can be(0..15) * @retval The new state of __EXTI_LINE__ (SET or RESET). */ -#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__)) - +#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__)) + /** * @brief Clears the EXTI's line pending flags. * @param __EXTI_LINE__: specifies the EXTI lines flags to clear. @@ -246,8 +246,8 @@ typedef enum * This parameter can be GPIO_PIN_x where x can be(0..15) * @retval The new state of __EXTI_LINE__ (SET or RESET). */ -#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__)) - +#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__)) + /** * @brief Clears the EXTI's line pending bits. * @param __EXTI_LINE__: specifies the EXTI lines to clear. @@ -273,7 +273,7 @@ typedef enum -/* Exported functions --------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ /* Initialization and de-initialization functions *******************************/ /** @addtogroup GPIO_Exported_Functions * @{ @@ -304,15 +304,15 @@ void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin); /** * @} - */ + */ /** * @} - */ + */ /** * @} - */ + */ #ifdef __cplusplus diff --git a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h index 9d9c3b3..71d8735 100644 --- a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h +++ b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h @@ -33,7 +33,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F1xx_HAL_GPIO_EX_H @@ -52,7 +52,7 @@ /** @defgroup GPIOEx GPIOEx * @{ - */ + */ /* Exported types ------------------------------------------------------------*/ @@ -60,17 +60,17 @@ /** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants * @{ - */ - + */ + /** @defgroup GPIOEx_EVENTOUT EVENTOUT Cortex Configuration * @brief This section propose definition to use the Cortex EVENTOUT signal. * @{ */ - -/** @defgroup GPIOEx_EVENTOUT_PIN EVENTOUT Pin + +/** @defgroup GPIOEx_EVENTOUT_PIN EVENTOUT Pin * @{ */ - + #define AFIO_EVENTOUT_PIN_0 AFIO_EVCR_PIN_PX0 /*!< EVENTOUT on pin 0 */ #define AFIO_EVENTOUT_PIN_1 AFIO_EVCR_PIN_PX1 /*!< EVENTOUT on pin 1 */ #define AFIO_EVENTOUT_PIN_2 AFIO_EVCR_PIN_PX2 /*!< EVENTOUT on pin 2 */ @@ -106,12 +106,12 @@ ((__PIN__) == AFIO_EVENTOUT_PIN_15)) /** * @} - */ - + */ + /** @defgroup GPIOEx_EVENTOUT_PORT EVENTOUT Port * @{ */ - + #define AFIO_EVENTOUT_PORT_A AFIO_EVCR_PORT_PA /*!< EVENTOUT on port A */ #define AFIO_EVENTOUT_PORT_B AFIO_EVCR_PORT_PB /*!< EVENTOUT on port B */ #define AFIO_EVENTOUT_PORT_C AFIO_EVCR_PORT_PC /*!< EVENTOUT on port C */ @@ -126,7 +126,7 @@ /** * @} */ - + /** * @} */ @@ -135,7 +135,7 @@ * @brief This section propose definition to remap the alternate function to some other port/pins. * @{ */ - + /** * @brief Enable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI. * @note ENABLE: Remap (NSS/PA15, SCK/PB3, MISO/PB4, MOSI/PB5) @@ -327,9 +327,9 @@ #endif /** - * @brief Enable the remapping of PD0 and PD1. When the HSE oscillator is not used - * (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and - * OSC_OUT. This is available only on 36, 48 and 64 pins packages (PD0 and PD1 are available + * @brief Enable the remapping of PD0 and PD1. When the HSE oscillator is not used + * (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and + * OSC_OUT. This is available only on 36, 48 and 64 pins packages (PD0 and PD1 are available * on 100-pin and 144-pin packages, no need for remapping). * @note ENABLE: PD0 remapped on OSC_IN, PD1 remapped on OSC_OUT. * @retval None @@ -337,9 +337,9 @@ #define __HAL_AFIO_REMAP_PD01_ENABLE() SET_BIT(AFIO->MAPR, AFIO_MAPR_PD01_REMAP) /** - * @brief Disable the remapping of PD0 and PD1. When the HSE oscillator is not used - * (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and - * OSC_OUT. This is available only on 36, 48 and 64 pins packages (PD0 and PD1 are available + * @brief Disable the remapping of PD0 and PD1. When the HSE oscillator is not used + * (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and + * OSC_OUT. This is available only on 36, 48 and 64 pins packages (PD0 and PD1 are available * on 100-pin and 144-pin packages, no need for remapping). * @note DISABLE: No remapping of PD0 and PD1 * @retval None @@ -817,12 +817,12 @@ /** * @} - */ - + */ + /** * @} */ - + /** @defgroup GPIOEx_Private_Macros GPIOEx Private Macros * @{ */ @@ -864,20 +864,20 @@ void HAL_GPIOEx_DisableEventout(void); /** * @} - */ + */ /** * @} - */ + */ /** * @} - */ + */ /** * @} - */ - + */ + #ifdef __cplusplus } #endif diff --git a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pcd.h b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pcd.h index 9489bd3..8dcc87f 100644 --- a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pcd.h +++ b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pcd.h @@ -33,7 +33,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F1xx_HAL_PCD_H @@ -57,9 +57,9 @@ /** @addtogroup PCD * @{ - */ + */ -/* Exported types ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ /** @defgroup PCD_Exported_Types PCD Exported Types * @{ */ @@ -90,12 +90,12 @@ typedef enum /** * @brief PCD endpoint buffer number */ -typedef enum +typedef enum { PCD_EP_NOBUF, PCD_EP_BUF0, PCD_EP_BUF1 -}PCD_EP_BUF_NUM; +}PCD_EP_BUF_NUM; #endif /* USB */ #if defined (USB_OTG_FS) @@ -110,14 +110,14 @@ typedef USB_CfgTypeDef PCD_InitTypeDef; typedef USB_EPTypeDef PCD_EPTypeDef; #endif /* USB */ -/** +/** * @brief PCD Handle Structure definition */ typedef struct { PCD_TypeDef *Instance; /*!< Register base address */ PCD_InitTypeDef Init; /*!< PCD required parameters */ - __IO uint8_t USB_Address; /*!< USB Address: not used by USB OTG FS */ + __IO uint8_t USB_Address; /*!< USB Address: not used by USB OTG FS */ PCD_EPTypeDef IN_ep[15]; /*!< IN endpoint parameters */ PCD_EPTypeDef OUT_ep[15]; /*!< OUT endpoint parameters */ HAL_LockTypeDef Lock; /*!< PCD peripheral status */ @@ -147,7 +147,7 @@ typedef struct /** * @} */ - + /** @defgroup PCD_PHY_Module PCD PHY Module * @{ */ @@ -359,11 +359,11 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); #define PCD_EP0MPS_64 DEP0CTL_MPS_64 #define PCD_EP0MPS_32 DEP0CTL_MPS_32 #define PCD_EP0MPS_16 DEP0CTL_MPS_16 -#define PCD_EP0MPS_08 DEP0CTL_MPS_8 +#define PCD_EP0MPS_08 DEP0CTL_MPS_8 /** * @} */ - + /** @defgroup PCD_ENDP PCD ENDP * @{ */ @@ -638,7 +638,7 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); { \ PCD_TX_DTOG((USBx), (bEpNum)); \ } - + /** * @brief Sets address in an endpoint register. * @param USBx: USB peripheral instance register address. @@ -655,7 +655,7 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); #define PCD_EP_TX_CNT(USBx, bEpNum) ((uint32_t *)(((USBx)->BTABLE+(bEpNum)*8+2)*2+ ((uint32_t)(USBx) + 0x400))) #define PCD_EP_RX_ADDRESS(USBx, bEpNum) ((uint32_t *)(((USBx)->BTABLE+(bEpNum)*8+4)*2+ ((uint32_t)(USBx) + 0x400))) #define PCD_EP_RX_CNT(USBx, bEpNum) ((uint32_t *)(((USBx)->BTABLE+(bEpNum)*8+6)*2+ ((uint32_t)(USBx) + 0x400))) - + #define PCD_SET_EP_RX_CNT(USBx, bEpNum,wCount) {\ uint32_t *pdwReg = PCD_EP_RX_CNT((USBx), (bEpNum)); \ PCD_SET_EP_CNT_RX_REG(pdwReg, (wCount));\ @@ -777,9 +777,9 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @brief Gets buffer 0/1 address of a double buffer endpoint. * @param USBx: USB peripheral instance register address. * @param bEpNum: Endpoint Number. - * @param bDir: endpoint dir EP_DBUF_OUT = OUT - * EP_DBUF_IN = IN - * @param wCount: Counter value + * @param bDir: endpoint dir EP_DBUF_OUT = OUT + * EP_DBUF_IN = IN + * @param wCount: Counter value * @retval None */ #define PCD_SET_EP_DBUF0_CNT(USBx, bEpNum, bDir, wCount) { \ @@ -825,7 +825,7 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); /** * @} */ - + /** * @} */ diff --git a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pcd_ex.h b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pcd_ex.h index 5e13c73..7e20d30 100644 --- a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pcd_ex.h +++ b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pcd_ex.h @@ -33,7 +33,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F1xx_HAL_PCD_EX_H @@ -75,7 +75,7 @@ HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size); #endif /* USB_OTG_FS */ #if defined (USB) -HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, +HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr, uint16_t ep_kind, uint32_t pmaadress); @@ -96,7 +96,7 @@ void HAL_PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state); */ /** * @} - */ + */ /** * @} diff --git a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h index b5f78ca..0c52f59 100644 --- a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h +++ b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h @@ -58,7 +58,7 @@ /** @defgroup PWR_Exported_Types PWR Exported Types * @{ - */ + */ /** * @brief PWR PVD configuration structure definition @@ -82,7 +82,7 @@ typedef struct /** @addtogroup PWR_Private_Constants * @{ - */ + */ #define PWR_EXTI_LINE_PVD ((uint32_t)0x00010000) /*!< External interrupt line 16 Connected to the PVD EXTI Line */ @@ -90,12 +90,12 @@ typedef struct * @} */ - + /* Exported constants --------------------------------------------------------*/ /** @defgroup PWR_Exported_Constants PWR Exported Constants * @{ - */ + */ /** @defgroup PWR_PVD_detection_level PWR PVD detection level * @{ @@ -107,8 +107,8 @@ typedef struct #define PWR_PVDLEVEL_4 PWR_CR_PLS_2V6 #define PWR_PVDLEVEL_5 PWR_CR_PLS_2V7 #define PWR_PVDLEVEL_6 PWR_CR_PLS_2V8 -#define PWR_PVDLEVEL_7 PWR_CR_PLS_2V9 - +#define PWR_PVDLEVEL_7 PWR_CR_PLS_2V9 + /** * @} */ @@ -222,7 +222,7 @@ typedef struct #define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD) /** - * @brief Disable interrupt on PVD Exti Line 16. + * @brief Disable interrupt on PVD Exti Line 16. * @retval None. */ #define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD) @@ -241,7 +241,7 @@ typedef struct /** - * @brief PVD EXTI line configuration: set falling edge trigger. + * @brief PVD EXTI line configuration: set falling edge trigger. * @retval None. */ #define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD) @@ -316,7 +316,7 @@ typedef struct #define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \ ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \ ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \ - ((MODE) == PWR_PVD_MODE_NORMAL)) + ((MODE) == PWR_PVD_MODE_NORMAL)) #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1)) @@ -338,8 +338,8 @@ typedef struct /** @addtogroup PWR_Exported_Functions PWR Exported Functions * @{ */ - -/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions + +/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions * @{ */ @@ -352,7 +352,7 @@ void HAL_PWR_DisableBkUpAccess(void); * @} */ -/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions +/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions * @{ */ diff --git a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h index b893074..0ef33fe 100644 --- a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h +++ b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h @@ -60,8 +60,8 @@ /** @defgroup RCC_Timeout RCC Timeout * @{ - */ - + */ + /* Disable Backup domain write protection state change timeout */ #define RCC_DBP_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */ /* LSE state change timeout */ @@ -75,7 +75,7 @@ /** * @} */ - + /** @defgroup RCC_Register_Offset Register offsets * @{ */ @@ -143,7 +143,7 @@ /** * @} */ - + /* CR register byte 2 (Bits[23:16]) base address */ #define RCC_CR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02)) @@ -214,7 +214,7 @@ ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \ ((__PCLK__) == RCC_HCLK_DIV16)) #define IS_RCC_MCO(__MCO__) ((__MCO__) == RCC_MCO) -#define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1)) +#define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1)) #define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) || \ ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \ ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \ @@ -230,8 +230,8 @@ * @{ */ -/** - * @brief RCC PLL configuration structure definition +/** + * @brief RCC PLL configuration structure definition */ typedef struct { @@ -239,14 +239,14 @@ typedef struct This parameter can be a value of @ref RCC_PLL_Config */ uint32_t PLLSource; /*!< PLLSource: PLL entry clock source. - This parameter must be a value of @ref RCC_PLL_Clock_Source */ + This parameter must be a value of @ref RCC_PLL_Clock_Source */ uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock This parameter must be a value of @ref RCCEx_PLL_Multiplication_Factor */ } RCC_PLLInitTypeDef; - + /** - * @brief RCC System, AHB and APB busses clock configuration structure definition + * @brief RCC System, AHB and APB busses clock configuration structure definition */ typedef struct { @@ -402,7 +402,7 @@ typedef struct /** * @} */ - + /** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source * @{ */ @@ -458,8 +458,8 @@ typedef struct #define RCC_IT_CSS ((uint8_t)RCC_CIR_CSSF) /*!< Clock Security System Interrupt flag */ /** * @} - */ - + */ + /** @defgroup RCC_Flag Flags * Elements values convention: XXXYYYYYb * - YYYYY : Flag position in the register @@ -503,8 +503,8 @@ typedef struct /** @defgroup RCC_Peripheral_Clock_Enable_Disable Peripheral Clock Enable Disable * @brief Enable or disable the AHB1 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. + * is disabled and the application software has to enable this clock before + * using it. * @{ */ #define __HAL_RCC_DMA1_CLK_ENABLE() do { \ @@ -572,9 +572,9 @@ typedef struct /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Clock Enable Disable * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ + * is disabled and the application software has to enable this clock before + * using it. + * @{ */ #define __HAL_RCC_TIM2_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -675,9 +675,9 @@ typedef struct /** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Clock Enable Disable * @brief Enable or disable the High Speed APB (APB2) peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before + * is disabled and the application software has to enable this clock before * using it. - * @{ + * @{ */ #define __HAL_RCC_AFIO_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -765,7 +765,7 @@ typedef struct /** * @} */ - + /** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status * @brief Get the enable or disable status of the APB2 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) @@ -799,9 +799,9 @@ typedef struct /** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset * @brief Force or release APB1 peripheral reset. - * @{ + * @{ */ -#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU) +#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU) #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) #define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST)) @@ -811,7 +811,7 @@ typedef struct #define __HAL_RCC_BKP_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_BKPRST)) #define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST)) -#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00) +#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00) #define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) #define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST)) @@ -827,9 +827,9 @@ typedef struct /** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset * @brief Force or release APB2 peripheral reset. - * @{ + * @{ */ -#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU) +#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU) #define __HAL_RCC_AFIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_AFIORST)) #define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPARST)) #define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPBRST)) @@ -841,7 +841,7 @@ typedef struct #define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST)) #define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST)) -#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00) +#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00) #define __HAL_RCC_AFIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_AFIORST)) #define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPARST)) #define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPBRST)) @@ -858,18 +858,18 @@ typedef struct */ /** @defgroup RCC_HSI_Configuration HSI Configuration - * @{ + * @{ */ /** @brief Macros to enable or disable the Internal High Speed oscillator (HSI). * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. * @note HSI can not be stopped if it is used as system clock source. In this case, - * you have to select another source of the system clock then stop the HSI. + * you have to select another source of the system clock then stop the HSI. * @note After enabling the HSI, the application software should wait on HSIRDY * flag to be set indicating that HSI clock is stable and can be used as - * system clock source. + * system clock source. * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator - * clock cycles. + * clock cycles. */ #define __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = ENABLE) #define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = DISABLE) @@ -880,7 +880,7 @@ typedef struct * @param _HSICALIBRATIONVALUE_ specifies the calibration trimming value. * (default is RCC_HSICALIBRATION_DEFAULT). * This parameter must be a number between 0 and 0x1F. - */ + */ #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) \ (MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << POSITION_VAL(RCC_CR_HSITRIM))) @@ -889,20 +889,20 @@ typedef struct */ /** @defgroup RCC_LSI_Configuration LSI Configuration - * @{ + * @{ */ /** @brief Macro to enable the Internal Low Speed oscillator (LSI). - * @note After enabling the LSI, the application software should wait on + * @note After enabling the LSI, the application software should wait on * LSIRDY flag to be set indicating that LSI clock is stable and can * be used to clock the IWDG and/or the RTC. */ #define __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = ENABLE) /** @brief Macro to disable the Internal Low Speed oscillator (LSI). - * @note LSI can not be disabled if the IWDG is running. + * @note LSI can not be disabled if the IWDG is running. * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator - * clock cycles. + * clock cycles. */ #define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = DISABLE) @@ -911,7 +911,7 @@ typedef struct */ /** @defgroup RCC_HSE_Configuration HSE Configuration - * @{ + * @{ */ /** @@ -964,16 +964,16 @@ typedef struct */ /** @defgroup RCC_LSE_Configuration LSE Configuration - * @{ + * @{ */ /** * @brief Macro to configure the External Low Speed oscillator (LSE). - * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro. + * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro. * @note As the LSE is in the Backup domain and write access is denied to - * this domain after reset, you have to enable write access using + * this domain after reset, you have to enable write access using * @ref HAL_PWR_EnableBkUpAccess() function before to configure the LSE - * (to be done once after reset). + * (to be done once after reset). * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application * software should wait on LSERDY flag to be set indicating that LSE clock * is stable and can be used to clock the RTC. @@ -1012,11 +1012,11 @@ typedef struct */ /** @defgroup RCC_PLL_Configuration PLL Configuration - * @{ + * @{ */ /** @brief Macro to enable the main PLL. - * @note After enabling the main PLL, the application software should wait on + * @note After enabling the main PLL, the application software should wait on * PLLRDY flag to be set indicating that PLL clock is stable and can * be used as system clock source. * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. @@ -1030,7 +1030,7 @@ typedef struct /** @brief Macro to configure the main PLL clock source and multiplication factors. * @note This function must be used only when the main PLL is disabled. - * + * * @param __RCC_PLLSOURCE__ specifies the PLL entry clock source. * This parameter can be one of the following values: * @arg @ref RCC_PLLSOURCE_HSI_DIV2 HSI oscillator clock selected as PLL clock entry @@ -1056,7 +1056,7 @@ typedef struct @endif * @arg @ref RCC_PLL_MUL8 PLLVCO = PLL clock entry x 8 * @arg @ref RCC_PLL_MUL9 PLLVCO = PLL clock entry x 9 - * + * */ #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__, __PLLMUL__)\ MODIFY_REG(RCC->CFGR, (RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL),((__RCC_PLLSOURCE__) | (__PLLMUL__) )) @@ -1074,7 +1074,7 @@ typedef struct */ /** @defgroup RCC_Get_Clock_source Get Clock source - * @{ + * @{ */ /** @@ -1102,8 +1102,8 @@ typedef struct */ /** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config - * @{ - */ + * @{ + */ #if defined(RCC_CFGR_MCO_3) /** @brief Macro to configure the MCO clock. @@ -1146,15 +1146,15 @@ typedef struct */ /** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration - * @{ + * @{ */ /** @brief Macro to configure the RTC clock (RTCCLK). * @note As the RTC clock configuration bits are in the Backup domain and write * access is denied to this domain after reset, you have to enable write * access using the Power Backup Access macro before to configure - * the RTC clock source (to be done once after reset). - * @note Once the RTC clock is configured it can't be changed unless the + * the RTC clock source (to be done once after reset). + * @note Once the RTC clock is configured it can't be changed unless the * Backup domain is reset using @ref __HAL_RCC_BACKUPRESET_FORCE() macro, or by * a Power On Reset (POR). * @@ -1167,12 +1167,12 @@ typedef struct * @note If the LSE or LSI is used as RTC clock source, the RTC continues to * work in STOP and STANDBY modes, and can be used as wakeup source. * However, when the HSE clock is used as RTC clock source, the RTC - * cannot be used in STOP and STANDBY modes. + * cannot be used in STOP and STANDBY modes. * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as * RTC clock source). */ #define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__)) - + /** @brief Macro to get the RTC clock source. * @retval The clock source can be one of the following values: * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock @@ -1384,7 +1384,7 @@ void HAL_RCC_CSSCallback(void); /** * @} */ - + #ifdef __cplusplus } #endif diff --git a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h index 4d38a3a..9871f4a 100644 --- a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h +++ b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h @@ -33,7 +33,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F1xx_HAL_RCC_EX_H @@ -52,7 +52,7 @@ /** @addtogroup RCCEx * @{ - */ + */ /** @addtogroup RCCEx_Private_Constants * @{ @@ -73,7 +73,7 @@ #endif /* STM32F105xC || STM32F107xC */ -#define CR_REG_INDEX ((uint8_t)1) +#define CR_REG_INDEX ((uint8_t)1) /** * @} @@ -213,15 +213,15 @@ * @} */ -/* Exported types ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ /** @defgroup RCCEx_Exported_Types RCCEx Exported Types * @{ */ #if defined(STM32F105xC) || defined(STM32F107xC) -/** - * @brief RCC PLL2 configuration structure definition +/** + * @brief RCC PLL2 configuration structure definition */ typedef struct { @@ -229,7 +229,7 @@ typedef struct This parameter can be a value of @ref RCCEx_PLL2_Config */ uint32_t PLL2MUL; /*!< PLL2MUL: Multiplication factor for PLL2 VCO input clock - This parameter must be a value of @ref RCCEx_PLL2_Multiplication_Factor*/ + This parameter must be a value of @ref RCCEx_PLL2_Multiplication_Factor*/ #if defined(STM32F105xC) || defined(STM32F107xC) uint32_t HSEPrediv2Value; /*!< The Prediv2 factor value. @@ -240,8 +240,8 @@ typedef struct #endif /* STM32F105xC || STM32F107xC */ -/** - * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition +/** + * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition */ typedef struct { @@ -255,37 +255,37 @@ typedef struct uint32_t HSEState; /*!< The new state of the HSE. This parameter can be a value of @ref RCC_HSE_Config */ - + uint32_t HSEPredivValue; /*!< The Prediv1 factor value (named PREDIV1 or PLLXTPRE in RM) This parameter can be a value of @ref RCCEx_Prediv1_Factor */ uint32_t LSEState; /*!< The new state of the LSE. This parameter can be a value of @ref RCC_LSE_Config */ - + uint32_t HSIState; /*!< The new state of the HSI. This parameter can be a value of @ref RCC_HSI_Config */ uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */ - + uint32_t LSIState; /*!< The new state of the LSI. This parameter can be a value of @ref RCC_LSI_Config */ - RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */ + RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */ #if defined(STM32F105xC) || defined(STM32F107xC) - RCC_PLL2InitTypeDef PLL2; /*!< PLL2 structure parameters */ + RCC_PLL2InitTypeDef PLL2; /*!< PLL2 structure parameters */ #endif /* STM32F105xC || STM32F107xC */ } RCC_OscInitTypeDef; #if defined(STM32F105xC) || defined(STM32F107xC) -/** - * @brief RCC PLLI2S configuration structure definition +/** + * @brief RCC PLLI2S configuration structure definition */ typedef struct { uint32_t PLLI2SMUL; /*!< PLLI2SMUL: Multiplication factor for PLLI2S VCO input clock - This parameter must be a value of @ref RCCEx_PLLI2S_Multiplication_Factor*/ + This parameter must be a value of @ref RCCEx_PLLI2S_Multiplication_Factor*/ #if defined(STM32F105xC) || defined(STM32F107xC) uint32_t HSEPrediv2Value; /*!< The Prediv2 factor value. @@ -295,8 +295,8 @@ typedef struct } RCC_PLLI2SInitTypeDef; #endif /* STM32F105xC || STM32F107xC */ -/** - * @brief RCC extended clocks structure definition +/** + * @brief RCC extended clocks structure definition */ typedef struct { @@ -306,7 +306,7 @@ typedef struct uint32_t RTCClockSelection; /*!< specifies the RTC clock source. This parameter can be a value of @ref RCC_RTC_Clock_Source */ - uint32_t AdcClockSelection; /*!< ADC clock source + uint32_t AdcClockSelection; /*!< ADC clock source This parameter can be a value of @ref RCCEx_ADC_Prescaler */ #if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\ @@ -316,9 +316,9 @@ typedef struct uint32_t I2s3ClockSelection; /*!< I2S3 clock source This parameter can be a value of @ref RCCEx_I2S3_Clock_Source */ - + #if defined(STM32F105xC) || defined(STM32F107xC) - RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters + RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters This parameter will be used only when PLLI2S is selected as Clock Source I2S2 or I2S3 */ #endif /* STM32F105xC || STM32F107xC */ @@ -327,7 +327,7 @@ typedef struct #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ || defined(STM32F105xC) || defined(STM32F107xC) - uint32_t UsbClockSelection; /*!< USB clock source + uint32_t UsbClockSelection; /*!< USB clock source This parameter can be a value of @ref RCCEx_USB_Prescaler */ #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ @@ -607,7 +607,7 @@ typedef struct #define RCC_IT_PLLI2SRDY ((uint8_t)RCC_CIR_PLL3RDYF) /** * @} - */ + */ /** @defgroup RCCEx_Flag RCCEx Flag * Elements values convention: 0XXYYYYYb @@ -621,7 +621,7 @@ typedef struct #define RCC_FLAG_PLLI2SRDY ((uint8_t)((CR_REG_INDEX << 5) | POSITION_VAL(RCC_CR_PLL3RDY))) /** * @} - */ + */ #endif /* STM32F105xC || STM32F107xC*/ /** @@ -636,8 +636,8 @@ typedef struct /** @defgroup RCCEx_Peripheral_Clock_Enable_Disable Peripheral Clock Enable Disable * @brief Enable or disable the AHB1 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. + * is disabled and the application software has to enable this clock before + * using it. * @{ */ @@ -739,7 +739,7 @@ typedef struct __HAL_RCC_ETHMACRX_CLK_DISABLE(); \ __HAL_RCC_ETHMAC_CLK_DISABLE(); \ } while(0) - + #endif /* STM32F107xC*/ /** @@ -789,9 +789,9 @@ typedef struct /** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Clock Enable Disable * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ + * is disabled and the application software has to enable this clock before + * using it. + * @{ */ #if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE)\ @@ -1174,9 +1174,9 @@ typedef struct /** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Clock Enable Disable * @brief Enable or disable the High Speed APB (APB2) peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before + * is disabled and the application software has to enable this clock before * using it. - * @{ + * @{ */ #if defined(STM32F101xG) || defined(STM32F103x6) || defined(STM32F103xB)\ @@ -1401,7 +1401,7 @@ typedef struct /** @defgroup RCCEx_Peripheral_Clock_Force_Release Peripheral Clock Force Release * @brief Force or release AHB peripheral reset. * @{ - */ + */ #define __HAL_RCC_AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFFU) #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_OTGFSRST)) #if defined(STM32F107xC) @@ -1421,7 +1421,7 @@ typedef struct /** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset * @brief Force or release APB1 peripheral reset. - * @{ + * @{ */ #if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE)\ @@ -1523,7 +1523,7 @@ typedef struct /** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset * @brief Force or release APB2 peripheral reset. - * @{ + * @{ */ #if defined(STM32F101xG) || defined(STM32F103x6) || defined(STM32F103xB)\ @@ -1593,8 +1593,8 @@ typedef struct */ /** @defgroup RCCEx_HSE_Configuration HSE Configuration - * @{ - */ + * @{ + */ #if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\ || defined(STM32F100xE) @@ -1642,11 +1642,11 @@ typedef struct #if defined(STM32F105xC) || defined(STM32F107xC) /** @defgroup RCCEx_PLLI2S_Configuration PLLI2S Configuration - * @{ - */ + * @{ + */ /** @brief Macros to enable the main PLLI2S. - * @note After enabling the main PLLI2S, the application software should wait on + * @note After enabling the main PLLI2S, the application software should wait on * PLLI2SRDY flag to be set indicating that PLLI2S clock is stable and can * be used as system clock source. * @note The main PLLI2S is disabled by hardware when entering STOP and STANDBY modes. @@ -1660,7 +1660,7 @@ typedef struct /** @brief macros to configure the main PLLI2S multiplication factor. * @note This function must be used only when the main PLLI2S is disabled. - * + * * @param __PLLI2SMUL__ specifies the multiplication factor for PLLI2S VCO output clock * This parameter can be one of the following values: * @arg @ref RCC_PLLI2S_MUL8 PLLI2SVCO = PLLI2S clock entry x 8 @@ -1672,7 +1672,7 @@ typedef struct * @arg @ref RCC_PLLI2S_MUL14 PLLI2SVCO = PLLI2S clock entry x 14 * @arg @ref RCC_PLLI2S_MUL16 PLLI2SVCO = PLLI2S clock entry x 16 * @arg @ref RCC_PLLI2S_MUL20 PLLI2SVCO = PLLI2S clock entry x 20 - * + * */ #define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SMUL__)\ MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PLL3MUL,(__PLLI2SMUL__)) @@ -1686,7 +1686,7 @@ typedef struct /** @defgroup RCCEx_Peripheral_Configuration Peripheral Configuration * @brief Macros to configure clock source of different peripherals. * @{ - */ + */ #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) @@ -1755,8 +1755,8 @@ typedef struct #if defined(STM32F105xC) || defined(STM32F107xC) /** @addtogroup RCCEx_HSE_Configuration - * @{ - */ + * @{ + */ /** * @brief Macro to configure the PLL2 & PLLI2S Predivision factor. @@ -1768,7 +1768,7 @@ typedef struct */ #define __HAL_RCC_HSE_PREDIV2_CONFIG(__HSE_PREDIV2_VALUE__) \ MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV2, (uint32_t)(__HSE_PREDIV2_VALUE__)) - + /** * @brief Macro to get prediv2 factor for PLL2 & PLL3. */ @@ -1779,11 +1779,11 @@ typedef struct */ /** @addtogroup RCCEx_PLLI2S_Configuration - * @{ - */ + * @{ + */ /** @brief Macros to enable the main PLL2. - * @note After enabling the main PLL2, the application software should wait on + * @note After enabling the main PLL2, the application software should wait on * PLL2RDY flag to be set indicating that PLL2 clock is stable and can * be used as system clock source. * @note The main PLL2 is disabled by hardware when entering STOP and STANDBY modes. @@ -1798,7 +1798,7 @@ typedef struct /** @brief macros to configure the main PLL2 multiplication factor. * @note This function must be used only when the main PLL2 is disabled. - * + * * @param __PLL2MUL__ specifies the multiplication factor for PLL2 VCO output clock * This parameter can be one of the following values: * @arg @ref RCC_PLL2_MUL8 PLL2VCO = PLL2 clock entry x 8 @@ -1810,7 +1810,7 @@ typedef struct * @arg @ref RCC_PLL2_MUL14 PLL2VCO = PLL2 clock entry x 14 * @arg @ref RCC_PLL2_MUL16 PLL2VCO = PLL2 clock entry x 16 * @arg @ref RCC_PLL2_MUL20 PLL2VCO = PLL2 clock entry x 20 - * + * */ #define __HAL_RCC_PLL2_CONFIG(__PLL2MUL__)\ MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PLL2MUL,(__PLL2MUL__)) @@ -1822,7 +1822,7 @@ typedef struct /** @defgroup RCCEx_I2S_Configuration I2S Configuration * @brief Macros to configure clock source of I2S peripherals. * @{ - */ + */ /** @brief Macro to configure the I2S2 clock. * @param __I2S2CLKSOURCE__ specifies the I2S2 clock source. @@ -1911,11 +1911,11 @@ HAL_StatusTypeDef HAL_RCCEx_DisablePLL2(void); /** * @} */ - + /** * @} */ - + #ifdef __cplusplus } #endif diff --git a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h index 70e27ef..7e1c530 100644 --- a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h +++ b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h @@ -890,7 +890,7 @@ typedef struct #define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) || \ ((MODE) == TIM_OCMODE_PWM2)) - + #define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) || \ ((MODE) == TIM_OCMODE_ACTIVE) || \ ((MODE) == TIM_OCMODE_INACTIVE) || \ @@ -918,10 +918,10 @@ typedef struct ((CHANNEL) == TIM_CHANNEL_3) || \ ((CHANNEL) == TIM_CHANNEL_4) || \ ((CHANNEL) == TIM_CHANNEL_ALL)) - + #define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ - ((CHANNEL) == TIM_CHANNEL_2)) - + ((CHANNEL) == TIM_CHANNEL_2)) + #define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ ((CHANNEL) == TIM_CHANNEL_2) || \ ((CHANNEL) == TIM_CHANNEL_3)) @@ -944,7 +944,7 @@ typedef struct #define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) || \ ((MODE) == TIM_ENCODERMODE_TI2) || \ - ((MODE) == TIM_ENCODERMODE_TI12)) + ((MODE) == TIM_ENCODERMODE_TI12)) #define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FF) == 0x00000000) && ((SOURCE) != 0x00000000)) @@ -970,9 +970,9 @@ typedef struct #define IS_TIM_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) || \ ((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) || \ ((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) || \ - ((PRESCALER) == TIM_CLOCKPRESCALER_DIV8)) + ((PRESCALER) == TIM_CLOCKPRESCALER_DIV8)) -#define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0xF) +#define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0xF) #define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_ETR) || \ ((SOURCE) == TIM_CLEARINPUTSOURCE_OCREFCLR) || \ @@ -1301,7 +1301,7 @@ void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelStat * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag * @arg TIM_FLAG_COM: Commutation interrupt flag * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag - * @arg TIM_FLAG_BREAK: Break interrupt flag + * @arg TIM_FLAG_BREAK: Break interrupt flag * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag @@ -1322,7 +1322,7 @@ void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelStat * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag * @arg TIM_FLAG_COM: Commutation interrupt flag * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag - * @arg TIM_FLAG_BREAK: Break interrupt flag + * @arg TIM_FLAG_BREAK: Break interrupt flag * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag @@ -1532,11 +1532,11 @@ mode. * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param __POLARITY__: Polarity for TIx source + * @param __POLARITY__: Polarity for TIx source * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge - * @note The polarity TIM_INPUTCHANNELPOLARITY_BOTHEDGE is not authorized for TIM Channel 4. + * @note The polarity TIM_INPUTCHANNELPOLARITY_BOTHEDGE is not authorized for TIM Channel 4. * @retval None */ #define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ diff --git a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h index e26cedc..b6410ac 100644 --- a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h +++ b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h @@ -33,7 +33,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F1xx_HAL_TIM_EX_H @@ -52,31 +52,31 @@ /** @addtogroup TIMEx * @{ - */ + */ -/* Exported types ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ /** @defgroup TIMEx_Exported_Types TIMEx Exported Types * @{ */ -/** - * @brief TIM Hall sensor Configuration Structure definition +/** + * @brief TIM Hall sensor Configuration Structure definition */ typedef struct { - + uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. This parameter can be a value of @ref TIM_Input_Capture_Polarity */ - + uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ - + uint32_t IC1Filter; /*!< Specifies the input capture filter. - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ - uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. - This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ } TIM_HallSensor_InitTypeDef; @@ -84,9 +84,9 @@ typedef struct defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F103xE) || defined (STM32F103xG) || \ defined (STM32F105xC) || defined (STM32F107xC) -/** - * @brief TIM Break and Dead time configuration Structure definition - */ +/** + * @brief TIM Break and Dead time configuration Structure definition + */ typedef struct { uint32_t OffStateRunMode; /*!< TIM off state in run mode @@ -94,34 +94,34 @@ typedef struct uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ uint32_t LockLevel; /*!< TIM Lock level - This parameter can be a value of @ref TIM_Lock_level */ - uint32_t DeadTime; /*!< TIM dead Time + This parameter can be a value of @ref TIM_Lock_level */ + uint32_t DeadTime; /*!< TIM dead Time This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */ - uint32_t BreakState; /*!< TIM Break State + uint32_t BreakState; /*!< TIM Break State This parameter can be a value of @ref TIM_Break_Input_enable_disable */ - uint32_t BreakPolarity; /*!< TIM Break input polarity + uint32_t BreakPolarity; /*!< TIM Break input polarity This parameter can be a value of @ref TIM_Break_Polarity */ - uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state - This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ + uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state + This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ } TIM_BreakDeadTimeConfigTypeDef; #endif /* defined(STM32F100xB) || defined(STM32F100xE) || */ /* defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || */ /* defined(STM32F105xC) || defined(STM32F107xC) */ -/** - * @brief TIM Master configuration Structure definition - */ +/** + * @brief TIM Master configuration Structure definition + */ typedef struct { - uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection - This parameter can be a value of @ref TIM_Master_Mode_Selection */ - uint32_t MasterSlaveMode; /*!< Master/slave mode selection + uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection + This parameter can be a value of @ref TIM_Master_Mode_Selection */ + uint32_t MasterSlaveMode; /*!< Master/slave mode selection This parameter can be a value of @ref TIM_Master_Slave_Mode */ }TIM_MasterConfigTypeDef; /** * @} - */ + */ /* Exported constants --------------------------------------------------------*/ #if defined (STM32F100xB) || defined (STM32F100xE) || \ @@ -130,7 +130,7 @@ typedef struct { /** @defgroup TIMEx_Exported_Constants TIMEx Exported Constants * @{ */ - + /** @defgroup TIMEx_Clock_Filter TIMEx Clock Filter * @{ */ @@ -281,7 +281,7 @@ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim); /** * @} - */ + */ /* End of exported functions -------------------------------------------------*/ /* Private functions----------------------------------------------------------*/ @@ -291,17 +291,17 @@ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim); void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma); /** * @} -*/ +*/ /* End of private functions --------------------------------------------------*/ /** * @} - */ + */ /** * @} */ - + #ifdef __cplusplus } #endif diff --git a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_usb.h b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_usb.h index d9d59f5..3579c3d 100644 --- a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_usb.h +++ b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_usb.h @@ -63,10 +63,10 @@ /** @defgroup USB_LL_Exported_Types USB Low Layer Exported Types * @{ */ -/** - * @brief USB Mode definition +/** + * @brief USB Mode definition */ -typedef enum +typedef enum { USB_DEVICE_MODE = 0, USB_HOST_MODE = 1, @@ -86,7 +86,7 @@ typedef enum { URB_STALL }USB_OTG_URBStateTypeDef; -/** +/** * @brief Host channel States definition */ typedef enum { @@ -96,36 +96,36 @@ typedef enum { HC_NAK, HC_NYET, HC_STALL, - HC_XACTERR, - HC_BBLERR, + HC_XACTERR, + HC_BBLERR, HC_DATATGLERR }USB_OTG_HCStateTypeDef; -/** - * @brief USB OTG Initialization Structure definition +/** + * @brief USB OTG Initialization Structure definition */ typedef struct { uint32_t dev_endpoints; /*!< Device Endpoints number. This parameter depends on the used USB core. This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ - + uint32_t Host_channels; /*!< Host Channels number. - This parameter Depends on the used USB core. + This parameter Depends on the used USB core. This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ - + uint32_t speed; /*!< USB Core speed. This parameter can be any value of @ref USB_Core_Speed_ */ - - uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. + + uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. This parameter can be any value of @ref USB_EP0_MPS_ */ - + uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */ - + uint32_t low_power_enable; /*!< Enable or disable the low power mode. */ - + uint32_t vbus_sensing_enable; /*!< Enable or disable the VBUS Sensing feature. */ - + uint32_t use_external_vbus; /*!< Enable or disable the use of the external VBUS. */ }USB_OTG_CfgTypeDef; @@ -133,34 +133,34 @@ typedef struct { uint8_t num; /*!< Endpoint number This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ - + uint8_t is_in; /*!< Endpoint direction This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ - + uint8_t is_stall; /*!< Endpoint stall condition This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ - + uint8_t type; /*!< Endpoint type This parameter can be any value of @ref USB_EP_Type_ */ - + uint8_t data_pid_start; /*!< Initial data PID This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ - + uint8_t even_odd_frame; /*!< IFrame parity This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ - + uint16_t tx_fifo_num; /*!< Transmission FIFO number This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ - + uint32_t maxpacket; /*!< Endpoint Max packet size This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */ - + uint8_t *xfer_buff; /*!< Pointer to transfer buffer */ - + uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address */ - + uint32_t xfer_len; /*!< Current transfer length */ - + uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */ }USB_OTG_EPTypeDef; @@ -168,81 +168,81 @@ typedef struct { uint8_t dev_addr ; /*!< USB device address. This parameter must be a number between Min_Data = 1 and Max_Data = 255 */ - + uint8_t ch_num; /*!< Host channel number. This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ - + uint8_t ep_num; /*!< Endpoint number. This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ - + uint8_t ep_is_in; /*!< Endpoint direction This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ - + uint8_t speed; /*!< USB Host speed. This parameter can be any value of @ref USB_Core_Speed_ */ - + uint8_t do_ping; /*!< Enable or disable the use of the PING protocol for HS mode. */ - + uint8_t process_ping; /*!< Execute the PING protocol for HS mode. */ - + uint8_t ep_type; /*!< Endpoint Type. This parameter can be any value of @ref USB_EP_Type_ */ - + uint16_t max_packet; /*!< Endpoint Max packet size. This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */ - + uint8_t data_pid; /*!< Initial data PID. This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ - + uint8_t *xfer_buff; /*!< Pointer to transfer buffer. */ - + uint32_t xfer_len; /*!< Current transfer length. */ - + uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer. */ - + uint8_t toggle_in; /*!< IN transfer current toggle flag. This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ - + uint8_t toggle_out; /*!< OUT transfer current toggle flag This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ - + uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address. */ - + uint32_t ErrCnt; /*!< Host channel error count.*/ - + USB_OTG_URBStateTypeDef urb_state; /*!< URB state. This parameter can be any value of @ref USB_OTG_URBStateTypeDef */ - + USB_OTG_HCStateTypeDef state; /*!< Host Channel state. This parameter can be any value of @ref USB_OTG_HCStateTypeDef */ }USB_OTG_HCTypeDef; #endif /* USB_OTG_FS */ #if defined (USB) -/** - * @brief USB Initialization Structure definition +/** + * @brief USB Initialization Structure definition */ typedef struct { uint32_t dev_endpoints; /*!< Device Endpoints number. - This parameter depends on the used USB core. + This parameter depends on the used USB core. This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ - + uint32_t speed; /*!< USB Core speed. This parameter can be any value of @ref USB_Core_Speed */ - - uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. + + uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. This parameter can be any value of @ref USB_EP0_MPS */ - + uint32_t phy_itface; /*!< Select the used PHY interface. This parameter can be any value of @ref USB_Core_PHY */ - + uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */ - + uint32_t low_power_enable; /*!< Enable or disable Low Power mode */ - + uint32_t lpm_enable; /*!< Enable or disable Battery charging. */ - + uint32_t battery_charging_enable; /*!< Enable or disable Battery charging. */ } USB_CfgTypeDef; @@ -250,39 +250,39 @@ typedef struct { uint8_t num; /*!< Endpoint number This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ - + uint8_t is_in; /*!< Endpoint direction This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ - + uint8_t is_stall; /*!< Endpoint stall condition This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ - + uint8_t type; /*!< Endpoint type This parameter can be any value of @ref USB_EP_Type */ - + uint16_t pmaadress; /*!< PMA Address This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ - + uint16_t pmaaddr0; /*!< PMA Address0 This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ - + uint16_t pmaaddr1; /*!< PMA Address1 This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ - + uint8_t doublebuffer; /*!< Double buffer enable This parameter can be 0 or 1 */ - - uint16_t tx_fifo_num; /*!< This parameter is not required by USB Device FS peripheral, it is used - only by USB OTG FS peripheral + + uint16_t tx_fifo_num; /*!< This parameter is not required by USB Device FS peripheral, it is used + only by USB OTG FS peripheral This parameter is added to ensure compatibility across USB peripherals */ - + uint32_t maxpacket; /*!< Endpoint Max packet size This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */ - + uint8_t *xfer_buff; /*!< Pointer to transfer buffer */ - + uint32_t xfer_len; /*!< Current transfer length */ - + uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */ } USB_EPTypeDef; @@ -447,7 +447,7 @@ typedef struct #define USBx_HC(i) ((USB_OTG_HostChannelTypeDef *)((uint32_t)USBx + USB_OTG_HOST_CHANNEL_BASE + (i)*USB_OTG_HOST_CHANNEL_SIZE)) #endif /* USB_OTG_FS */ -#if defined (USB) +#if defined (USB) /** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS * @{ */ @@ -457,7 +457,7 @@ typedef struct #define DEP0CTL_MPS_8 3 /** * @} - */ + */ /** @defgroup USB_LL_EP_Type USB Low Layer EP Type * @{ @@ -469,7 +469,7 @@ typedef struct #define EP_TYPE_MSK 3 /** * @} - */ + */ #define BTABLE_ADDRESS (0x000) #endif /* USB */ @@ -537,7 +537,7 @@ HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx); HAL_StatusTypeDef USB_DriveVbus (USB_OTG_GlobalTypeDef *USBx, uint8_t state); uint32_t USB_GetHostSpeed (USB_OTG_GlobalTypeDef *USBx); uint32_t USB_GetCurrentFrame (USB_OTG_GlobalTypeDef *USBx); -HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, +HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num, uint8_t epnum, uint8_t dev_address, @@ -595,7 +595,7 @@ void USB_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, ui /** * @} - */ + */ /** * @} diff --git a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c index 0e0af69..19a4699 100644 --- a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c +++ b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c @@ -13,9 +13,9 @@ ============================================================================== [..] The common HAL driver contains a set of generic and common APIs that can be - used by the PPP peripheral drivers and the user to start using the HAL. + used by the PPP peripheral drivers and the user to start using the HAL. [..] - The HAL contains two APIs' categories: + The HAL contains two APIs' categories: (+) Common HAL APIs (+) Services HAL APIs @@ -109,7 +109,7 @@ static __IO uint32_t uwTick; * @{ */ -/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions +/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions * @brief Initialization and de-initialization functions * @verbatim @@ -117,36 +117,36 @@ static __IO uint32_t uwTick; ##### Initialization and de-initialization functions ##### =============================================================================== [..] This section provides functions allowing to: - (+) Initializes the Flash interface, the NVIC allocation and initial clock - configuration. It initializes the source of time base also when timeout + (+) Initializes the Flash interface, the NVIC allocation and initial clock + configuration. It initializes the source of time base also when timeout is needed and the backup domain when enabled. (+) de-Initializes common part of the HAL. - (+) Configure The time base source to have 1ms time base with a dedicated - Tick interrupt priority. - (++) Systick timer is used by default as source of time base, but user - can eventually implement his proper time base source (a general purpose - timer for example or other time source), keeping in mind that Time base - duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and + (+) Configure The time base source to have 1ms time base with a dedicated + Tick interrupt priority. + (++) Systick timer is used by default as source of time base, but user + can eventually implement his proper time base source (a general purpose + timer for example or other time source), keeping in mind that Time base + duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and handled in milliseconds basis. - (++) Time base configuration function (HAL_InitTick ()) is called automatically - at the beginning of the program after reset by HAL_Init() or at any time - when clock is configured, by HAL_RCC_ClockConfig(). - (++) Source of time base is configured to generate interrupts at regular - time intervals. Care must be taken if HAL_Delay() is called from a - peripheral ISR process, the Tick interrupt line must have higher priority - (numerically lower) than the peripheral interrupt. Otherwise the caller - ISR process will be blocked. - (++) functions affecting time base configurations are declared as __Weak + (++) Time base configuration function (HAL_InitTick ()) is called automatically + at the beginning of the program after reset by HAL_Init() or at any time + when clock is configured, by HAL_RCC_ClockConfig(). + (++) Source of time base is configured to generate interrupts at regular + time intervals. Care must be taken if HAL_Delay() is called from a + peripheral ISR process, the Tick interrupt line must have higher priority + (numerically lower) than the peripheral interrupt. Otherwise the caller + ISR process will be blocked. + (++) functions affecting time base configurations are declared as __Weak to make override possible in case of other implementations in user file. - + @endverbatim * @{ */ /** - * @brief This function configures the Flash prefetch, + * @brief This function configures the Flash prefetch, * Configures time base source, NVIC and Low level hardware - * @note This function is called at the beginning of program after reset and before + * @note This function is called at the beginning of program after reset and before * the clock configuration * @note The time base configuration is based on MSI clock when exiting from Reset. * Once done, time base tick start incrementing. @@ -200,10 +200,10 @@ HAL_StatusTypeDef HAL_DeInit(void) __HAL_RCC_AHB_FORCE_RESET(); __HAL_RCC_AHB_RELEASE_RESET(); #endif - + /* De-Init the low level hardware */ HAL_MspDeInit(); - + /* Return function status */ return HAL_OK; } @@ -231,15 +231,15 @@ __weak void HAL_MspDeInit(void) } /** - * @brief This function configures the source of the time base. - * The time source is configured to have 1ms time base with a dedicated + * @brief This function configures the source of the time base. + * The time source is configured to have 1ms time base with a dedicated * Tick interrupt priority. * @note This function is called automatically at the beginning of program after - * reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig(). - * @note In the default implementation, SysTick timer is the source of time base. - * It is used to generate interrupts at regular time intervals. - * Care must be taken if HAL_Delay() is called from a peripheral ISR process, - * The the SysTick interrupt must have higher priority (numerically lower) + * reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig(). + * @note In the default implementation, SysTick timer is the source of time base. + * It is used to generate interrupts at regular time intervals. + * Care must be taken if HAL_Delay() is called from a peripheral ISR process, + * The the SysTick interrupt must have higher priority (numerically lower) * than the peripheral interrupt. Otherwise the caller ISR process will be blocked. * The function is declared as __Weak to be overwritten in case of other * implementation in user file. @@ -262,7 +262,7 @@ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) * @} */ -/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions +/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions * @brief HAL Control functions * @verbatim @@ -280,7 +280,7 @@ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) (+) Enable/Disable Debug module during Sleep mode (+) Enable/Disable Debug module during STOP mode (+) Enable/Disable Debug module during STANDBY mode - + @endverbatim * @{ */ @@ -290,7 +290,7 @@ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) * used as application time base. * @note In the default implementation, this variable is incremented each 1ms * in Systick ISR. - * @note This function is declared as __weak to be overwritten in case of other + * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ @@ -301,7 +301,7 @@ __weak void HAL_IncTick(void) /** * @brief Provides a tick value in millisecond. - * @note This function is declared as __weak to be overwritten in case of other + * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ @@ -311,7 +311,7 @@ __weak uint32_t HAL_GetTick(void) } /** - * @brief This function provides accurate delay (in milliseconds) based + * @brief This function provides accurate delay (in milliseconds) based * on variable incremented. * @note In the default implementation , SysTick timer is the source of time base. * It is used to generate interrupts at regular time intervals where uwTick @@ -334,7 +334,7 @@ __weak void HAL_Delay(__IO uint32_t Delay) * @brief Suspend Tick increment. * @note In the default implementation , SysTick timer is the source of time base. It is * used to generate interrupts at regular time intervals. Once HAL_SuspendTick() - * is called, the the SysTick interrupt will be disabled and so Tick increment + * is called, the the SysTick interrupt will be disabled and so Tick increment * is suspended. * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. @@ -350,7 +350,7 @@ __weak void HAL_SuspendTick(void) * @brief Resume Tick increment. * @note In the default implementation , SysTick timer is the source of time base. It is * used to generate interrupts at regular time intervals. Once HAL_ResumeTick() - * is called, the the SysTick interrupt will be enabled and so Tick increment + * is called, the the SysTick interrupt will be enabled and so Tick increment * is resumed. * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. @@ -377,7 +377,7 @@ uint32_t HAL_GetHalVersion(void) * STM32F101xC/D/E and STM32F103xC/D/E, * STM32F101xF/G and STM32F103xF/G * STM32F10xx4 and STM32F10xx6 - * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in + * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in * debug mode (not accessible by the user software in normal mode). * Refer to errata sheet of these devices for more details. * @retval Device revision identifier @@ -393,7 +393,7 @@ uint32_t HAL_GetREVID(void) * STM32F101xC/D/E and STM32F103xC/D/E, * STM32F101xF/G and STM32F103xF/G * STM32F10xx4 and STM32F10xx6 - * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in + * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in * debug mode (not accessible by the user software in normal mode). * Refer to errata sheet of these devices for more details. * @retval Device identifier @@ -418,7 +418,7 @@ void HAL_DBGMCU_EnableDBGSleepMode(void) * STM32F101xC/D/E and STM32F103xC/D/E, * STM32F101xF/G and STM32F103xF/G * STM32F10xx4 and STM32F10xx6 - * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in + * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in * debug mode (not accessible by the user software in normal mode). * Refer to errata sheet of these devices for more details. * @retval None @@ -434,18 +434,18 @@ void HAL_DBGMCU_DisableDBGSleepMode(void) * STM32F101xC/D/E and STM32F103xC/D/E, * STM32F101xF/G and STM32F103xF/G * STM32F10xx4 and STM32F10xx6 - * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in + * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in * debug mode (not accessible by the user software in normal mode). * Refer to errata sheet of these devices for more details. * Note: On all STM32F1 devices: - * If the system tick timer interrupt is enabled during the Stop mode + * If the system tick timer interrupt is enabled during the Stop mode * debug (DBG_STOP bit set in the DBGMCU_CR register ), it will wakeup * the system from Stop mode. - * Workaround: To debug the Stop mode, disable the system tick timer + * Workaround: To debug the Stop mode, disable the system tick timer * interrupt. * Refer to errata sheet of these devices for more details. * Note: On all STM32F1 devices: - * If the system tick timer interrupt is enabled during the Stop mode + * If the system tick timer interrupt is enabled during the Stop mode * debug (DBG_STOP bit set in the DBGMCU_CR register ), it will wakeup * the system from Stop mode. * Workaround: To debug the Stop mode, disable the system tick timer @@ -464,7 +464,7 @@ void HAL_DBGMCU_EnableDBGStopMode(void) * STM32F101xC/D/E and STM32F103xC/D/E, * STM32F101xF/G and STM32F103xF/G * STM32F10xx4 and STM32F10xx6 - * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in + * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in * debug mode (not accessible by the user software in normal mode). * Refer to errata sheet of these devices for more details. * @retval None @@ -480,7 +480,7 @@ void HAL_DBGMCU_DisableDBGStopMode(void) * STM32F101xC/D/E and STM32F103xC/D/E, * STM32F101xF/G and STM32F103xF/G * STM32F10xx4 and STM32F10xx6 - * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in + * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in * debug mode (not accessible by the user software in normal mode). * Refer to errata sheet of these devices for more details. * @retval None @@ -496,7 +496,7 @@ void HAL_DBGMCU_EnableDBGStandbyMode(void) * STM32F101xC/D/E and STM32F103xC/D/E, * STM32F101xF/G and STM32F103xF/G * STM32F10xx4 and STM32F10xx6 - * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in + * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in * debug mode (not accessible by the user software in normal mode). * Refer to errata sheet of these devices for more details. * @retval None diff --git a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c index 1c9d886..836503c 100644 --- a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c +++ b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c @@ -10,19 +10,19 @@ * functionalities of the CORTEX: * + Initialization and de-initialization functions * + Peripheral Control functions - * - * @verbatim + * + * @verbatim ============================================================================== ##### How to use this driver ##### ============================================================================== - [..] + [..] *** How to configure Interrupts using Cortex HAL driver *** =========================================================== - [..] + [..] This section provide functions allowing to configure the NVIC interrupts (IRQ). The Cortex-M3 exceptions are managed by CMSIS functions. - + (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() function according to the following table. @@ -36,35 +36,35 @@ -------------------------------------------------------------------------------------------------------------------------- NVIC_PRIORITYGROUP_1 | 0-1 | 0-7 | 1 bits for pre-emption priority | | | 3 bits for subpriority - -------------------------------------------------------------------------------------------------------------------------- + -------------------------------------------------------------------------------------------------------------------------- NVIC_PRIORITYGROUP_2 | 0-3 | 0-3 | 2 bits for pre-emption priority | | | 2 bits for subpriority - -------------------------------------------------------------------------------------------------------------------------- + -------------------------------------------------------------------------------------------------------------------------- NVIC_PRIORITYGROUP_3 | 0-7 | 0-1 | 3 bits for pre-emption priority | | | 1 bits for subpriority - -------------------------------------------------------------------------------------------------------------------------- + -------------------------------------------------------------------------------------------------------------------------- NVIC_PRIORITYGROUP_4 | 0-15 | 0 | 4 bits for pre-emption priority - | | | 0 bits for subpriority + | | | 0 bits for subpriority ========================================================================================================================== - (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority() + (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority() + + (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ() - (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ() - - -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ pre-emption is no more possible. + -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ pre-emption is no more possible. The pending IRQ priority will be managed only by the sub priority. - + -@- IRQ priority order (sorted by highest to lowest priority): (+@) Lowest pre-emption priority (+@) Lowest sub priority (+@) Lowest hardware priority (IRQ number) - - [..] + + [..] *** How to configure Systick using Cortex HAL driver *** ======================================================== [..] Setup SysTick Timer for 1 msec interrupts. - + (+) The HAL_SYSTICK_Config()function calls the SysTick_Config() function which is a CMSIS function that: (++) Configures the SysTick Reload register with value passed as function parameter. @@ -73,21 +73,21 @@ (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK). (++) Enables the SysTick Interrupt. (++) Starts the SysTick Counter. - + (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the function HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the HAL_SYSTICK_Config() function call. (+) You can change the SysTick IRQ priority by calling the - HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function + HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function. (+) To adjust the SysTick time base, use the following formula: - + Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s) (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function (++) Reload Value should not exceed 0xFFFFFF - + @endverbatim ****************************************************************************** * @attention @@ -146,15 +146,15 @@ /** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions + * @brief Initialization and Configuration functions * -@verbatim +@verbatim ============================================================================== ##### Initialization and de-initialization functions ##### ============================================================================== [..] This section provide the Cortex HAL driver functions allowing to configure Interrupts - Systick functionalities + Systick functionalities @endverbatim * @{ @@ -164,7 +164,7 @@ /** * @brief Sets the priority grouping field (pre-emption priority and subpriority) * using the required unlock sequence. - * @param PriorityGroup: The priority grouping bits length. + * @param PriorityGroup: The priority grouping bits length. * This parameter can be one of the following values: * @arg NVIC_PRIORITYGROUP_0: 0 bits for pre-emption priority * 4 bits for subpriority @@ -176,15 +176,15 @@ * 1 bits for subpriority * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority * 0 bits for subpriority - * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. - * The pending IRQ priority will be managed only by the subpriority. + * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. + * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); - + /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); } @@ -196,29 +196,29 @@ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) * @param PreemptPriority: The pre-emption priority for the IRQn channel. * This parameter can be a value between 0 and 15 - * A lower priority value indicates a higher priority + * A lower priority value indicates a higher priority * @param SubPriority: the subpriority level for the IRQ channel. * This parameter can be a value between 0 and 15 - * A lower priority value indicates a higher priority. + * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { uint32_t prioritygroup = 0x00; - + /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); - + prioritygroup = NVIC_GetPriorityGrouping(); - + NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); } /** * @brief Enables a device specific interrupt in the NVIC interrupt controller. * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig() - * function should be called before. + * function should be called before. * @param IRQn External interrupt number * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) @@ -237,7 +237,7 @@ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) * @brief Disables a device specific interrupt in the NVIC interrupt controller. * @param IRQn External interrupt number * This parameter can be an enumerator of IRQn_Type enumeration - * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) * @retval None */ void HAL_NVIC_DisableIRQ(IRQn_Type IRQn) @@ -276,17 +276,17 @@ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) */ /** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions - * @brief Cortex control functions + * @brief Cortex control functions * -@verbatim +@verbatim ============================================================================== ##### Peripheral Control functions ##### ============================================================================== [..] This subsection provides a set of functions allowing to control the CORTEX - (NVIC, SYSTICK, MPU) functionalities. - - + (NVIC, SYSTICK, MPU) functionalities. + + @endverbatim * @{ */ @@ -318,7 +318,7 @@ void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init) assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable)); assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable)); assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size)); - + MPU->RBAR = MPU_Init->BaseAddress; MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | @@ -381,26 +381,26 @@ void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPre * @brief Sets Pending bit of an external interrupt. * @param IRQn External interrupt number * This parameter can be an enumerator of IRQn_Type enumeration - * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) * @retval None */ void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ +{ /* Set interrupt pending */ NVIC_SetPendingIRQ(IRQn); } /** - * @brief Gets Pending Interrupt (reads the pending register in the NVIC + * @brief Gets Pending Interrupt (reads the pending register in the NVIC * and returns the pending bit for the specified interrupt). * @param IRQn External interrupt number * This parameter can be an enumerator of IRQn_Type enumeration - * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) * @retval status: - 0 Interrupt status is not pending. * - 1 Interrupt status is pending. */ uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ +{ /* Return 1 if pending else 0 */ return NVIC_GetPendingIRQ(IRQn); } @@ -409,11 +409,11 @@ uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn) * @brief Clears the pending bit of an external interrupt. * @param IRQn External interrupt number * This parameter can be an enumerator of IRQn_Type enumeration - * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) * @retval None */ void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ +{ /* Clear pending interrupt */ NVIC_ClearPendingIRQ(IRQn); } @@ -422,12 +422,12 @@ void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn) * @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit). * @param IRQn External interrupt number * This parameter can be an enumerator of IRQn_Type enumeration - * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) * @retval status: - 0 Interrupt status is not pending. * - 1 Interrupt status is pending. */ uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn) -{ +{ /* Return 1 if active else 0 */ return NVIC_GetActive(IRQn); } diff --git a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c index 4a48d5f..a249c81 100644 --- a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c +++ b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c @@ -5,56 +5,56 @@ * @version V1.0.4 * @date 29-April-2016 * @brief DMA HAL module driver. - * - * This file provides firmware functions to manage the following + * + * This file provides firmware functions to manage the following * functionalities of the Direct Memory Access (DMA) peripheral: * + Initialization and de-initialization functions * + IO operation functions * + Peripheral State and errors functions - @verbatim - ============================================================================== + @verbatim + ============================================================================== ##### How to use this driver ##### - ============================================================================== + ============================================================================== [..] (#) Enable and configure the peripheral to be connected to the DMA Channel - (except for internal SRAM / FLASH memories: no initialization is + (except for internal SRAM / FLASH memories: no initialization is necessary) please refer to Reference manual for connection between peripherals and DMA requests. - (#) For a given Channel, program the required configuration through the following parameters: - Transfer Direction, Source and Destination data formats, - Circular or Normal mode, Channel Priority level, Source and Destination Increment mode, + (#) For a given Channel, program the required configuration through the following parameters: + Transfer Direction, Source and Destination data formats, + Circular or Normal mode, Channel Priority level, Source and Destination Increment mode, using HAL_DMA_Init() function. - (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error + (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error detection. - + (#) Use HAL_DMA_Abort() function to abort the current transfer - + -@- In Memory-to-Memory transfer mode, Circular mode is not allowed. *** Polling mode IO operation *** - ================================= - [..] - (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source + ================================= + [..] + (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source address and destination address and the Length of data to be transferred - (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this + (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this case a fixed Timeout can be configured by User depending from his application. - *** Interrupt mode IO operation *** - =================================== + *** Interrupt mode IO operation *** + =================================== [..] (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority() - (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ() - (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of - Source address and destination address and the Length of data to be transferred. - In this case the DMA interrupt is configured + (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ() + (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of + Source address and destination address and the Length of data to be transferred. + In this case the DMA interrupt is configured (+) Use HAL_DMAy_Channelx_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine - (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can - add his own function by customization of function pointer XferCpltCallback and - XferErrorCallback (i.e a member of DMA handle structure). + (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can + add his own function by customization of function pointer XferCpltCallback and + XferErrorCallback (i.e a member of DMA handle structure). *** DMA HAL driver macros list *** - ============================================= + ============================================= [..] Below the list of most used macros in DMA HAL driver. @@ -64,10 +64,10 @@ (+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Channel pending flags. (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Channel interrupts. (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Channel interrupts. - (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel interrupt has occurred or not. + (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel interrupt has occurred or not. - [..] - (@) You can refer to the DMA HAL driver header file for more useful macros + [..] + (@) You can refer to the DMA HAL driver header file for more useful macros @endverbatim ****************************************************************************** @@ -98,7 +98,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Includes ------------------------------------------------------------------*/ #include "stm32f1xx_hal.h" @@ -142,41 +142,41 @@ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t */ /** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and de-initialization functions + * @brief Initialization and de-initialization functions * -@verbatim +@verbatim =============================================================================== ##### Initialization and de-initialization functions ##### - =============================================================================== + =============================================================================== [..] This section provides functions allowing to initialize the DMA Channel source - and destination addresses, incrementation and data sizes, transfer direction, + and destination addresses, incrementation and data sizes, transfer direction, circular/normal mode selection, memory-to-memory mode selection and Channel priority value. [..] The HAL_DMA_Init() function follows the DMA configuration procedures as described in - reference manual. + reference manual. @endverbatim * @{ */ - + /** * @brief Initializes the DMA according to the specified * parameters in the DMA_InitTypeDef and create the associated handle. * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. + * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) -{ +{ uint32_t tmp = 0; - + /* Check the DMA handle allocation */ if(hdma == NULL) { return HAL_ERROR; } - + /* Check the parameters */ assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); assert_param(IS_DMA_DIRECTION(hdma->Init.Direction)); @@ -186,24 +186,24 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment)); assert_param(IS_DMA_MODE(hdma->Init.Mode)); assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); - + if(hdma->State == HAL_DMA_STATE_RESET) - { + { /* Allocate lock resource and initialize it */ hdma->Lock = HAL_UNLOCKED; } - + /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; /* Get the CR register value */ tmp = hdma->Instance->CCR; - + /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR bits */ tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \ DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \ DMA_CCR_DIR)); - + /* Prepare the DMA Channel configuration */ tmp |= hdma->Init.Direction | hdma->Init.PeriphInc | hdma->Init.MemInc | @@ -211,21 +211,21 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) hdma->Init.Mode | hdma->Init.Priority; /* Write to DMA Channel CR register */ - hdma->Instance->CCR = tmp; - + hdma->Instance->CCR = tmp; + /* Initialise the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; /* Initialize the DMA state*/ hdma->State = HAL_DMA_STATE_READY; - + return HAL_OK; } /** - * @brief DeInitializes the DMA peripheral + * @brief DeInitializes the DMA peripheral * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. + * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) @@ -235,7 +235,7 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) { return HAL_ERROR; } - + /* Check the parameters */ assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); @@ -247,16 +247,16 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) /* Disable the selected DMA Channelx */ __HAL_DMA_DISABLE(hdma); - + /* Reset DMA Channel control register */ hdma->Instance->CCR = 0; - + /* Reset DMA Channel Number of Data to Transfer register */ hdma->Instance->CNDTR = 0; - + /* Reset DMA Channel peripheral address register */ hdma->Instance->CPAR = 0; - + /* Reset DMA Channel memory address register */ hdma->Instance->CMAR = 0; @@ -264,7 +264,7 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); - + /* Initialize the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; @@ -281,20 +281,20 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) * @} */ -/** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions - * @brief I/O operation functions +/** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions + * @brief I/O operation functions * -@verbatim +@verbatim =============================================================================== ##### IO operation functions ##### - =============================================================================== + =============================================================================== [..] This section provides functions allowing to: (+) Configure the source, destination address and data length and Start DMA transfer - (+) Configure the source, destination address and data length and + (+) Configure the source, destination address and data length and Start DMA transfer with interrupt (+) Abort DMA transfer (+) Poll for transfer complete - (+) Handle DMA interrupt request + (+) Handle DMA interrupt request @endverbatim * @{ @@ -303,7 +303,7 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) /** * @brief Starts the DMA Transfer. * @param hdma : pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. + * the configuration information for the specified DMA Channel. * @param SrcAddress: The source memory Buffer address * @param DstAddress: The destination memory Buffer address * @param DataLength: The length of data to be transferred from source to destination @@ -319,23 +319,23 @@ HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, ui /* Check the parameters */ assert_param(IS_DMA_BUFFER_SIZE(DataLength)); - + /* Disable the peripheral */ __HAL_DMA_DISABLE(hdma); - + /* Configure the source, destination address and the data length */ DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); /* Enable the Peripheral */ __HAL_DMA_ENABLE(hdma); - return HAL_OK; + return HAL_OK; } /** * @brief Start the DMA Transfer with interrupt enabled. * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. + * the configuration information for the specified DMA Channel. * @param SrcAddress: The source memory Buffer address * @param DstAddress: The destination memory Buffer address * @param DataLength: The length of data to be transferred from source to destination @@ -351,50 +351,50 @@ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, /* Check the parameters */ assert_param(IS_DMA_BUFFER_SIZE(DataLength)); - + /* Disable the peripheral */ __HAL_DMA_DISABLE(hdma); - + /* Configure the source, destination address and the data length */ DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); - + /* Enable the transfer complete interrupt */ __HAL_DMA_ENABLE_IT(hdma, DMA_IT_TC); /* Enable the Half transfer complete interrupt */ - __HAL_DMA_ENABLE_IT(hdma, DMA_IT_HT); + __HAL_DMA_ENABLE_IT(hdma, DMA_IT_HT); /* Enable the transfer Error interrupt */ __HAL_DMA_ENABLE_IT(hdma, DMA_IT_TE); - + /* Enable the Peripheral */ __HAL_DMA_ENABLE(hdma); - + return HAL_OK; -} +} /** * @brief Aborts the DMA Transfer. * @param hdma : pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. - * - * @note After disabling a DMA Channel, a check for wait until the DMA Channel is - * effectively disabled is added. If a Channel is disabled + * + * @note After disabling a DMA Channel, a check for wait until the DMA Channel is + * effectively disabled is added. If a Channel is disabled * while a data transfer is ongoing, the current data will be transferred * and the Channel will be effectively disabled only after the transfer of - * this single data is finished. + * this single data is finished. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) { uint32_t tickstart = 0x00; - + /* Disable the channel */ __HAL_DMA_DISABLE(hdma); /* Get tick */ tickstart = HAL_GetTick(); - + /* Check if the DMA Channel is effectively disabled */ while((hdma->Instance->CCR & DMA_CCR_EN) != 0) { @@ -415,10 +415,10 @@ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) } /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(hdma); - + return HAL_OK; } @@ -426,7 +426,7 @@ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) * @brief Polling for transfer complete. * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. - * @param CompleteLevel: Specifies the DMA level complete. + * @param CompleteLevel: Specifies the DMA level complete. * @param Timeout: Timeout duration. * @retval HAL status */ @@ -434,7 +434,7 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp { uint32_t temp; uint32_t tickstart = 0x00; - + /* Get the level transfer complete flag */ if(CompleteLevel == HAL_DMA_FULL_TRANSFER) { @@ -453,19 +453,19 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp while(__HAL_DMA_GET_FLAG(hdma, temp) == RESET) { if((__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)) != RESET)) - { + { /* Clear the transfer error flags */ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); - + /* Update error code */ SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TE); /* Change the DMA state */ hdma->State= HAL_DMA_STATE_ERROR; - + /* Process Unlocked */ __HAL_UNLOCK(hdma); - + return HAL_ERROR; } /* Check for the Timeout */ @@ -475,13 +475,13 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp { /* Update error code */ SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TIMEOUT); - + /* Change the DMA state */ hdma->State = HAL_DMA_STATE_TIMEOUT; /* Process Unlocked */ __HAL_UNLOCK(hdma); - + return HAL_TIMEOUT; } } @@ -492,21 +492,21 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp /* Clear the transfer complete flag */ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); - /* The selected Channelx EN bit is cleared (DMA is disabled and + /* The selected Channelx EN bit is cleared (DMA is disabled and all transfers are complete) */ hdma->State = HAL_DMA_STATE_READY; } else - { + { /* Clear the half transfer complete flag */ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); - - /* The selected Channelx EN bit is cleared (DMA is disabled and + + /* The selected Channelx EN bit is cleared (DMA is disabled and all transfers of half buffer are complete) */ hdma->State = HAL_DMA_STATE_READY_HALF; } - + /* Process unlocked */ __HAL_UNLOCK(hdma); @@ -516,7 +516,7 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp /** * @brief Handles DMA interrupt request. * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. + * the configuration information for the specified DMA Channel. * @retval None */ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) @@ -528,19 +528,19 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) { /* Disable the transfer error interrupt */ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE); - + /* Clear the transfer error flag */ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); - + /* Update error code */ SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TE); - + /* Change the DMA state */ hdma->State = HAL_DMA_STATE_ERROR; - + /* Process Unlocked */ - __HAL_UNLOCK(hdma); - + __HAL_UNLOCK(hdma); + if (hdma->XferErrorCallback != NULL) { /* Transfer error callback */ @@ -553,7 +553,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)) != RESET) { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != RESET) - { + { /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0) { @@ -573,7 +573,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) } } } - + /* Transfer Complete Interrupt management ***********************************/ if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)) != RESET) { @@ -586,18 +586,18 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) } /* Clear the transfer complete flag */ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); - + /* Update error code */ SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_NONE); /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(hdma); - + if(hdma->XferCpltCallback != NULL) - { + { /* Transfer complete callback */ hdma->XferCpltCallback(hdma); } @@ -610,9 +610,9 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) */ /** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions - * @brief Peripheral State functions + * @brief Peripheral State functions * -@verbatim +@verbatim =============================================================================== ##### State and Errors functions ##### =============================================================================== @@ -628,7 +628,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) /** * @brief Returns the DMA state. * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. + * the configuration information for the specified DMA Channel. * @retval HAL state */ HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma) @@ -662,7 +662,7 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma) /** * @brief Sets the DMA Transfer parameter. * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. + * the configuration information for the specified DMA Channel. * @param SrcAddress: The source memory Buffer address * @param DstAddress: The destination memory Buffer address * @param DataLength: The length of data to be transferred from source to destination @@ -672,13 +672,13 @@ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t { /* Configure DMA Channel data length */ hdma->Instance->CNDTR = DataLength; - + /* Peripheral to Memory */ if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) { /* Configure DMA Channel destination address */ hdma->Instance->CPAR = DstAddress; - + /* Configure DMA Channel source address */ hdma->Instance->CMAR = SrcAddress; } @@ -687,7 +687,7 @@ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t { /* Configure DMA Channel source address */ hdma->Instance->CPAR = SrcAddress; - + /* Configure DMA Channel destination address */ hdma->Instance->CMAR = DstAddress; } diff --git a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c index b5d6c1a..b59e08c 100644 --- a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c +++ b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c @@ -5,22 +5,22 @@ * @version V1.0.4 * @date 29-April-2016 * @brief FLASH HAL module driver. - * This file provides firmware functions to manage the following + * This file provides firmware functions to manage the following * functionalities of the internal FLASH memory: * + Program operations functions - * + Memory Control functions + * + Memory Control functions * + Peripheral State functions - * + * @verbatim ============================================================================== ##### FLASH peripheral features ##### ============================================================================== - [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses - to the Flash memory. It implements the erase and program Flash memory operations + [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses + to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms. [..] The Flash memory interface accelerates code execution with a system of instruction - prefetch. + prefetch. [..] The FLASH main features are: (+) Flash memory read operations @@ -32,16 +32,16 @@ ##### How to use this driver ##### ============================================================================== - [..] - This driver provides functions and macros to configure and program the FLASH + [..] + This driver provides functions and macros to configure and program the FLASH memory of all STM32F1xx devices. - + (#) FLASH Memory I/O Programming functions: this group includes all needed functions to erase and program the main memory: (++) Lock and Unlock the FLASH interface (++) Erase function: Erase page, erase all pages (++) Program functions: half word, word and doubleword - + (#) FLASH Option Bytes Programming functions: this group includes all needed functions to manage the Option Bytes: (++) Lock and Unlock the Option Bytes @@ -53,22 +53,22 @@ (++) Program the data Option Bytes (++) Get the Write protection. (++) Get the user option bytes. - - (#) Interrupts and flags management functions : this group + + (#) Interrupts and flags management functions : this group includes all needed functions to: (++) Handle FLASH interrupts (++) Wait for last FLASH operation according to its status - (++) Get error flag status + (++) Get error flag status [..] In addition to these function, this driver includes a set of macros allowing to handle the following operations: - + (+) Set/Get the latency (+) Enable/Disable the prefetch buffer (+) Enable/Disable the half cycle access (+) Enable/Disable the FLASH interrupts (+) Monitor the FLASH flags status - + @endverbatim ****************************************************************************** * @attention @@ -97,7 +97,7 @@ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - ****************************************************************************** + ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -127,7 +127,7 @@ /** @defgroup FLASH_Private_Macros FLASH Private Macros * @{ */ - + /** * @} */ @@ -156,11 +156,11 @@ static void FLASH_SetErrorCode(void); /** @defgroup FLASH_Exported_Functions FLASH Exported Functions * @{ */ - -/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions - * @brief Programming operation functions + +/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions + * @brief Programming operation functions * -@verbatim +@verbatim @endverbatim * @{ */ @@ -170,17 +170,17 @@ static void FLASH_SetErrorCode(void); * @note The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface * The function HAL_FLASH_Lock() should be called after to lock the FLASH interface * - * @note If an erase and a program operations are requested simultaneously, + * @note If an erase and a program operations are requested simultaneously, * the erase operation is performed before the program one. - * - * @note FLASH should be previously erased before new programmation (only exception to this + * + * @note FLASH should be previously erased before new programmation (only exception to this * is when 0x0000 is programmed) * * @param TypeProgram: Indicate the way to program at a specified address. * This parameter can be a value of @ref FLASH_Type_Program * @param Address: Specifies the address to be programmed. * @param Data: Specifies the data to be programmed - * + * * @retval HAL_StatusTypeDef HAL Status */ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data) @@ -188,7 +188,7 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint HAL_StatusTypeDef status = HAL_ERROR; uint8_t index = 0; uint8_t nbiterations = 0; - + /* Process Locked */ __HAL_LOCK(&pFlash); @@ -210,7 +210,7 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint status = FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE); } #endif /* FLASH_BANK2_END */ - + if(status == HAL_OK) { if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD) @@ -239,7 +239,7 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint #endif /* FLASH_BANK2_END */ /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - + /* If the program operation is completed, disable the PG Bit */ CLEAR_BIT(FLASH->CR, FLASH_CR_PG); #if defined(FLASH_BANK2_END) @@ -248,7 +248,7 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint { /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE); - + /* If the program operation is completed, disable the PG Bit */ CLEAR_BIT(FLASH->CR2, FLASH_CR2_PG); } @@ -272,20 +272,20 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint * @note The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface * The function HAL_FLASH_Lock() should be called after to lock the FLASH interface * - * @note If an erase and a program operations are requested simultaneously, + * @note If an erase and a program operations are requested simultaneously, * the erase operation is performed before the program one. * * @param TypeProgram: Indicate the way to program at a specified address. * This parameter can be a value of @ref FLASH_Type_Program * @param Address: Specifies the address to be programmed. * @param Data: Specifies the data to be programmed - * + * * @retval HAL_StatusTypeDef HAL Status */ HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data) { HAL_StatusTypeDef status = HAL_OK; - + /* Process Locked */ __HAL_LOCK(&pFlash); @@ -299,7 +299,7 @@ HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, u { return HAL_ERROR; } - + if(Address <= FLASH_BANK1_END) { /* Enable End of FLASH Operation and Error source interrupts */ @@ -314,7 +314,7 @@ HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, u /* Enable End of FLASH Operation and Error source interrupts */ __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR); #endif /* FLASH_BANK2_END */ - + pFlash.Address = Address; pFlash.Data = Data; @@ -350,7 +350,7 @@ HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, u void HAL_FLASH_IRQHandler(void) { uint32_t addresstmp = 0; - + /* Check FLASH operation error flags */ #if defined(FLASH_BANK2_END) if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR_BANK1) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR_BANK1) || \ @@ -363,10 +363,10 @@ void HAL_FLASH_IRQHandler(void) addresstmp = pFlash.Address; /* Reset address */ pFlash.Address = 0xFFFFFFFF; - + /*Save the Error code*/ FLASH_SetErrorCode(); - + /* FLASH error interrupt user callback */ HAL_FLASH_OperationErrorCallback(addresstmp); @@ -386,7 +386,7 @@ void HAL_FLASH_IRQHandler(void) /* Clear FLASH End of Operation pending bit */ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); #endif /* FLASH_BANK2_END */ - + /* Process can continue only if no error detected */ if(pFlash.ProcedureOnGoing != FLASH_PROC_NONE) { @@ -445,17 +445,17 @@ void HAL_FLASH_IRQHandler(void) { /* Nb of 16-bit data to program can be decreased */ pFlash.DataRemaining--; - + /* Check if there are still 16-bit data to program */ if(pFlash.DataRemaining != 0) { /* Increment address to 16-bit */ pFlash.Address += 2; addresstmp = pFlash.Address; - + /* Shift to have next 16-bit data */ pFlash.Data = (pFlash.Data >> 16); - + /* Operation is completed, disable the PG Bit */ CLEAR_BIT(FLASH->CR, FLASH_CR_PG); @@ -474,11 +474,11 @@ void HAL_FLASH_IRQHandler(void) { HAL_FLASH_EndOfOperationCallback(pFlash.Address - 2); } - else + else { HAL_FLASH_EndOfOperationCallback(pFlash.Address - 6); } - + /* Reset Address and stop Program procedure*/ pFlash.Address = 0xFFFFFFFF; pFlash.ProcedureOnGoing = FLASH_PROC_NONE; @@ -486,14 +486,14 @@ void HAL_FLASH_IRQHandler(void) } } } - + #if defined(FLASH_BANK2_END) /* Check FLASH End of Operation flag */ if(__HAL_FLASH_GET_FLAG( FLASH_FLAG_EOP_BANK2)) { /* Clear FLASH End of Operation pending bit */ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP_BANK2); - + /* Process can continue only if no error detected */ if(pFlash.ProcedureOnGoing != FLASH_PROC_NONE) { @@ -501,13 +501,13 @@ void HAL_FLASH_IRQHandler(void) { /* Nb of pages to erased can be decreased */ pFlash.DataRemaining--; - + /* Check if there are still pages to erase*/ if(pFlash.DataRemaining != 0) { /* Indicate user which page address has been erased*/ HAL_FLASH_EndOfOperationCallback(pFlash.Address); - + /* Increment page address to next page */ pFlash.Address += FLASH_PAGE_SIZE; addresstmp = pFlash.Address; @@ -520,7 +520,7 @@ void HAL_FLASH_IRQHandler(void) else { /*No more pages to Erase*/ - + /*Reset Address and stop Erase pages procedure*/ pFlash.Address = 0xFFFFFFFF; pFlash.ProcedureOnGoing = FLASH_PROC_NONE; @@ -539,7 +539,7 @@ void HAL_FLASH_IRQHandler(void) /* MassErase ended. Return the selected bank*/ /* FLASH EOP interrupt user callback */ HAL_FLASH_EndOfOperationCallback(0); - + pFlash.ProcedureOnGoing = FLASH_PROC_NONE; } } @@ -547,17 +547,17 @@ void HAL_FLASH_IRQHandler(void) { /* Nb of 16-bit data to program can be decreased */ pFlash.DataRemaining--; - + /* Check if there are still 16-bit data to program */ if(pFlash.DataRemaining != 0) { /* Increment address to 16-bit */ pFlash.Address += 2; addresstmp = pFlash.Address; - + /* Shift to have next 16-bit data */ pFlash.Data = (pFlash.Data >> 16); - + /* Operation is completed, disable the PG Bit */ CLEAR_BIT(FLASH->CR2, FLASH_CR2_PG); @@ -576,11 +576,11 @@ void HAL_FLASH_IRQHandler(void) { HAL_FLASH_EndOfOperationCallback(pFlash.Address-2); } - else + else { HAL_FLASH_EndOfOperationCallback(pFlash.Address-6); } - + /* Reset Address and stop Program procedure*/ pFlash.Address = 0xFFFFFFFF; pFlash.ProcedureOnGoing = FLASH_PROC_NONE; @@ -588,15 +588,15 @@ void HAL_FLASH_IRQHandler(void) } } } -#endif +#endif if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE) { #if defined(FLASH_BANK2_END) /* Operation is completed, disable the PG, PER and MER Bits for both bank */ CLEAR_BIT(FLASH->CR, (FLASH_CR_PG | FLASH_CR_PER | FLASH_CR_MER)); - CLEAR_BIT(FLASH->CR2, (FLASH_CR2_PG | FLASH_CR2_PER | FLASH_CR2_MER)); - + CLEAR_BIT(FLASH->CR2, (FLASH_CR2_PG | FLASH_CR2_PER | FLASH_CR2_MER)); + /* Disable End of FLASH Operation and Error source interrupts for both banks */ __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP_BANK1 | FLASH_IT_ERR_BANK1 | FLASH_IT_EOP_BANK2 | FLASH_IT_ERR_BANK2); #else @@ -617,7 +617,7 @@ void HAL_FLASH_IRQHandler(void) * @brief FLASH end of operation interrupt callback * @param ReturnValue: The value saved in this parameter depends on the ongoing procedure * - Mass Erase: No return value expected - * - Pages Erase: Address of the page which has been erased + * - Pages Erase: Address of the page which has been erased * (if 0xFFFFFFFF, it means that all the selected pages have been erased) * - Program: Address which was selected for data program * @retval none @@ -628,7 +628,7 @@ __weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue) UNUSED(ReturnValue); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_FLASH_EndOfOperationCallback could be implemented in the user file - */ + */ } /** @@ -645,22 +645,22 @@ __weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue) UNUSED(ReturnValue); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_FLASH_OperationErrorCallback could be implemented in the user file - */ + */ } /** * @} */ -/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions - * @brief management functions +/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions + * @brief management functions * -@verbatim +@verbatim =============================================================================== ##### Peripheral Control functions ##### - =============================================================================== + =============================================================================== [..] - This subsection provides a set of functions allowing to control the FLASH + This subsection provides a set of functions allowing to control the FLASH memory operations. @endverbatim @@ -695,9 +695,9 @@ HAL_StatusTypeDef HAL_FLASH_Unlock(void) { return HAL_ERROR; } - + #endif /* FLASH_BANK2_END */ - return HAL_OK; + return HAL_OK; } /** @@ -708,13 +708,13 @@ HAL_StatusTypeDef HAL_FLASH_Lock(void) { /* Set the LOCK Bit to lock the FLASH Registers access */ SET_BIT(FLASH->CR, FLASH_CR_LOCK); - + #if defined(FLASH_BANK2_END) /* Set the LOCK Bit to lock the FLASH BANK2 Registers access */ SET_BIT(FLASH->CR2, FLASH_CR2_LOCK); #endif /* FLASH_BANK2_END */ - return HAL_OK; + return HAL_OK; } @@ -733,23 +733,23 @@ HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void) else { return HAL_ERROR; - } - - return HAL_OK; + } + + return HAL_OK; } /** * @brief Lock the FLASH Option Control Registers access. - * @retval HAL Status + * @retval HAL Status */ HAL_StatusTypeDef HAL_FLASH_OB_Lock(void) { /* Clear the OPTWRE Bit to lock the FLASH Option Byte Registers access */ CLEAR_BIT(FLASH->CR, FLASH_CR_OPTWRE); - - return HAL_OK; + + return HAL_OK; } - + /** * @brief Launch the option byte loading. * @note This function will reset automatically the MCU. @@ -759,21 +759,21 @@ HAL_StatusTypeDef HAL_FLASH_OB_Launch(void) { /* Initiates a system reset request to launch the option byte loading */ HAL_NVIC_SystemReset(); - - return HAL_OK; + + return HAL_OK; } /** * @} - */ + */ -/** @defgroup FLASH_Exported_Functions_Group3 Peripheral State functions - * @brief Peripheral State functions +/** @defgroup FLASH_Exported_Functions_Group3 Peripheral State functions + * @brief Peripheral State functions * -@verbatim +@verbatim =============================================================================== ##### Peripheral State functions ##### - =============================================================================== + =============================================================================== [..] This subsection permit to get in run-time the status of the FLASH peripheral. @@ -787,9 +787,9 @@ HAL_StatusTypeDef HAL_FLASH_OB_Launch(void) * @ref FLASH_Error_Codes */ uint32_t HAL_FLASH_GetError(void) -{ +{ return pFlash.ErrorCode; -} +} /** * @} */ @@ -812,7 +812,7 @@ static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data) { /* Clean the error context */ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; - + #if defined(FLASH_BANK2_END) if(Address <= FLASH_BANK1_END) { @@ -842,11 +842,11 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset. Even if the FLASH operation fails, the BUSY flag will be reset and an error flag will be set */ - + uint32_t tickstart = HAL_GetTick(); - - while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY)) - { + + while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY)) + { if (Timeout != HAL_MAX_DELAY) { if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) @@ -855,16 +855,16 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) } } } - + /* Check FLASH End of Operation flag */ if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP)) { /* Clear FLASH End of Operation pending bit */ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); } - - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) || - __HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) || + + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) || + __HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR)) { /*Save the error code*/ @@ -883,15 +883,15 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) * @retval HAL_StatusTypeDef HAL Status */ HAL_StatusTypeDef FLASH_WaitForLastOperationBank2(uint32_t Timeout) -{ +{ /* Wait for the FLASH BANK2 operation to complete by polling on BUSY flag to be reset. Even if the FLASH BANK2 operation fails, the BUSY flag will be reset and an error flag will be set */ - + uint32_t tickstart = HAL_GetTick(); - - while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY_BANK2)) - { + + while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY_BANK2)) + { if (Timeout != HAL_MAX_DELAY) { if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) @@ -900,7 +900,7 @@ HAL_StatusTypeDef FLASH_WaitForLastOperationBank2(uint32_t Timeout) } } } - + /* Check FLASH End of Operation flag */ if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP_BANK2)) { @@ -917,7 +917,7 @@ HAL_StatusTypeDef FLASH_WaitForLastOperationBank2(uint32_t Timeout) /* If there is an error flag set */ return HAL_OK; - + } #endif /* FLASH_BANK2_END */ @@ -926,7 +926,7 @@ HAL_StatusTypeDef FLASH_WaitForLastOperationBank2(uint32_t Timeout) * @retval None */ static void FLASH_SetErrorCode(void) -{ +{ #if defined(FLASH_BANK2_END) if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR_BANK2)) #else @@ -956,7 +956,7 @@ static void FLASH_SetErrorCode(void) #else __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_WRPERR | FLASH_FLAG_PGERR); #endif /* FLASH_BANK2_END */ -} +} /** * @} */ diff --git a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c index 91e4d5a..0416efe 100644 --- a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c +++ b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c @@ -5,27 +5,27 @@ * @version V1.0.4 * @date 29-April-2016 * @brief Extended FLASH HAL module driver. - * - * This file provides firmware functions to manage the following + * + * This file provides firmware functions to manage the following * functionalities of the FLASH peripheral: * + Extended Initialization/de-initialization functions * + Extended I/O operation functions - * + Extended Peripheral Control functions - * + * + Extended Peripheral Control functions + * @verbatim ============================================================================== ##### Flash peripheral extended features ##### ============================================================================== - + ##### How to use this driver ##### ============================================================================== - [..] This driver provides functions to configure and program the FLASH memory + [..] This driver provides functions to configure and program the FLASH memory of all STM32F1xxx devices. It includes - + (++) Set/Reset the write protection (++) Program the user Option Bytes (++) Get the Read protection Level - + @endverbatim ****************************************************************************** * @attention @@ -54,7 +54,7 @@ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - ****************************************************************************** + ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -80,7 +80,7 @@ extern FLASH_ProcessTypeDef pFlash; /** * @} */ - + /** @defgroup FLASHEx FLASHEx * @brief FLASH HAL Extension module driver * @{ @@ -104,7 +104,7 @@ extern FLASH_ProcessTypeDef pFlash; */ /** * @} - */ + */ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ @@ -132,37 +132,37 @@ static uint8_t FLASH_OB_GetUser(void); /** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions * @{ */ - + /** @defgroup FLASHEx_Exported_Functions_Group1 FLASHEx Memory Erasing functions * @brief FLASH Memory Erasing functions * -@verbatim +@verbatim ============================================================================== - ##### FLASH Erasing Programming functions ##### + ##### FLASH Erasing Programming functions ##### ============================================================================== [..] The FLASH Memory Erasing functions, includes the following functions: (+) @ref HAL_FLASHEx_Erase: return only when erase has been done - (+) @ref HAL_FLASHEx_Erase_IT: end of erase is done when @ref HAL_FLASH_EndOfOperationCallback + (+) @ref HAL_FLASHEx_Erase_IT: end of erase is done when @ref HAL_FLASH_EndOfOperationCallback is called with parameter 0xFFFFFFFF [..] Any operation of erase should follow these steps: - (#) Call the @ref HAL_FLASH_Unlock() function to enable the flash control register and + (#) Call the @ref HAL_FLASH_Unlock() function to enable the flash control register and program memory access. (#) Call the desired function to erase page. - (#) Call the @ref HAL_FLASH_Lock() to disable the flash program memory access + (#) Call the @ref HAL_FLASH_Lock() to disable the flash program memory access (recommended to protect the FLASH memory against possible unwanted operation). @endverbatim * @{ */ - + /** * @brief Perform a mass erase or erase the specified FLASH memory pages * @note To correctly run this function, the @ref HAL_FLASH_Unlock() function * must be called before. - * Call the @ref HAL_FLASH_Lock() to disable the flash memory access + * Call the @ref HAL_FLASH_Lock() to disable the flash memory access * (recommended to protect the FLASH memory against possible unwanted operation) * @param[in] pEraseInit pointer to an FLASH_EraseInitTypeDef structure that * contains the configuration information for the erasing. @@ -196,14 +196,14 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t { /*Mass erase to be done*/ FLASH_MassErase(FLASH_BANK_BOTH); - + /* Wait for last operation to be completed */ if ((FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK) && \ (FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK)) { status = HAL_OK; } - + /* If the erase operation is completed, disable the MER Bit */ CLEAR_BIT(FLASH->CR, FLASH_CR_MER); CLEAR_BIT(FLASH->CR2, FLASH_CR2_MER); @@ -217,15 +217,15 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t { /*Mass erase to be done*/ FLASH_MassErase(FLASH_BANK_2); - + /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE); - + /* If the erase operation is completed, disable the MER Bit */ CLEAR_BIT(FLASH->CR2, FLASH_CR2_MER); } } - else + else #endif /* FLASH_BANK2_END */ { /* Mass Erase requested for Bank1 */ @@ -234,10 +234,10 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t { /*Mass erase to be done*/ FLASH_MassErase(FLASH_BANK_1); - + /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - + /* If the erase operation is completed, disable the MER Bit */ CLEAR_BIT(FLASH->CR, FLASH_CR_MER); } @@ -249,30 +249,30 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t /* Check the parameters */ assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress)); assert_param(IS_FLASH_NB_PAGES(pEraseInit->PageAddress, pEraseInit->NbPages)); - + #if defined(FLASH_BANK2_END) /* Page Erase requested on address located on bank2 */ if(pEraseInit->PageAddress > FLASH_BANK1_END) - { + { /* Wait for last operation to be completed */ if (FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK) { /*Initialization of PageError variable*/ *PageError = 0xFFFFFFFF; - + /* Erase by page by page to be done*/ for(address = pEraseInit->PageAddress; address < (pEraseInit->PageAddress + (pEraseInit->NbPages)*FLASH_PAGE_SIZE); address += FLASH_PAGE_SIZE) { FLASH_PageErase(address); - + /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE); - + /* If the erase operation is completed, disable the PER Bit */ CLEAR_BIT(FLASH->CR2, FLASH_CR2_PER); - + if (status != HAL_OK) { /* In case of error, stop erase procedure and return the faulty address */ @@ -291,20 +291,20 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t { /*Initialization of PageError variable*/ *PageError = 0xFFFFFFFF; - + /* Erase page by page to be done*/ for(address = pEraseInit->PageAddress; address < ((pEraseInit->NbPages * FLASH_PAGE_SIZE) + pEraseInit->PageAddress); address += FLASH_PAGE_SIZE) { FLASH_PageErase(address); - + /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - + /* If the erase operation is completed, disable the PER Bit */ CLEAR_BIT(FLASH->CR, FLASH_CR_PER); - + if (status != HAL_OK) { /* In case of error, stop erase procedure and return the faulty address */ @@ -326,7 +326,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t * @brief Perform a mass erase or erase the specified FLASH memory pages with interrupt enabled * @note To correctly run this function, the @ref HAL_FLASH_Unlock() function * must be called before. - * Call the @ref HAL_FLASH_Lock() to disable the flash memory access + * Call the @ref HAL_FLASH_Lock() to disable the flash memory access * (recommended to protect the FLASH memory against possible unwanted operation) * @param pEraseInit pointer to an FLASH_EraseInitTypeDef structure that * contains the configuration information for the erasing. @@ -345,7 +345,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) { return HAL_ERROR; } - + /* Check the parameters */ assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); @@ -355,7 +355,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) #if defined(FLASH_BANK2_END) /* Enable End of FLASH Operation and Error source interrupts */ __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP_BANK2 | FLASH_IT_ERR_BANK2); - + #endif if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) { @@ -389,12 +389,12 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) /** @defgroup FLASHEx_Exported_Functions_Group2 Option Bytes Programming functions * @brief Option Bytes Programming functions * -@verbatim +@verbatim + ============================================================================== + ##### Option Bytes Programming functions ##### ============================================================================== - ##### Option Bytes Programming functions ##### - ============================================================================== [..] - This subsection provides a set of functions allowing to control the FLASH + This subsection provides a set of functions allowing to control the FLASH option bytes operations. @endverbatim @@ -566,7 +566,7 @@ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit) uint32_t HAL_FLASHEx_OBGetUserData(uint32_t DATAAdress) { uint32_t value = 0; - + if (DATAAdress == OB_DATA_ADDRESS_DATA0) { /* Get value programmed in OB USER Data0 */ @@ -577,7 +577,7 @@ uint32_t HAL_FLASHEx_OBGetUserData(uint32_t DATAAdress) /* Get value programmed in OB USER Data1 */ value = READ_BIT(FLASH->OBR, FLASH_OBR_DATA1) >> FLASH_POSITION_OB_USERDATA1_BIT; } - + return value; } @@ -594,7 +594,7 @@ uint32_t HAL_FLASHEx_OBGetUserData(uint32_t DATAAdress) */ /** - * @brief Full erase of FLASH memory Bank + * @brief Full erase of FLASH memory Bank * @param Banks Banks to be erased * This parameter can be one of the following values: * @arg @ref FLASH_BANK_1 Bank1 to be erased @@ -645,14 +645,14 @@ static void FLASH_MassErase(uint32_t Banks) /** * @brief Enable the write protection of the desired pages - * @note An option byte erase is done automatically in this function. - * @note When the memory read protection level is selected (RDP level = 1), + * @note An option byte erase is done automatically in this function. + * @note When the memory read protection level is selected (RDP level = 1), * it is not possible to program or erase the flash page i if - * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 - * + * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 + * * @param WriteProtectPage specifies the page(s) to be write protected. - * The value of this parameter depend on device used within the same series - * @retval HAL status + * The value of this parameter depend on device used within the same series + * @retval HAL status */ static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage) { @@ -667,25 +667,25 @@ static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage) #if defined(FLASH_WRP3_WRP3) uint16_t WRP3_Data = 0xFFFF; #endif /* FLASH_WRP3_WRP3 */ - + /* Check the parameters */ assert_param(IS_OB_WRP(WriteProtectPage)); - + /* Get current write protected pages and the new pages to be protected ******/ WriteProtectPage = (uint32_t)(~((~FLASH_OB_GetWRP()) | WriteProtectPage)); - + #if defined(OB_WRP_PAGES0TO15MASK) WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO15MASK); #elif defined(OB_WRP_PAGES0TO31MASK) WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO31MASK); #endif /* OB_WRP_PAGES0TO31MASK */ - + #if defined(OB_WRP_PAGES16TO31MASK) WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES16TO31MASK) >> 8); #elif defined(OB_WRP_PAGES32TO63MASK) WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO63MASK) >> 8); #endif /* OB_WRP_PAGES32TO63MASK */ - + #if defined(OB_WRP_PAGES64TO95MASK) WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES64TO95MASK) >> 16); #endif /* OB_WRP_PAGES64TO95MASK */ @@ -694,26 +694,26 @@ static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage) #endif /* OB_WRP_PAGES32TO47MASK */ #if defined(OB_WRP_PAGES96TO127MASK) - WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES96TO127MASK) >> 24); + WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES96TO127MASK) >> 24); #elif defined(OB_WRP_PAGES48TO255MASK) - WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO255MASK) >> 24); + WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO255MASK) >> 24); #elif defined(OB_WRP_PAGES48TO511MASK) - WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO511MASK) >> 24); + WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO511MASK) >> 24); #elif defined(OB_WRP_PAGES48TO127MASK) - WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) >> 24); + WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) >> 24); #endif /* OB_WRP_PAGES96TO127MASK */ - + /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); if(status == HAL_OK) - { + { /* Clean the error context */ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; /* To be able to write again option byte, need to perform a option byte erase */ status = HAL_FLASHEx_OBErase(); - if (status == HAL_OK) + if (status == HAL_OK) { /* Enable write protection */ SET_BIT(FLASH->CR, FLASH_CR_OPTPG); @@ -722,7 +722,7 @@ static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage) if(WRP0_Data != 0xFF) { OB->WRP0 &= WRP0_Data; - + /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); } @@ -732,7 +732,7 @@ static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage) if((status == HAL_OK) && (WRP1_Data != 0xFF)) { OB->WRP1 &= WRP1_Data; - + /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); } @@ -742,7 +742,7 @@ static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage) if((status == HAL_OK) && (WRP2_Data != 0xFF)) { OB->WRP2 &= WRP2_Data; - + /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); } @@ -752,7 +752,7 @@ static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage) if((status == HAL_OK) && (WRP3_Data != 0xFF)) { OB->WRP3 &= WRP3_Data; - + /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); } @@ -762,20 +762,20 @@ static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage) CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG); } } - + return status; } /** * @brief Disable the write protection of the desired pages - * @note An option byte erase is done automatically in this function. - * @note When the memory read protection level is selected (RDP level = 1), - * it is not possible to program or erase the flash page i if - * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 - * + * @note An option byte erase is done automatically in this function. + * @note When the memory read protection level is selected (RDP level = 1), + * it is not possible to program or erase the flash page i if + * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 + * * @param WriteProtectPage specifies the page(s) to be write unprotected. - * The value of this parameter depend on device used within the same series - * @retval HAL status + * The value of this parameter depend on device used within the same series + * @retval HAL status */ static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage) { @@ -790,7 +790,7 @@ static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage) #if defined(FLASH_WRP3_WRP3) uint16_t WRP3_Data = 0xFFFF; #endif /* FLASH_WRP3_WRP3 */ - + /* Check the parameters */ assert_param(IS_OB_WRP(WriteProtectPage)); @@ -802,13 +802,13 @@ static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage) #elif defined(OB_WRP_PAGES0TO31MASK) WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO31MASK); #endif /* OB_WRP_PAGES0TO31MASK */ - + #if defined(OB_WRP_PAGES16TO31MASK) WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES16TO31MASK) >> 8); #elif defined(OB_WRP_PAGES32TO63MASK) WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO63MASK) >> 8); #endif /* OB_WRP_PAGES32TO63MASK */ - + #if defined(OB_WRP_PAGES64TO95MASK) WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES64TO95MASK) >> 16); #endif /* OB_WRP_PAGES64TO95MASK */ @@ -817,27 +817,27 @@ static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage) #endif /* OB_WRP_PAGES32TO47MASK */ #if defined(OB_WRP_PAGES96TO127MASK) - WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES96TO127MASK) >> 24); + WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES96TO127MASK) >> 24); #elif defined(OB_WRP_PAGES48TO255MASK) - WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO255MASK) >> 24); + WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO255MASK) >> 24); #elif defined(OB_WRP_PAGES48TO511MASK) - WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO511MASK) >> 24); + WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO511MASK) >> 24); #elif defined(OB_WRP_PAGES48TO127MASK) - WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) >> 24); + WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) >> 24); #endif /* OB_WRP_PAGES96TO127MASK */ - + /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); if(status == HAL_OK) - { + { /* Clean the error context */ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; /* To be able to write again option byte, need to perform a option byte erase */ status = HAL_FLASHEx_OBErase(); - if (status == HAL_OK) + if (status == HAL_OK) { SET_BIT(FLASH->CR, FLASH_CR_OPTPG); @@ -845,7 +845,7 @@ static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage) if(WRP0_Data != 0xFF) { OB->WRP0 |= WRP0_Data; - + /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); } @@ -855,7 +855,7 @@ static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage) if((status == HAL_OK) && (WRP1_Data != 0xFF)) { OB->WRP1 |= WRP1_Data; - + /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); } @@ -865,7 +865,7 @@ static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage) if((status == HAL_OK) && (WRP2_Data != 0xFF)) { OB->WRP2 |= WRP2_Data; - + /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); } @@ -875,7 +875,7 @@ static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage) if((status == HAL_OK) && (WRP3_Data != 0xFF)) { OB->WRP3 |= WRP3_Data; - + /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); } @@ -899,18 +899,18 @@ static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage) static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t ReadProtectLevel) { HAL_StatusTypeDef status = HAL_OK; - + /* Check the parameters */ assert_param(IS_OB_RDP_LEVEL(ReadProtectLevel)); - + /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - + if(status == HAL_OK) - { + { /* Clean the error context */ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; - + /* If the previous operation is completed, proceed to erase the option bytes */ SET_BIT(FLASH->CR, FLASH_CR_OPTER); SET_BIT(FLASH->CR, FLASH_CR_STRT); @@ -925,26 +925,26 @@ static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t ReadProtectLevel) { /* Enable the Option Bytes Programming operation */ SET_BIT(FLASH->CR, FLASH_CR_OPTPG); - + WRITE_REG(OB->RDP, ReadProtectLevel); - + /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + /* if the program operation is completed, disable the OPTPG Bit */ CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG); } } - + return status; } /** - * @brief Program the FLASH User Option Byte. + * @brief Program the FLASH User Option Byte. * @note Programming of the OB should be performed only after an erase (otherwise PGERR occurs) - * @param UserConfig The FLASH User Option Bytes values FLASH_OBR_IWDG_SW(Bit2), + * @param UserConfig The FLASH User Option Bytes values FLASH_OBR_IWDG_SW(Bit2), * FLASH_OBR_nRST_STOP(Bit3),FLASH_OBR_nRST_STDBY(Bit4). - * And BFBF2(Bit5) for STM32F101xG and STM32F103xG . + * And BFBF2(Bit5) for STM32F101xG and STM32F103xG . * @retval HAL status */ static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t UserConfig) @@ -961,15 +961,15 @@ static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t UserConfig) /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - + if(status == HAL_OK) - { + { /* Clean the error context */ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; /* Enable the Option Bytes Programming operation */ - SET_BIT(FLASH->CR, FLASH_CR_OPTPG); - + SET_BIT(FLASH->CR, FLASH_CR_OPTPG); + #if defined(FLASH_BANK2_END) OB->USER = (UserConfig | 0xF0); #else @@ -982,44 +982,44 @@ static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t UserConfig) /* if the program operation is completed, disable the OPTPG Bit */ CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG); } - - return status; + + return status; } /** * @brief Programs a half word at a specified Option Byte Data address. * @note The function @ref HAL_FLASH_Unlock() should be called before to unlock the FLASH interface * The function @ref HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes - * The function @ref HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes + * The function @ref HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes * (system reset will occur) * Programming of the OB should be performed only after an erase (otherwise PGERR occurs) * @param Address specifies the address to be programmed. - * This parameter can be 0x1FFFF804 or 0x1FFFF806. + * This parameter can be 0x1FFFF804 or 0x1FFFF806. * @param Data specifies the data to be programmed. * @retval HAL status */ static HAL_StatusTypeDef FLASH_OB_ProgramData(uint32_t Address, uint8_t Data) { HAL_StatusTypeDef status = HAL_ERROR; - + /* Check the parameters */ assert_param(IS_OB_DATA_ADDRESS(Address)); - + /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - + if(status == HAL_OK) { /* Clean the error context */ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; /* Enables the Option Bytes Programming operation */ - SET_BIT(FLASH->CR, FLASH_CR_OPTPG); + SET_BIT(FLASH->CR, FLASH_CR_OPTPG); *(__IO uint16_t*)Address = Data; - + /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - + /* If the program operation is completed, disable the OPTPG Bit */ CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG); } @@ -1048,7 +1048,7 @@ static uint32_t FLASH_OB_GetRDP(void) { uint32_t readstatus = OB_RDP_LEVEL_0; uint32_t tmp_reg = 0; - + /* Read RDP level bits */ tmp_reg = READ_BIT(FLASH->OBR, FLASH_OBR_RDPRT); @@ -1056,7 +1056,7 @@ static uint32_t FLASH_OB_GetRDP(void) { readstatus = OB_RDP_LEVEL_1; } - else + else { readstatus = OB_RDP_LEVEL_0; } @@ -1066,9 +1066,9 @@ static uint32_t FLASH_OB_GetRDP(void) /** * @brief Return the FLASH User Option Byte value. - * @retval The FLASH User Option Bytes values: FLASH_OBR_IWDG_SW(Bit2), + * @retval The FLASH User Option Bytes values: FLASH_OBR_IWDG_SW(Bit2), * FLASH_OBR_nRST_STOP(Bit3),FLASH_OBR_nRST_STDBY(Bit4). - * And FLASH_OBR_BFB2(Bit5) for STM32F101xG and STM32F103xG . + * And FLASH_OBR_BFB2(Bit5) for STM32F101xG and STM32F103xG . */ static uint8_t FLASH_OB_GetUser(void) { @@ -1095,8 +1095,8 @@ static uint8_t FLASH_OB_GetUser(void) /** * @brief Erase the specified FLASH memory page * @param PageAddress FLASH page to erase - * The value of this parameter depend on device used within the same series - * + * The value of this parameter depend on device used within the same series + * * @retval None */ void FLASH_PageErase(uint32_t PageAddress) @@ -1106,7 +1106,7 @@ void FLASH_PageErase(uint32_t PageAddress) #if defined(FLASH_BANK2_END) if(PageAddress > FLASH_BANK1_END) - { + { /* Proceed to erase the page */ SET_BIT(FLASH->CR2, FLASH_CR2_PER); WRITE_REG(FLASH->AR2, PageAddress); diff --git a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c index 9e048ad..4e7c78a 100644 --- a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c +++ b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c @@ -5,89 +5,89 @@ * @version V1.0.4 * @date 29-April-2016 * @brief GPIO HAL module driver. - * This file provides firmware functions to manage the following + * This file provides firmware functions to manage the following * functionalities of the General Purpose Input/Output (GPIO) peripheral: * + Initialization and de-initialization functions * + IO operation functions - * + * @verbatim ============================================================================== ##### GPIO Peripheral features ##### - ============================================================================== - [..] + ============================================================================== + [..] Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each port bit of the General Purpose IO (GPIO) Ports, can be individually configured by software in several modes: - (+) Input mode + (+) Input mode (+) Analog mode (+) Output mode (+) Alternate function mode (+) External interrupt/event lines - [..] - During and just after reset, the alternate functions and external interrupt + [..] + During and just after reset, the alternate functions and external interrupt lines are not active and the I/O ports are configured in input floating mode. - - [..] - All GPIO pins have weak internal pull-up and pull-down resistors, which can be + + [..] + All GPIO pins have weak internal pull-up and pull-down resistors, which can be activated or not. [..] In Output or Alternate mode, each IO can be configured on open-drain or push-pull type and the IO speed can be selected depending on the VDD value. - [..] - All ports have external interrupt/event capability. To use external interrupt - lines, the port must be configured in input mode. All available GPIO pins are + [..] + All ports have external interrupt/event capability. To use external interrupt + lines, the port must be configured in input mode. All available GPIO pins are connected to the 16 external interrupt/event lines from EXTI0 to EXTI15. - - [..] + + [..] The external interrupt/event controller consists of up to 20 edge detectors in connectivity line devices, or 19 edge detectors in other devices for generating event/interrupt requests. Each input line can be independently configured to select the type (event or interrupt) and the corresponding trigger event (rising or falling or both). Each line can also masked independently. A pending register maintains the status line of the interrupt requests - + ##### How to use this driver ##### - ============================================================================== - [..] - (#) Enable the GPIO APB2 clock using the following function : __HAL_RCC_GPIOx_CLK_ENABLE(). - + ============================================================================== + [..] + (#) Enable the GPIO APB2 clock using the following function : __HAL_RCC_GPIOx_CLK_ENABLE(). + (#) Configure the GPIO pin(s) using HAL_GPIO_Init(). (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure - (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef + (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef structure. - (++) In case of Output or alternate function mode selection: the speed is + (++) In case of Output or alternate function mode selection: the speed is configured through "Speed" member from GPIO_InitTypeDef structure - (++) Analog mode is required when a pin is to be used as ADC channel + (++) Analog mode is required when a pin is to be used as ADC channel or DAC output. - (++) In case of external interrupt/event selection the "Mode" member from - GPIO_InitTypeDef structure select the type (interrupt or event) and + (++) In case of external interrupt/event selection the "Mode" member from + GPIO_InitTypeDef structure select the type (interrupt or event) and the corresponding trigger event (rising or falling or both). - - (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority + + (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using HAL_NVIC_EnableIRQ(). - + (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin(). - - (#) To set/reset the level of a pin configured in output mode use + + (#) To set/reset the level of a pin configured in output mode use HAL_GPIO_WritePin()/HAL_GPIO_TogglePin(). - + (#) To lock pin configuration until next reset use HAL_GPIO_LockPin(). - - (#) During and just after reset, the alternate functions are not + + (#) During and just after reset, the alternate functions are not active and the GPIO pins are configured in input floating mode (except JTAG pins). - - (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose - (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has + + (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose + (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has priority over the GPIO function. - - (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as - general purpose PD0 and PD1, respectively, when the HSE oscillator is off. + + (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as + general purpose PD0 and PD1, respectively, when the HSE oscillator is off. The HSE has priority over the GPIO function. - + @endverbatim ****************************************************************************** * @attention @@ -116,8 +116,8 @@ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - ****************************************************************************** - */ + ****************************************************************************** + */ /* Includes ------------------------------------------------------------------*/ #include "stm32f1xx_hal.h" @@ -138,14 +138,14 @@ /** @defgroup GPIO_Private_Constants GPIO Private Constants * @{ */ - + #define GPIO_MODE ((uint32_t)0x00000003) #define EXTI_MODE ((uint32_t)0x10000000) #define GPIO_MODE_IT ((uint32_t)0x00010000) #define GPIO_MODE_EVT ((uint32_t)0x00020000) -#define RISING_EDGE ((uint32_t)0x00100000) -#define FALLING_EDGE ((uint32_t)0x00200000) -#define GPIO_OUTPUT_TYPE ((uint32_t)0x00000010) +#define RISING_EDGE ((uint32_t)0x00100000) +#define FALLING_EDGE ((uint32_t)0x00200000) +#define GPIO_OUTPUT_TYPE ((uint32_t)0x00000010) #define GPIO_NUMBER ((uint32_t)16) /* Definitions for bit manipulation of CRL and CRH register */ @@ -157,7 +157,7 @@ #define GPIO_CR_CNF_GP_OUTPUT_OD ((uint32_t)0x00000004) /*!< 01: General purpose output Open-drain */ #define GPIO_CR_CNF_AF_OUTPUT_PP ((uint32_t)0x00000008) /*!< 10: Alternate function output Push-pull */ #define GPIO_CR_CNF_AF_OUTPUT_OD ((uint32_t)0x0000000C) /*!< 11: Alternate function output Open-drain */ - + /** * @} */ @@ -174,14 +174,14 @@ /** @defgroup GPIO_Exported_Functions_Group1 Initialization and deinitialization functions * @brief Initialization and Configuration functions * -@verbatim +@verbatim =============================================================================== ##### Initialization and deinitialization functions ##### =============================================================================== [..] This section provides functions allowing to initialize and de-initialize the GPIOs to be ready for use. - + @endverbatim * @{ */ @@ -202,7 +202,7 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) uint32_t config = 0x00; __IO uint32_t *configregister; /* Store the address of CRL or CRH register based on pin number */ uint32_t registeroffset = 0; /* offset used during computation of CNF and MODE bits placement inside CRL or CRH register */ - + /* Check the parameters */ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); @@ -213,7 +213,7 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { /* Get the IO position */ ioposition = ((uint32_t)0x01) << position; - + /* Get the current IO position */ iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; @@ -231,28 +231,28 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_PP; break; - + /* If we are configuring the pin in OUTPUT open-drain mode */ case GPIO_MODE_OUTPUT_OD: /* Check the GPIO speed parameter */ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_OD; break; - + /* If we are configuring the pin in ALTERNATE FUNCTION push-pull mode */ case GPIO_MODE_AF_PP: /* Check the GPIO speed parameter */ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_PP; break; - + /* If we are configuring the pin in ALTERNATE FUNCTION open-drain mode */ case GPIO_MODE_AF_OD: /* Check the GPIO speed parameter */ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_OD; break; - + /* If we are configuring the pin in INPUT (also applicable to EVENT and IT mode) */ case GPIO_MODE_INPUT: case GPIO_MODE_IT_RISING: @@ -264,46 +264,46 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) /* Check the GPIO pull parameter */ assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); if(GPIO_Init->Pull == GPIO_NOPULL) - { + { config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_FLOATING; } else if(GPIO_Init->Pull == GPIO_PULLUP) { config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD; - + /* Set the corresponding ODR bit */ GPIOx->BSRR = ioposition; } else /* GPIO_PULLDOWN */ { config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD; - + /* Reset the corresponding ODR bit */ GPIOx->BRR = ioposition; } - break; - + break; + /* If we are configuring the pin in INPUT analog mode */ case GPIO_MODE_ANALOG: config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG; break; - + /* Parameters are checked with assert_param */ default: break; } - + /* Check if the current bit belongs to first half or last half of the pin count number in order to address CRH or CRL register*/ configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH; registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2) : ((position - 8) << 2); - + /* Apply the new configuration of the pin to the register */ MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset ), (config << registeroffset)); - + /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ - if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) + if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) { /* Enable AFIO Clock */ __HAL_RCC_AFIO_CLK_ENABLE(); @@ -311,46 +311,46 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) CLEAR_BIT(temp, ((uint32_t)0x0F) << (4 * (position & 0x03))); SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03))); AFIO->EXTICR[position >> 2] = temp; - + /* Configure the interrupt mask */ if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) { - SET_BIT(EXTI->IMR, iocurrent); - } + SET_BIT(EXTI->IMR, iocurrent); + } else { - CLEAR_BIT(EXTI->IMR, iocurrent); - } - + CLEAR_BIT(EXTI->IMR, iocurrent); + } + /* Configure the event mask */ if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) { - SET_BIT(EXTI->EMR, iocurrent); - } + SET_BIT(EXTI->EMR, iocurrent); + } else { - CLEAR_BIT(EXTI->EMR, iocurrent); + CLEAR_BIT(EXTI->EMR, iocurrent); } - + /* Enable or disable the rising trigger */ if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) { - SET_BIT(EXTI->RTSR, iocurrent); - } + SET_BIT(EXTI->RTSR, iocurrent); + } else { - CLEAR_BIT(EXTI->RTSR, iocurrent); + CLEAR_BIT(EXTI->RTSR, iocurrent); } - + /* Enable or disable the falling trigger */ if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) { - SET_BIT(EXTI->FTSR, iocurrent); - } + SET_BIT(EXTI->FTSR, iocurrent); + } else { - CLEAR_BIT(EXTI->FTSR, iocurrent); + CLEAR_BIT(EXTI->FTSR, iocurrent); } } } @@ -365,13 +365,13 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) * @retval None */ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) -{ +{ uint32_t position = 0x00; uint32_t iocurrent = 0x00; uint32_t tmp = 0x00; __IO uint32_t *configregister; /* Store the address of CRL or CRH register based on pin number */ uint32_t registeroffset = 0; - + /* Check the parameters */ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Pin)); @@ -389,33 +389,33 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) in order to address CRH or CRL register */ configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH; registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2) : ((position - 8) << 2); - + /* CRL/CRH default value is floating input(0x04) shifted to correct position */ MODIFY_REG(*configregister, ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset ), GPIO_CRL_CNF0_0 << registeroffset); - + /* ODR default value is 0 */ CLEAR_BIT(GPIOx->ODR, iocurrent); - + /*------------------------- EXTI Mode Configuration --------------------*/ /* Clear the External Interrupt or Event for the current IO */ - + tmp = AFIO->EXTICR[position >> 2]; tmp &= (((uint32_t)0x0F) << (4 * (position & 0x03))); if(tmp == (GPIO_GET_INDEX(GPIOx) << (4 * (position & 0x03)))) { tmp = ((uint32_t)0x0F) << (4 * (position & 0x03)); CLEAR_BIT(AFIO->EXTICR[position >> 2], tmp); - + /* Clear EXTI line configuration */ CLEAR_BIT(EXTI->IMR, (uint32_t)iocurrent); CLEAR_BIT(EXTI->EMR, (uint32_t)iocurrent); - + /* Clear Rising Falling edge configuration */ CLEAR_BIT(EXTI->RTSR, (uint32_t)iocurrent); CLEAR_BIT(EXTI->FTSR, (uint32_t)iocurrent); } } - + position++; } } @@ -424,10 +424,10 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) * @} */ -/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions - * @brief GPIO Read and Write +/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions + * @brief GPIO Read and Write * -@verbatim +@verbatim =============================================================================== ##### IO operation functions ##### =============================================================================== @@ -464,11 +464,11 @@ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) /** * @brief Sets or clears the selected data port bit. - * - * @note This function uses GPIOx_BSRR register to allow atomic read/modify + * + * @note This function uses GPIOx_BSRR register to allow atomic read/modify * accesses. In this way, there is no risk of an IRQ occurring between * the read and the modify access. - * + * * @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral * @param GPIO_Pin: specifies the port bit to be written. * This parameter can be one of GPIO_PIN_x where x can be (0..15). @@ -496,7 +496,7 @@ void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState Pin /** * @brief Toggles the specified GPIO pin - * @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral + * @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral * @param GPIO_Pin: Specifies the pins to be toggled. * @retval None */ @@ -555,8 +555,8 @@ HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) { /* EXTI line interrupt detected */ - if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET) - { + if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET) + { __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin); HAL_GPIO_EXTI_Callback(GPIO_Pin); } @@ -573,7 +573,7 @@ __weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) UNUSED(GPIO_Pin); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_GPIO_EXTI_Callback could be implemented in the user file - */ + */ } /** diff --git a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c index 31493e6..da0b4a5 100644 --- a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c +++ b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c @@ -5,24 +5,24 @@ * @version V1.0.4 * @date 29-April-2016 * @brief GPIO Extension HAL module driver. - * This file provides firmware functions to manage the following + * This file provides firmware functions to manage the following * functionalities of the General Purpose Input/Output (GPIO) extension peripheral. * + Extended features functions - * + * @verbatim ============================================================================== ##### GPIO Peripheral extension features ##### - ============================================================================== + ============================================================================== [..] GPIO module on STM32F1 family, manage also the AFIO register: (+) Possibility to use the EVENTOUT Cortex feature - + ##### How to use this driver ##### ============================================================================== [..] This driver provides functions to use EVENTOUT Cortex feature (#) Configure EVENTOUT Cortex feature using the function HAL_GPIOEx_ConfigEventout() (#) Activate EVENTOUT Cortex feature using the HAL_GPIOEx_EnableEventout() (#) Deactivate EVENTOUT Cortex feature using the HAL_GPIOEx_DisableEventout() - + @endverbatim ****************************************************************************** * @attention @@ -51,8 +51,8 @@ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - ****************************************************************************** - */ + ****************************************************************************** + */ /* Includes ------------------------------------------------------------------*/ #include "stm32f1xx_hal.h" @@ -73,21 +73,21 @@ */ /** @defgroup GPIOEx_Exported_Functions_Group1 Extended features functions - * @brief Extended features functions + * @brief Extended features functions * -@verbatim +@verbatim ============================================================================== ##### Extended features functions ##### - ============================================================================== + ============================================================================== [..] This section provides functions allowing to: (+) Configure EVENTOUT Cortex feature using the function HAL_GPIOEx_ConfigEventout() (+) Activate EVENTOUT Cortex feature using the HAL_GPIOEx_EnableEventout() (+) Deactivate EVENTOUT Cortex feature using the HAL_GPIOEx_DisableEventout() - + @endverbatim * @{ */ - + /** * @brief Configures the port and pin on which the EVENTOUT Cortex signal will be connected. * @param GPIO_PortSource Select the port used to output the Cortex EVENTOUT signal. @@ -95,13 +95,13 @@ * @param GPIO_PinSource Select the pin used to output the Cortex EVENTOUT signal. * This parameter can be a value of @ref GPIOEx_EVENTOUT_PIN. * @retval None - */ + */ void HAL_GPIOEx_ConfigEventout(uint32_t GPIO_PortSource, uint32_t GPIO_PinSource) { /* Verify the parameters */ assert_param(IS_AFIO_EVENTOUT_PORT(GPIO_PortSource)); assert_param(IS_AFIO_EVENTOUT_PIN(GPIO_PinSource)); - + /* Apply the new configuration */ MODIFY_REG(AFIO->EVCR, (AFIO_EVCR_PORT)|(AFIO_EVCR_PIN), (GPIO_PortSource)|(GPIO_PinSource)); } @@ -127,11 +127,11 @@ void HAL_GPIOEx_DisableEventout(void) /** * @} */ - + /** * @} */ - + #endif /* HAL_GPIO_MODULE_ENABLED */ /** diff --git a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pcd.c b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pcd.c index 91461a3..42d38ae 100644 --- a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pcd.c +++ b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pcd.c @@ -5,11 +5,11 @@ * @version V1.0.4 * @date 29-April-2016 * @brief PCD HAL module driver. - * This file provides firmware functions to manage the following + * This file provides firmware functions to manage the following * functionalities of the USB Peripheral Controller: * + Initialization and de-initialization functions * + IO operation functions - * + Peripheral Control functions + * + Peripheral Control functions * + Peripheral State functions * @verbatim @@ -31,7 +31,7 @@ (+++) __HAL_RCC_USB_CLK_ENABLE(); For USB Device FS peripheral available on STM32F102xx and STM32F103xx devices (+++) __HAL_RCC_USB_OTG_FS_CLK_ENABLE(); For USB OTG FS peripheral available - on STM32F105xx and STM32F107xx devices + on STM32F105xx and STM32F107xx devices (##) Initialize the related GPIO clocks (##) Configure PCD pin-out @@ -101,7 +101,7 @@ /* Private macros ------------------------------------------------------------*/ /** @defgroup PCD_Private_Macros PCD Private Macros * @{ - */ + */ #define PCD_MIN(a, b) (((a) < (b)) ? (a) : (b)) #define PCD_MAX(a, b) (((a) > (b)) ? (a) : (b)) /** @@ -128,15 +128,15 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd); * @{ */ -/** @defgroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions +/** @defgroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions * @verbatim =============================================================================== ##### Initialization and de-initialization functions ##### =============================================================================== [..] This section provides functions allowing to: - + @endverbatim * @{ */ @@ -150,36 +150,36 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd); HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) { uint32_t index = 0; - + /* Check the PCD handle allocation */ if(hpcd == NULL) { return HAL_ERROR; } - + /* Check the parameters */ assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance)); if(hpcd->State == HAL_PCD_STATE_RESET) - { + { /* Allocate lock resource and initialize it */ hpcd->Lock = HAL_UNLOCKED; /* Init the low level hardware : GPIO, CLOCK, NVIC... */ HAL_PCD_MspInit(hpcd); } - + hpcd->State = HAL_PCD_STATE_BUSY; - + /* Disable the Interrupts */ __HAL_PCD_DISABLE(hpcd); - + /*Init the Core (common init.) */ USB_CoreInit(hpcd->Instance, hpcd->Init); - + /* Force Device Mode*/ USB_SetCurrentMode(hpcd->Instance , USB_DEVICE_MODE); - + /* Init endpoints structures */ for (index = 0; index < 15 ; index++) { @@ -193,7 +193,7 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) hpcd->IN_ep[index].xfer_buff = 0; hpcd->IN_ep[index].xfer_len = 0; } - + for (index = 0; index < 15 ; index++) { hpcd->OUT_ep[index].is_in = 0; @@ -205,19 +205,19 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) hpcd->OUT_ep[index].xfer_buff = 0; hpcd->OUT_ep[index].xfer_len = 0; } - + /* Init Device */ USB_DevInit(hpcd->Instance, hpcd->Init); - + hpcd->USB_Address = 0; hpcd->State= HAL_PCD_STATE_READY; - - USB_DevDisconnect (hpcd->Instance); + + USB_DevDisconnect (hpcd->Instance); return HAL_OK; } /** - * @brief DeInitializes the PCD peripheral + * @brief DeInitializes the PCD peripheral * @param hpcd: PCD handle * @retval HAL status */ @@ -228,17 +228,17 @@ HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd) { return HAL_ERROR; } - + hpcd->State = HAL_PCD_STATE_BUSY; - + /* Stop Device */ HAL_PCD_Stop(hpcd); - + /* DeInit the low level hardware */ HAL_PCD_MspDeInit(hpcd); - - hpcd->State = HAL_PCD_STATE_RESET; - + + hpcd->State = HAL_PCD_STATE_RESET; + return HAL_OK; } @@ -274,15 +274,15 @@ __weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd) * @} */ -/** @defgroup PCD_Exported_Functions_Group2 IO operation functions - * @brief Data transfers functions +/** @defgroup PCD_Exported_Functions_Group2 IO operation functions + * @brief Data transfers functions * @verbatim =============================================================================== ##### IO operation functions ##### =============================================================================== [..] - This subsection provides a set of functions allowing to manage the PCD data + This subsection provides a set of functions allowing to manage the PCD data transfers. @endverbatim @@ -310,7 +310,7 @@ HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd) * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd) -{ +{ __HAL_LOCK(hpcd); __HAL_PCD_DISABLE(hpcd); USB_StopDevice(hpcd->Instance); @@ -331,7 +331,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) uint32_t index = 0, ep_intr = 0, epint = 0, epnum = 0; uint32_t fifoemptymsk = 0, temp = 0; USB_OTG_EPTypeDef *ep = NULL; - + /* ensure that we are in device mode */ if (USB_GetMode(hpcd->Instance) == USB_OTG_MODE_DEVICE) { @@ -340,40 +340,40 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) { return; } - + if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_MMIS)) { /* incorrect mode, acknowledge the interrupt */ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_MMIS); } - + if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OEPINT)) { epnum = 0; - + /* Read in the device interrupt bits */ ep_intr = USB_ReadDevAllOutEpInterrupt(hpcd->Instance); - + while ( ep_intr ) { if (ep_intr & 0x1) { epint = USB_ReadDevOutEPInterrupt(hpcd->Instance, epnum); - + if(( epint & USB_OTG_DOEPINT_XFRC) == USB_OTG_DOEPINT_XFRC) { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_XFRC); - + HAL_PCD_DataOutStageCallback(hpcd, epnum); } - + if(( epint & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP) { /* Inform the upper layer that a setup packet is available */ HAL_PCD_SetupStageCallback(hpcd); CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STUP); } - + if(( epint & USB_OTG_DOEPINT_OTEPDIS) == USB_OTG_DOEPINT_OTEPDIS) { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPDIS); @@ -383,27 +383,27 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) ep_intr >>= 1; } } - + if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IEPINT)) { /* Read in the device interrupt bits */ ep_intr = USB_ReadDevAllInEpInterrupt(hpcd->Instance); - + epnum = 0; - + while ( ep_intr ) { if (ep_intr & 0x1) /* In ITR */ { epint = USB_ReadDevInEPInterrupt(hpcd->Instance, epnum); - + if(( epint & USB_OTG_DIEPINT_XFRC) == USB_OTG_DIEPINT_XFRC) { fifoemptymsk = 0x1 << epnum; USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk; - + CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_XFRC); - + HAL_PCD_DataInStageCallback(hpcd, epnum); } if(( epint & USB_OTG_DIEPINT_TOC) == USB_OTG_DIEPINT_TOC) @@ -431,35 +431,35 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) ep_intr >>= 1; } } - + /* Handle Resume Interrupt */ if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT)) { /* Clear the Remote Wake-up signalling */ USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG; - + HAL_PCD_ResumeCallback(hpcd); - + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT); } - + /* Handle Suspend Interrupt */ if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP)) { if((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS) { - + HAL_PCD_SuspendCallback(hpcd); } __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP); } - + /* Handle Reset Interrupt */ if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBRST)) { - USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG; + USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG; USB_FlushTxFifo(hpcd->Instance , 0 ); - + for (index = 0; index < hpcd->Init.dev_endpoints ; index++) { USBx_INEP(index)->DIEPINT = 0xFF; @@ -467,41 +467,41 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) } USBx_DEVICE->DAINT = 0xFFFFFFFF; USBx_DEVICE->DAINTMSK |= 0x10001; - + USBx_DEVICE->DOEPMSK |= (USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM); USBx_DEVICE->DIEPMSK |= (USB_OTG_DIEPMSK_TOM | USB_OTG_DIEPMSK_XFRCM | USB_OTG_DIEPMSK_EPDM); - + /* Set Default Address to 0 */ USBx_DEVICE->DCFG &= ~USB_OTG_DCFG_DAD; - + /* setup EP0 to receive SETUP packets */ USB_EP0_OutStart(hpcd->Instance, (uint8_t *)hpcd->Setup); - + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBRST); } - + /* Handle Enumeration done Interrupt */ if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE)) { USB_ActivateSetup(hpcd->Instance); hpcd->Instance->GUSBCFG &= ~USB_OTG_GUSBCFG_TRDT; - + hpcd->Init.speed = USB_OTG_SPEED_FULL; hpcd->Init.ep0_mps = USB_OTG_FS_MAX_PACKET_SIZE ; hpcd->Instance->GUSBCFG |= (uint32_t)((USBD_FS_TRDT_VALUE << 10) & USB_OTG_GUSBCFG_TRDT); - + HAL_PCD_ResetCallback(hpcd); - + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE); } - + /* Handle RxQLevel Interrupt */ if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL)) { USB_MASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL); temp = USBx->GRXSTSP; ep = &hpcd->OUT_ep[temp & USB_OTG_GRXSTSP_EPNUM]; - + if(((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_DATA_UPDT) { if((temp & USB_OTG_GRXSTSP_BCNT) != 0) @@ -518,40 +518,40 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) } USB_UNMASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL); } - + /* Handle SOF Interrupt */ if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SOF)) { HAL_PCD_SOFCallback(hpcd); __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SOF); } - + /* Handle Incomplete ISO IN Interrupt */ if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR)) { HAL_PCD_ISOINIncompleteCallback(hpcd, epnum); __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR); } - + /* Handle Incomplete ISO OUT Interrupt */ if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT)) { HAL_PCD_ISOOUTIncompleteCallback(hpcd, epnum); __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT); } - + /* Handle Connection event Interrupt */ if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT)) { HAL_PCD_ConnectCallback(hpcd); __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT); } - + /* Handle Disconnection event Interrupt */ if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OTGINT)) { temp = hpcd->Instance->GOTGINT; - + if((temp & USB_OTG_GOTGINT_SEDET) == USB_OTG_GOTGINT_SEDET) { HAL_PCD_DisconnectCallback(hpcd); @@ -571,7 +571,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) { uint32_t wInterrupt_Mask = 0; - + if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_CTR)) { /* servicing of the endpoint correct transfer interrupt */ @@ -588,34 +588,34 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_PMAOVR)) { - __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_PMAOVR); + __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_PMAOVR); } if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_ERR)) { - __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ERR); + __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ERR); } if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_WKUP)) - { + { hpcd->Instance->CNTR &= ~(USB_CNTR_LP_MODE); - + /*set wInterrupt_Mask global variable*/ wInterrupt_Mask = USB_CNTR_CTRM | USB_CNTR_WKUPM | USB_CNTR_SUSPM | USB_CNTR_ERRM \ | USB_CNTR_ESOFM | USB_CNTR_RESETM; - + /*Set interrupt mask*/ hpcd->Instance->CNTR = wInterrupt_Mask; - + HAL_PCD_ResumeCallback(hpcd); - - __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_WKUP); + + __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_WKUP); } if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_SUSP)) { /* clear of the ISTR bit must be done after setting of CNTR_FSUSP */ - __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SUSP); - + __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SUSP); + /* Force low-power mode in the macrocell */ hpcd->Instance->CNTR |= USB_CNTR_FSUSP; hpcd->Instance->CNTR |= USB_CNTR_LP_MODE; @@ -627,14 +627,14 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_SOF)) { - __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SOF); + __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SOF); HAL_PCD_SOFCallback(hpcd); } if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_ESOF)) { /* clear ESOF flag in ISTR */ - __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ESOF); + __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ESOF); } } #endif /* USB */ @@ -810,9 +810,9 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) @verbatim =============================================================================== ##### Peripheral Control functions ##### - =============================================================================== + =============================================================================== [..] - This subsection provides a set of functions allowing to control the PCD data + This subsection provides a set of functions allowing to control the PCD data transfers. @endverbatim @@ -866,14 +866,14 @@ HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address) * @param hpcd: PCD handle * @param ep_addr: endpoint address * @param ep_mps: endpoint max packet size - * @param ep_type: endpoint type + * @param ep_type: endpoint type * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type) { HAL_StatusTypeDef ret = HAL_OK; PCD_EPTypeDef *ep = NULL; - + if ((ep_addr & 0x80) == 0x80) { ep = &hpcd->IN_ep[ep_addr & 0x7F]; @@ -883,11 +883,11 @@ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint ep = &hpcd->OUT_ep[ep_addr & 0x7F]; } ep->num = ep_addr & 0x7F; - + ep->is_in = (0x80 & ep_addr) != 0; ep->maxpacket = ep_mps; ep->type = ep_type; - + __HAL_LOCK(hpcd); USB_ActivateEndpoint(hpcd->Instance , ep); __HAL_UNLOCK(hpcd); @@ -901,9 +901,9 @@ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) -{ +{ PCD_EPTypeDef *ep = NULL; - + if ((ep_addr & 0x80) == 0x80) { ep = &hpcd->IN_ep[ep_addr & 0x7F]; @@ -913,9 +913,9 @@ HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) ep = &hpcd->OUT_ep[ep_addr & 0x7F]; } ep->num = ep_addr & 0x7F; - + ep->is_in = (0x80 & ep_addr) != 0; - + __HAL_LOCK(hpcd); USB_DeactivateEndpoint(hpcd->Instance , ep); __HAL_UNLOCK(hpcd); @@ -934,18 +934,18 @@ HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len) { PCD_EPTypeDef *ep = NULL; - + ep = &hpcd->OUT_ep[ep_addr & 0x7F]; - + /*setup and start the Xfer */ - ep->xfer_buff = pBuf; + ep->xfer_buff = pBuf; ep->xfer_len = len; ep->xfer_count = 0; ep->is_in = 0; ep->num = ep_addr & 0x7F; - + __HAL_LOCK(hpcd); - + if ((ep_addr & 0x7F) == 0 ) { USB_EP0StartXfer(hpcd->Instance , ep); @@ -955,7 +955,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, u USB_EPStartXfer(hpcd->Instance , ep); } __HAL_UNLOCK(hpcd); - + return HAL_OK; } @@ -980,18 +980,18 @@ uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len) { PCD_EPTypeDef *ep = NULL; - + ep = &hpcd->IN_ep[ep_addr & 0x7F]; - + /*setup and start the Xfer */ - ep->xfer_buff = pBuf; + ep->xfer_buff = pBuf; ep->xfer_len = len; ep->xfer_count = 0; ep->is_in = 1; ep->num = ep_addr & 0x7F; - + __HAL_LOCK(hpcd); - + if ((ep_addr & 0x7F) == 0 ) { USB_EP0StartXfer(hpcd->Instance , ep); @@ -1000,9 +1000,9 @@ HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, { USB_EPStartXfer(hpcd->Instance , ep); } - + __HAL_UNLOCK(hpcd); - + return HAL_OK; } @@ -1015,7 +1015,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { PCD_EPTypeDef *ep = NULL; - + if ((0x80 & ep_addr) == 0x80) { ep = &hpcd->IN_ep[ep_addr & 0x7F]; @@ -1024,19 +1024,19 @@ HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { ep = &hpcd->OUT_ep[ep_addr]; } - + ep->is_stall = 1; ep->num = ep_addr & 0x7F; ep->is_in = ((ep_addr & 0x80) == 0x80); - + __HAL_LOCK(hpcd); USB_EPSetStall(hpcd->Instance , ep); if((ep_addr & 0x7F) == 0) { USB_EP0_OutStart(hpcd->Instance, (uint8_t *)hpcd->Setup); } - __HAL_UNLOCK(hpcd); - + __HAL_UNLOCK(hpcd); + return HAL_OK; } @@ -1049,7 +1049,7 @@ HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { PCD_EPTypeDef *ep = NULL; - + if ((0x80 & ep_addr) == 0x80) { ep = &hpcd->IN_ep[ep_addr & 0x7F]; @@ -1058,15 +1058,15 @@ HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { ep = &hpcd->OUT_ep[ep_addr]; } - + ep->is_stall = 0; ep->num = ep_addr & 0x7F; ep->is_in = ((ep_addr & 0x80) == 0x80); - - __HAL_LOCK(hpcd); + + __HAL_LOCK(hpcd); USB_EPClearStall(hpcd->Instance , ep); - __HAL_UNLOCK(hpcd); - + __HAL_UNLOCK(hpcd); + return HAL_OK; } @@ -1079,7 +1079,7 @@ HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { __HAL_LOCK(hpcd); - + if ((ep_addr & 0x80) == 0x80) { USB_FlushTxFifo(hpcd->Instance, ep_addr & 0x7F); @@ -1088,9 +1088,9 @@ HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { USB_FlushRxFifo(hpcd->Instance); } - - __HAL_UNLOCK(hpcd); - + + __HAL_UNLOCK(hpcd); + return HAL_OK; } @@ -1116,8 +1116,8 @@ HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd) /** * @} */ - -/** @defgroup PCD_Exported_Functions_Group4 Peripheral State functions + +/** @defgroup PCD_Exported_Functions_Group4 Peripheral State functions * @brief Peripheral State functions * @verbatim @@ -1125,7 +1125,7 @@ HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd) ##### Peripheral State functions ##### =============================================================================== [..] - This subsection permits to get in run-time the status of the peripheral + This subsection permits to get in run-time the status of the peripheral and the data flow. @endverbatim @@ -1159,53 +1159,53 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd) * check FIFO for the next packet to be loaded * @param hpcd: PCD handle * @param epnum : endpoint number - * This parameter can be a value from 0 to 15 + * This parameter can be a value from 0 to 15 * @retval HAL status */ static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum) { - USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; USB_OTG_EPTypeDef *ep = NULL; int32_t len = 0; uint32_t len32b = 0; uint32_t fifoemptymsk = 0; - + ep = &hpcd->IN_ep[epnum]; len = ep->xfer_len - ep->xfer_count; - + if (len > ep->maxpacket) { len = ep->maxpacket; } - + len32b = (len + 3) / 4; - + while ((USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) > len32b && ep->xfer_count < ep->xfer_len && ep->xfer_len != 0) { /* Write the FIFO */ len = ep->xfer_len - ep->xfer_count; - + if (len > ep->maxpacket) { len = ep->maxpacket; } len32b = (len + 3) / 4; - + USB_WritePacket(USBx, ep->xfer_buff, epnum, len); - + ep->xfer_buff += len; ep->xfer_count += len; } - + if(len <= 0) { fifoemptymsk = 0x1 << epnum; USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk; - + } - + return HAL_OK; } #endif /* USB_OTG_FS */ @@ -1221,79 +1221,79 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) PCD_EPTypeDef *ep = NULL; uint16_t count = 0; uint8_t epindex = 0; - __IO uint16_t wIstr = 0; + __IO uint16_t wIstr = 0; __IO uint16_t wEPVal = 0; - + /* stay in loop while pending interrupts */ while (((wIstr = hpcd->Instance->ISTR) & USB_ISTR_CTR) != 0) { /* extract highest priority endpoint number */ epindex = (uint8_t)(wIstr & USB_ISTR_EP_ID); - + if (epindex == 0) { /* Decode and service control endpoint interrupt */ - - /* DIR bit = origin of the interrupt */ + + /* DIR bit = origin of the interrupt */ if ((wIstr & USB_ISTR_DIR) == 0) { /* DIR = 0 */ - + /* DIR = 0 => IN int */ /* DIR = 0 implies that (EP_CTR_TX = 1) always */ PCD_CLEAR_TX_EP_CTR(hpcd->Instance, PCD_ENDP0); ep = &hpcd->IN_ep[0]; - + ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num); ep->xfer_buff += ep->xfer_count; - + /* TX COMPLETE */ HAL_PCD_DataInStageCallback(hpcd, 0); - - + + if((hpcd->USB_Address > 0)&& ( ep->xfer_len == 0)) { hpcd->Instance->DADDR = (hpcd->USB_Address | USB_DADDR_EF); hpcd->USB_Address = 0; } - + } else { /* DIR = 1 */ - + /* DIR = 1 & CTR_RX => SETUP or OUT int */ /* DIR = 1 & (CTR_TX | CTR_RX) => 2 int pending */ ep = &hpcd->OUT_ep[0]; wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0); - + if ((wEPVal & USB_EP_SETUP) != 0) { /* Get SETUP Packet*/ ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); - USB_ReadPMA(hpcd->Instance, (uint8_t*)hpcd->Setup ,ep->pmaadress , ep->xfer_count); - /* SETUP bit kept frozen while CTR_RX = 1*/ - PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0); - + USB_ReadPMA(hpcd->Instance, (uint8_t*)hpcd->Setup ,ep->pmaadress , ep->xfer_count); + /* SETUP bit kept frozen while CTR_RX = 1*/ + PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0); + /* Process SETUP Packet*/ HAL_PCD_SetupStageCallback(hpcd); } - + else if ((wEPVal & USB_EP_CTR_RX) != 0) { PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0); /* Get Control Data OUT Packet*/ ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); - + if (ep->xfer_count != 0) { USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, ep->xfer_count); ep->xfer_buff+=ep->xfer_count; } - + /* Process Control Data OUT Packet*/ HAL_PCD_DataOutStageCallback(hpcd, 0); - + PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket); PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID); } @@ -1302,15 +1302,15 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) else { /* Decode and service non control endpoints interrupt */ - + /* process related endpoint register */ wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, epindex); if ((wEPVal & USB_EP_CTR_RX) != 0) - { + { /* clear int flag */ PCD_CLEAR_RX_EP_CTR(hpcd->Instance, epindex); ep = &hpcd->OUT_ep[epindex]; - + /* OUT double Buffering*/ if (ep->doublebuffer == 0) { @@ -1340,12 +1340,12 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count); } } - PCD_FreeUserBuffer(hpcd->Instance, ep->num, PCD_EP_DBUF_OUT); + PCD_FreeUserBuffer(hpcd->Instance, ep->num, PCD_EP_DBUF_OUT); } /*multi-packet on the NON control OUT endpoint*/ ep->xfer_count+=count; ep->xfer_buff+=count; - + if ((ep->xfer_len == 0) || (count < ep->maxpacket)) { /* RX COMPLETE */ @@ -1355,16 +1355,16 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) { HAL_PCD_EP_Receive(hpcd, ep->num, ep->xfer_buff, ep->xfer_len); } - + } /* if((wEPVal & EP_CTR_RX) */ - + if ((wEPVal & USB_EP_CTR_TX) != 0) { ep = &hpcd->IN_ep[epindex]; - + /* clear int flag */ PCD_CLEAR_TX_EP_CTR(hpcd->Instance, epindex); - + /* IN double Buffering*/ if (ep->doublebuffer == 0) { @@ -1394,12 +1394,12 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) USB_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, ep->xfer_count); } } - PCD_FreeUserBuffer(hpcd->Instance, ep->num, PCD_EP_DBUF_IN); + PCD_FreeUserBuffer(hpcd->Instance, ep->num, PCD_EP_DBUF_IN); } /*multi-packet on the NON control IN endpoint*/ ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num); ep->xfer_buff+=ep->xfer_count; - + /* Zero Length Packet? */ if (ep->xfer_len == 0) { @@ -1410,7 +1410,7 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) { HAL_PCD_EP_Transmit(hpcd, ep->num, ep->xfer_buff, ep->xfer_len); } - } + } } } return HAL_OK; @@ -1424,7 +1424,7 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) /** * @} */ - + #endif /* STM32F102x6 || STM32F102xB || */ /* STM32F103x6 || STM32F103xB || */ /* STM32F103xE || STM32F103xG || */ diff --git a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pcd_ex.c b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pcd_ex.c index b34328a..5f3002d 100644 --- a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pcd_ex.c +++ b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pcd_ex.c @@ -5,10 +5,10 @@ * @version V1.0.4 * @date 29-April-2016 * @brief Extended PCD HAL module driver. - * This file provides firmware functions to manage the following + * This file provides firmware functions to manage the following * functionalities of the USB Peripheral Controller: - * + Extended features functions: Update FIFO configuration, - * PMA configuration for EPs + * + Extended features functions: Update FIFO configuration, + * PMA configuration for EPs * ****************************************************************************** * @attention @@ -72,7 +72,7 @@ */ /** @defgroup PCDEx_Exported_Functions_Group1 Peripheral Control functions - * @brief PCDEx control functions + * @brief PCDEx control functions * @verbatim =============================================================================== @@ -98,19 +98,19 @@ HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uin { uint8_t index = 0; uint32_t Tx_Offset = 0; - + /* TXn min size = 16 words. (n : Transmit FIFO index) - When a TxFIFO is not used, the Configuration should be as follows: + When a TxFIFO is not used, the Configuration should be as follows: case 1 : n > m and Txn is not used (n,m : Transmit FIFO indexes) --> Txm can use the space allocated for Txn. case2 : n < m and Txn is not used (n,m : Transmit FIFO indexes) --> Txn should be configured with the minimum space of 16 words - The FIFO is used optimally when used TxFIFOs are allocated in the top + The FIFO is used optimally when used TxFIFOs are allocated in the top of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones. When DMA is used 3n * FIFO locations should be reserved for internal DMA registers */ - + Tx_Offset = hpcd->Instance->GRXFSIZ; - + if(fifo == 0) { hpcd->Instance->DIEPTXF0_HNPTXFSIZ = (size << 16) | Tx_Offset; @@ -122,12 +122,12 @@ HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uin { Tx_Offset += (hpcd->Instance->DIEPTXF[index] >> 16); } - + /* Multiply Tx_Size by 2 to get higher performance */ hpcd->Instance->DIEPTXF[fifo - 1] = (size << 16) | Tx_Offset; - + } - + return HAL_OK; } @@ -162,14 +162,14 @@ HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size) * @retval HAL status */ -HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, +HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr, uint16_t ep_kind, uint32_t pmaadress) { PCD_EPTypeDef *ep = NULL; - + /* initialize ep structure*/ if ((0x80 & ep_addr) == 0x80) { @@ -179,7 +179,7 @@ HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, { ep = &hpcd->OUT_ep[ep_addr]; } - + /* Here we check if the endpoint is single or double Buffer*/ if (ep_kind == PCD_SNG_BUF) { @@ -196,8 +196,8 @@ HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, ep->pmaaddr0 = pmaadress & 0xFFFF; ep->pmaaddr1 = (pmaadress & 0xFFFF0000) >> 16; } - - return HAL_OK; + + return HAL_OK; } #endif /* USB */ /** @@ -205,12 +205,12 @@ HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, */ /** @defgroup PCDEx_Exported_Functions_Group2 Peripheral State functions - * @brief Manage device connection state + * @brief Manage device connection state * @{ */ /** - * @brief Software Device Connection, - * this function is not required by USB OTG FS peripheral, it is used + * @brief Software Device Connection, + * this function is not required by USB OTG FS peripheral, it is used * only by USB Device FS peripheral. * @param hpcd: PCD handle * @param state: connection state (0 : disconnected / 1: connected) @@ -223,7 +223,7 @@ __weak void HAL_PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state) UNUSED(state); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_PCDEx_SetConnectionState could be implemented in the user file - */ + */ } /** * @} diff --git a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c index e178e42..bf00707 100644 --- a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c +++ b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c @@ -9,7 +9,7 @@ * This file provides firmware functions to manage the following * functionalities of the Power Controller (PWR) peripheral: * + Initialization/de-initialization functions - * + Peripheral Control functions + * + Peripheral Control functions * ****************************************************************************** * @attention @@ -61,10 +61,10 @@ /** @defgroup PWR_Private_Constants PWR Private Constants * @{ */ - + /** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask * @{ - */ + */ #define PVD_MODE_IT ((uint32_t)0x00010000) #define PVD_MODE_EVT ((uint32_t)0x00020000) #define PVD_RISING_EDGE ((uint32_t)0x00000001) @@ -76,7 +76,7 @@ /** @defgroup PWR_register_alias_address PWR Register alias address * @{ - */ + */ /* ------------- PWR registers bit address in the alias region ---------------*/ #define PWR_OFFSET (PWR_BASE - PERIPH_BASE) #define PWR_CR_OFFSET 0x00 @@ -86,10 +86,10 @@ /** * @} */ - + /** @defgroup PWR_CR_register_alias PWR CR Register alias address * @{ - */ + */ /* --- CR Register ---*/ /* Alias word address of LPSDSR bit */ #define LPSDSR_BIT_NUMBER POSITION_VAL(PWR_CR_LPDS) @@ -117,7 +117,7 @@ /** * @} */ - + /** * @} */ @@ -147,7 +147,7 @@ static void PWR_OverloadWfe(void) * @{ */ -/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions +/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions * @brief Initialization and de-initialization functions * @verbatim @@ -168,7 +168,7 @@ static void PWR_OverloadWfe(void) */ /** - * @brief Deinitializes the PWR peripheral registers to their default reset values. + * @brief Deinitializes the PWR peripheral registers to their default reset values. * @retval None */ void HAL_PWR_DeInit(void) @@ -207,14 +207,14 @@ void HAL_PWR_DisableBkUpAccess(void) * @} */ -/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions +/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions * @brief Low Power modes configuration functions * @verbatim =============================================================================== ##### Peripheral Control functions ##### =============================================================================== - + *** PVD configuration *** ========================= [..] @@ -241,12 +241,12 @@ void HAL_PWR_DisableBkUpAccess(void) ===================================== [..] The device features 3 low-power modes: - (+) Sleep mode: CPU clock off, all peripherals including Cortex-M3 core peripherals like + (+) Sleep mode: CPU clock off, all peripherals including Cortex-M3 core peripherals like NVIC, SysTick, etc. are kept running (+) Stop mode: All clocks are stopped (+) Standby mode: 1.8V domain powered off - - + + *** Sleep mode *** ================== [..] @@ -255,7 +255,7 @@ void HAL_PWR_DisableBkUpAccess(void) functions with (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction - + (+) Exit: (++) WFI entry mode, Any peripheral interrupt acknowledged by the nested vectored interrupt controller (NVIC) can wake up the device from Sleep mode. @@ -268,7 +268,7 @@ void HAL_PWR_DisableBkUpAccess(void) [..] The Stop mode is based on the Cortex-M3 deepsleep mode combined with peripheral clock gating. The voltage regulator can be configured either in normal or low-power mode. - In Stop mode, all clocks in the 1.8 V domain are stopped, the PLL, the HSI and the HSE RC + In Stop mode, all clocks in the 1.8 V domain are stopped, the PLL, the HSI and the HSE RC oscillators are disabled. SRAM and register contents are preserved. In Stop mode, all I/O pins keep the same state as in Run mode. @@ -287,27 +287,27 @@ void HAL_PWR_DisableBkUpAccess(void) ==================== [..] The Standby mode allows to achieve the lowest power consumption. It is based on the - Cortex-M3 deepsleep mode, with the voltage regulator disabled. The 1.8 V domain is - consequently powered off. The PLL, the HSI oscillator and the HSE oscillator are also - switched off. SRAM and register contents are lost except for registers in the Backup domain + Cortex-M3 deepsleep mode, with the voltage regulator disabled. The 1.8 V domain is + consequently powered off. The PLL, the HSI oscillator and the HSE oscillator are also + switched off. SRAM and register contents are lost except for registers in the Backup domain and Standby circuitry - + (+) Entry: (++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function. (+) Exit: - (++) WKUP pin rising edge, RTC alarm event rising edge, external Reset in + (++) WKUP pin rising edge, RTC alarm event rising edge, external Reset in NRSTpin, IWDG Reset *** Auto-wakeup (AWU) from low-power mode *** ============================================= [..] - - (+) The MCU can be woken up from low-power mode by an RTC Alarm event, + + (+) The MCU can be woken up from low-power mode by an RTC Alarm event, without depending on an external interrupt (Auto-wakeup mode). - + (+) RTC auto-wakeup (AWU) from the Stop and Standby modes - (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to + (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function. *** PWR Workarounds linked to Silicon Limitation *** @@ -316,8 +316,8 @@ void HAL_PWR_DisableBkUpAccess(void) Below the list of all silicon limitations known on STM32F1xx prouct. (#)Workarounds Implemented inside PWR HAL Driver - (##)Debugging Stop mode with WFE entry - overloaded the WFE by an internal function - + (##)Debugging Stop mode with WFE entry - overloaded the WFE by an internal function + @endverbatim * @{ */ @@ -339,11 +339,11 @@ void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD) /* Set PLS[7:5] bits according to PVDLevel value */ MODIFY_REG(PWR->CR, PWR_CR_PLS, sConfigPVD->PVDLevel); - + /* Clear any previous config. Keep it clear if no event or IT mode is selected */ __HAL_PWR_PVD_EXTI_DISABLE_EVENT(); __HAL_PWR_PVD_EXTI_DISABLE_IT(); - __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); + __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); /* Configure interrupt mode */ @@ -351,19 +351,19 @@ void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD) { __HAL_PWR_PVD_EXTI_ENABLE_IT(); } - + /* Configure event mode */ if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT) { __HAL_PWR_PVD_EXTI_ENABLE_EVENT(); } - + /* Configure the edge */ if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE) { __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); } - + if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE) { __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); @@ -425,7 +425,7 @@ void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx) * @note In Sleep mode, all I/O pins keep the same state as in Run mode. * @param Regulator: Regulator state as no effect in SLEEP mode - allows to support portability from legacy software * @param SLEEPEntry: Specifies if SLEEP mode is entered with WFI or WFE instruction. - * When WFI entry is used, tick interrupt have to be disabled if not desired as + * When WFI entry is used, tick interrupt have to be disabled if not desired as * the interrupt wake up source. * This parameter can be one of the following values: * @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction @@ -457,14 +457,14 @@ void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) } /** - * @brief Enters Stop mode. + * @brief Enters Stop mode. * @note In Stop mode, all I/O pins keep the same state as in Run mode. * @note When exiting Stop mode by using an interrupt or a wakeup event, * HSI RC oscillator is selected as system clock. * @note When the voltage regulator operates in low power mode, an additional - * startup delay is incurred when waking up from Stop mode. + * startup delay is incurred when waking up from Stop mode. * By keeping the internal regulator ON during Stop mode, the consumption - * is higher although the startup time is reduced. + * is higher although the startup time is reduced. * @param Regulator: Specifies the regulator state in Stop mode. * This parameter can be one of the following values: * @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON @@ -472,7 +472,7 @@ void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) * @param STOPEntry: Specifies if Stop mode in entered with WFI or WFE instruction. * This parameter can be one of the following values: * @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction - * @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction + * @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction * @retval None */ void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry) @@ -481,7 +481,7 @@ void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry) assert_param(IS_PWR_REGULATOR(Regulator)); assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); - /* Clear PDDS bit in PWR register to specify entering in STOP mode when CPU enter in Deepsleep */ + /* Clear PDDS bit in PWR register to specify entering in STOP mode when CPU enter in Deepsleep */ CLEAR_BIT(PWR->CR, PWR_CR_PDDS); /* Select the voltage regulator mode by setting LPDS bit in PWR register according to Regulator parameter value */ @@ -510,7 +510,7 @@ void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry) /** * @brief Enters Standby mode. * @note In Standby mode, all I/O pins are high impedance except for: - * - Reset pad (still available) + * - Reset pad (still available) * - TAMPER pin if configured for tamper or calibration out. * - WKUP pin (PA0) if enabled. * @retval None @@ -533,11 +533,11 @@ void HAL_PWR_EnterSTANDBYMode(void) /** - * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode. - * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor + * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode. + * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor * re-enters SLEEP mode when an interruption handling is over. * Setting this bit is useful when the processor is expected to run only on - * interruptions handling. + * interruptions handling. * @retval None */ void HAL_PWR_EnableSleepOnExit(void) @@ -548,9 +548,9 @@ void HAL_PWR_EnableSleepOnExit(void) /** - * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode. - * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor - * re-enters SLEEP mode when an interruption handling is over. + * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode. + * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor + * re-enters SLEEP mode when an interruption handling is over. * @retval None */ void HAL_PWR_DisableSleepOnExit(void) @@ -561,8 +561,8 @@ void HAL_PWR_DisableSleepOnExit(void) /** - * @brief Enables CORTEX M3 SEVONPEND bit. - * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes + * @brief Enables CORTEX M3 SEVONPEND bit. + * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes * WFE to wake up when an interrupt moves from inactive to pended. * @retval None */ @@ -574,9 +574,9 @@ void HAL_PWR_EnableSEVOnPend(void) /** - * @brief Disables CORTEX M3 SEVONPEND bit. - * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes - * WFE to wake up when an interrupt moves from inactive to pended. + * @brief Disables CORTEX M3 SEVONPEND bit. + * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes + * WFE to wake up when an interrupt moves from inactive to pended. * @retval None */ void HAL_PWR_DisableSEVOnPend(void) @@ -613,7 +613,7 @@ __weak void HAL_PWR_PVDCallback(void) { /* NOTE : This function Should not be modified, when the callback is needed, the HAL_PWR_PVDCallback could be implemented in the user file - */ + */ } /** diff --git a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c index a862695..e23f65c 100644 --- a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c +++ b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c @@ -5,18 +5,18 @@ * @version V1.0.4 * @date 29-April-2016 * @brief RCC HAL module driver. - * This file provides firmware functions to manage the following + * This file provides firmware functions to manage the following * functionalities of the Reset and Clock Control (RCC) peripheral: * + Initialization and de-initialization functions * + Peripheral Control functions - * - @verbatim + * + @verbatim ============================================================================== ##### RCC specific features ##### ============================================================================== - [..] + [..] After reset the device is running from Internal High Speed oscillator - (HSI 8MHz) with Flash 0 wait state, Flash prefetch buffer is enabled, + (HSI 8MHz) with Flash 0 wait state, Flash prefetch buffer is enabled, and all peripherals are off except internal SRAM, Flash and JTAG. (+) There is no prescaler on High speed (AHB) and Low speed (APB) buses; all peripherals mapped on these buses are running at HSI speed. @@ -26,22 +26,22 @@ [..] Once the device started from reset, the user application has to: (+) Configure the clock source to be used to drive the System clock (if the application needs higher frequency/performance) - (+) Configure the System clock frequency and Flash settings + (+) Configure the System clock frequency and Flash settings (+) Configure the AHB and APB buses prescalers (+) Enable the clock for the peripheral(s) to be used (+) Configure the clock source(s) for peripherals whose clocks are not - derived from the System clock (I2S, RTC, ADC, USB OTG FS) + derived from the System clock (I2S, RTC, ADC, USB OTG FS) ##### RCC Limitations ##### ============================================================================== - [..] - A delay between an RCC peripheral clock enable and the effective peripheral - enabling should be taken into account in order to manage the peripheral read/write + [..] + A delay between an RCC peripheral clock enable and the effective peripheral + enabling should be taken into account in order to manage the peripheral read/write from/to registers. (+) This delay depends on the peripheral mapping. (++) AHB & APB peripherals, 1 dummy read is necessary - [..] + [..] Workarounds: (#) For AHB & APB peripherals, a dummy read to the peripheral register has been inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro. @@ -74,9 +74,9 @@ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - ****************************************************************************** + ****************************************************************************** */ - + /* Includes ------------------------------------------------------------------*/ #include "stm32f1xx_hal.h" @@ -131,10 +131,10 @@ * @{ */ -/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions +/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions * - @verbatim + @verbatim =============================================================================== ##### Initialization and de-initialization functions ##### =============================================================================== @@ -152,19 +152,19 @@ (#) HSE (high-speed external), 4 to 24 MHz (STM32F100xx) or 4 to 16 MHz (STM32F101x/STM32F102x/STM32F103x) or 3 to 25 MHz (STM32F105x/STM32F107x) crystal oscillator used directly or through the PLL as System clock source. Can be used also as RTC clock source. - (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source. + (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source. (#) PLL (clocked by HSI or HSE), featuring different output clocks: (++) The first output is used to generate the high speed system clock (up to 72 MHz for STM32F10xxx or up to 24 MHz for STM32F100xx) (++) The second output is used to generate the clock for the USB OTG FS (48 MHz) (#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE() - and if a HSE clock failure occurs(HSE used directly or through PLL as System + and if a HSE clock failure occurs(HSE used directly or through PLL as System clock source), the System clocks automatically switched to HSI and an interrupt - is generated if enabled. The interrupt is linked to the Cortex-M3 NMI - (Non-Maskable Interrupt) exception vector. + is generated if enabled. The interrupt is linked to the Cortex-M3 NMI + (Non-Maskable Interrupt) exception vector. - (#) MCO1 (microcontroller clock output), used to output SYSCLK, HSI, + (#) MCO1 (microcontroller clock output), used to output SYSCLK, HSI, HSE or PLL clock (divided by 2) on PA8 pin + PLL2CLK, PLL3CLK/2, PLL3CLK and XTI for STM32F105x/STM32F107x [..] System, AHB and APB buses clocks configuration @@ -179,19 +179,19 @@ -@- All the peripheral clocks are derived from the System clock (SYSCLK) except: (+@) RTC: RTC clock can be derived either from the LSI, LSE or HSE clock - divided by 128. + divided by 128. (+@) USB OTG FS and RTC: USB OTG FS require a frequency equal to 48 MHz to work correctly. This clock is derived of the main PLL through PLL Multiplier. (+@) I2S interface on STM32F105x/STM32F107x can be derived from PLL3CLK (+@) IWDG clock which is always the LSI clock. (#) For STM32F10xxx, the maximum frequency of the SYSCLK and HCLK/PCLK2 is 72 MHz, PCLK1 36 MHz. - For STM32F100xx, the maximum frequency of the SYSCLK and HCLK/PCLK1/PCLK2 is 24 MHz. + For STM32F100xx, the maximum frequency of the SYSCLK and HCLK/PCLK1/PCLK2 is 24 MHz. Depending on the SYSCLK frequency, the flash latency should be adapted accordingly. @endverbatim * @{ */ - + /* Additional consideration on the SYSCLK based on Latency settings: +-----------------------------------------------+ @@ -225,16 +225,16 @@ void HAL_RCC_DeInit(void) /* Reset HSEON, CSSON, & PLLON bits */ CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON); - + /* Reset HSEBYP bit */ CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); - + /* Reset CFGR register */ CLEAR_REG(RCC->CFGR); - + /* Set HSITRIM bits to the reset value */ MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, ((uint32_t)0x10 << POSITION_VAL(RCC_CR_HSITRIM))); - + #if (defined(STM32F105xC) || defined(STM32F107xC) || defined (STM32F100xB) || defined (STM32F100xE)) /* Reset CFGR2 register */ CLEAR_REG(RCC->CFGR2); @@ -265,19 +265,19 @@ void HAL_RCC_DeInit(void) HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { uint32_t tickstart = 0; - + /* Check the parameters */ assert_param(RCC_OscInitStruct != NULL); assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); - - /*------------------------------- HSE Configuration ------------------------*/ + + /*------------------------------- HSE Configuration ------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); - + /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ - if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) + if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE))) { if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) @@ -289,14 +289,14 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); - + /* Check the HSE State */ if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF) { /* Get Start Tick */ tickstart = HAL_GetTick(); - + /* Wait till HSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) { @@ -310,7 +310,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { /* Get Start Tick */ tickstart = HAL_GetTick(); - + /* Wait till HSE is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) { @@ -322,15 +322,15 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) } } } - /*----------------------------- HSI Configuration --------------------------*/ + /*----------------------------- HSI Configuration --------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) { /* Check the parameters */ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); - - /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ - if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) + + /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ + if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2))) { /* When HSI is used as system clock it will not disabled */ @@ -352,10 +352,10 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { /* Enable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_ENABLE(); - + /* Get Start Tick */ tickstart = HAL_GetTick(); - + /* Wait till HSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) { @@ -364,7 +364,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) return HAL_TIMEOUT; } } - + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); } @@ -372,10 +372,10 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_DISABLE(); - + /* Get Start Tick */ tickstart = HAL_GetTick(); - + /* Wait till HSI is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) { @@ -387,22 +387,22 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) } } } - /*------------------------------ LSI Configuration -------------------------*/ + /*------------------------------ LSI Configuration -------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); - + /* Check the LSI State */ if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF) { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); - + /* Get Start Tick */ tickstart = HAL_GetTick(); - - /* Wait till LSI is ready */ + + /* Wait till LSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) { if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) @@ -410,7 +410,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) return HAL_TIMEOUT; } } - /* To have a fully stabilized clock in the specified range, a software delay of 1ms + /* To have a fully stabilized clock in the specified range, a software delay of 1ms should be added.*/ HAL_Delay(1); } @@ -418,11 +418,11 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); - + /* Get Start Tick */ tickstart = HAL_GetTick(); - - /* Wait till LSI is disabled */ + + /* Wait till LSI is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) { if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) @@ -432,7 +432,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) } } } - /*------------------------------ LSE Configuration -------------------------*/ + /*------------------------------ LSE Configuration -------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) { /* Check the parameters */ @@ -440,10 +440,10 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) /* Enable Power Clock*/ __HAL_RCC_PWR_CLK_ENABLE(); - + /* Enable write access to Backup domain */ SET_BIT(PWR->CR, PWR_CR_DBP); - + /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); @@ -462,8 +462,8 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { /* Get Start Tick */ tickstart = HAL_GetTick(); - - /* Wait till LSE is ready */ + + /* Wait till LSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) { if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) @@ -476,8 +476,8 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { /* Get Start Tick */ tickstart = HAL_GetTick(); - - /* Wait till LSE is disabled */ + + /* Wait till LSE is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) { if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) @@ -494,7 +494,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) assert_param(IS_RCC_PLL2(RCC_OscInitStruct->PLL2.PLL2State)); if ((RCC_OscInitStruct->PLL2.PLL2State) != RCC_PLL2_NONE) { - /* This bit can not be cleared if the PLL2 clock is used indirectly as system + /* This bit can not be cleared if the PLL2 clock is used indirectly as system clock (i.e. it is used as PLL clock entry that is used as system clock). */ if((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \ (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \ @@ -517,13 +517,13 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { return HAL_ERROR; } - + /* Disable the main PLL2. */ __HAL_RCC_PLL2_DISABLE(); - + /* Get Start Tick */ tickstart = HAL_GetTick(); - + /* Wait till PLL2 is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) { @@ -532,19 +532,19 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) return HAL_TIMEOUT; } } - + /* Configure the HSE prediv2 factor --------------------------------*/ __HAL_RCC_HSE_PREDIV2_CONFIG(RCC_OscInitStruct->PLL2.HSEPrediv2Value); /* Configure the main PLL2 multiplication factors. */ __HAL_RCC_PLL2_CONFIG(RCC_OscInitStruct->PLL2.PLL2MUL); - + /* Enable the main PLL2. */ __HAL_RCC_PLL2_ENABLE(); - + /* Get Start Tick */ tickstart = HAL_GetTick(); - + /* Wait till PLL2 is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == RESET) { @@ -561,11 +561,11 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) /* Disable the main PLL2. */ __HAL_RCC_PLL2_DISABLE(); - + /* Get Start Tick */ tickstart = HAL_GetTick(); - - /* Wait till PLL2 is disabled */ + + /* Wait till PLL2 is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) { if((HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE) @@ -585,19 +585,19 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { /* Check if the PLL is used as system clock or not */ if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) - { + { if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) { /* Check the parameters */ assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL)); - + /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); - + /* Get Start Tick */ tickstart = HAL_GetTick(); - + /* Wait till PLL is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) { @@ -615,7 +615,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) assert_param(IS_RCC_HSE_PREDIV(RCC_OscInitStruct->HSEPredivValue)); #if defined(RCC_CFGR2_PREDIV1SRC) assert_param(IS_RCC_PREDIV1_SOURCE(RCC_OscInitStruct->Prediv1Source)); - + /* Set PREDIV1 source */ SET_BIT(RCC->CFGR2, RCC_OscInitStruct->Prediv1Source); #endif /* RCC_CFGR2_PREDIV1SRC */ @@ -629,10 +629,10 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) RCC_OscInitStruct->PLL.PLLMUL); /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); - + /* Get Start Tick */ tickstart = HAL_GetTick(); - + /* Wait till PLL is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) { @@ -646,11 +646,11 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); - + /* Get Start Tick */ tickstart = HAL_GetTick(); - - /* Wait till PLL is disabled */ + + /* Wait till PLL is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) @@ -665,29 +665,29 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) return HAL_ERROR; } } - + return HAL_OK; } /** - * @brief Initializes the CPU, AHB and APB buses clocks according to the specified + * @brief Initializes the CPU, AHB and APB buses clocks according to the specified * parameters in the RCC_ClkInitStruct. * @param RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that * contains the configuration information for the RCC peripheral. - * @param FLatency FLASH Latency + * @param FLatency FLASH Latency * The value of this parameter depend on device used within the same series - * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency + * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency * and updated by @ref HAL_RCC_GetHCLKFreq() function called within this function * * @note The HSI is used (enabled by hardware) as system clock source after * start-up from Reset, wake-up from STOP and STANDBY mode, or in case * of failure of the HSE used directly or indirectly as system clock * (if the Clock Security System CSS is enabled). - * + * * @note A switch from one clock source to another occurs only if the target - * clock source is ready (clock stable after start-up delay or PLL locked). + * clock source is ready (clock stable after start-up delay or PLL locked). * If a clock source which is not yet ready is selected, the switch will - * occur when the clock source will be ready. + * occur when the clock source will be ready. * You can use @ref HAL_RCC_GetClockConfig() function to know which clock is * currently used as system clock source. * @retval HAL status @@ -695,23 +695,23 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { uint32_t tickstart = 0; - + /* Check the parameters */ assert_param(RCC_ClkInitStruct != NULL); assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType)); assert_param(IS_FLASH_LATENCY(FLatency)); - /* To correctly read data from FLASH memory, the number of wait states (LATENCY) - must be correctly programmed according to the frequency of the CPU clock + /* To correctly read data from FLASH memory, the number of wait states (LATENCY) + must be correctly programmed according to the frequency of the CPU clock (HCLK) of the device. */ #if defined(FLASH_ACR_LATENCY) /* Increasing the number of wait states because of higher CPU frequency */ if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY)) - { + { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); - + /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) @@ -728,15 +728,15 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); } - /*------------------------- SYSCLK Configuration ---------------------------*/ + /*------------------------- SYSCLK Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) - { + { assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); - + /* HSE is selected as System Clock Source */ if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) { - /* Check the HSE ready flag */ + /* Check the HSE ready flag */ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) { return HAL_ERROR; @@ -745,7 +745,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui /* PLL is selected as System Clock Source */ else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) { - /* Check the PLL ready flag */ + /* Check the PLL ready flag */ if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) { return HAL_ERROR; @@ -754,7 +754,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui /* HSI is selected as System Clock Source */ else { - /* Check the HSI ready flag */ + /* Check the HSI ready flag */ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) { return HAL_ERROR; @@ -764,7 +764,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui /* Get Start Tick */ tickstart = HAL_GetTick(); - + if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) { while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE) @@ -794,44 +794,44 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui return HAL_TIMEOUT; } } - } - } + } + } #if defined(FLASH_ACR_LATENCY) /* Decreasing the number of wait states because of lower CPU frequency */ if(FLatency < (FLASH->ACR & FLASH_ACR_LATENCY)) - { + { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); - + /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) { return HAL_ERROR; } - } + } #endif /* FLASH_ACR_LATENCY */ - /*-------------------------- PCLK1 Configuration ---------------------------*/ + /*-------------------------- PCLK1 Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); } - - /*-------------------------- PCLK2 Configuration ---------------------------*/ + + /*-------------------------- PCLK2 Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3)); } - + /* Update the SystemCoreClock global variable */ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_BITNUMBER]; /* Configure the source of time base considering new system clocks settings*/ HAL_InitTick (TICK_INT_PRIORITY); - + return HAL_OK; } @@ -842,12 +842,12 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui /** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions * @brief RCC clocks control functions * - @verbatim + @verbatim =============================================================================== ##### Peripheral Control functions ##### - =============================================================================== + =============================================================================== [..] - This subsection provides a set of functions allowing to control the RCC Clocks + This subsection provides a set of functions allowing to control the RCC Clocks frequencies. @endverbatim @@ -893,7 +893,7 @@ void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_M assert_param(IS_RCC_MCO(RCC_MCOx)); assert_param(IS_RCC_MCODIV(RCC_MCODiv)); assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource)); - + /* Configure the MCO1 pin in alternate function mode */ gpio.Mode = GPIO_MODE_AF_PP; gpio.Speed = GPIO_SPEED_FREQ_HIGH; @@ -902,9 +902,9 @@ void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_M /* MCO1 Clock Enable */ MCO1_CLK_ENABLE(); - + HAL_GPIO_Init(MCO1_GPIO_PORT, &gpio); - + /* Configure the MCO clock source */ __HAL_RCC_MCO1_CONFIG(RCC_MCOSource, RCC_MCODiv); } @@ -914,8 +914,8 @@ void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_M * @note If a failure is detected on the HSE oscillator clock, this oscillator * is automatically disabled and an interrupt is generated to inform the * software about the failure (Clock Security System Interrupt, CSSI), - * allowing the MCU to perform rescue operations. The CSSI is linked to - * the Cortex-M3 NMI (Non-Maskable Interrupt) exception vector. + * allowing the MCU to perform rescue operations. The CSSI is linked to + * the Cortex-M3 NMI (Non-Maskable Interrupt) exception vector. * @retval None */ void HAL_RCC_EnableCSS(void) @@ -933,9 +933,9 @@ void HAL_RCC_DisableCSS(void) } /** - * @brief Returns the SYSCLK frequency - * @note The system frequency computed by this function is not the real - * frequency in the chip. It is calculated based on the predefined + * @brief Returns the SYSCLK frequency + * @note The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined * constant and the selected clock source: * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*) * @note If SYSCLK source is HSE, function returns a value based on HSE_VALUE @@ -949,16 +949,16 @@ void HAL_RCC_DisableCSS(void) * 8 MHz), user has to ensure that HSE_VALUE is same as the real * frequency of the crystal used. Otherwise, this function may * have wrong result. - * + * * @note The result of this function could be not correct when using fractional * value for HSE crystal. - * - * @note This function can be used by the user application to compute the + * + * @note This function can be used by the user application to compute the * baud-rate for the communication peripherals or configure other parameters. - * + * * @note Each time SYSCLK changes, this function must be called to update the * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. - * + * * @retval SYSCLK frequency */ uint32_t HAL_RCC_GetSysClockFreq(void) @@ -980,9 +980,9 @@ uint32_t HAL_RCC_GetSysClockFreq(void) #if defined(RCC_CFGR2_PREDIV1SRC) uint32_t prediv2 = 0, pll2mul = 0; #endif /*RCC_CFGR2_PREDIV1SRC*/ - + tmpreg = RCC->CFGR; - + /* Get SYSCLK source -------------------------------------------------------*/ switch (tmpreg & RCC_CFGR_SWS) { @@ -1016,7 +1016,7 @@ uint32_t HAL_RCC_GetSysClockFreq(void) /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */ pllclk = (uint32_t)((HSE_VALUE / prediv) * pllmul); } - + /* If PLLMUL was set to 13 means that it was to cover the case PLLMUL 6.5 (avoid using float) */ /* In this case need to divide pllclk by 2 */ if (pllmul == aPLLMULFactorTable[(uint32_t)(RCC_CFGR_PLLMULL6_5) >> POSITION_VAL(RCC_CFGR_PLLMULL)]) @@ -1047,11 +1047,11 @@ uint32_t HAL_RCC_GetSysClockFreq(void) } /** - * @brief Returns the HCLK frequency + * @brief Returns the HCLK frequency * @note Each time HCLK changes, this function must be called to update the * right HCLK value. Otherwise, any configuration based on this function will be incorrect. - * - * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency + * + * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency * and updated within this function * @retval HCLK frequency */ @@ -1061,7 +1061,7 @@ uint32_t HAL_RCC_GetHCLKFreq(void) } /** - * @brief Returns the PCLK1 frequency + * @brief Returns the PCLK1 frequency * @note Each time PCLK1 changes, this function must be called to update the * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK1 frequency @@ -1070,10 +1070,10 @@ uint32_t HAL_RCC_GetPCLK1Freq(void) { /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_BITNUMBER]); -} +} /** - * @brief Returns the PCLK2 frequency + * @brief Returns the PCLK2 frequency * @note Each time PCLK2 changes, this function must be called to update the * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK2 frequency @@ -1082,12 +1082,12 @@ uint32_t HAL_RCC_GetPCLK2Freq(void) { /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_BITNUMBER]); -} +} /** - * @brief Configures the RCC_OscInitStruct according to the internal + * @brief Configures the RCC_OscInitStruct according to the internal * RCC configuration registers. - * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that + * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that * will be configured. * @retval None */ @@ -1129,9 +1129,9 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { RCC_OscInitStruct->HSIState = RCC_HSI_OFF; } - + RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR & RCC_CR_HSITRIM) >> POSITION_VAL(RCC_CR_HSITRIM)); - + /* Get the LSE configuration -----------------------------------------------*/ if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP) { @@ -1145,7 +1145,7 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { RCC_OscInitStruct->LSEState = RCC_LSE_OFF; } - + /* Get the LSI configuration -----------------------------------------------*/ if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION) { @@ -1155,7 +1155,7 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { RCC_OscInitStruct->LSIState = RCC_LSI_OFF; } - + /* Get the PLL configuration -----------------------------------------------*/ if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON) @@ -1184,9 +1184,9 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) } /** - * @brief Get the RCC_ClkInitStruct according to the internal + * @brief Get the RCC_ClkInitStruct according to the internal * RCC configuration registers. - * @param RCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that + * @param RCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that * contains the current clock configuration. * @param pFLatency Pointer on the Flash Latency. * @retval None @@ -1199,25 +1199,25 @@ void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pF /* Set all possible values for the Clock type parameter --------------------*/ RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; - - /* Get the SYSCLK configuration --------------------------------------------*/ + + /* Get the SYSCLK configuration --------------------------------------------*/ RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW); - - /* Get the HCLK configuration ----------------------------------------------*/ - RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE); - - /* Get the APB1 configuration ----------------------------------------------*/ - RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1); - - /* Get the APB2 configuration ----------------------------------------------*/ + + /* Get the HCLK configuration ----------------------------------------------*/ + RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE); + + /* Get the APB1 configuration ----------------------------------------------*/ + RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1); + + /* Get the APB2 configuration ----------------------------------------------*/ RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3); - + #if defined(FLASH_ACR_LATENCY) - /* Get the Flash Wait State (Latency) configuration ------------------------*/ - *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY); + /* Get the Flash Wait State (Latency) configuration ------------------------*/ + *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY); #else /* For VALUE lines devices, only LATENCY_0 can be set*/ - *pFLatency = (uint32_t)FLASH_LATENCY_0; + *pFLatency = (uint32_t)FLASH_LATENCY_0; #endif } @@ -1233,7 +1233,7 @@ void HAL_RCC_NMI_IRQHandler(void) { /* RCC Clock Security System interrupt user callback */ HAL_RCC_CSSCallback(); - + /* Clear RCC CSS pending bit */ __HAL_RCC_CLEAR_IT(RCC_IT_CSS); } @@ -1247,7 +1247,7 @@ __weak void HAL_RCC_CSSCallback(void) { /* NOTE : This function Should not be modified, when the callback is needed, the HAL_RCC_CSSCallback could be implemented in the user file - */ + */ } /** diff --git a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c index c0cc7d1..7f863f5 100644 --- a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c +++ b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c @@ -5,10 +5,10 @@ * @version V1.0.4 * @date 29-April-2016 * @brief Extended RCC HAL module driver. - * This file provides firmware functions to manage the following + * This file provides firmware functions to manage the following * functionalities RCC extension peripheral: * + Extended Peripheral Control functions - * + * ****************************************************************************** * @attention * @@ -36,8 +36,8 @@ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - ****************************************************************************** - */ + ****************************************************************************** + */ /* Includes ------------------------------------------------------------------*/ #include "stm32f1xx_hal.h" @@ -78,22 +78,22 @@ * @{ */ -/** @defgroup RCCEx_Exported_Functions_Group1 Peripheral Control functions - * @brief Extended Peripheral Control functions +/** @defgroup RCCEx_Exported_Functions_Group1 Peripheral Control functions + * @brief Extended Peripheral Control functions * -@verbatim +@verbatim =============================================================================== ##### Extended Peripheral Control functions ##### - =============================================================================== + =============================================================================== [..] - This subsection provides a set of functions allowing to control the RCC Clocks + This subsection provides a set of functions allowing to control the RCC Clocks frequencies. - [..] + [..] (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to - select the RTC clock source; in this case the Backup domain will be reset in - order to modify the RTC Clock source, as consequence RTC registers (including + select the RTC clock source; in this case the Backup domain will be reset in + order to modify the RTC Clock source, as consequence RTC registers (including the backup registers) are set to their reset values. - + @endverbatim * @{ */ @@ -104,12 +104,12 @@ * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that * contains the configuration information for the Extended Peripherals clocks(RTC clock). * - * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select - * the RTC clock source; in this case the Backup domain will be reset in - * order to modify the RTC Clock source, as consequence RTC registers (including + * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select + * the RTC clock source; in this case the Backup domain will be reset in + * order to modify the RTC Clock source, as consequence RTC registers (including * the backup registers) are set to their reset values. * - * @note In case of STM32F105xC or STM32F107xC devices, PLLI2S will be enabled if requested on + * @note In case of STM32F105xC or STM32F107xC devices, PLLI2S will be enabled if requested on * one of 2 I2S interfaces. When PLLI2S is enabled, you need to call HAL_RCCEx_DisablePLLI2S to * manually disable it. * @@ -124,8 +124,8 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); - - /*------------------------------- RTC/LCD Configuration ------------------------*/ + + /*------------------------------- RTC/LCD Configuration ------------------------*/ if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) { /* check for RTC Parameters used to output RTCCLK */ @@ -133,22 +133,22 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /* Enable Power Clock*/ __HAL_RCC_PWR_CLK_ENABLE(); - + /* Enable write access to Backup domain */ SET_BIT(PWR->CR, PWR_CR_DBP); - + /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); - + while((PWR->CR & PWR_CR_DBP) == RESET) { if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) { return HAL_TIMEOUT; - } + } } - - /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ + + /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL); if((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) { @@ -165,32 +165,32 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk { /* Get timeout */ tickstart = HAL_GetTick(); - - /* Wait till LSE is ready */ + + /* Wait till LSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) { if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) { return HAL_TIMEOUT; - } - } + } + } } } - __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); + __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); } - /*------------------------------ ADC clock Configuration ------------------*/ + /*------------------------------ ADC clock Configuration ------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) { /* Check the parameters */ assert_param(IS_RCC_ADCPLLCLK_DIV(PeriphClkInit->AdcClockSelection)); - + /* Configure the ADC clock source */ __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection); } #if defined(STM32F105xC) || defined(STM32F107xC) - /*------------------------------ I2S2 Configuration ------------------------*/ + /*------------------------------ I2S2 Configuration ------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) { /* Check the parameters */ @@ -200,17 +200,17 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk __HAL_RCC_I2S2_CONFIG(PeriphClkInit->I2s2ClockSelection); } - /*------------------------------ I2S3 Configuration ------------------------*/ + /*------------------------------ I2S3 Configuration ------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S3) == RCC_PERIPHCLK_I2S3) { /* Check the parameters */ assert_param(IS_RCC_I2S3CLKSOURCE(PeriphClkInit->I2s3ClockSelection)); - + /* Configure the I2S3 clock source */ __HAL_RCC_I2S3_CONFIG(PeriphClkInit->I2s3ClockSelection); } - /*------------------------------ PLL I2S Configuration ----------------------*/ + /*------------------------------ PLL I2S Configuration ----------------------*/ /* Check that PLLI2S need to be enabled */ if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_I2S2SRC) || HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_I2S3SRC)) { @@ -241,13 +241,13 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /* Configure the main PLLI2S multiplication factors. */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SMUL); - + /* Enable the main PLLI2S. */ __HAL_RCC_PLLI2S_ENABLE(); - + /* Get Start Tick*/ tickstart = HAL_GetTick(); - + /* Wait till PLLI2S is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) { @@ -271,12 +271,12 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ || defined(STM32F105xC) || defined(STM32F107xC) - /*------------------------------ USB clock Configuration ------------------*/ + /*------------------------------ USB clock Configuration ------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) { /* Check the parameters */ assert_param(IS_RCC_USBPLLCLK_DIV(PeriphClkInit->UsbClockSelection)); - + /* Configure the USB clock source */ __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection); } @@ -288,14 +288,14 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /** * @brief Get the PeriphClkInit according to the internal * RCC configuration registers. - * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that + * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that * returns the configuration information for the Extended Peripherals clocks(RTC, I2S, ADC clocks). * @retval None */ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { uint32_t srcclk = 0; - + /* Set all possible values for the extended clock type parameter------------*/ PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_RTC; @@ -410,17 +410,17 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClk)); - + switch (PeriphClk) { #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ || defined(STM32F105xC) || defined(STM32F107xC) - case RCC_PERIPHCLK_USB: + case RCC_PERIPHCLK_USB: { /* Get RCC configuration ------------------------------------------------------*/ temp_reg = RCC->CFGR; - + /* Check if PLL is enabled */ if (HAL_IS_BIT_SET(RCC->CR,RCC_CR_PLLON)) { @@ -448,7 +448,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */ pllclk = (uint32_t)((HSE_VALUE / prediv1) * pllmul); } - + /* If PLLMUL was set to 13 means that it was to cover the case PLLMUL 6.5 (avoid using float) */ /* In this case need to divide pllclk by 2 */ if (pllmul == aPLLMULFactorTable[(uint32_t)(RCC_CFGR_PLLMULL6_5) >> POSITION_VAL(RCC_CFGR_PLLMULL)]) @@ -474,12 +474,12 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /* USBCLK = PLLVCO = (2 x PLLCLK) / USB prescaler */ if (__HAL_RCC_GET_USB_SOURCE() == RCC_USBCLKSOURCE_PLL_DIV2) { - /* Prescaler of 2 selected for USB */ + /* Prescaler of 2 selected for USB */ frequency = pllclk; } else { - /* Prescaler of 3 selected for USB */ + /* Prescaler of 3 selected for USB */ frequency = (2 * pllclk) / 3; } #else @@ -491,7 +491,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) } else { - /* Prescaler of 1.5 selected for USB */ + /* Prescaler of 1.5 selected for USB */ frequency = (pllclk * 2) / 3; } #endif @@ -501,7 +501,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ #if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\ || defined(STM32F107xC) - case RCC_PERIPHCLK_I2S2: + case RCC_PERIPHCLK_I2S2: { #if defined(STM32F103xE) || defined(STM32F103xG) /* SYSCLK used as source clock for I2S2 */ @@ -552,7 +552,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) break; } #endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ - case RCC_PERIPHCLK_RTC: + case RCC_PERIPHCLK_RTC: { /* Get RCC BDCR configuration ------------------------------------------------------*/ temp_reg = RCC->BDCR; @@ -578,12 +578,12 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) } break; } - case RCC_PERIPHCLK_ADC: + case RCC_PERIPHCLK_ADC: { frequency = HAL_RCC_GetPCLK2Freq() / (((__HAL_RCC_GET_ADC_SOURCE() >> POSITION_VAL(RCC_CFGR_ADCPRE_DIV4)) + 1) * 2); break; } - default: + default: { break; } @@ -599,10 +599,10 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /** @defgroup RCCEx_Exported_Functions_Group2 PLLI2S Management function * @brief PLLI2S Management functions * -@verbatim +@verbatim =============================================================================== ##### Extended PLLI2S Management functions ##### - =============================================================================== + =============================================================================== [..] This subsection provides a set of functions allowing to control the PLLI2S activation or deactivation @@ -641,8 +641,8 @@ HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit) /* Get Start Tick*/ tickstart = HAL_GetTick(); - - /* Wait till PLLI2S is ready */ + + /* Wait till PLLI2S is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) { if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE) @@ -653,17 +653,17 @@ HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit) /* Configure the HSE prediv2 factor --------------------------------*/ __HAL_RCC_HSE_PREDIV2_CONFIG(PLLI2SInit->HSEPrediv2Value); - + /* Configure the main PLLI2S multiplication factors. */ __HAL_RCC_PLLI2S_CONFIG(PLLI2SInit->PLLI2SMUL); - + /* Enable the main PLLI2S. */ __HAL_RCC_PLLI2S_ENABLE(); - + /* Get Start Tick*/ tickstart = HAL_GetTick(); - + /* Wait till PLLI2S is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) { @@ -699,8 +699,8 @@ HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void) /* Get Start Tick*/ tickstart = HAL_GetTick(); - - /* Wait till PLLI2S is ready */ + + /* Wait till PLLI2S is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) { if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE) @@ -714,7 +714,7 @@ HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void) /* PLLI2S is currently used by I2S2 or I2S3. Cannot be disabled.*/ return HAL_ERROR; } - + return HAL_OK; } @@ -725,10 +725,10 @@ HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void) /** @defgroup RCCEx_Exported_Functions_Group3 PLL2 Management function * @brief PLL2 Management functions * -@verbatim +@verbatim =============================================================================== ##### Extended PLL2 Management functions ##### - =============================================================================== + =============================================================================== [..] This subsection provides a set of functions allowing to control the PLL2 activation or deactivation @@ -747,7 +747,7 @@ HAL_StatusTypeDef HAL_RCCEx_EnablePLL2(RCC_PLL2InitTypeDef *PLL2Init) { uint32_t tickstart = 0; - /* This bit can not be cleared if the PLL2 clock is used indirectly as system + /* This bit can not be cleared if the PLL2 clock is used indirectly as system clock (i.e. it is used as PLL clock entry that is used as system clock). */ if((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \ (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \ @@ -771,10 +771,10 @@ HAL_StatusTypeDef HAL_RCCEx_EnablePLL2(RCC_PLL2InitTypeDef *PLL2Init) /* Disable the main PLL2. */ __HAL_RCC_PLL2_DISABLE(); - + /* Get Start Tick*/ tickstart = HAL_GetTick(); - + /* Wait till PLL2 is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) { @@ -783,19 +783,19 @@ HAL_StatusTypeDef HAL_RCCEx_EnablePLL2(RCC_PLL2InitTypeDef *PLL2Init) return HAL_TIMEOUT; } } - + /* Configure the HSE prediv2 factor --------------------------------*/ __HAL_RCC_HSE_PREDIV2_CONFIG(PLL2Init->HSEPrediv2Value); /* Configure the main PLL2 multiplication factors. */ __HAL_RCC_PLL2_CONFIG(PLL2Init->PLL2MUL); - + /* Enable the main PLL2. */ __HAL_RCC_PLL2_ENABLE(); - + /* Get Start Tick*/ tickstart = HAL_GetTick(); - + /* Wait till PLL2 is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == RESET) { @@ -818,7 +818,7 @@ HAL_StatusTypeDef HAL_RCCEx_DisablePLL2(void) { uint32_t tickstart = 0; - /* This bit can not be cleared if the PLL2 clock is used indirectly as system + /* This bit can not be cleared if the PLL2 clock is used indirectly as system clock (i.e. it is used as PLL clock entry that is used as system clock). */ if((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \ (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \ @@ -833,8 +833,8 @@ HAL_StatusTypeDef HAL_RCCEx_DisablePLL2(void) /* Get Start Tick*/ tickstart = HAL_GetTick(); - - /* Wait till PLL2 is disabled */ + + /* Wait till PLL2 is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) { if((HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE) diff --git a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c index 938c948..f904f82 100644 --- a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c +++ b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c @@ -5,7 +5,7 @@ * @version V1.0.4 * @date 29-April-2016 * @brief TIM HAL module driver - * This file provides firmware functions to manage the following + * This file provides firmware functions to manage the following * functionalities of the Timer (TIM) peripheral: * + Time Base Initialization * + Time Base Start @@ -19,11 +19,11 @@ * + Time Input Capture Initialization * + Time Input Capture Channel Configuration * + Time Input Capture Start - * + Time Input Capture Start Interruption + * + Time Input Capture Start Interruption * + Time Input Capture Start DMA * + Time One Pulse Initialization * + Time One Pulse Channel Configuration - * + Time One Pulse Start + * + Time One Pulse Start * + Time Encoder Interface Initialization * + Time Encoder Interface Start * + Time Encoder Interface Start Interruption @@ -37,18 +37,18 @@ ============================================================================== [..] The Timer features include: (#) 16-bit up, down, up/down auto-reload counter. - (#) 16-bit programmable prescaler allowing dividing (also on the fly) the + (#) 16-bit programmable prescaler allowing dividing (also on the fly) the counter clock frequency either by any factor between 1 and 65536. (#) Up to 4 independent channels for: (++) Input Capture (++) Output Compare (++) PWM generation (Edge and Center-aligned Mode) - (++) One-pulse mode output + (++) One-pulse mode output ##### How to use this driver ##### ============================================================================== [..] - (#) Initialize the TIM low level resources by implementing the following functions + (#) Initialize the TIM low level resources by implementing the following functions depending from feature used : (++) Time Base : HAL_TIM_Base_MspInit() (++) Input Capture : HAL_TIM_IC_MspInit() @@ -64,21 +64,21 @@ __HAL_RCC_GPIOx_CLK_ENABLE(); (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init(); - (#) The external Clock can be configured, if needed (the default clock is the + (#) The external Clock can be configured, if needed (the default clock is the internal clock from the APBx), using the following function: - HAL_TIM_ConfigClockSource, the clock configuration should be done before + HAL_TIM_ConfigClockSource, the clock configuration should be done before any start function. - (#) Configure the TIM in the desired functioning mode using one of the + (#) Configure the TIM in the desired functioning mode using one of the Initialization function of this driver: (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base - (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an + (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an Output Compare signal. - (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a + (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a PWM signal. - (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an + (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an external signal. - (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer + (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer in One Pulse Mode. (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface. @@ -176,10 +176,10 @@ static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, * @{ */ -/** @defgroup TIM_Exported_Functions_Group1 Time Base functions - * @brief Time Base functions +/** @defgroup TIM_Exported_Functions_Group1 Time Base functions + * @brief Time Base functions * -@verbatim +@verbatim ============================================================================== ##### Time Base functions ##### ============================================================================== @@ -220,7 +220,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; - + /* Init the low level hardware : GPIO, CLOCK, NVIC */ HAL_TIM_Base_MspInit(htim); } @@ -238,7 +238,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) } /** - * @brief DeInitializes the TIM Base peripheral + * @brief DeInitializes the TIM Base peripheral * @param htim : TIM Base handle * @retval HAL status */ @@ -451,10 +451,10 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim) * @} */ -/** @defgroup TIM_Exported_Functions_Group2 Time Output Compare functions - * @brief Time Output Compare functions +/** @defgroup TIM_Exported_Functions_Group2 Time Output Compare functions + * @brief Time Output Compare functions * -@verbatim +@verbatim ============================================================================== ##### Time Output Compare functions ##### ============================================================================== @@ -495,7 +495,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim) { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; - + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_OC_MspInit(htim); } @@ -513,7 +513,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim) } /** - * @brief DeInitializes the TIM peripheral + * @brief DeInitializes the TIM peripheral * @param htim : TIM Output Compare handle * @retval HAL status */ @@ -569,13 +569,13 @@ __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM Output Compare signal generation. - * @param htim : TIM Output Compare handle + * @param htim : TIM Output Compare handle * @param Channel : TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) @@ -955,10 +955,10 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) * @} */ -/** @defgroup TIM_Exported_Functions_Group3 Time PWM functions - * @brief Time PWM functions +/** @defgroup TIM_Exported_Functions_Group3 Time PWM functions + * @brief Time PWM functions * -@verbatim +@verbatim ============================================================================== ##### Time PWM functions ##### ============================================================================== @@ -999,7 +999,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; - + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_PWM_MspInit(htim); } @@ -1017,7 +1017,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) } /** - * @brief DeInitializes the TIM peripheral + * @brief DeInitializes the TIM peripheral * @param htim : TIM handle * @retval HAL status */ @@ -1462,10 +1462,10 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel * @} */ -/** @defgroup TIM_Exported_Functions_Group4 Time Input Capture functions - * @brief Time Input Capture functions +/** @defgroup TIM_Exported_Functions_Group4 Time Input Capture functions + * @brief Time Input Capture functions * -@verbatim +@verbatim ============================================================================== ##### Time Input Capture functions ##### ============================================================================== @@ -1506,7 +1506,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; - + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_IC_MspInit(htim); } @@ -1524,7 +1524,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) } /** - * @brief DeInitializes the TIM peripheral + * @brief DeInitializes the TIM peripheral * @param htim : TIM Input Capture handle * @retval HAL status */ @@ -1931,10 +1931,10 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) * @} */ -/** @defgroup TIM_Exported_Functions_Group5 Time One Pulse functions - * @brief Time One Pulse functions +/** @defgroup TIM_Exported_Functions_Group5 Time One Pulse functions + * @brief Time One Pulse functions * -@verbatim +@verbatim ============================================================================== ##### Time One Pulse functions ##### ============================================================================== @@ -1980,7 +1980,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePul { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; - + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_OnePulse_MspInit(htim); } @@ -2004,7 +2004,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePul } /** - * @brief DeInitializes the TIM One Pulse + * @brief DeInitializes the TIM One Pulse * @param htim : TIM One Pulse handle * @retval HAL status */ @@ -2069,13 +2069,13 @@ __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim) */ HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { - /* Enable the Capture compare and the Input Capture channels + /* Enable the Capture compare and the Input Capture channels (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and - if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output - in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together + if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output + in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together - No need to enable the counter, it's enabled automatically by hardware + No need to enable the counter, it's enabled automatically by hardware (the counter starts in response to a stimulus and generate a pulse */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); @@ -2105,7 +2105,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t Output /* Disable the Capture compare and the Input Capture channels (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and - if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output + if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); @@ -2135,13 +2135,13 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t Output */ HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { - /* Enable the Capture compare and the Input Capture channels + /* Enable the Capture compare and the Input Capture channels (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and - if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output - in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together + if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output + in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together - No need to enable the counter, it's enabled automatically by hardware + No need to enable the counter, it's enabled automatically by hardware (the counter starts in response to a stimulus and generate a pulse */ /* Enable the TIM Capture/Compare 1 interrupt */ @@ -2180,10 +2180,10 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Out /* Disable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); - /* Disable the Capture compare and the Input Capture channels + /* Disable the Capture compare and the Input Capture channels (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and - if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output + if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); @@ -2205,10 +2205,10 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Out * @} */ -/** @defgroup TIM_Exported_Functions_Group6 Time Encoder functions - * @brief Time Encoder functions +/** @defgroup TIM_Exported_Functions_Group6 Time Encoder functions + * @brief Time Encoder functions * -@verbatim +@verbatim ============================================================================== ##### Time Encoder functions ##### ============================================================================== @@ -2260,7 +2260,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_Ini { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; - + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_Encoder_MspInit(htim); } @@ -2318,7 +2318,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_Ini /** - * @brief DeInitializes the TIM Encoder interface + * @brief DeInitializes the TIM Encoder interface * @param htim : TIM Encoder handle * @retval HAL status */ @@ -2731,10 +2731,10 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Cha /** * @} */ -/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management - * @brief IRQ handler management +/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management + * @brief IRQ handler management * -@verbatim +@verbatim ============================================================================== ##### IRQ handler management ##### ============================================================================== @@ -2881,9 +2881,9 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) */ /** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions - * @brief Peripheral Control functions + * @brief Peripheral Control functions * -@verbatim +@verbatim ============================================================================== ##### Peripheral Control functions ##### ============================================================================== @@ -2909,7 +2909,7 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel) @@ -2978,7 +2978,7 @@ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitT * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel) @@ -3276,11 +3276,11 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O } /** - * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral + * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral * @param htim : TIM handle * @param BurstBaseAddress : TIM Base address from where the DMA will start the Data write * This parameter can be one of the following values: - * @arg TIM_DMABASE_CR1 + * @arg TIM_DMABASE_CR1 * @arg TIM_DMABASE_CR2 * @arg TIM_DMABASE_SMCR * @arg TIM_DMABASE_DIER @@ -3289,13 +3289,13 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O * @arg TIM_DMABASE_CCMR1 * @arg TIM_DMABASE_CCMR2 * @arg TIM_DMABASE_CCER - * @arg TIM_DMABASE_CNT - * @arg TIM_DMABASE_PSC + * @arg TIM_DMABASE_CNT + * @arg TIM_DMABASE_PSC * @arg TIM_DMABASE_ARR * @arg TIM_DMABASE_RCR * @arg TIM_DMABASE_CCR1 * @arg TIM_DMABASE_CCR2 - * @arg TIM_DMABASE_CCR3 + * @arg TIM_DMABASE_CCR3 * @arg TIM_DMABASE_CCR4 * @arg TIM_DMABASE_BDTR * @arg TIM_DMABASE_DCR @@ -3439,7 +3439,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t } /** - * @brief Stops the TIM DMA Burst mode + * @brief Stops the TIM DMA Burst mode * @param htim : TIM handle * @param BurstRequestSrc : TIM DMA Request sources to disable * @retval HAL status @@ -3499,11 +3499,11 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t B } /** - * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory + * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory * @param htim : TIM handle * @param BurstBaseAddress : TIM Base address from where the DMA will starts the Data read * This parameter can be one of the following values: - * @arg TIM_DMABASE_CR1 + * @arg TIM_DMABASE_CR1 * @arg TIM_DMABASE_CR2 * @arg TIM_DMABASE_SMCR * @arg TIM_DMABASE_DIER @@ -3512,13 +3512,13 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t B * @arg TIM_DMABASE_CCMR1 * @arg TIM_DMABASE_CCMR2 * @arg TIM_DMABASE_CCER - * @arg TIM_DMABASE_CNT - * @arg TIM_DMABASE_PSC + * @arg TIM_DMABASE_CNT + * @arg TIM_DMABASE_PSC * @arg TIM_DMABASE_ARR * @arg TIM_DMABASE_RCR * @arg TIM_DMABASE_CCR1 * @arg TIM_DMABASE_CCR2 - * @arg TIM_DMABASE_CCR3 + * @arg TIM_DMABASE_CCR3 * @arg TIM_DMABASE_CCR4 * @arg TIM_DMABASE_BDTR * @arg TIM_DMABASE_DCR @@ -3663,7 +3663,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B } /** - * @brief Stop the DMA burst reading + * @brief Stop the DMA burst reading * @param htim : TIM handle * @param BurstRequestSrc : TIM DMA Request sources to disable. * @retval HAL status @@ -3732,7 +3732,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t Bu * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source - * @arg TIM_EVENTSOURCE_COM: Timer COM event source + * @arg TIM_EVENTSOURCE_COM: Timer COM event source * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source * @note TIM6 and TIM7 can only generate an update event. @@ -3776,7 +3776,7 @@ HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventS * @arg TIM_CHANNEL_3: TIM Channel 3 * @arg TIM_CHANNEL_4: TIM Channel 4 * @retval HAL status - */ + */ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel) { uint32_t tmpsmcr = 0; @@ -3901,7 +3901,7 @@ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInp * @param sClockSourceConfig : pointer to a TIM_ClockConfigTypeDef structure that * contains the clock source information for the TIM peripheral. * @retval HAL status - */ + */ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig) { uint32_t tmpsmcr = 0; @@ -3939,7 +3939,7 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); - + /* Configure the ETR Clock source */ TIM_ETR_SetConfig(htim->Instance, sClockSourceConfig->ClockPrescaler, @@ -3965,7 +3965,7 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); - + /* Configure the ETR Clock source */ TIM_ETR_SetConfig(htim->Instance, sClockSourceConfig->ClockPrescaler, @@ -3984,7 +3984,7 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo /* Check TI1 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); - + TIM_TI1_ConfigInputStage(htim->Instance, sClockSourceConfig->ClockPolarity, sClockSourceConfig->ClockFilter); @@ -4104,7 +4104,7 @@ HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_S * @param htim : TIM handle. * @param sSlaveConfig : pointer to a TIM_SlaveConfigTypeDef structure that * contains the selected trigger (internal trigger input, filtered - * timer input or external trigger input) and the ) and the Slave + * timer input or external trigger input) and the ) and the Slave * mode (Disable, Reset, Gated, Trigger, External clock mode 1). * @retval HAL status */ @@ -4139,7 +4139,7 @@ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TI * @param htim: TIM handle. * @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that * contains the selected trigger (internal trigger input, filtered - * timer input or external trigger input) and the ) and the Slave + * timer input or external trigger input) and the ) and the Slave * mode (Disable, Reset, Gated, Trigger, External clock mode 1). * @retval HAL status */ @@ -4245,9 +4245,9 @@ uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel) */ /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions - * @brief TIM Callbacks functions + * @brief TIM Callbacks functions * -@verbatim +@verbatim ============================================================================== ##### TIM Callbacks functions ##### ============================================================================== @@ -4264,7 +4264,7 @@ uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel) */ /** - * @brief Period elapsed callback in non blocking mode + * @brief Period elapsed callback in non blocking mode * @param htim : TIM handle * @retval None */ @@ -4278,7 +4278,7 @@ __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) } /** - * @brief Output Compare callback in non blocking mode + * @brief Output Compare callback in non blocking mode * @param htim : TIM OC handle * @retval None */ @@ -4291,7 +4291,7 @@ __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) */ } /** - * @brief Input Capture callback in non blocking mode + * @brief Input Capture callback in non blocking mode * @param htim : TIM IC handle * @retval None */ @@ -4305,7 +4305,7 @@ __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) } /** - * @brief PWM Pulse finished callback in non blocking mode + * @brief PWM Pulse finished callback in non blocking mode * @param htim : TIM handle * @retval None */ @@ -4319,7 +4319,7 @@ __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) } /** - * @brief Hall Trigger detection callback in non blocking mode + * @brief Hall Trigger detection callback in non blocking mode * @param htim : TIM handle * @retval None */ @@ -4333,7 +4333,7 @@ __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) } /** - * @brief Timer error callback in non blocking mode + * @brief Timer error callback in non blocking mode * @param htim : TIM handle * @retval None */ @@ -4350,15 +4350,15 @@ __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim) * @} */ -/** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions - * @brief Peripheral State functions +/** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions + * @brief Peripheral State functions * -@verbatim +@verbatim ============================================================================== ##### Peripheral State functions ##### ============================================================================== [..] - This subsection permit to get in run-time the status of the peripheral + This subsection permit to get in run-time the status of the peripheral and the data flow. @endverbatim @@ -4438,7 +4438,7 @@ HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim) */ /** - * @brief TIM DMA error callback + * @brief TIM DMA error callback * @param hdma : pointer to DMA handle. * @retval None */ @@ -4584,7 +4584,7 @@ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) TIMx->RCR = Structure->RepetitionCounter; } - /* Generate an update event to reload the Prescaler + /* Generate an update event to reload the Prescaler and the repetition counter(only for TIM1 and TIM8) value immediatly */ TIMx->EGR = TIM_EGR_UG; } @@ -5019,8 +5019,8 @@ static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, * @param TIM_ICFilter : Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None - * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1 - * (on channel2 path) is used as the input signal. Therefore CCMR1 must be + * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1 + * (on channel2 path) is used as the input signal. Therefore CCMR1 must be * protected against un-initialized filter and polarity values. */ void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, @@ -5063,9 +5063,9 @@ void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ * @param TIMx to select the TIM peripheral. * @param TIM_ICPolarity : The Input Polarity. * This parameter can be one of the following values: - * @arg TIM_ICPOLARITY_RISING - * @arg TIM_ICPOLARITY_FALLING - * @arg TIM_ICPOLARITY_BOTHEDGE + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE * @param TIM_ICFilter : Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None @@ -5098,9 +5098,9 @@ static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, * @param TIMx to select the TIM peripheral * @param TIM_ICPolarity : The Input Polarity. * This parameter can be one of the following values: - * @arg TIM_ICPOLARITY_RISING - * @arg TIM_ICPOLARITY_FALLING - * @arg TIM_ICPOLARITY_BOTHEDGE + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE * @param TIM_ICSelection : specifies the input to be used. * This parameter can be one of the following values: * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2. @@ -5109,8 +5109,8 @@ static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, * @param TIM_ICFilter : Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None - * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2 - * (on channel1 path) is used as the input signal. Therefore CCMR1 must be + * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2 + * (on channel1 path) is used as the input signal. Therefore CCMR1 must be * protected against un-initialized filter and polarity values. */ static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, @@ -5146,8 +5146,8 @@ static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 * @param TIMx to select the TIM peripheral. * @param TIM_ICPolarity : The Input Polarity. * This parameter can be one of the following values: - * @arg TIM_ICPOLARITY_RISING - * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING * @arg TIM_ICPOLARITY_BOTHEDGE * @param TIM_ICFilter : Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. @@ -5181,8 +5181,8 @@ static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, * @param TIMx to select the TIM peripheral * @param TIM_ICPolarity : The Input Polarity. * This parameter can be one of the following values: - * @arg TIM_ICPOLARITY_RISING - * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING * @arg TIM_ICPOLARITY_BOTHEDGE * @param TIM_ICSelection : specifies the input to be used. * This parameter can be one of the following values: @@ -5192,8 +5192,8 @@ static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, * @param TIM_ICFilter : Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None - * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4 - * (on channel1 path) is used as the input signal. Therefore CCMR2 must be + * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4 + * (on channel1 path) is used as the input signal. Therefore CCMR2 must be * protected against un-initialized filter and polarity values. */ static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, @@ -5229,8 +5229,8 @@ static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 * @param TIMx to select the TIM peripheral * @param TIM_ICPolarity : The Input Polarity. * This parameter can be one of the following values: - * @arg TIM_ICPOLARITY_RISING - * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING * @arg TIM_ICPOLARITY_BOTHEDGE * @param TIM_ICSelection : specifies the input to be used. * This parameter can be one of the following values: @@ -5239,8 +5239,8 @@ static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 * @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC. * @param TIM_ICFilter : Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. - * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3 - * (on channel1 path) is used as the input signal. Therefore CCMR2 must be + * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3 + * (on channel1 path) is used as the input signal. Therefore CCMR2 must be * protected against un-initialized filter and polarity values. * @retval None */ diff --git a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c index 416dad8..75d4584 100644 --- a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c +++ b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c @@ -185,7 +185,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSen { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; - + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIMEx_HallSensor_MspInit(htim); } diff --git a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_usb.c b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_usb.c index 24f343d..1b673cd 100644 --- a/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_usb.c +++ b/stm32cubemx/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_usb.c @@ -6,11 +6,11 @@ * @date 29-April-2016 * @brief USB Low Layer HAL module driver. * - * This file provides firmware functions to manage the following + * This file provides firmware functions to manage the following * functionalities of the USB Peripheral Controller: * + Initialization/de-initialization functions * + I/O operation functions - * + Peripheral Control functions + * + Peripheral Control functions * + Peripheral State functions * @verbatim @@ -19,7 +19,7 @@ ============================================================================== [..] (#) Fill parameters of Init structure in USB_OTG_CfgTypeDef structure. - + (#) Call USB_CoreInit() API to initialize the USB Core peripheral. (#) The upper HAL HCD/PCD driver will call the right routines for its internal processes. @@ -53,7 +53,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Includes ------------------------------------------------------------------*/ #include "stm32f1xx_hal.h" @@ -73,7 +73,7 @@ defined(STM32F103x6) || defined(STM32F103xB) || \ defined(STM32F103xE) || defined(STM32F103xG) || \ defined(STM32F105xC) || defined(STM32F107xC) - + /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ @@ -100,17 +100,17 @@ static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx); @verbatim =============================================================================== ##### Peripheral Control functions ##### - =============================================================================== + =============================================================================== [..] - This subsection provides a set of functions allowing to control the PCD data + This subsection provides a set of functions allowing to control the PCD data transfers. - + @endverbatim * @{ */ - + /*============================================================================== - USB OTG FS peripheral available on STM32F105xx and STM32F107xx devices + USB OTG FS peripheral available on STM32F105xx and STM32F107xx devices ==============================================================================*/ #if defined (USB_OTG_FS) @@ -125,13 +125,13 @@ HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c { /* Select FS Embedded PHY */ USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL; - + /* Reset after a PHY select and set Host mode */ USB_CoreReset(USBx); - + /* Deactivate the power down*/ USBx->GCCFG = USB_OTG_GCCFG_PWRDWN; - + return HAL_OK; } @@ -166,28 +166,28 @@ HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx) * This parameter can be one of the these values: * @arg USB_DEVICE_MODE: Peripheral mode mode * @arg USB_HOST_MODE: Host mode - * @arg USB_DRD_MODE: Dual Role Device mode + * @arg USB_DRD_MODE: Dual Role Device mode * @retval HAL status */ HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx , USB_ModeTypeDef mode) { - USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD); - + USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD); + if ( mode == USB_HOST_MODE) { USBx->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD; } else if ( mode == USB_DEVICE_MODE) { - USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD; + USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD; } HAL_Delay(50); - + return HAL_OK; } /** - * @brief USB_DevInit : Initializes the USB_OTG controller registers + * @brief USB_DevInit : Initializes the USB_OTG controller registers * for device mode * @param USBx : Selected device * @param cfg : pointer to a USB_OTG_CfgTypeDef structure that contains @@ -197,34 +197,34 @@ HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx , USB_ModeTypeD HAL_StatusTypeDef USB_DevInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) { uint32_t index = 0; - + for (index = 0; index < 15 ; index++) { USBx->DIEPTXF[index] = 0; } - + /*Activate VBUS Sensing B */ USBx->GCCFG |= USB_OTG_GCCFG_VBUSBSEN; /* Restart the Phy Clock */ USBx_PCGCCTL = 0; - + /* Device mode configuration */ USBx_DEVICE->DCFG |= DCFG_FRAME_INTERVAL_80; - + /* Set Full speed phy */ USB_SetDevSpeed (USBx , USB_OTG_SPEED_FULL); - + /* Flush the FIFOs */ USB_FlushTxFifo(USBx , 0x10); /* all Tx FIFOs */ USB_FlushRxFifo(USBx); - + /* Clear all pending Device Interrupts */ USBx_DEVICE->DIEPMSK = 0; USBx_DEVICE->DOEPMSK = 0; USBx_DEVICE->DAINT = 0xFFFFFFFF; USBx_DEVICE->DAINTMSK = 0; - + for (index = 0; index < cfg.dev_endpoints; index++) { if ((USBx_INEP(index)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) @@ -235,11 +235,11 @@ HAL_StatusTypeDef USB_DevInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c { USBx_INEP(index)->DIEPCTL = 0; } - + USBx_INEP(index)->DIEPTSIZ = 0; USBx_INEP(index)->DIEPINT = 0xFF; } - + for (index = 0; index < cfg.dev_endpoints; index++) { if ((USBx_OUTEP(index)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) @@ -250,38 +250,38 @@ HAL_StatusTypeDef USB_DevInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c { USBx_OUTEP(index)->DOEPCTL = 0; } - + USBx_OUTEP(index)->DOEPTSIZ = 0; USBx_OUTEP(index)->DOEPINT = 0xFF; } - + USBx_DEVICE->DIEPMSK &= ~(USB_OTG_DIEPMSK_TXFURM); - + /* Disable all interrupts. */ USBx->GINTMSK = 0; - + /* Clear any pending interrupts */ USBx->GINTSTS = 0xBFFFFFFF; - + /* Enable the common interrupts */ USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM; - + /* Enable interrupts matching to the Device mode ONLY */ USBx->GINTMSK |= (USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_USBRST |\ USB_OTG_GINTMSK_ENUMDNEM | USB_OTG_GINTMSK_IEPINT |\ USB_OTG_GINTMSK_OEPINT | USB_OTG_GINTMSK_IISOIXFRM|\ USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM); - + if(cfg.Sof_enable) { USBx->GINTMSK |= USB_OTG_GINTMSK_SOFM; } - + if (cfg.vbus_sensing_enable == ENABLE) { - USBx->GINTMSK |= (USB_OTG_GINTMSK_SRQIM | USB_OTG_GINTMSK_OTGINT); + USBx->GINTMSK |= (USB_OTG_GINTMSK_SRQIM | USB_OTG_GINTMSK_OTGINT); } - + return HAL_OK; } @@ -296,9 +296,9 @@ HAL_StatusTypeDef USB_DevInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c HAL_StatusTypeDef USB_FlushTxFifo (USB_OTG_GlobalTypeDef *USBx, uint32_t num ) { uint32_t count = 0; - - USBx->GRSTCTL = ( USB_OTG_GRSTCTL_TXFFLSH |(uint32_t)( num << 6)); - + + USBx->GRSTCTL = ( USB_OTG_GRSTCTL_TXFFLSH |(uint32_t)( num << 6)); + do { if (++count > 200000) @@ -307,7 +307,7 @@ HAL_StatusTypeDef USB_FlushTxFifo (USB_OTG_GlobalTypeDef *USBx, uint32_t num ) } } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH); - + return HAL_OK; } @@ -319,9 +319,9 @@ HAL_StatusTypeDef USB_FlushTxFifo (USB_OTG_GlobalTypeDef *USBx, uint32_t num ) HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx) { uint32_t count = 0; - + USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH; - + do { if (++count > 200000) @@ -330,12 +330,12 @@ HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx) } } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH); - + return HAL_OK; } /** - * @brief USB_SetDevSpeed :Initializes the DevSpd field of DCFG register + * @brief USB_SetDevSpeed :Initializes the DevSpd field of DCFG register * depending the PHY type and the enumeration speed of the device. * @param USBx : Selected device * @param speed : device speed @@ -351,7 +351,7 @@ HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx , uint8_t speed) } /** - * @brief USB_GetDevSpeed :Return the Dev Speed + * @brief USB_GetDevSpeed :Return the Dev Speed * @param USBx : Selected device * @retval speed : device speed * This parameter can be one of the these values: @@ -361,7 +361,7 @@ HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx , uint8_t speed) uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx) { uint8_t speed = 0; - + if (((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ)|| ((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_FS_PHY_48MHZ)) { @@ -371,7 +371,7 @@ uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx) { speed = USB_OTG_SPEED_LOW; } - + return speed; } @@ -393,28 +393,28 @@ HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTy { ep->data_pid_start = 0; } - + if (ep->is_in == 1) { USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num))); - + if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_USBAEP) == 0) { USBx_INEP(ep->num)->DIEPCTL |= ((ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ ) | (ep->type << 18 ) |\ - ((ep->num) << 22 ) | (USB_OTG_DIEPCTL_SD0PID_SEVNFRM) | (USB_OTG_DIEPCTL_USBAEP)); + ((ep->num) << 22 ) | (USB_OTG_DIEPCTL_SD0PID_SEVNFRM) | (USB_OTG_DIEPCTL_USBAEP)); } } else { USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16); - + if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0) { USBx_OUTEP(ep->num)->DOEPCTL |= ((ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ ) | (ep->type << 18 ) |\ (USB_OTG_DIEPCTL_SD0PID_SEVNFRM)| (USB_OTG_DOEPCTL_USBAEP)); } } - + return HAL_OK; } @@ -451,16 +451,16 @@ HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EP HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep) { uint16_t pktcnt = 0; - + /* IN endpoint */ if (ep->is_in == 1) { /* Zero Length Packet? */ if (ep->xfer_len == 0) { - USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); + USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1 << 19)) ; - USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); + USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); } else { @@ -470,17 +470,17 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDe * exist ? 1 : 0) */ USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); - USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); + USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (((ep->xfer_len + ep->maxpacket -1)/ ep->maxpacket) << 19)) ; - USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); - + USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); + if (ep->type == EP_TYPE_ISOC) { - USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT); - USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & (1 << 29)); + USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT); + USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & (1 << 29)); } } - + if (ep->type != EP_TYPE_ISOC) { /* Enable the Tx FIFO Empty Interrupt for this EP */ @@ -489,7 +489,7 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDe USBx_DEVICE->DIEPEMPMSK |= 1 << ep->num; } } - + if (ep->type == EP_TYPE_ISOC) { if ((USBx_DEVICE->DSTS & ( 1 << 8 )) == 0) @@ -500,11 +500,11 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDe { USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; } - } - + } + /* EP enable, IN data in FIFO */ USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); - + if (ep->type == EP_TYPE_ISOC) { USB_WritePacket(USBx, ep->xfer_buff, ep->num, ep->xfer_len); @@ -516,9 +516,9 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDe * pktcnt = N * xfersize = N * maxpacket */ - USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ); - USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT); - + USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ); + USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT); + if (ep->xfer_len == 0) { USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->maxpacket); @@ -530,7 +530,7 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDe USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (pktcnt << 19)); USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket * pktcnt)); } - + if (ep->type == EP_TYPE_ISOC) { if ((USBx_DEVICE->DSTS & ( 1 << 8 )) == 0) @@ -545,7 +545,7 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDe /* EP enable */ USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA); } - + return HAL_OK; } @@ -576,7 +576,7 @@ HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeD */ USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); - + if(ep->xfer_len > ep->maxpacket) { ep->xfer_len = ep->maxpacket; @@ -584,15 +584,15 @@ HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeD USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1 << 19)); USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); } - + /* Enable the Tx FIFO Empty Interrupt for this EP */ if (ep->xfer_len > 0) { USBx_DEVICE->DIEPEMPMSK |= 1 << (ep->num); } - + /* EP enable, IN data in FIFO */ - USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); + USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); } else /* OUT endpoint */ { @@ -602,24 +602,24 @@ HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeD */ USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ); USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT); - + if (ep->xfer_len > 0) { ep->xfer_len = ep->maxpacket; } - + USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1 << 19)); USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket)); - + /* EP enable */ USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA); } - + return HAL_OK; } /** - * @brief USB_WritePacket : Writes a packet into the Tx FIFO associated + * @brief USB_WritePacket : Writes a packet into the Tx FIFO associated * with the EP/channel * @param USBx : Selected device * @param src : pointer to source buffer @@ -630,7 +630,7 @@ HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeD HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len) { uint32_t count32b = 0 , index = 0; - + count32b = (len + 3) / 4; for (index = 0; index < count32b; index++, src += 4) { @@ -640,7 +640,7 @@ HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uin } /** - * @brief USB_ReadPacket : read a packet from the Tx FIFO associated + * @brief USB_ReadPacket : read a packet from the Tx FIFO associated * with the EP/channel * @param USBx : Selected device * @param dest : destination pointer @@ -651,11 +651,11 @@ void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len) { uint32_t index = 0; uint32_t count32b = (len + 3) / 4; - + for ( index = 0; index < count32b; index++, dest += 4 ) { *(__packed uint32_t *)dest = USBx_DFIFO(0); - + } return ((void *)dest); } @@ -663,7 +663,7 @@ void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len) /** * @brief USB_EPSetStall : set a stall condition over an EP * @param USBx : Selected device - * @param ep: pointer to endpoint structure + * @param ep: pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep) @@ -673,7 +673,7 @@ HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == 0) { USBx_INEP(ep->num)->DIEPCTL &= ~(USB_OTG_DIEPCTL_EPDIS); - } + } USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_STALL; } else @@ -681,7 +681,7 @@ HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) == 0) { USBx_OUTEP(ep->num)->DOEPCTL &= ~(USB_OTG_DOEPCTL_EPDIS); - } + } USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_STALL; } return HAL_OK; @@ -722,7 +722,7 @@ HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDe HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx) { uint32_t index = 0; - + /* Clear Pending interrupt */ for (index = 0; index < 15 ; index++) { @@ -730,16 +730,16 @@ HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx) USBx_OUTEP(index)->DOEPINT = 0xFF; } USBx_DEVICE->DAINT = 0xFFFFFFFF; - + /* Clear interrupt masks */ USBx_DEVICE->DIEPMSK = 0; USBx_DEVICE->DOEPMSK = 0; USBx_DEVICE->DAINTMSK = 0; - + /* Flush the FIFO */ USB_FlushRxFifo(USBx); USB_FlushTxFifo(USBx , 0x10 ); - + return HAL_OK; } @@ -754,7 +754,7 @@ HAL_StatusTypeDef USB_SetDevAddress (USB_OTG_GlobalTypeDef *USBx, uint8_t addre { USBx_DEVICE->DCFG &= ~ (USB_OTG_DCFG_DAD); USBx_DEVICE->DCFG |= (address << 4) & USB_OTG_DCFG_DAD; - + return HAL_OK; } @@ -767,7 +767,7 @@ HAL_StatusTypeDef USB_DevConnect (USB_OTG_GlobalTypeDef *USBx) { USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_SDIS ; HAL_Delay(3); - + return HAL_OK; } @@ -780,7 +780,7 @@ HAL_StatusTypeDef USB_DevDisconnect (USB_OTG_GlobalTypeDef *USBx) { USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS; HAL_Delay(3); - + return HAL_OK; } @@ -792,7 +792,7 @@ HAL_StatusTypeDef USB_DevDisconnect (USB_OTG_GlobalTypeDef *USBx) uint32_t USB_ReadInterrupts (USB_OTG_GlobalTypeDef *USBx) { uint32_t tmpreg = 0; - + tmpreg = USBx->GINTSTS; tmpreg &= USBx->GINTMSK; return tmpreg; @@ -849,7 +849,7 @@ uint32_t USB_ReadDevOutEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum) uint32_t USB_ReadDevInEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum) { uint32_t tmpreg = 0, msk = 0, emp = 0; - + msk = USBx_DEVICE->DIEPMSK; emp = USBx_DEVICE->DIEPEMPMSK; msk |= ((emp >> epnum) & 0x1) << 7; @@ -873,7 +873,7 @@ void USB_ClearInterrupts (USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt) * @param USBx : Selected device * @retval return core mode : Host or Device * This parameter can be one of the these values: - * 0 : Host + * 0 : Host * 1 : Device */ uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx) @@ -890,13 +890,13 @@ HAL_StatusTypeDef USB_ActivateSetup (USB_OTG_GlobalTypeDef *USBx) { /* Set the MPS of the IN EP based on the enumeration speed */ USBx_INEP(0)->DIEPCTL &= ~USB_OTG_DIEPCTL_MPSIZ; - + if((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_LS_PHY_6MHZ) { USBx_INEP(0)->DIEPCTL |= 3; } USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGINAK; - + return HAL_OK; } @@ -912,13 +912,13 @@ HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t *psetup) USBx_OUTEP(0)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1 << 19)); USBx_OUTEP(0)->DOEPTSIZ |= (3 * 8); USBx_OUTEP(0)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_STUPCNT; - + return HAL_OK; } /** - * @brief USB_HostInit : Initializes the USB OTG controller registers - * for Host mode + * @brief USB_HostInit : Initializes the USB OTG controller registers + * for Host mode * @param USBx : Selected device * @param cfg : pointer to a USB_OTG_CfgTypeDef structure that contains * the configuration information for the specified USBx peripheral. @@ -927,81 +927,81 @@ HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t *psetup) HAL_StatusTypeDef USB_HostInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) { uint32_t index = 0; - + /* Restart the Phy Clock */ USBx_PCGCCTL = 0; - + /* no VBUS sensing*/ USBx->GCCFG &=~ (USB_OTG_GCCFG_VBUSASEN); USBx->GCCFG &=~ (USB_OTG_GCCFG_VBUSBSEN); - + /* Disable the FS/LS support mode only */ if((cfg.speed == USB_OTG_SPEED_FULL)&& (USBx != USB_OTG_FS)) { - USBx_HOST->HCFG |= USB_OTG_HCFG_FSLSS; + USBx_HOST->HCFG |= USB_OTG_HCFG_FSLSS; } else { - USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSS); + USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSS); } - + /* Make sure the FIFOs are flushed. */ USB_FlushTxFifo(USBx, 0x10 ); /* all Tx FIFOs */ USB_FlushRxFifo(USBx); - + /* Clear all pending HC Interrupts */ for (index = 0; index < cfg.Host_channels; index++) { USBx_HC(index)->HCINT = 0xFFFFFFFF; USBx_HC(index)->HCINTMSK = 0; } - + /* Enable VBUS driving */ USB_DriveVbus(USBx, 1); - + HAL_Delay(200); - + /* Disable all interrupts. */ USBx->GINTMSK = 0; - + /* Clear any pending interrupts */ USBx->GINTSTS = 0xFFFFFFFF; - + if(USBx == USB_OTG_FS) { /* set Rx FIFO size */ - USBx->GRXFSIZ = (uint32_t )0x80; + USBx->GRXFSIZ = (uint32_t )0x80; USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t )(((0x60 << 16)& USB_OTG_NPTXFD) | 0x80); USBx->HPTXFSIZ = (uint32_t )(((0x40 << 16)& USB_OTG_HPTXFSIZ_PTXFD) | 0xE0); } - + /* Enable the common interrupts */ USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM; - + /* Enable interrupts matching to the Host mode ONLY */ USBx->GINTMSK |= (USB_OTG_GINTMSK_PRTIM | USB_OTG_GINTMSK_HCIM |\ USB_OTG_GINTMSK_SOFM |USB_OTG_GINTSTS_DISCINT|\ USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM); - + return HAL_OK; } /** - * @brief USB_InitFSLSPClkSel : Initializes the FSLSPClkSel field of the + * @brief USB_InitFSLSPClkSel : Initializes the FSLSPClkSel field of the * HCFG register on the PHY type and set the right frame interval * @param USBx : Selected device * @param freq : clock frequency * This parameter can be one of the these values: - * HCFG_48_MHZ : Full Speed 48 MHz Clock - * HCFG_6_MHZ : Low Speed 6 MHz Clock + * HCFG_48_MHZ : Full Speed 48 MHz Clock + * HCFG_6_MHZ : Low Speed 6 MHz Clock * @retval HAL status */ HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx , uint8_t freq) { USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSPCS); USBx_HOST->HCFG |= (freq & USB_OTG_HCFG_FSLSPCS); - + if (freq == HCFG_48_MHZ) { USBx_HOST->HFIR = (uint32_t)48000; @@ -1023,15 +1023,15 @@ HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx , uint8_t freq HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx) { __IO uint32_t hprt0 = 0; - + hprt0 = USBx_HPRT0; - + hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\ USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG ); - - USBx_HPRT0 = (USB_OTG_HPRT_PRST | hprt0); + + USBx_HPRT0 = (USB_OTG_HPRT_PRST | hprt0); HAL_Delay (10); /* See Note #1 */ - USBx_HPRT0 = ((~USB_OTG_HPRT_PRST) & hprt0); + USBx_HPRT0 = ((~USB_OTG_HPRT_PRST) & hprt0); return HAL_OK; } @@ -1039,18 +1039,18 @@ HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx) * @brief USB_DriveVbus : activate or de-activate vbus * @param state : VBUS state * This parameter can be one of the these values: - * 0 : VBUS Active + * 0 : VBUS Active * 1 : VBUS Inactive * @retval HAL status */ HAL_StatusTypeDef USB_DriveVbus (USB_OTG_GlobalTypeDef *USBx, uint8_t state) { __IO uint32_t hprt0 = 0; - + hprt0 = USBx_HPRT0; hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\ USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG ); - + if (((hprt0 & USB_OTG_HPRT_PPWR) == 0 ) && (state == 1 )) { USBx_HPRT0 = (USB_OTG_HPRT_PPWR | hprt0); @@ -1073,7 +1073,7 @@ HAL_StatusTypeDef USB_DriveVbus (USB_OTG_GlobalTypeDef *USBx, uint8_t state) uint32_t USB_GetHostSpeed (USB_OTG_GlobalTypeDef *USBx) { __IO uint32_t hprt0 = 0; - + hprt0 = USBx_HPRT0; return ((hprt0 & USB_OTG_HPRT_PSPD) >> 17); } @@ -1111,7 +1111,7 @@ uint32_t USB_GetCurrentFrame (USB_OTG_GlobalTypeDef *USBx) * This parameter can be a value from 0 to32K * @retval HAL state */ -HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, +HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num, uint8_t epnum, uint8_t dev_address, @@ -1121,9 +1121,9 @@ HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, { /* Clear old interrupt conditions for this host channel. */ USBx_HC(ch_num)->HCINT = 0xFFFFFFFF; - + /* Enable channel interrupts required for this transfer. */ - switch (ep_type) + switch (ep_type) { case EP_TYPE_CTRL: case EP_TYPE_BULK: @@ -1133,13 +1133,13 @@ HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCINTMSK_DTERRM |\ USB_OTG_HCINTMSK_AHBERR |\ USB_OTG_HCINTMSK_NAKM ; - - if (epnum & 0x80) + + if (epnum & 0x80) { USBx_HC(ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM; } break; - + case EP_TYPE_INTR: USBx_HC(ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM |\ USB_OTG_HCINTMSK_STALLM |\ @@ -1148,33 +1148,33 @@ HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCINTMSK_NAKM |\ USB_OTG_HCINTMSK_AHBERR |\ USB_OTG_HCINTMSK_FRMORM ; - - if (epnum & 0x80) + + if (epnum & 0x80) { USBx_HC(ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM; } - + break; - + case EP_TYPE_ISOC: USBx_HC(ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM |\ USB_OTG_HCINTMSK_ACKM |\ USB_OTG_HCINTMSK_AHBERR |\ USB_OTG_HCINTMSK_FRMORM ; - - if (epnum & 0x80) + + if (epnum & 0x80) { USBx_HC(ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_TXERRM | USB_OTG_HCINTMSK_BBERRM); } break; } - + /* Enable the top level host channel interrupt. */ USBx_HOST->HAINTMSK |= (1 << ch_num); - + /* Make sure host channel interrupts are enabled. */ USBx->GINTMSK |= USB_OTG_GINTMSK_HCIM; - + /* Program the HCCHAR register */ USBx_HC(ch_num)->HCCHAR = (((dev_address << 22) & USB_OTG_HCCHAR_DAD) |\ (((epnum & 0x7F)<< 11) & USB_OTG_HCCHAR_EPNUM)|\ @@ -1182,12 +1182,12 @@ HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, (((speed == HPRT0_PRTSPD_LOW_SPEED)<< 17) & USB_OTG_HCCHAR_LSDEV)|\ ((ep_type << 18) & USB_OTG_HCCHAR_EPTYP)|\ (mps & USB_OTG_HCCHAR_MPSIZ)); - + if (ep_type == EP_TYPE_INTR) { USBx_HC(ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM ; } - + return HAL_OK; } @@ -1209,12 +1209,12 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDe uint16_t num_packets = 0; uint16_t max_hc_pkt_count = 256; uint32_t tmpreg = 0; - + /* Compute the expected number of packets associated to the transfer */ if (hc->xfer_len > 0) { num_packets = (hc->xfer_len + hc->max_packet - 1) / hc->max_packet; - + if (num_packets > max_hc_pkt_count) { num_packets = max_hc_pkt_count; @@ -1229,31 +1229,31 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDe { hc->xfer_len = num_packets * hc->max_packet; } - + /* Initialize the HCTSIZn register */ USBx_HC(hc->ch_num)->HCTSIZ = (((hc->xfer_len) & USB_OTG_HCTSIZ_XFRSIZ)) |\ ((num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) |\ (((hc->data_pid) << 29) & USB_OTG_HCTSIZ_DPID); - + is_oddframe = (USBx_HOST->HFNUM & 0x01) ? 0 : 1; USBx_HC(hc->ch_num)->HCCHAR &= ~USB_OTG_HCCHAR_ODDFRM; USBx_HC(hc->ch_num)->HCCHAR |= (is_oddframe << 29); - + /* Set host channel enable */ tmpreg = USBx_HC(hc->ch_num)->HCCHAR; tmpreg &= ~USB_OTG_HCCHAR_CHDIS; tmpreg |= USB_OTG_HCCHAR_CHENA; USBx_HC(hc->ch_num)->HCCHAR = tmpreg; - + if((hc->ep_is_in == 0) && (hc->xfer_len > 0)) { - switch(hc->ep_type) + switch(hc->ep_type) { /* Non periodic transfer */ case EP_TYPE_CTRL: case EP_TYPE_BULK: len_words = (hc->xfer_len + 3) / 4; - + /* check if there is enough space in FIFO space */ if(len_words > (USBx->HNPTXSTS & 0xFFFF)) { @@ -1261,7 +1261,7 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDe USBx->GINTMSK |= USB_OTG_GINTMSK_NPTXFEM; } break; - + /* Periodic transfer */ case EP_TYPE_INTR: case EP_TYPE_ISOC: @@ -1270,18 +1270,18 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDe if(len_words > (USBx_HOST->HPTXSTS & 0xFFFF)) /* split the transfer */ { /* need to process data in ptxfempty interrupt */ - USBx->GINTMSK |= USB_OTG_GINTMSK_PTXFEM; + USBx->GINTMSK |= USB_OTG_GINTMSK_PTXFEM; } break; - + default: break; } - + /* Write packet into the Tx FIFO. */ USB_WritePacket(USBx, hc->xfer_buff, hc->ch_num, hc->xfer_len); } - + return HAL_OK; } @@ -1305,12 +1305,12 @@ uint32_t USB_HC_ReadInterrupt (USB_OTG_GlobalTypeDef *USBx) HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx , uint8_t hc_num) { uint32_t count = 0; - + /* Check for space in the request queue to issue the halt. */ if (((USBx_HC(hc_num)->HCCHAR) & (HCCHAR_CTRL << 18)) || ((USBx_HC(hc_num)->HCCHAR) & (HCCHAR_BULK << 18))) { USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHDIS; - + if ((USBx->HNPTXSTS & 0xFFFF) == 0) { USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA; @@ -1322,7 +1322,7 @@ HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx , uint8_t hc_num) { break; } - } + } while ((USBx_HC(hc_num)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); } else @@ -1333,7 +1333,7 @@ HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx , uint8_t hc_num) else { USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHDIS; - + if ((USBx_HOST->HPTXSTS & 0xFFFF) == 0) { USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA; @@ -1345,15 +1345,15 @@ HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx , uint8_t hc_num) { break; } - } + } while ((USBx_HC(hc_num)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); } else { - USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA; + USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA; } } - + return HAL_OK; } @@ -1368,17 +1368,17 @@ HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx , uint8_t ch_num) { uint8_t num_packets = 1; uint32_t tmpreg = 0; - + USBx_HC(ch_num)->HCTSIZ = ((num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) |\ USB_OTG_HCTSIZ_DOPING; - + /* Set host channel enable */ tmpreg = USBx_HC(ch_num)->HCCHAR; tmpreg &= ~USB_OTG_HCCHAR_CHDIS; tmpreg |= USB_OTG_HCCHAR_CHENA; USBx_HC(ch_num)->HCCHAR = tmpreg; - - return HAL_OK; + + return HAL_OK; } /** @@ -1391,13 +1391,13 @@ HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx) uint8_t index; uint32_t count = 0; uint32_t value = 0; - + USB_DisableGlobalInt(USBx); - + /* Flush FIFO */ USB_FlushTxFifo(USBx, 0x10); USB_FlushRxFifo(USBx); - + /* Flush out any leftover queued requests. */ for (index = 0; index <= 15; index++) { @@ -1407,7 +1407,7 @@ HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx) value &= ~USB_OTG_HCCHAR_EPDIR; USBx_HC(index)->HCCHAR = value; } - + /* Halt all channels to put them into a known state. */ for (index = 0; index <= 15; index++) { @@ -1416,7 +1416,7 @@ HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx) value |= USB_OTG_HCCHAR_CHENA; value &= ~USB_OTG_HCCHAR_EPDIR; USBx_HC(index)->HCCHAR = value; - + do { if (++count > 1000) @@ -1426,12 +1426,12 @@ HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx) } while ((USBx_HC(index)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); } - + /* Clear any pending Host interrupts */ USBx_HOST->HAINT = 0xFFFFFFFF; USBx->GINTSTS = 0xFFFFFFFF; USB_EnableGlobalInt(USBx); - + return HAL_OK; } @@ -1465,7 +1465,7 @@ HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx) #endif /* USB_OTG_FS */ /*============================================================================== - USB Device FS peripheral available on STM32F102xx and STM32F103xx devices + USB Device FS peripheral available on STM32F102xx and STM32F103xx devices ==============================================================================*/ #if defined (USB) /** @@ -1477,7 +1477,7 @@ HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx) */ HAL_StatusTypeDef USB_CoreInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg) { - /* NOTE : - This function is not required by USB Device FS peripheral, it is used + /* NOTE : - This function is not required by USB Device FS peripheral, it is used only by USB OTG FS peripheral. - This function is added to ensure compatibility across platforms. */ @@ -1493,14 +1493,14 @@ HAL_StatusTypeDef USB_CoreInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg) HAL_StatusTypeDef USB_EnableGlobalInt(USB_TypeDef *USBx) { uint32_t winterruptmask = 0; - + /* Set winterruptmask variable */ winterruptmask = USB_CNTR_CTRM | USB_CNTR_WKUPM | USB_CNTR_SUSPM | USB_CNTR_ERRM \ | USB_CNTR_ESOFM | USB_CNTR_RESETM; - + /* Set interrupt mask */ USBx->CNTR |= winterruptmask; - + return HAL_OK; } @@ -1513,14 +1513,14 @@ HAL_StatusTypeDef USB_EnableGlobalInt(USB_TypeDef *USBx) HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx) { uint32_t winterruptmask = 0; - + /* Set winterruptmask variable */ winterruptmask = USB_CNTR_CTRM | USB_CNTR_WKUPM | USB_CNTR_SUSPM | USB_CNTR_ERRM \ | USB_CNTR_ESOFM | USB_CNTR_RESETM; - + /* Clear interrupt mask */ USBx->CNTR &= ~winterruptmask; - + return HAL_OK; } @@ -1534,7 +1534,7 @@ HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx) */ HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx , USB_ModeTypeDef mode) { - /* NOTE : - This function is not required by USB Device FS peripheral, it is used + /* NOTE : - This function is not required by USB Device FS peripheral, it is used only by USB OTG FS peripheral. - This function is added to ensure compatibility across platforms. */ @@ -1542,7 +1542,7 @@ HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx , USB_ModeTypeDef mode) } /** - * @brief USB_DevInit : Initializes the USB controller registers + * @brief USB_DevInit : Initializes the USB controller registers * for device mode * @param USBx : Selected device * @param cfg : pointer to a USB_CfgTypeDef structure that contains @@ -1550,20 +1550,20 @@ HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx , USB_ModeTypeDef mode) * @retval HAL status */ HAL_StatusTypeDef USB_DevInit (USB_TypeDef *USBx, USB_CfgTypeDef cfg) -{ +{ /* Init Device */ /*CNTR_FRES = 1*/ USBx->CNTR = USB_CNTR_FRES; - + /*CNTR_FRES = 0*/ USBx->CNTR = 0; - + /*Clear pending interrupts*/ USBx->ISTR = 0; - + /*Set Btable Address*/ USBx->BTABLE = BTABLE_ADDRESS; - + return HAL_OK; } @@ -1577,7 +1577,7 @@ HAL_StatusTypeDef USB_DevInit (USB_TypeDef *USBx, USB_CfgTypeDef cfg) */ HAL_StatusTypeDef USB_FlushTxFifo (USB_TypeDef *USBx, uint32_t num ) { - /* NOTE : - This function is not required by USB Device FS peripheral, it is used + /* NOTE : - This function is not required by USB Device FS peripheral, it is used only by USB OTG FS peripheral. - This function is added to ensure compatibility across platforms. */ @@ -1591,7 +1591,7 @@ HAL_StatusTypeDef USB_FlushTxFifo (USB_TypeDef *USBx, uint32_t num ) */ HAL_StatusTypeDef USB_FlushRxFifo(USB_TypeDef *USBx) { - /* NOTE : - This function is not required by USB Device FS peripheral, it is used + /* NOTE : - This function is not required by USB Device FS peripheral, it is used only by USB OTG FS peripheral. - This function is added to ensure compatibility across platforms. */ @@ -1623,11 +1623,11 @@ HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep) break; default: break; - } - + } + PCD_SET_EP_ADDRESS(USBx, ep->num, ep->num); - - if (ep->doublebuffer == 0) + + if (ep->doublebuffer == 0) { if (ep->is_in) { @@ -1635,7 +1635,7 @@ HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep) PCD_SET_EP_TX_ADDRESS(USBx, ep->num, ep->pmaadress); PCD_CLEAR_TX_DTOG(USBx, ep->num); /* Configure NAK status for the Endpoint*/ - PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK); + PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK); } else { @@ -1655,16 +1655,16 @@ HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep) PCD_SET_EP_DBUF(USBx, ep->num); /*Set buffer address for double buffered mode*/ PCD_SET_EP_DBUF_ADDR(USBx, ep->num,ep->pmaaddr0, ep->pmaaddr1); - + if (ep->is_in==0) { /* Clear the data toggle bits for the endpoint IN/OUT*/ PCD_CLEAR_RX_DTOG(USBx, ep->num); PCD_CLEAR_TX_DTOG(USBx, ep->num); - + /* Reset value of the data toggle bits for the endpoint out*/ PCD_TX_DTOG(USBx, ep->num); - + PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); } @@ -1679,7 +1679,7 @@ HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep) PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS); } } - + return HAL_OK; } @@ -1691,13 +1691,13 @@ HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep) */ HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep) { - if (ep->doublebuffer == 0) + if (ep->doublebuffer == 0) { if (ep->is_in) { PCD_CLEAR_TX_DTOG(USBx, ep->num); /* Configure DISABLE status for the Endpoint*/ - PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); + PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); } else { @@ -1708,16 +1708,16 @@ HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep) } /*Double Buffer*/ else - { + { if (ep->is_in==0) { /* Clear the data toggle bits for the endpoint IN/OUT*/ PCD_CLEAR_RX_DTOG(USBx, ep->num); PCD_CLEAR_TX_DTOG(USBx, ep->num); - + /* Reset value of the data toggle bits for the endpoint out*/ PCD_TX_DTOG(USBx, ep->num); - + PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS); PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); } @@ -1732,7 +1732,7 @@ HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep) PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS); } } - + return HAL_OK; } @@ -1746,7 +1746,7 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx , USB_EPTypeDef *ep) { uint16_t pmabuffer = 0; uint32_t len = ep->xfer_len; - + /* IN endpoint */ if (ep->is_in == 1) { @@ -1754,16 +1754,16 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx , USB_EPTypeDef *ep) if (ep->xfer_len > ep->maxpacket) { len=ep->maxpacket; - ep->xfer_len-=len; + ep->xfer_len-=len; } else - { + { len=ep->xfer_len; ep->xfer_len =0; } - + /* configure and validate Tx endpoint */ - if (ep->doublebuffer == 0) + if (ep->doublebuffer == 0) { USB_WritePMA(USBx, ep->xfer_buff, ep->pmaadress, len); PCD_SET_EP_TX_CNT(USBx, ep->num, len); @@ -1786,7 +1786,7 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx , USB_EPTypeDef *ep) USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, len); PCD_FreeUserBuffer(USBx, ep->num, ep->is_in); } - + PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_VALID); } else /* OUT endpoint */ @@ -1795,16 +1795,16 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx , USB_EPTypeDef *ep) if (ep->xfer_len > ep->maxpacket) { len=ep->maxpacket; - ep->xfer_len-=len; + ep->xfer_len-=len; } else { len=ep->xfer_len; ep->xfer_len =0; } - + /* configure and validate Rx endpoint */ - if (ep->doublebuffer == 0) + if (ep->doublebuffer == 0) { /*Set RX buffer count*/ PCD_SET_EP_RX_CNT(USBx, ep->num, len); @@ -1814,15 +1814,15 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx , USB_EPTypeDef *ep) /*Set the Double buffer counter*/ PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, len); } - + PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); } - + return HAL_OK; } /** - * @brief USB_WritePacket : Writes a packet into the Tx FIFO associated + * @brief USB_WritePacket : Writes a packet into the Tx FIFO associated * with the EP/channel * @param USBx : Selected device * @param src : pointer to source buffer @@ -1832,7 +1832,7 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx , USB_EPTypeDef *ep) */ HAL_StatusTypeDef USB_WritePacket(USB_TypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len) { - /* NOTE : - This function is not required by USB Device FS peripheral, it is used + /* NOTE : - This function is not required by USB Device FS peripheral, it is used only by USB OTG FS peripheral. - This function is added to ensure compatibility across platforms. */ @@ -1840,7 +1840,7 @@ HAL_StatusTypeDef USB_WritePacket(USB_TypeDef *USBx, uint8_t *src, uint8_t ch_ep } /** - * @brief USB_ReadPacket : read a packet from the Tx FIFO associated + * @brief USB_ReadPacket : read a packet from the Tx FIFO associated * with the EP/channel * @param USBx : Selected device * @param dest : destination pointer @@ -1849,7 +1849,7 @@ HAL_StatusTypeDef USB_WritePacket(USB_TypeDef *USBx, uint8_t *src, uint8_t ch_ep */ void *USB_ReadPacket(USB_TypeDef *USBx, uint8_t *dest, uint16_t len) { - /* NOTE : - This function is not required by USB Device FS peripheral, it is used + /* NOTE : - This function is not required by USB Device FS peripheral, it is used only by USB OTG FS peripheral. - This function is added to ensure compatibility across platforms. */ @@ -1859,21 +1859,21 @@ void *USB_ReadPacket(USB_TypeDef *USBx, uint8_t *dest, uint16_t len) /** * @brief USB_EPSetStall : set a stall condition over an EP * @param USBx : Selected device - * @param ep: pointer to endpoint structure + * @param ep: pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_EPSetStall(USB_TypeDef *USBx , USB_EPTypeDef *ep) { if (ep->num == 0) { - /* This macro sets STALL status for RX & TX*/ - PCD_SET_EP_TXRX_STATUS(USBx, ep->num, USB_EP_RX_STALL, USB_EP_TX_STALL); + /* This macro sets STALL status for RX & TX*/ + PCD_SET_EP_TXRX_STATUS(USBx, ep->num, USB_EP_RX_STALL, USB_EP_TX_STALL); } else { if (ep->is_in) { - PCD_SET_EP_TX_STATUS(USBx, ep->num , USB_EP_TX_STALL); + PCD_SET_EP_TX_STATUS(USBx, ep->num , USB_EP_TX_STALL); } else { @@ -1913,13 +1913,13 @@ HAL_StatusTypeDef USB_StopDevice(USB_TypeDef *USBx) { /* disable all interrupts and force USB reset */ USBx->CNTR = USB_CNTR_FRES; - + /* clear interrupt status register */ USBx->ISTR = 0; - + /* switch-off device */ USBx->CNTR = (USB_CNTR_FRES | USB_CNTR_PDWN); - + return HAL_OK; } @@ -1932,12 +1932,12 @@ HAL_StatusTypeDef USB_StopDevice(USB_TypeDef *USBx) */ HAL_StatusTypeDef USB_SetDevAddress (USB_TypeDef *USBx, uint8_t address) { - if(address == 0) + if(address == 0) { /* set device address and enable function */ USBx->DADDR = USB_DADDR_EF; } - + return HAL_OK; } @@ -1948,7 +1948,7 @@ HAL_StatusTypeDef USB_SetDevAddress (USB_TypeDef *USBx, uint8_t address) */ HAL_StatusTypeDef USB_DevConnect (USB_TypeDef *USBx) { - /* NOTE : - This function is not required by USB Device FS peripheral, it is used + /* NOTE : - This function is not required by USB Device FS peripheral, it is used only by USB OTG FS peripheral. - This function is added to ensure compatibility across platforms. */ @@ -1962,7 +1962,7 @@ HAL_StatusTypeDef USB_DevConnect (USB_TypeDef *USBx) */ HAL_StatusTypeDef USB_DevDisconnect (USB_TypeDef *USBx) { - /* NOTE : - This function is not required by USB Device FS peripheral, it is used + /* NOTE : - This function is not required by USB Device FS peripheral, it is used only by USB OTG FS peripheral. - This function is added to ensure compatibility across platforms. */ @@ -1977,7 +1977,7 @@ HAL_StatusTypeDef USB_DevDisconnect (USB_TypeDef *USBx) uint32_t USB_ReadInterrupts (USB_TypeDef *USBx) { uint32_t tmpreg = 0; - + tmpreg = USBx->ISTR; return tmpreg; } @@ -1989,7 +1989,7 @@ uint32_t USB_ReadInterrupts (USB_TypeDef *USBx) */ uint32_t USB_ReadDevAllOutEpInterrupt (USB_TypeDef *USBx) { - /* NOTE : - This function is not required by USB Device FS peripheral, it is used + /* NOTE : - This function is not required by USB Device FS peripheral, it is used only by USB OTG FS peripheral. - This function is added to ensure compatibility across platforms. */ @@ -2003,7 +2003,7 @@ uint32_t USB_ReadDevAllOutEpInterrupt (USB_TypeDef *USBx) */ uint32_t USB_ReadDevAllInEpInterrupt (USB_TypeDef *USBx) { - /* NOTE : - This function is not required by USB Device FS peripheral, it is used + /* NOTE : - This function is not required by USB Device FS peripheral, it is used only by USB OTG FS peripheral. - This function is added to ensure compatibility across platforms. */ @@ -2019,7 +2019,7 @@ uint32_t USB_ReadDevAllInEpInterrupt (USB_TypeDef *USBx) */ uint32_t USB_ReadDevOutEPInterrupt (USB_TypeDef *USBx , uint8_t epnum) { - /* NOTE : - This function is not required by USB Device FS peripheral, it is used + /* NOTE : - This function is not required by USB Device FS peripheral, it is used only by USB OTG FS peripheral. - This function is added to ensure compatibility across platforms. */ @@ -2035,7 +2035,7 @@ uint32_t USB_ReadDevOutEPInterrupt (USB_TypeDef *USBx , uint8_t epnum) */ uint32_t USB_ReadDevInEPInterrupt (USB_TypeDef *USBx , uint8_t epnum) { - /* NOTE : - This function is not required by USB Device FS peripheral, it is used + /* NOTE : - This function is not required by USB Device FS peripheral, it is used only by USB OTG FS peripheral. - This function is added to ensure compatibility across platforms. */ @@ -2050,7 +2050,7 @@ uint32_t USB_ReadDevInEPInterrupt (USB_TypeDef *USBx , uint8_t epnum) */ void USB_ClearInterrupts (USB_TypeDef *USBx, uint32_t interrupt) { - /* NOTE : - This function is not required by USB Device FS peripheral, it is used + /* NOTE : - This function is not required by USB Device FS peripheral, it is used only by USB OTG FS peripheral. - This function is added to ensure compatibility across platforms. */ @@ -2064,7 +2064,7 @@ void USB_ClearInterrupts (USB_TypeDef *USBx, uint32_t interrupt) */ HAL_StatusTypeDef USB_EP0_OutStart(USB_TypeDef *USBx, uint8_t *psetup) { - /* NOTE : - This function is not required by USB Device FS peripheral, it is used + /* NOTE : - This function is not required by USB Device FS peripheral, it is used only by USB OTG FS peripheral. - This function is added to ensure compatibility across platforms. */ @@ -2079,7 +2079,7 @@ HAL_StatusTypeDef USB_EP0_OutStart(USB_TypeDef *USBx, uint8_t *psetup) HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_TypeDef *USBx) { USBx->CNTR |= USB_CNTR_RESUME; - + return HAL_OK; } @@ -2107,7 +2107,7 @@ void USB_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, ui uint32_t nbytes = (wNBytes + 1) >> 1; /* nbytes = (wNBytes + 1) / 2 */ uint32_t index = 0, temp1 = 0, temp2 = 0; uint16_t *pdwVal = NULL; - + pdwVal = (uint16_t *)(wPMABufAddr * 2 + (uint32_t)USBx + 0x400); for (index = nbytes; index != 0; index--) { @@ -2133,7 +2133,7 @@ void USB_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uin uint32_t nbytes = (wNBytes + 1) >> 1;/* /2*/ uint32_t index = 0; uint32_t *pdwVal = NULL; - + pdwVal = (uint32_t *)(wPMABufAddr * 2 + (uint32_t)USBx + 0x400); for (index = nbytes; index != 0; index--) { @@ -2163,7 +2163,7 @@ void USB_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uin static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx) { uint32_t count = 0; - + /* Wait for AHB master IDLE state. */ do { @@ -2173,11 +2173,11 @@ static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx) } } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0); - + /* Core Soft Reset */ count = 0; USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST; - + do { if (++count > 200000) @@ -2186,7 +2186,7 @@ static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx) } } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST); - + return HAL_OK; } /** |