diff options
| author | Trygve Laugstøl <trygvis@inamo.no> | 2018-08-15 13:47:39 +0200 |
|---|---|---|
| committer | Trygve Laugstøl <trygvis@inamo.no> | 2018-08-15 13:47:39 +0200 |
| commit | 5b53ca0700189ebb98278a8081bdabf527f1bb12 (patch) | |
| tree | 66c24061b124b3cfde10ae61621aec7c2f119c6f /Kintex-7/mw/Chip:XC7K480T.mw | |
| parent | 73275bb5b82f990d5201d2eb151321f7774c2041 (diff) | |
| download | semantic-sandbox-5b53ca0700189ebb98278a8081bdabf527f1bb12.tar.gz semantic-sandbox-5b53ca0700189ebb98278a8081bdabf527f1bb12.tar.bz2 semantic-sandbox-5b53ca0700189ebb98278a8081bdabf527f1bb12.tar.xz semantic-sandbox-5b53ca0700189ebb98278a8081bdabf527f1bb12.zip | |
o Kintex-7.
Diffstat (limited to 'Kintex-7/mw/Chip:XC7K480T.mw')
| -rw-r--r-- | Kintex-7/mw/Chip:XC7K480T.mw | 43 |
1 files changed, 43 insertions, 0 deletions
diff --git a/Kintex-7/mw/Chip:XC7K480T.mw b/Kintex-7/mw/Chip:XC7K480T.mw new file mode 100644 index 0000000..b5a1bf3 --- /dev/null +++ b/Kintex-7/mw/Chip:XC7K480T.mw @@ -0,0 +1,43 @@ += Overview = + +[[Part number::]] is an FPGA in the [[Chip family::Kintex-7]] family from [[Manufacturer::Xilinx]]. + +{|class='wikitable' +!Logic Cells +|[[Xilix logic cells::477760]] +|- +!Slices +|[[Xilix 7 series slices::74650]] +|- +!Distributed RAM +|[[Distributed RAM::6788 kB]] +|- +!RAM blocks +|[[RAM blocks::955]] +|- +!RAM block size +|[[RAM block size::36 kB]] +|- +!Total RAM +|[[RAM::34380 kB]] +|- +!Clock management tiles +|[[Xilix clock management tiles::8]] +|- +!Available IO +|[[Available IO::400]] +|- +!IO banks +|[[IO banks::8]] +|- +|} + += Hard cores = + +* [[Has hard core::Gigabit transceiver;32]] +* [[Has hard core::PCIe;1]] +* [[Has hard core::PCIe Gen 2;1]] + +[[Category:Generated]] +[[Category:Xilinx Kintex-7 family chip|Kintex-7]] +[[Category:Kintex-7 generated data set]] |