7 files changed, 301 insertions, 0 deletions

diff --git a/Kintex-7/mw/Chip:XC7K160T.mw b/Kintex-7/mw/Chip:XC7K160T.mw
new file mode 100644
index 0000000..0698263
--- /dev/null
+++ b/Kintex-7/mw/Chip:XC7K160T.mw
@@ -0,0 +1,43 @@
+= Overview =
+
+[[Part number::]] is an FPGA in the [[Chip family::Kintex-7]] family from [[Manufacturer::Xilinx]].
+
+{|class='wikitable'
+!Logic Cells
+|[[Xilix logic cells::162240]]
+|-
+!Slices
+|[[Xilix 7 series slices::25350]]
+|-
+!Distributed RAM
+|[[Distributed RAM::2188 kB]]
+|-
+!RAM blocks
+|[[RAM blocks::325]]
+|-
+!RAM block size
+|[[RAM block size::36 kB]]
+|-
+!Total RAM
+|[[RAM::11700 kB]]
+|-
+!Clock management tiles
+|[[Xilix clock management tiles::8]]
+|-
+!Available IO
+|[[Available IO::400]]
+|-
+!IO banks
+|[[IO banks::8]]
+|-
+|}
+
+= Hard cores =
+
+* [[Has hard core::Gigabit transceiver;8]]
+* [[Has hard core::PCIe;1]]
+* [[Has hard core::PCIe Gen 2;1]]
+
+[[Category:Generated]]
+[[Category:Xilinx Kintex-7 family chip|Kintex-7]]
+[[Category:Kintex-7 generated data set]]
diff --git a/Kintex-7/mw/Chip:XC7K325T.mw b/Kintex-7/mw/Chip:XC7K325T.mw
new file mode 100644
index 0000000..bcd44c6
--- /dev/null
+++ b/Kintex-7/mw/Chip:XC7K325T.mw
@@ -0,0 +1,43 @@
+= Overview =
+
+[[Part number::]] is an FPGA in the [[Chip family::Kintex-7]] family from [[Manufacturer::Xilinx]].
+
+{|class='wikitable'
+!Logic Cells
+|[[Xilix logic cells::326080]]
+|-
+!Slices
+|[[Xilix 7 series slices::50950]]
+|-
+!Distributed RAM
+|[[Distributed RAM::4000 kB]]
+|-
+!RAM blocks
+|[[RAM blocks::445]]
+|-
+!RAM block size
+|[[RAM block size::36 kB]]
+|-
+!Total RAM
+|[[RAM::16020 kB]]
+|-
+!Clock management tiles
+|[[Xilix clock management tiles::10]]
+|-
+!Available IO
+|[[Available IO::500]]
+|-
+!IO banks
+|[[IO banks::10]]
+|-
+|}
+
+= Hard cores =
+
+* [[Has hard core::Gigabit transceiver;16]]
+* [[Has hard core::PCIe;1]]
+* [[Has hard core::PCIe Gen 2;1]]
+
+[[Category:Generated]]
+[[Category:Xilinx Kintex-7 family chip|Kintex-7]]
+[[Category:Kintex-7 generated data set]]
diff --git a/Kintex-7/mw/Chip:XC7K355T.mw b/Kintex-7/mw/Chip:XC7K355T.mw
new file mode 100644
index 0000000..1043a31
--- /dev/null
+++ b/Kintex-7/mw/Chip:XC7K355T.mw
@@ -0,0 +1,43 @@
+= Overview =
+
+[[Part number::]] is an FPGA in the [[Chip family::Kintex-7]] family from [[Manufacturer::Xilinx]].
+
+{|class='wikitable'
+!Logic Cells
+|[[Xilix logic cells::356160]]
+|-
+!Slices
+|[[Xilix 7 series slices::55650]]
+|-
+!Distributed RAM
+|[[Distributed RAM::5088 kB]]
+|-
+!RAM blocks
+|[[RAM blocks::715]]
+|-
+!RAM block size
+|[[RAM block size::36 kB]]
+|-
+!Total RAM
+|[[RAM::25740 kB]]
+|-
+!Clock management tiles
+|[[Xilix clock management tiles::6]]
+|-
+!Available IO
+|[[Available IO::300]]
+|-
+!IO banks
+|[[IO banks::6]]
+|-
+|}
+
+= Hard cores =
+
+* [[Has hard core::Gigabit transceiver;24]]
+* [[Has hard core::PCIe;1]]
+* [[Has hard core::PCIe Gen 2;1]]
+
+[[Category:Generated]]
+[[Category:Xilinx Kintex-7 family chip|Kintex-7]]
+[[Category:Kintex-7 generated data set]]
diff --git a/Kintex-7/mw/Chip:XC7K410T.mw b/Kintex-7/mw/Chip:XC7K410T.mw
new file mode 100644
index 0000000..733e056
--- /dev/null
+++ b/Kintex-7/mw/Chip:XC7K410T.mw
@@ -0,0 +1,43 @@
+= Overview =
+
+[[Part number::]] is an FPGA in the [[Chip family::Kintex-7]] family from [[Manufacturer::Xilinx]].
+
+{|class='wikitable'
+!Logic Cells
+|[[Xilix logic cells::406720]]
+|-
+!Slices
+|[[Xilix 7 series slices::63550]]
+|-
+!Distributed RAM
+|[[Distributed RAM::5663 kB]]
+|-
+!RAM blocks
+|[[RAM blocks::795]]
+|-
+!RAM block size
+|[[RAM block size::36 kB]]
+|-
+!Total RAM
+|[[RAM::28620 kB]]
+|-
+!Clock management tiles
+|[[Xilix clock management tiles::10]]
+|-
+!Available IO
+|[[Available IO::500]]
+|-
+!IO banks
+|[[IO banks::10]]
+|-
+|}
+
+= Hard cores =
+
+* [[Has hard core::Gigabit transceiver;16]]
+* [[Has hard core::PCIe;1]]
+* [[Has hard core::PCIe Gen 2;1]]
+
+[[Category:Generated]]
+[[Category:Xilinx Kintex-7 family chip|Kintex-7]]
+[[Category:Kintex-7 generated data set]]
diff --git a/Kintex-7/mw/Chip:XC7K420T.mw b/Kintex-7/mw/Chip:XC7K420T.mw
new file mode 100644
index 0000000..dc59e81
--- /dev/null
+++ b/Kintex-7/mw/Chip:XC7K420T.mw
@@ -0,0 +1,43 @@
+= Overview =
+
+[[Part number::]] is an FPGA in the [[Chip family::Kintex-7]] family from [[Manufacturer::Xilinx]].
+
+{|class='wikitable'
+!Logic Cells
+|[[Xilix logic cells::416960]]
+|-
+!Slices
+|[[Xilix 7 series slices::65150]]
+|-
+!Distributed RAM
+|[[Distributed RAM::5938 kB]]
+|-
+!RAM blocks
+|[[RAM blocks::835]]
+|-
+!RAM block size
+|[[RAM block size::36 kB]]
+|-
+!Total RAM
+|[[RAM::30060 kB]]
+|-
+!Clock management tiles
+|[[Xilix clock management tiles::8]]
+|-
+!Available IO
+|[[Available IO::400]]
+|-
+!IO banks
+|[[IO banks::8]]
+|-
+|}
+
+= Hard cores =
+
+* [[Has hard core::Gigabit transceiver;32]]
+* [[Has hard core::PCIe;1]]
+* [[Has hard core::PCIe Gen 2;1]]
+
+[[Category:Generated]]
+[[Category:Xilinx Kintex-7 family chip|Kintex-7]]
+[[Category:Kintex-7 generated data set]]
diff --git a/Kintex-7/mw/Chip:XC7K480T.mw b/Kintex-7/mw/Chip:XC7K480T.mw
new file mode 100644
index 0000000..b5a1bf3
--- /dev/null
+++ b/Kintex-7/mw/Chip:XC7K480T.mw
@@ -0,0 +1,43 @@
+= Overview =
+
+[[Part number::]] is an FPGA in the [[Chip family::Kintex-7]] family from [[Manufacturer::Xilinx]].
+
+{|class='wikitable'
+!Logic Cells
+|[[Xilix logic cells::477760]]
+|-
+!Slices
+|[[Xilix 7 series slices::74650]]
+|-
+!Distributed RAM
+|[[Distributed RAM::6788 kB]]
+|-
+!RAM blocks
+|[[RAM blocks::955]]
+|-
+!RAM block size
+|[[RAM block size::36 kB]]
+|-
+!Total RAM
+|[[RAM::34380 kB]]
+|-
+!Clock management tiles
+|[[Xilix clock management tiles::8]]
+|-
+!Available IO
+|[[Available IO::400]]
+|-
+!IO banks
+|[[IO banks::8]]
+|-
+|}
+
+= Hard cores =
+
+* [[Has hard core::Gigabit transceiver;32]]
+* [[Has hard core::PCIe;1]]
+* [[Has hard core::PCIe Gen 2;1]]
+
+[[Category:Generated]]
+[[Category:Xilinx Kintex-7 family chip|Kintex-7]]
+[[Category:Kintex-7 generated data set]]
diff --git a/Kintex-7/mw/Chip:XC7K70T.mw b/Kintex-7/mw/Chip:XC7K70T.mw
new file mode 100644
index 0000000..206e1bc
--- /dev/null
+++ b/Kintex-7/mw/Chip:XC7K70T.mw
@@ -0,0 +1,43 @@
+= Overview =
+
+[[Part number::]] is an FPGA in the [[Chip family::Kintex-7]] family from [[Manufacturer::Xilinx]].
+
+{|class='wikitable'
+!Logic Cells
+|[[Xilix logic cells::65600]]
+|-
+!Slices
+|[[Xilix 7 series slices::10250]]
+|-
+!Distributed RAM
+|[[Distributed RAM::838 kB]]
+|-
+!RAM blocks
+|[[RAM blocks::135]]
+|-
+!RAM block size
+|[[RAM block size::36 kB]]
+|-
+!Total RAM
+|[[RAM::4860 kB]]
+|-
+!Clock management tiles
+|[[Xilix clock management tiles::6]]
+|-
+!Available IO
+|[[Available IO::300]]
+|-
+!IO banks
+|[[IO banks::6]]
+|-
+|}
+
+= Hard cores =
+
+* [[Has hard core::Gigabit transceiver;8]]
+* [[Has hard core::PCIe;1]]
+* [[Has hard core::PCIe Gen 2;1]]
+
+[[Category:Generated]]
+[[Category:Xilinx Kintex-7 family chip|Kintex-7]]
+[[Category:Kintex-7 generated data set]]