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* ARM: use <target/arm.h> not armv4_5.hDavid Brownell2009-12-071-168/+3
| | | | | | | | | | | | | | Move most declarations in <target/armv4_5.h> to <target/arm.h> and update users. What's left in the older file is stuff that I think should be removed ... the old register cache access stuff, which makes it awkward to support microcontroller profile (Cortex-M) cores. The armv4_5_run_algorithm() declaration was moved too, even though it's not yet as generic as it probably ought to be. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: rename some generic routinesDavid Brownell2009-12-071-3/+3
| | | | | | | | | | | | | | | | Rename some (mostly) generic ARM functions: armv4_5_arch_state() --> arm_arch_state() armv4_5_get_gdb_reg_list() --> arm_get_gdb_reg_list() armv4_5_init_arch_info() --> arm_init_arch_info() Cores using the microcontroller profile may want a different arch_state() routine though. (Also fix strange indentation in arm_arch_state: use tabs only! And update a call to it, removing assignment-in-conditional.) Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: move opcode macros to <target/arm_opcodes.h>David Brownell2009-12-071-167/+0
| | | | | | | | | | | | | | | Move the ARM opcode macros from <target/armv4_5.h>, and a few Thumb2 ones from <target/armv7m.h>, to more appropriate homes in a new <target/arm_opcodes.h> file. Removed duplicate opcodes from that v7m/Thumb2 set. Protected a few macro argument references by adding missing parentheses. Tightening up some of the line lengths turned up a curious artifact: the macros for the Thumb opcodes are all 32 bits wide, not 16 bits. There's currently no explanation for why it's done that way... Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: remove mrc_opcode(), use MRC() or MCR()David Brownell2009-12-071-12/+0
| | | | | | | | | | | | Get rid of mrc_opcode() in favor of ARMV4_5_MRC() or, where arm*20t should have used it, ARMV4_5_MCR() instead. Basically, *writing* coprocessor registers shouldn't have used the *read* opcode ... and both should stick to standard opcode constructors, not rearranging parameter sequence any more than already needed. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: doc updates for main headerDavid Brownell2009-12-041-3/+11
| | | | Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: rename armv4_5_build_reg_cache() as arm_*()David Brownell2009-12-041-2/+1
| | | | Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: rename armv4_5_algorithm as arm_algorithmDavid Brownell2009-12-041-1/+1
| | | | Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: misc generic cleanupDavid Brownell2009-12-041-9/+17
| | | | | | | | | | | Remove an undesirable use of the CPSR symbol ... it needs to vanish. Flag mode-to-number stuff as obsolete; say why ... should also vanish. Get rid of no-longer-used mode and state typedefs. Comment a few of the implicit ties to "classic ARM". Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: ARMV4_5_COMMON_MAGIC --> ARM_COMMON_MAGICDavid Brownell2009-12-041-2/+2
| | | | Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: switch target_to_armv4_5() to target_to_arm()David Brownell2009-12-041-2/+0
| | | | | | And remove that old symbol. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: rename armv4_5_state_* as arm_state_*David Brownell2009-12-041-5/+5
| | | | | | And make arm_state_strings[] be const. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: rename armv4_5_mode_* AS arm_mode_*David Brownell2009-12-041-11/+11
| | | | Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: rename ARMV4_5_MODE_* as ARM_MODE_*David Brownell2009-12-041-9/+9
| | | | Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: rename ARMV4_5_STATE_* as ARM_STATE_*David Brownell2009-12-041-3/+3
| | | | Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: remove semihosting globalsDavid Brownell2009-12-041-0/+6
| | | | | | | | Store a flag and errno in in "struct arm". Have "poll" output report when semihosting is active. Shrink some of the affected lines. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* change #include "target.h" to <target/target.h>Zachary T Welch2009-12-031-1/+1
| | | | | | | | | | | | Changes from the flat namespace to heirarchical one. Instead of writing: #include "target.h" the following form should be used. #include <target/target.h> The exception is from .c files in the same directory.
* change #include "command.h" to <helper/command.h>Zachary T Welch2009-12-031-1/+1
| | | | | | | | | | | | Changes from the flat namespace to heirarchical one. Instead of writing: #include "command.h" the following form should be used. #include <helper/command.h> The exception is from .c files in the same directory.
* target: "mcr" and "mrc" are ARM-specificDavid Brownell2009-12-011-0/+15
| | | | | | | | | | | | | | Switch "mrc" and "mcr" commands to be toplevel ARM operations, as they should initially have been. Correct the usage message for both commands: it matches ARM documentation (as one wants!) instead of reordering them to match the funky mrc() and mcr() method usage (sigh). For Cortex-A8: restore a line that got accidentally dropped, so the secure monitor mode shadow registers will show again. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* remove target_type register_command callbackZachary T Welch2009-11-241-1/+4
| | | | | | Uses chaining of command_registration structures to eliminate all target_type register_callback routines. Exports the command_handler registration arrays for those target types that are used by others.
* ARM: new DPM interfaceDavid Brownell2009-11-241-0/+6
| | | | | | | | | | | | | | | | | | | First version of interface for sharing code between ARMv6 and ARMv7a debug modules ... now the architecture includes debug support. (Not the same as for the trimmed-down v7m or v6m though!) This is a first version of an interface that will let the ARM11 and Cortex-A8 support share code, features, and bugfixes. Based on existing code from both of those cores. The ARM v7-AR architecture specification calls this commonality the "Debug Programmer's Model (DPM)", which seemed to be an appropriate acronym -- a TLA even! -- for use in our code. Made it so. :) The initial scope of this just supports register access, and is geared towards supporting top level "struct arm" mechanisms. Later, things like breakpoint and watchpoint support should be included. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: remove 'armv4_5_common_s' migration #defineDavid Brownell2009-11-221-3/+0
| | | | | | Finish migrating from the old symbol to the new one. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: define two register utilitiesDavid Brownell2009-11-221-0/+8
| | | | | | | | | | | | | | Define arm_reg_current() ... returning handle to a given register, and encapsulating the current mode's register shadowing. It's got one current use, for reporting the current register set to GDB. This will let later patches clean up much ARMV4_5_CORE_REG_MODE() nastiness, saving a bit of code. Define and use arm_set_cpsr() ... initially it updates the cached CPSR and sets up state used by arm_reg_current(), plus any SPSR handle. (Later: can also set up for T and J bits.) Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: simplify CPSR handlingDavid Brownell2009-11-221-11/+5
| | | | | | | | | | | | | | Stash a pointer to the CPSR in the "struct arm", to help get rid of the (common) references to its index in the register cache. This removes almost all references to CPSR offsets outside of the toplevel ARM code ... except a pair related to the current ARM11 "simulator" logic (which should be removable soonish). This is a net minor code shrink of a few hundred bytes of object code, and also makes the code more readable. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: pass 'struct reg *' to register r/w routinesDavid Brownell2009-11-201-3/+3
| | | | | | | | | | | | | | | | Implementations need to access the register struct they modify; make it easier and less error-prone to identify the instance. (This removes over 10% of the ARMV4_5_CORE_REG_MODE nastiness...) Plus some minor fixes noted when making these updates: ARM7/ARM9 accessor methods should be static; don't leave CPSR wrongly marked "dirty"; note significant XScale omissions in register handling; and have armv4_5_build_reg_cache() record its result. Rename "struct armv4_5_core_reg" as "struct arm_reg"; it's used for more than those older architecture generations. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* target: create/use register_cache_invalidate()David Brownell2009-11-191-2/+0
| | | | | | | | | | | | | | | Create a generic register_cache_invalidate(), and use it to replace three all-but-identical core-specific routines: - armv4_5_invalidate_core_regs() - armv7m_invalidate_core_regs - mips32_invalidate_core_regs() too. Make cache->num_regs be unsigned, avoiding various errors. Net code shrink and simplification. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: remove per-register mallocDavid Brownell2009-11-191-0/+1
| | | | | | | Just pre-allocate memory for the cached register value. Shrinks heap overhead; increases locality-of-reference. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARMv7-A: use standard ARM core statesDavid Brownell2009-11-191-0/+1
| | | | | | | | | | | | | | | We don't want an ARMv7-specific core state enumeration just to add ThumbEE state. Update the generic stuff to handle that, and replace the V7-specific bits with it. For Cortex-A8: on debug entry, check both the T and J bits instead of just the T bit. When the J bit is set, set the right state and warn appropriately. (And while we're at it, move the generic arm struct to the front of the v7a structure, for somewhat better code generation.) Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: setup "secure monitor mode" shadow regsDavid Brownell2009-11-181-2/+3
| | | | | | | | | | | | | Teach the "armv4_5" register code to understand about the secure monitor mode: - Add the other three shadowed registers to the arrays - Support another internal mode number (sigh) in mappings - Catch malloc/calloc failures building that register cache This should kick in for Cortex-A8 and ARM1176. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: add "core_type" field to "struct arm"David Brownell2009-11-181-1/+9
| | | | | | | | | | It's used to flag cores with the "TrustZone" extension, and is used in subsequent patches to set up support for the registers shadowed by its new secure monitor mode. The ARM1176 and Cortex-A8 both support this new mode. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: add is_arm_mode()David Brownell2009-11-171-3/+3
| | | | | | | | | | | | | | | | | | Add a new is_arm_mode() predicate, and use it to replace almost all calls to current armv4_5_mode_to_number(). Eventually those internal mode numbers should vanish... along with their siblings in the armv7a.c file. Remove a handful of superfluous checks ... e.g. the mode number was just initialized, or (debug entry methods) already validated. Move one of the macros using internal mode numbers into the only file which uses that macro. Make the tables manipulated with those numbers be read-only and, where possible, static so they're not confused with part of the generic ARM interface. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: add arm_mode_name()David Brownell2009-11-171-2/+2
| | | | | | | | | | | | | | | Add and use arm_mode_name() to map from PSR bits to user meaningful names. It uses a new table which, later, can be used to hold other mode-coupled data. Add definitions for the "Secure Monitor" mode, as seen on some ARM11 cores (like ARM1176) and on Cortex-A8. The previous mode name scheme didn't understand that mode. Remove the old mechanism ... there were two copies, caused by Cortex-A8 needing to add "Secure Monitor" mode support. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: only use one set of dummy FPA registersDavid Brownell2009-11-171-0/+2
| | | | | | | | | | | | | | | | All ARM cores need to provide obsolete FPA registers in their GDB register dumps. (Even though cores with floating point support now generally use some version of VFP...) Clean up that support a bit by sharing the same dummy registers, and removing the duplicate copies. Eventually we shouldn't need to export those dummies. (This makes the ARMv7-M support include the armv4_5 header, and cleans up related #includes, but doesn't yet use anything from there except those dummies.) Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* target: don't include "log.h" from "armv4_5.h"David Brownell2009-11-161-1/+0
| | | | | | | No point in multiple includes, and that file doesn't use its functions any more. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: move mode functions out of headerDavid Brownell2009-11-161-38/+4
| | | | | | | | | They're really too big to inline, at least for code that's not in any performance-critical loops. Also move the associated string table to the rodata section. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* target: less implicit inclusion of "etm.h"David Brownell2009-11-161-1/+1
| | | | | | | Don't include it in more headers than necessary; just use it in the few files that actually need it. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* target: no implicit #includes of "register.h"David Brownell2009-11-161-1/+0
| | | | | | | | | | | | Same deal: "register.h" got needlessly included all over the place because of being in a few widely included headers. So take it out of the header files which included it, and put it in files which use it ... reduce needless interdependencies. Also, don't need that extra "types.h" inclusion. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* target: less implicit inclusion of "command.h"David Brownell2009-11-161-1/+0
| | | | | | | | | | Lots of files still include it, often through needless duplicate inclusion of "log.h"; sigh. This cleans up the inclusion graph a bunch, so there are fewer inclusion paths, but it doesn't change much otherwise. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: memory utils aren't ARM7/ARM9 dependentDavid Brownell2009-11-151-3/+6
| | | | | | | | | | | | | | | | The arm7_9_checksum_memory() and arm7_9_blank_check_memory() routines are not actually specific to the ARM7 and ARM9 core generations ... they can work for any core which can run algorithms using basic ARM (not Thumb) instructions. Rename them; move the declarations to a more generic site; likewise move the code (and tidy it a bit in the process). NOTE: the blank_check() method falsely returned a success status (0) on one error path, when the algorithm failed. Fixed this bug. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* command_context_t -> struct command_contextZachary T Welch2009-11-131-1/+1
| | | | Remove misleading typedef and redundant suffix from struct command_context.
* target_t -> struct targetZachary T Welch2009-11-131-11/+11
| | | | Remove misleading typedef and redundant suffix from struct target.
* reg_t -> struct regZachary T Welch2009-11-131-1/+1
| | | | Remove misleading typedef and redundant suffix from struct reg.
* armv4_5_common_t -> struct armZachary T Welch2009-11-131-5/+5
| | | | Remove misleading typedef and just use struct arm.
* etm_context_t -> struct etm_contextZachary T Welch2009-11-131-1/+1
| | | | Remove misleading typedef and redundant suffix from struct etm_context.
* reg_cache_t -> struct reg_cacheZachary T Welch2009-11-131-2/+2
| | | | Remove misleading typedef and redundant suffix from struct reg_cache.
* armv4_5_core_reg_t -> struct armv4_5_core_regZachary T Welch2009-11-131-2/+2
| | | | Remove misleading typedef and redundant suffix from struct armv4_5_core_reg.
* armv4_5_algorithm_t -> struct armv4_5_algorithmZachary T Welch2009-11-131-2/+2
| | | | Remove misleading typedef and redundant suffix from struct armv4_5_algorithm.
* reg_param_t -> struct reg_paramZachary T Welch2009-11-131-1/+1
| | | | Remove misleading typedef and redundant suffix from struct reg_param.
* mem_param_t -> struct mem_paramZachary T Welch2009-11-131-1/+1
| | | | Remove misleading typedef and redundant suffix from struct mem_param.
* ETM: remove old mid-level ETM handleDavid Brownell2009-11-111-0/+1
| | | | | | | | | | | | | | | | | | Now that nothing uses the old ETM handle any more, remove it. Add minimal header tweaks, letting non-ARM7 and non-ARM9 cores access ETM facilities. Now ARM11 could support standard ETM (and ETB) access as soon as it derives from "struct arm" ... its scanchain 6 is used access the ETM, just like ARM7 and ARM9. The Cortex parts (both M3 and A8) will need modified access methods (via ETM init parameters), so they use the DAP. Our first A8 target (OMAP3) needs that for both ETM and ETB, but the M3 ETM isn't very useful without SWO trace support (it's painfully stripped down), so that support won't be worth adding for a while. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: start generalized base typeDavid Brownell2009-11-111-5/+31
| | | | | | | | | | | | | | | | Rename "struct armv4_5_common_s" as "struct arm". It needs a bit more work to be properly generic, and to move out of this header, but it's the best start we have on that today. Add and initialize an optional ETM pointer, since that will be the first thing that gets generalized. The intent being: all ARMs should eventually derive from this "struct arm", so they can reuse the current ETM logic. (And later, more.) Currently the ARM cores that *don't* so derive are only ARMv7-M (and thus Cortex-M3) and ARM11. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
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