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* target: no implicit #includes of "register.h"David Brownell2009-11-161-0/+1
| | | | | | | | | | | | Same deal: "register.h" got needlessly included all over the place because of being in a few widely included headers. So take it out of the header files which included it, and put it in files which use it ... reduce needless interdependencies. Also, don't need that extra "types.h" inclusion. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* target: don't implicitly include "breakpoint.h"David Brownell2009-11-161-0/+1
| | | | | | | | | | | Most files in the tree seem to have ended up including this, and *quite* needlessly ... only code implementing or using breakpoints actually needs these declarations. So take it out of the header files which included it, and put it in files which use it ... reduce needless interdependencies. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* command_t -> struct commandZachary T Welch2009-11-131-1/+1
| | | | Remove misleading typedef and redundant suffix from struct command.
* command_context_t -> struct command_contextZachary T Welch2009-11-131-3/+3
| | | | Remove misleading typedef and redundant suffix from struct command_context.
* target_t -> struct targetZachary T Welch2009-11-131-45/+45
| | | | Remove misleading typedef and redundant suffix from struct target.
* reg_t -> struct regZachary T Welch2009-11-131-4/+4
| | | | Remove misleading typedef and redundant suffix from struct reg.
* target_type_t -> struct target_typeZachary T Welch2009-11-131-1/+1
| | | | Remove misleading typedef and redundant suffix from struct target_type.
* cortex_m3_dwt_comparator_t -> struct cortex_m3_dwt_comparatorZachary T Welch2009-11-131-5/+5
| | | | Remove misleading typedef and redundant suffix from struct cortex_m3_dwt_comparator.
* cortex_m3_fp_comparator_t -> struct cortex_m3_fp_comparatorZachary T Welch2009-11-131-4/+4
| | | | Remove misleading typedef and redundant suffix from struct cortex_m3_fp_comparator.
* breakpoint_t -> struct breakpointZachary T Welch2009-11-131-9/+9
| | | | Remove misleading typedef and redundant suffix from struct breakpoint.
* arm_instruction_t -> struct arm_instructionZachary T Welch2009-11-131-1/+1
| | | | Remove misleading typedef and redundant suffix from struct arm_instruction.
* reg_cache_t -> struct reg_cacheZachary T Welch2009-11-131-1/+1
| | | | Remove misleading typedef and redundant suffix from struct reg_cache.
* cortex_m3_common_t -> struct cortex_m3_commonZachary T Welch2009-11-131-26/+26
| | | | Remove misleading typedef and redundant suffix from struct cortex_m3_common.
* watchpoint_t -> struct watchpointZachary T Welch2009-11-131-5/+5
| | | | Remove misleading typedef and redundant suffix from struct watchpoint.
* armv7m_common_t -> struct armv7m_commonZachary T Welch2009-11-131-12/+12
| | | | Remove misleading typedef and redundant suffix from struct armv7m_common.
* swjdp_common_t -> struct swjdp_commonZachary T Welch2009-11-131-21/+21
| | | | Remove misleading typedef and redundant suffix from struct swjdp_common.
* jtag_tap_t -> struct jtag_tapZachary T Welch2009-11-131-1/+1
| | | | | Search and destroy the jtag_tap_t typedef. This also cleans up a layering violation, removing the declaration from types.h.
* add CMD_NAME macro for command handlersZachary T Welch2009-11-131-1/+1
| | | | | By introducing the CMD_NAME macro, this parameter may be integrated as args[-1] in command.[ch], without touching any other call sites.
* use COMMAND_HANDLER macro to define all commandsZachary T Welch2009-11-131-9/+3
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* change argv to args in command handlersZachary T Welch2009-11-111-5/+5
| | | | | | | | | | | Subsequent patches expect all command handlers to use a uniform parameter naming scheme. In the entire tree, these two files used standard 'argv' instead of our non-standard 'args'. This patch opts to reduces the noise required to unify the command handlers, using dominant 'args' form. A future patch may be used to convert us back to the standard argv, but that requires coordination with all developers to minimize disruptions.
* Revert "target: add target->type->has_mmu fn"David Brownell2009-11-091-7/+0
| | | | | | | | | | | | | | | | This patch introduced a bug preventing flash writes from working on Cortex-M3 targets like the STM32. Moreover, it's the wrong approach for handling no-MMU targets. The right way to handle no-MMU targets is to provide accessors for physical addresses, and use them everywhere; and any code which tries to work with virtual-to-physical mappings should use a identity mapping (which can be defaulted). And ... we can tell if a target has an MMU by seeing if it's got an mmu() method. No such methood means no MMU. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* Cortex-M3: fix (debug) message priorityDavid Brownell2009-11-081-1/+1
| | | | Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* Cortex-M3: use the new inheritance/nesting schemeDavid Brownell2009-11-051-104/+88
| | | | | | | | | | | | Use new target_to_cm3() and target_to_armv7m() inlines, instead of a series of x->arch_info conversions. Remove arch_info, since nothing uses it. Also fix an omission: the Cortex-M3 commands didn't verify that they were operating on that kind of target. Add comment about the ARMv7M version of that omission. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* Improve cortex_m3 command argument parsing.Zachary T Welch2009-11-051-6/+2
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* watchpoint_add() cleanupDavid Brownell2009-11-051-1/+1
| | | | | | | | | | | | Fail watchpoint_add() if it's the same address but the parameters are different ... don't just assume having the same address means the same watchpoint! (Note that overlapping watchpoints aren't detected...) Handle unrecognized return codes more sanely; don't exit()! And describe command params right. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* Cortex-M3: expose most DWT registersDavid Brownell2009-11-051-21/+142
| | | | | | | | | | | | | | | | | | | | | | | Expose most DWT registers via Tcl; there are a few more, but those are mostly for profiling along with the ITM. Having this set available enables operations which aren't possible with just the standard watchpoint operations. The cycle counter may be interesting. Turn it on after reset by setting the LSB of the dwt_ctrl register, and it counts CPU clocks. You can program the comparator 0 watchpoint to trigger on a given cycle count, rather than a data address. Likewise, comparator 1 may be able to match data values given address matches from one or two other comparators. (Not all hardware supports this capability though; try it. That is something the standard watchpoint methods should eventually handle, for the single address case.) Minor cleanup: remove needless functional indirection for exposing the v7m architctural registers. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* Cortex-M3: minor cleanupDavid Brownell2009-11-051-10/+4
| | | | | | | | | | | There's no reason to read which interrupts are enabled from the NVIC; that state isn't used. Plus, it's highly dynamic since firmware can change it at any time; remove the support for those state records. Remove duplicate definition of DWT_CTRL address; shrink a line. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* Cortex-M3: DWT cleanup/fixesDavid Brownell2009-11-051-56/+115
| | | | | | | | | | | | | Fix the watchpoint error checks, and do them in add(), not later in set() when it's mostly too late. Support the full range of watchpoint sizes (1 to 32K bytes each), and check alignments. Minor cleanup of DWT access: shrink lines, use "+" for address calculations, comment a few issues. Add debug message reporting DWT capabilities, matching the message for FBP, and some minor code and spec review comments. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* target: add target->type->has_mmu fn.Øyvind Harboe2009-11-051-0/+7
| | | | | | | | | improve default target->read/write_phys_memory, produce more sensible error messages if the mmu interface functions have not been implemented yet vs. will not be implemented(e.g. cortex m3). Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* target: remove unused interface fn that clutters codeØyvind Harboe2009-11-051-6/+0
| | | | | | | | | The quit entry point was not being invoked. Just a source of confusion at this point. XScale ran 100x reset upon quit, but that code made no sense, wasn't commented and never invoke. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* debug interface: get rid of unused pre_debug fnØyvind Harboe2009-11-051-3/+0
| | | | | | Removing unused code makes it much less mysterius. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* Cortex-M3: remove exports and forward declsDavid Brownell2009-10-281-161/+144
| | | | | | | | | | | Unneeded exports cause confusion about the module interfaces. Make most functions static, and fix some line-too-long issues. Delete some now-obviously-unused code. The forward decls are just code clutter; move their references later, after the normal declarations. (Or vice versa.) Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* - fix a regression when using cortex_m3 emulated dcc channelntfreak2009-09-011-10/+19
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2659 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net> Tweak disassembly commands:oharboe2009-08-251-12/+16
| | | | | | | | | | | | | | | | | | For ARMv4/ARMv5: - better command parameter error checking - don't require an instruction count; default to one - recognize thumb function addresses - make function static - shorten some too-long lines For Cortex-M3: - don't require an instruction count; default to one With the relevant doc updates. --- Nyet done: invoke the thumb2 disassembler on v4/v5, to better handle branch instructions. git-svn-id: svn://svn.berlios.de/openocd/trunk@2624 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net> Clean up some Cortex-M3 reset handling.oharboe2009-08-191-17/+39
| | | | | | | | | | | | | | - AIRCR_SYSRESETREQ is generic; use it on any system where SRST won't fly, not just on Stellaris-based ones. - Reformat and improve comments about the Stellaris quirk; and xref the only public docs (an email) about the issue. It seems that *most* Stellaris chips have this problem. Tempest parts aren't yet in general sampling; and if rev B silicon for earlier chips exists, it's not very visible yet. git-svn-id: svn://svn.berlios.de/openocd/trunk@2595 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net> Add "cortex_m3 vector_catch" command ↵oharboe2009-08-181-3/+78
| | | | | | | | | | | | | | | | and docs. One minor issue with this is that the core debug support uses this mechanism, then trashes its state over reset. Users can Work around that (for now) by re-assigning the desired config after reset. Also fixes "target halted due to target-not-halted" goof. When we can't describe the reason using OpenOCD's limited vocabulary, say "reason undefined" instead of saying it's not halted. git-svn-id: svn://svn.berlios.de/openocd/trunk@2588 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net>:ntfreak2009-07-211-44/+59
| | | | | | | | | | | | | | | | | | | | | | Clean up treatment of registers in ARMv7-M and Cortex-M3. - At the arch level: * Just list registers and names; don't impose core-specific policy about how they are accessed. * Each register has a symbol. * Remove the register mode field (irrelevant to debugger) - At the core/implementation level: * Just map the registers to their relevant access methods; don't require the arch level to say how that should work (cores other than Cortex-M3 could do it differently). * Don't use undefined bits from register 20. * Use register IDs that are part of the ARMv7-M interface. In short, there's now a real distinction between the arch and core layers. git-svn-id: svn://svn.berlios.de/openocd/trunk@2554 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net>:ntfreak2009-07-211-30/+17
| | | | | | | | | Revert parts of the previous ARMv7-M register patch. It turns out that part of the issue is a documentation problem for the Cortex-M3 r1 parts. So for the rest, simpler fixes are possible (in followup patch). git-svn-id: svn://svn.berlios.de/openocd/trunk@2552 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Magnus Lundin <lundin@mlu.mine.nu>, Oyvind Harboe <oyvind.harboe@zylin.com>, ↵zwelch2009-07-161-18/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | David Brownell <david-b@pacbell.net>: Some cleanup of the ARMv7-M support: - Reference the relevant ARMv7-M ARM doc (DDI 0405C to non-Vendors), and update the Cortex-M3 doc refs (DDI 0337C is no longer available). - Those registers aren't actually general, and some are incorrect (per all public docs anyway). Update comments and code accordingly. * What the Core Debug facility exposes is *implementation-specific* not architectural. These values aren't fully portable. They match Cortex-M3 ... so no current implementation will make trouble, but the next v7m implementation might. * Four of the registers are actually not exposed that way. Before Cortex-M3 r2p0 they are read/written through MRS/MSR instructions. In that newest silicon, they are four bytes in one register, not four separate registers. - Update the CM3 code to report when that one register is available, and not try to access it when it isn't. Also declare the register numbers that an eventual MRS/MSR solution will need to be using. - Stop line wrapping the exception labels. So for parts before r2p0 OpenOCD behavior is effectively unchanged, and still buggy; but for those newer parts a few things might now be correct. Most current Cortex-M3 parts use r1p1 (or earlier); this seems to include most LM3S parts and all STM32 parts. Parts using r2p0 are available, and include fourth generation LM3S parts ("Tempest") plus AT91SAM3 and LPC17xx parts which are now sampling. git-svn-id: svn://svn.berlios.de/openocd/trunk@2543 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net>:zwelch2009-07-151-2/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Initial support for disassembling Thumb2 code. This works only for Cortex-M3 cores so far. Eventually other cores will also need Thumb2 support ... but they don't yet support any kind of disassembly. - Update the 16-bit Thumb decoder: * Understand CPS, REV*, SETEND, {U,S}XT{B,H} opcodes added by ARMv6. (It already seems to treat CPY as MOV.) * Understand CB, CBNZ, WFI, IT, and other opcodes added by in Thumb2. - A new Thumb2 instruction decode routine is provided. * This has a different signature: pass the target, not the instruction, so it can fetch a second halfword when needed. The instruction size is likewise returned to the caller. * 32-bit instructions are recognized but not yet decoded. - Start using the current "UAL" syntax in some cases. "SWI" is renamed as "SVC"; "LDMIA" as "LDM"; "STMIA" as "STM". - Define a new "cortex_m3 disassemble addr count" command to give access to this disassembly. Sanity checked against "objdump -d" output; a bunch of the new instructions checked out fine. git-svn-id: svn://svn.berlios.de/openocd/trunk@2530 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Magnus Lundin Thc cortex_m3_poll function does not identify that a target ↵oharboe2009-07-121-9/+12
| | | | | | | | | | | is running unless we transition from RESET. This patch correctly identifies a running target. Patch made a tad more palatable by David Brownell <david-b@pacbell.net> git-svn-id: svn://svn.berlios.de/openocd/trunk@2510 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Refactor code, create target_state_name()duane2009-06-281-5/+5
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2409 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Add Breakpoint/Watchpoint unique ID to help debug hardware debug register ↵duane2009-06-271-6/+30
| | | | | | leakage git-svn-id: svn://svn.berlios.de/openocd/trunk@2408 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Remove whitespace that occurs before ')'.zwelch2009-06-231-12/+12
| | | | | | | - Replace '[ \t]*[)]' with ')'. git-svn-id: svn://svn.berlios.de/openocd/trunk@2377 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Remove whitespace that occurs after '('.zwelch2009-06-231-5/+5
| | | | | | | - Replace '([ \t]*' with '('. git-svn-id: svn://svn.berlios.de/openocd/trunk@2376 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* - Fixes '[|]' whitespacezwelch2009-06-231-4/+4
| | | | | | | | | | - Replace ')\([|]\)(' with ') \1 ('. - Replace ')\([|]\)\(\w\)' with ') \1 \2'. - Replace '\(\w\)\([|]\)(' with '\1 \2 ('. - Replace '\(\w\)\([|]\)\(\w\)' with '\1 \2 \3'. git-svn-id: svn://svn.berlios.de/openocd/trunk@2374 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* - Fixes '=' whitespacezwelch2009-06-231-4/+4
| | | | | | | | | - Replace ')\(=\)\(\w\)' with ') \1 \2'. - Replace '\(\w\)\(=\)(' with '\1 \2 ('. - Replace '\(\w\)\(=\)\(\w\)' with '\1 \2 \3'. git-svn-id: svn://svn.berlios.de/openocd/trunk@2372 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* - Fixes '<<' whitespacezwelch2009-06-231-2/+2
| | | | | | | | | - Replace ')\(<<\)\(\w\)' with ') \1 \2'. - Replace '\(\w\)\(<<\)(' with '\1 \2 ('. - Replace '\(\w\)\(<<\)\(\w\)' with '\1 \2 \3'. git-svn-id: svn://svn.berlios.de/openocd/trunk@2370 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* - Fixes '!=' whitespacezwelch2009-06-231-1/+1
| | | | | | | | | - Replace ')\(!=\)\(\w\)' with ') \1 \2'. - Replace '\(\w\)\(!=\)(' with '\1 \2 ('. - Replace '\(\w\)\(!=\)\(\w\)' with '\1 \2 \3'. git-svn-id: svn://svn.berlios.de/openocd/trunk@2363 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* - Replace 'while(' with 'while ('.zwelch2009-06-231-2/+2
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2358 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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