summaryrefslogtreecommitdiff
path: root/src/target/cortex_m3.c
Commit message (Collapse)AuthorAgeFilesLines
* types: write memory now uses constØyvind Harboe2011-04-011-2/+2
| | | | Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* cortex_m3: allow scripts to override resetAaron Carroll2011-02-021-0/+10
| | | | | | | If a handler for the reset-assert event it present, skip the usual reset handling. This is needed, for example, for board-level resets. Signed-off-by: Aaron Carroll <aaronc@cse.unsw.edu.au>
* error handling: the error number is not part of the user interfaceØyvind Harboe2011-01-031-1/+1
| | | | | | | | Do not propagate error number to user. This is for internal programming purposes only. Error messages to the user is reported as text via LOG_ERROR(). Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* cortex_m3: change cortec_m3 reset_config behaviourSpencer Oliver2010-12-031-18/+2
| | | | | | | | | Currently the cmd 'cortex_m3 reset_config' will overide the default target's 'reset_config'. Chnage the behaviour to use the target 'reset_config' if configured and fallback if not. Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
* cortex_m3: report detected error condition in pollØyvind Harboe2010-11-091-6/+13
| | | | | | | | | | | | If the CPU crashed at some point, poll will discover this. Previously the poll fn would clear the error and print a warning, rather than propagating the error. The new behavior is to report the error back up, but still clear the error. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* Make systesetreq typos read sysresetreq insteadPeter Stuge2010-10-251-1/+1
| | | | Signed-off-by: Peter Stuge <peter@stuge.se>
* propagate return status of set_breakpoint() up call chainMike Dunn2010-09-131-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | Hi everyone, I figured since I was poking around in the breakpoint code on other arches, I'd add this change to those arches that don't do it already. This patch propagates the return code of <arch>_set_breakpoint() up the call stack. This ensures that the higher layer breakpoint infrastructure is aware that an error ocurred, in which case the breakpoint is not recorded. Normally I wouldn't touch code that I can't test, but the code is very uniform across architectures, and the change is rather benign, so I figured after careful inspection that it is safe. If the maintainers or others think this is imprudent, the patch can be dropped. Also changed the error code to something more appropriate in two cases where hardware resources are unavailable. Comments and criticisms of course gratefully received. Mike Signed-off-by: Mike Dunn <mikedunn@newsguy.com> Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* cortex m3: add cortex_m3 reset_config cmdSpencer Oliver2010-08-311-51/+75
| | | | | | | | | | | | This new cmd adds the ability to choose the Cortex-M3 reset method used. It defaults to using SRST for reset if available otherwise it falls back to using NVIC VECTRESET. This is known to work on all cores. Move any luminary specific reset handling to the stellaris cfg file. Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
* arm_adi_v5: mem_ap_write error propagationØyvind Harboe2010-07-191-20/+71
| | | | Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* arm_adi_v5: error propagation of mem_ap_read_atomic_u32 failureØyvind Harboe2010-07-191-15/+40
| | | | Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* mem_ap_read_u32 error propagationØyvind Harboe2010-07-191-11/+33
| | | | Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* arm_adi_v5: add error propagation for dap_setup_accessportØyvind Harboe2010-07-191-4/+12
| | | | Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* debug: debug entry error propagationØyvind Harboe2010-07-191-2/+9
| | | | Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* arm7/9: remove unused post_restore_contextØyvind Harboe2010-03-171-1/+0
| | | | | | | Unused. If something should happen after context restore, then the calling code can just do it afterwards. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* ADIv5 share DAP command supportDavid Brownell2010-03-051-21/+23
| | | | | | | | | | | | | | Get rid of needless and undesirable code duplication for all the DAP commands (resolving a FIXME) ... there's no need for coreas to have private copies of that stuff. Stick a pointer to the DAP in "struct arm", letting common code get to it. Also rename the "swjdp_info" symbol; just call it "dap". This is an overall code shrink. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* rename "swjdp_common" as "adiv5_dap"David Brownell2010-03-041-21/+21
| | | | | | | | | | | | | This partially corrects an inappropriate name choice (and its associated FIXME). There are still too many variables named "swjdp", bug little current code actually relies on them referencing an SWJ-DP instead of some other flavor of DAP. Only the two new dap_to{swd,jtag}() calls could behave differently on an SWJ-DP instead of a SW-DP or a JTAG-DP. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ADIv5: use new DAP ops for AP read/writeDavid Brownell2010-03-021-4/+12
| | | | | | | | | | | | | | | | | | | Make ADIv5 internals use the two new transport-neutral calls for reading and writing DP registers; and do the same for external callers. Also, bugfix some of their call sites to handle the fault returns, instead of ignoring them. Remove most of the JTAG-specific calls, using their code as the bodies of the JTAG-specific implementation for the new methods. NOTE that there's a remaining issue: mem_ap_read_buf_u32() makes calls which are JTAG-specific. A later patch will need to remove those, so JTAG-specific operations can be removed from this file, and so that SWD support will be able to properly drop in as just a transport layer to the ADIv5 infrastructure. (The way read results are posted may need some more attention in the transport-neutrality interface.) Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ADIv5: use new dap_run() operationDavid Brownell2010-03-021-8/+15
| | | | | | | | | | Make ADIv5 use one of the new transport-neutral interfaces: call dap_run(), not jtagdp_transaction_endcheck(). Also, make that old interface private; and bugfix some of its call sites to handle the fault returns, instead of ignoring them. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* semihosting: add armv7m semihosting supportSpencer Oliver2010-02-281-1/+4
| | | | | | | do_semihosting and arm_semihosting now check the core type and use the generic arm structure. Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
* CortexM3: move disassemble cmd to arm cmd groupSpencer Oliver2010-02-281-51/+0
| | | | | | | Rather than using a Cortex disassemble cmd, we now use the arm generic version. Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
* ADIv5: remove ATOMIC/COMPOSITE interface modeDavid Brownell2010-02-211-4/+0
| | | | | | | | | | | | | This removes context-sensitivity from the programming interface and makes it possible to know what a block of code does without needing to know the previous history (specifically, the DAP's "trans_mode" setting). The mode was only set to ATOMIC briefly after DAP initialization, making this patch be primarily cleanup; almost everything depends on COMPOSITE. The transactions which shouldn't have been queued were already properly flushing the queue. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ADIv5 clean up AP selection and register cachingDavid Brownell2010-02-211-4/+3
| | | | | | | | | | | | | | | | | | | Handling of AP (and AP register bank) selection, and cached AP registers, is pretty loose ... start tightening it: - It's "AP bank" select support ... there are no DP banks. Rename. + dap_dp_bankselect() becomes dap_ap_bankselect() + "dp_select_value" struct field becomes "ap_bank_value" - Remove duplicate AP cache init paths ... only use dap_ap_select(), and don't make Cortex (A8 or M3) cores roll their own code. - For dap_ap_bankselect(), pass up any fault code from writing the SELECT register. (Nothing yet checks those codes.) - Add various bits of Doxygen Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: keep a handle to the PCDavid Brownell2010-02-211-3/+3
| | | | | | | | | | | | | | | | Keep a handle to the PC in "struct arm", and use it. This register is used a fair amount, so this is a net minor code shrink (other than some line length fixes), but mostly it's to make things more readable. For XScale, fix a dodgy sequence while stepping. It was initializing a variable to a non-NULL value, then updating it to handle the step-over-active-breakpoint case, and then later testing for non-NULL to see if it should reverse that step-over-active logic. It should have done like ARM7/ARM9 does: init to NULL. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARMv7-M: start using "struct arm"David Brownell2010-02-211-2/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | This sets up a few of the core "struct arm" data structures so they can be used with ARMv7-M cores. Specifically, it: - defines new ARM core_modes to match the microcontroller modes (e.g. HANDLER not IRQ, and two types of thread mode); - Establishes a new microcontroller "core_type", which can be used to make sure v7-M (and v6-M) cores are handled right; - adds "struct arm" to "struct armv7m" and arranges for the target_to_armv7m() converter to use it; - sets up the arm.core_cache and arm.cpsr values - makes the Cortex-M3 code maintain arm.map and arm.core_mode. This is currently set up as a parallel data structure, primarily to minimize special cases for the semihosting support with microcontroller profile cores. Later patches can rip out the duplicative ARMv7-M support and start reusing core ARM code. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ADIv5: cleanup, rename swjdp_transaction_endcheck()David Brownell2010-01-291-4/+4
| | | | | | | | | | | | | | | | Make messages reference "DAP" if they're actually transport-agnostic, or "JTAG-DP" when they're JTAG-specific. Saying SWJ-DP is often wrong (on most Cortex-A8 chips) and is confusing even if correct (since we don't yet support SWD). Rename a JTAG-specific routine to jtagdp_transaction_endcheck() to highlight that it's JTAG-specific, and that identify DAP clients undesirably depending on JTAG. (They will all need to change for SWD support.) Shrink a few overlong lines of code. Copy a comment from code removed in a previous patch (for the ARMv7-M "dap baseaddr" command). Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* Cortex-M3: report lockup, and recoverDavid Brownell2010-01-271-0/+15
| | | | | | | | | | | | ARMv7-M defines a "lockup" state that's entered in certain double fault sequences which can't be recovered from without external help. OpenOCD has previously ignored this. Issue a diagnostic saying the chip has locked up, and force exit from this state by halting the core. It's not clear this is the best way to handle lockup; but there should now be less confusion. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* BUILD: remove cygwin gcc 3.4.4 build warningsSpencer Oliver2010-01-201-2/+2
| | | | Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
* ARMV7M: handle bkpt instruction on resume/stepSpencer Oliver2010-01-201-2/+23
| | | | | | | | | | Skip over a bkpt instruction if found on resume/step. Only software breakpoints known to OpenOCD are currently handled. So this handles the special case of either a user added bkpt or library added, eg. semi-hosting support. Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
* Cortex-M3: improved core exception handlingDavid Brownell2010-01-131-21/+24
| | | | | | | | | | | | | | | | | | | | | | This updates three aspects of debugger/exception interactions: - Save the user's "vector_catch" setting, and restore it after reset. Previously, it was obliterated (rather annoyingly) each time. - Don't catch BusFault and HardFault exceptions unless the user says to do so. Target firmware may need to handle them. - Don't modify SHCSR to prevent escalating BusFault to HardFault. Target firmware may expect to handle it as a HardFault. Those simplifications fix several bugs. In one annoying case, OpenOCD would cause the target to lock up on ome faults which triggered after the debugger disconnected. NOTE: a known remaining issue is that OpenOCD can still leave DEMCR set after an otherwise-clean OpenOCD shutdown. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARMv7: help/usage updatesDavid Brownell2010-01-071-6/+6
| | | | | | | | | | | | | | | | | | Provide helptext which was sometimes missing; update some of it to be more accurate. Usage syntax messages have the same EBNF as the User's Guide; there should be no angle brackets in either place. Don't use "&function"; functions are like arrays, their address is their name. Shrink some overlong lines, remove some empties. Add a couple comments about things that should change: those extra TCK cycles for MEM-AP reads are in the wrong place (that might explain some problems we've seen); the DAP command tables should be shared, not copied. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* Cortex-M3: minor breakpoint cleanupDavid Brownell2010-01-021-12/+25
| | | | | | | Shrink some lines, add some comments, simplify some tests. During debug startup, log the core revision level too. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* streamline and document helptext mode displaysDavid Brownell2010-01-021-1/+1
| | | | | | | | | | | | | | | | | | | Most commands are usable only at runtime; so don't bother saying that, it's noise. Moreover, tokens like EXEC are cryptic. Be more clear: highlight only the commands which may (also) be used during the config stage, thus matching the docs more closely. There are - Configuration commands (per documentation) - And also some commands that valid at *any* time. Update the docs to note that "help" now shows this mode info. This also highlighted a few mistakes in command configuration, mostly commands listed as "valid at any time" which shouldn't have been. This just fixes ones I noted when sanity testing. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* Cortex-M3: cleanupDavid Brownell2009-12-201-45/+111
| | | | | | | | | | | | Misc: - Introduce some "struct reg" temporaries, for clarity - Shorten lines - Add some missing whitespace - Clean up comments - Add notes about some fault handling issues - Most of these errata workarounds are for *OLD* chip revisions Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* target: move 'extern' decls to *.h filesDavid Brownell2009-12-081-5/+0
| | | | | | | | The exception being declarations for drivers. Those should be split out in some clean way -- like driver add/remove calls made by initialization code -- but that's for another day. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: list number of HW breakpoints/watchpointsDavid Brownell2009-12-071-0/+6
| | | | | | | | | | | | | | | When starting up, say how many hardware breakpoints and watchpoints are available on various targets. This makes it easier to tell GDB how many of those resources exist. Its remote protocol currently has no way to ask OpenOCD for that information, so it must configured by hand (or not at all). Update the docs to mention this; remove obsolete "don't do this" info. Presentation of GDB setup information is still a mess, but at least it calls out the three components that need setup. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: move opcode macros to <target/arm_opcodes.h>David Brownell2009-12-071-1/+2
| | | | | | | | | | | | | | | Move the ARM opcode macros from <target/armv4_5.h>, and a few Thumb2 ones from <target/armv7m.h>, to more appropriate homes in a new <target/arm_opcodes.h> file. Removed duplicate opcodes from that v7m/Thumb2 set. Protected a few macro argument references by adding missing parentheses. Tightening up some of the line lengths turned up a curious artifact: the macros for the Thumb opcodes are all 32 bits wide, not 16 bits. There's currently no explanation for why it's done that way... Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* Cortex-M3: don't chain "struct arm" commandsDavid Brownell2009-11-281-3/+0
| | | | | | | | | | | | Those commands presume support for the "classic" set of CPU modes (FIQ, supervisor, IRQ, etc) ... which aren't supported by the ARMv7-M or ARMv6-M architectures. They also presume a "struct arm" base type, which this code doesn't use. We haven't cleaned up the register handling enough to be able to share any of those "base" methods. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* target: uplevel add_{break,watch}point() error checksDavid Brownell2009-11-281-7/+0
| | | | | | | | | | | | | | | | | | | | | | | | In target_type.h it's documented that the target must be halted for add_breakpoint() ... and with slight ambiguity, also for its add_watchpoint() sibling. So rather than verifying that constraint in the CPU drivers, do it in the target_add_{break,watch}point() routines. Add minor paranoia on the remove_*point() paths too: save the return value, and print it out in in the LOG_DEBUG message in case it's nonzero. Note that with some current cores, like all ARMv7 ones I've looked at, there's no technical issue preventing watchpoint or breakpoint add/remove operations on active cores. This model seems deeply wired into OpenOCD though. ALSO: the ARM targets were fairly "good" about enforcing that constraint themselves. The MIPS ones were relied on other code to catch such stuff, but it's not clear such code existed ... keep an eye out for new issues on MIPS. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* remove target_type register_command callbackZachary T Welch2009-11-241-7/+7
| | | | | | Uses chaining of command_registration structures to eliminate all target_type register_callback routines. Exports the command_handler registration arrays for those target types that are used by others.
* cortex_m3: use register_commands()Zachary T Welch2009-11-241-19/+36
|
* use COMMAND_REGISTER macroZachary T Welch2009-11-241-4/+4
| | | | | Replaces direct calls to register_command() with a macro, to allow its parameters to be changed and callers updated in phases.
* target: create/use register_cache_invalidate()David Brownell2009-11-191-5/+6
| | | | | | | | | | | | | | | Create a generic register_cache_invalidate(), and use it to replace three all-but-identical core-specific routines: - armv4_5_invalidate_core_regs() - armv7m_invalidate_core_regs - mips32_invalidate_core_regs() too. Make cache->num_regs be unsigned, avoiding various errors. Net code shrink and simplification. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* use COMMAND_PARSE_ON_OFF where appropriateZachary T Welch2009-11-181-12/+5
| | | | Updates all command parsing of "on" and "off" arguments.
* ARM: only use one set of dummy FPA registersDavid Brownell2009-11-171-0/+3
| | | | | | | | | | | | | | | | All ARM cores need to provide obsolete FPA registers in their GDB register dumps. (Even though cores with floating point support now generally use some version of VFP...) Clean up that support a bit by sharing the same dummy registers, and removing the duplicate copies. Eventually we shouldn't need to export those dummies. (This makes the ARMv7-M support include the armv4_5 header, and cleans up related #includes, but doesn't yet use anything from there except those dummies.) Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* command_handler: change 'cmd_ctx' to CMD_CTXZachary T Welch2009-11-171-12/+15
| | | | Convert all command handler 'cmd_ctx' parameter usage with CMD_CTX.
* command_handler: change 'args' to CMD_ARGVZachary T Welch2009-11-171-8/+8
| | | | | This patch converts all instances of 'args' in COMMAND_HANDLER routines to use CMD_ARGV macro.
* command_handler: change to 'argc' to CMD_ARGCZachary T Welch2009-11-171-7/+7
| | | | | This patch converts all instances of 'argc' in COMMAND_HANDLER routines to use CMD_ARGC.
* target: simplify register get/set opsDavid Brownell2009-11-171-6/+5
| | | | | | | | | | | No need to indirect from registered integers to pointers. Just stash the pointers directly in the register struct, and don't even bother registering. This is a small code shrink, speeds register access just a smidgeon, and gets rid of another rude exit() path. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* Cortex-M3: don't exit()David Brownell2009-11-161-24/+10
| | | | | | | Get rid of undesirable and needless exit() calls from the Cortex-M3 support. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* move ARRAY_SIZE macro to types.hZachary T Welch2009-11-161-5/+2
| | | | | | | | The ARRAY_SIZE macro was defined in several target files, so move it to types.h. This patch also removes two other identical macros: DIM (from jtag.h) and asizeof (from arm11.h).
generated by cgit v1.2.3 (git 2.39.1) at 2024-05-18 21:04:28 +0000