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path: root/src/target/cortex_a8.c
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* target: no implicit #includes of "register.h"David Brownell2009-11-161-2/+1
* target: don't implicitly include "breakpoint.h"David Brownell2009-11-161-0/+1
* ARM: memory utils aren't ARM7/ARM9 dependentDavid Brownell2009-11-151-2/+3
* target: make "examined" flag be per-targetDavid Brownell2009-11-151-3/+3
* command_t -> struct commandZachary T Welch2009-11-131-1/+1
* command_context_t -> struct command_contextZachary T Welch2009-11-131-2/+2
* target_t -> struct targetZachary T Welch2009-11-131-47/+47
* target_type_t -> struct target_typeZachary T Welch2009-11-131-1/+1
* armv4_5_common_t -> struct armZachary T Welch2009-11-131-1/+1
* cortex_a8_wrp_t -> struct cortex_a8_wrpZachary T Welch2009-11-131-1/+1
* cortex_a8_brp_t -> struct cortex_a8_brpZachary T Welch2009-11-131-3/+3
* breakpoint_t -> struct breakpointZachary T Welch2009-11-131-9/+9
* working_area_t -> struct working_areaZachary T Welch2009-11-131-1/+1
* reg_cache_t -> struct reg_cacheZachary T Welch2009-11-131-1/+1
* cortex_a8_common_t -> struct cortex_a8_commonZachary T Welch2009-11-131-11/+11
* armv7a_common_t -> struct armv7a_commonZachary T Welch2009-11-131-23/+23
* swjdp_common_t -> struct swjdp_commonZachary T Welch2009-11-131-18/+18
* jtag_tap_t -> struct jtag_tapZachary T Welch2009-11-131-1/+1
* use COMMAND_HANDLER macro to define all commandsZachary T Welch2009-11-131-4/+2
* Cortex-A8: fix indentDavid Brownell2009-11-131-28/+28
* cortex_a8: remove declarations, use static keywordZachary T Welch2009-11-111-106/+82
* Cortex-A8: use the new inheritance/nesting schemeDavid Brownell2009-11-051-105/+41
* cortex_a8: add mrc mcr interface.Øyvind Harboe2009-11-051-0/+29
* target: remove unused interface fn that clutters codeØyvind Harboe2009-11-051-1/+0
* debug interface: get rid of unused pre_debug fnØyvind Harboe2009-11-051-4/+0
* Cleanup: nuke trailling whitespacesYauheni Kaliuta2009-10-131-10/+10
* It is not possible to invalidate I-Cache on memory writes while the target is...mlu2009-10-021-0/+3
* Make sure that DSCR_DTR_RX is not full before writingmlu2009-10-021-0/+27
* More error reporting in Cortex_a8 execute_opcodemlu2009-10-021-0/+6
* Added asser_reset and deassert_reset for cortex_a8mlu2009-10-021-2/+2
* Added asser_reset and deassert_reset for cortex_a8mlu2009-10-021-22/+56
* Remove annoying end-of-line whitespace from most src/*dbrownell2009-09-211-4/+4
* Avoid cache invalidation when writing to hardware debug registersmlu2009-09-191-4/+19
* Move Cortex A8 debug access initialisation from omap3530.cfg to cortex_a8.cmlu2009-09-181-28/+39
* Use a variable armv7a->debug_base instead of hardedcoded OMAP3530_DEBUG_BASEmlu2009-09-161-28/+31
* Check return values to avoid infinite wait in loop on error.mlu2009-09-141-4/+8
* Cache invalidation when writing to memorymlu2009-09-141-0/+18
* Fix argument passing in cortex_a8_write_cp.mlu2009-09-131-2/+1
* Load PC with bit 0 set to 1 when resuming to say in Thumb instruction state.mlu2009-09-081-2/+7
* Improved handling of instruction set state, helps for debugging Thumb state.mlu2009-09-071-7/+5
* Matt Hsu <matt@0xlab.org> This patch simply enables the halting debug mode.oharboe2009-09-041-0/+7
* Matt Hsu <matt@0xlab.org> Tidy up the bit-offset operation for DSCR registeroharboe2009-09-041-6/+6
* Matt Hsu <matt@0xlab.org> and Holger Hans Peter Freyther <zecke@selfish.org> ...oharboe2009-08-261-5/+23
* Matt Hsu <matt@0xlab.org> and Holger Hans Peter Freyther <zecke@selfish.org> ...oharboe2009-08-261-1/+1
* Matt Hsu <matt@0xlab.org> cortex_a8_exec_opcode is writing the ARM instructio...oharboe2009-08-261-1/+9
* Matt Hsu <matt@0xlab.org> Wait for the DTRRX to be full before reading it. Re...oharboe2009-08-261-4/+9
* Matt Hsu <matt@0xlab.org> and Holger Hans Peter Freyther <zecke@selfish.org> ...oharboe2009-08-261-0/+8
* - fix build warningsntfreak2009-08-251-16/+16
* David Brownell The rest of the Cortex-A8 support from Magnus: replace the pre...oharboe2009-08-251-60/+1303
* Remove whitespace that occurs after '('.zwelch2009-06-231-2/+2
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