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* It is not possible to invalidate I-Cache on memory writes while the target is...mlu2009-10-021-0/+3
* Make sure that DSCR_DTR_RX is not full before writingmlu2009-10-021-0/+27
* More error reporting in Cortex_a8 execute_opcodemlu2009-10-021-0/+6
* Added asser_reset and deassert_reset for cortex_a8mlu2009-10-021-2/+2
* Added asser_reset and deassert_reset for cortex_a8mlu2009-10-021-22/+56
* Minor ETB and ETM bugfixes and doc updatesdbrownell2009-10-022-54/+82
* ARMv7A: Report fault status registers when in Abort statemlu2009-10-011-0/+23
* Add DSCR_DTR_RX_FULL bit definemlu2009-09-301-0/+1
* ARM11 command handling fixesdbrownell2009-09-291-41/+41
* ETM: fix build issue on MinGW.dbrownell2009-09-291-20/+21
* ETB: cleanup needless symbol exports and forward decls.dbrownell2009-09-292-40/+35
* Shrink symbols exported from arm9tdmi.c and remove a forward ref.dbrownell2009-09-281-35/+38
* When setting up an ETM, cache its ETM_CONFIG register. Thendbrownell2009-09-232-51/+178
* Start cleaning up ETM register handling. On one ARM926 ETM+ETBdbrownell2009-09-232-167/+176
* Initial ETM cleanups. Most of these are cosmetic:dbrownell2009-09-232-83/+113
* Remove annoying end-of-line whitespace from most src/*dbrownell2009-09-2111-63/+63
* Debug message updates:dbrownell2009-09-201-12/+1
* Added CPUDBG_WCR_BASE definemlu2009-09-191-0/+1
* Avoid cache invalidation when writing to hardware debug registersmlu2009-09-191-4/+19
* Minor behavior fixes for the two JTAG reset events (C/internal,dbrownell2009-09-191-1/+2
* Move Cortex A8 debug access initialisation from omap3530.cfg to cortex_a8.cmlu2009-09-181-28/+39
* srst_gates_jtag option. at91sam9260 needs retesting, and possibly srst_gates_...oharboe2009-09-171-1/+12
* The "arm9tdmi.c" file is more of a generic ARM9 support file:dbrownell2009-09-171-3/+17
* Remove unused varables (moved to armv7a)mlu2009-09-161-5/+0
* Use a variable armv7a->debug_base instead of hardedcoded OMAP3530_DEBUG_BASEmlu2009-09-161-28/+31
* Define debug_base, debug_ap, memory_ap in armv7a_common_tmlu2009-09-151-0/+7
* Updated mode string list.mlu2009-09-151-2/+2
* Definy symbolic values for VA to PA address translation operationsmlu2009-09-151-0/+10
* Check return values to avoid infinite wait in loop on error.mlu2009-09-141-4/+8
* Cache invalidation when writing to memorymlu2009-09-141-0/+18
* More CortexA8 debug register definitions.mlu2009-09-131-0/+4
* Fix argument passing in cortex_a8_write_cp.mlu2009-09-131-2/+1
* David Brownell <david-b@pacbell.net> oharboe2009-09-123-26/+40
* Nicolas Pitre <nico@cam.org> put feroceon target definition at the end so to ...oharboe2009-09-111-86/+79
* Nicolas Pitre <nico@cam.org> Dragonite supportoharboe2009-09-114-20/+76
* spelling mistakeoharboe2009-09-111-2/+2
* do not use dynamically sized stack arrays, not compatible with embedded OS'soharboe2009-09-111-10/+24
* registering a target event twice caused infinite loop. Same bug as in jtag/co...oharboe2009-09-111-4/+9
* Nicolas Pitre <nico@cam.org> tighten error checking in bulk_writeoharboe2009-09-111-4/+15
* Alexei Babich <a.babich@rez.ru> fix problems with unecessary tailend byte acc...oharboe2009-09-101-0/+12
* David Brownell <david-b@pacbell.net> oharboe2009-09-094-4/+20
* Report correct core instruction state for ARMv/A targetsmlu2009-09-081-1/+1
* Load PC with bit 0 set to 1 when resuming to say in Thumb instruction state.mlu2009-09-081-2/+7
* David Brownell <david-b@pacbell.net> oharboe2009-09-081-0/+86
* David Brownell <david-b@pacbell.net> oharboe2009-09-081-35/+137
* Improved handling of instruction set state, helps for debugging Thumb state.mlu2009-09-071-7/+5
* Mahr, Stefan <Stefan.Mahr@sphairon.com> removes the endianness swapping in mi...oharboe2009-09-041-44/+0
* Matt Hsu <matt@0xlab.org> This patch simply enables the halting debug mode.oharboe2009-09-041-0/+7
* more debug output for breakpointsoharboe2009-09-041-2/+10
* Matt Hsu <matt@0xlab.org> Tidy up the bit-offset operation for DSCR registeroharboe2009-09-042-6/+15
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