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* target.cfg: TAP id for Hilscher netX 500David Brownell2009-11-201-9/+7
| | | | | | Based on email from "Martin Kaul <martin.kaul@leuze.de>". Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* update 'nand device' usage in scriptsZachary T Welch2009-11-193-4/+8
| | | | Add $_FLASHNAME variable to update 'nand device' command syntax.
* update 'flash bank' usage in scriptsZachary T Welch2009-11-1958-69/+138
| | | | | Sets $_FLASHNAME to "$_CHIPNAME.flash" and passes it as the first argument to 'flash bank'.
* ARM: "armv4_5" command prefix becomes "arm"David Brownell2009-11-165-5/+5
| | | | | | | | | | Rename the "armv4_5" command prefix to straight "arm" so it makes more sense for newer cores. Add a simple compatibility script. Make sure all the commands give the same "not an ARM" diagnostic message (and fail properly) when called against non-ARM targets. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM11: ETM + ETB supportDavid Brownell2009-11-134-4/+15
| | | | | | | | | | | Kick in ETM (and ETB) support for ARM11. Tested on OMAP 2420, so update that configuration. (That's an ARM1136ejs, ETB, OpenGL ES1.1, C55x DSP, etc.) Also update the other ARM11 ETM + ETB targets in the tree to set up these modules. (Not tested.) Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* iMX2* + ETB targets: hook up ETM and ETBDavid Brownell2009-11-132-1/+10
| | | | | | | ARM9 cores with an ETB will have a matching ETM. Hook them both up by default. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* target.cfg: label ETBs correctlyDavid Brownell2009-11-135-28/+26
| | | | | | | | | | | | | | | | | | Various cores with an ETB have its TAP misnamed ... either as a boundary scan TAP or as the iMX "Secure JTAG Controller" (which is, among other things, a JRC that could be used to shorten scan chains). Use the correct name for these TAPs, which we can recognize since their IDs were assigned by ARM and these chips all document the presence of an ETB. The 0x2b900f0f is ETB11; the 0x1b900f0f is an older module, just called "ETB". Also shrink the ETB's IR configuration; the default IR-Capture value is fine, and the mask can specify that all four bits are safe to check (per ARM documentation). Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* target.cfg: (re)move some bogus reset_config linesDavid Brownell2009-11-105-13/+3
| | | | | | | General rule, this is all board-specific and doesn't belong in target config files. Some of these were just cosmetic. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* stm32.cfg: remove reset_configThomas Kindler2009-11-101-3/+0
| | | | | | | | | | | | | | | Here's a patch for the double-reset problem on STM32. I've tested downloading and debugging with GDB and Eclipse, and everything seems to work fine. This effectively sets reset_config to none. trst_only would also be ok, but that's better left to a board configuration file since not all boards wire it up. The NVIC is used to trigger reset, which at least on this chip also pulses nSRST so the whole system does get rest -- exactly once. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM11: remove old mrc/mcr commandsØyvind Harboe2009-11-103-8/+8
| | | | | | Switch to new commands in config scripts Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* telo.cfg: fix search pathsØyvind Harboe2009-11-102-8/+8
| | | | | | | Add the missing "target/" prefix for scripts in the target folder. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* finish removing deprecated/obsolete commandsDavid Brownell2009-11-096-12/+2
| | | | | | | | | | | | | | | | | | | | It's been about a year since these were deprecated and, in most cases, removed. There's no point in carrying that documentation, or backwards compatibility for "jtag_device" and "jtag_speed", around forever. (Or a few remnants of obsolete code...) Removed a few obsolete uses of "jtag_speed": - The Calao stuff hasn't worked since July 2008. (Those Atmel targets need to work with a 32KHz core clock after reset until board-specific init-reset code sets up the PLL and enables a faster JTAg clock.) - Parport speed controls don't actually work (tops out at about 1 MHz on typical HW). - In general, speed controls need to live in board.cfg files (or sometimes target.cfg files), not interface.cfg ... Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* target.cfg: remove "-work-area-virt 0"David Brownell2009-11-0844-45/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The semantics of "-work-area-virt 0" (or phys) changed with the patch to require specifying physical or virtrual work area addresses. Specifying zero was previously a NOP. Now it means that address zero is valid. This patch addresses three related issues: - MMU-less processors should never specify work-area-virt; remove those specifications. Such processors include ARM7TDMI, Cortex-M3, and ARM966. - MMU-equipped processors *can* specify work-area-virt... but zero won't be appropriate, except in mischievous contexts (which hide null pointer exceptions). Remove those specs from those processors too. If any of those mappings is valid, someone will need to submit a patch adding it ... along with a comment saying what OS provides the mapping, and in which context. Example, say "works with Linux 2.6.30+, in kernel mode". (Note that ARM Linux doesn't map kernel memory to zero ...) - Clarify docs on that "-virt" and other work area stuff. Seems to me work-area-virt is quite problematic; not every operating system provides such static mappings; if they do, they're not in every MMU context... Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* JTAG: support KT-LINK adapterKrzysztof Kajstura2009-11-041-0/+10
| | | | Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* PXA255: support Intel "Lubbock" platformDavid Brownell2009-11-041-0/+110
| | | | | | | | | | | | | | | | | | Config for Intel's "Lubbock" PXA255 development board. Even more so than the PXA255 itself, this is obsolete. AFAIK this was the first generally available development platform for PXA255. Intel stopped providing these after other devel boards became available. One interesting thing about this board from the OpenOCD perspective is probably its flash configuration. Each bank is 32 bits wide, built from two 16-bit StrataFlash chips wired in parallel. This doubles throughput ... it reads/writes 32 bits in the time a single chip takes to write just 16 bits. This conf mostly works, given XScale bugfixes, but has some issues (notably: no access to the on-board SDRAM) flagged by FIXMEs. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* remove "-ircapture 0x1 -irmask 0x1" from stm32.cfgFreddie Chopin2009-11-011-2/+5
| | | | | | | | Gets rid of the runtime warning "stm32.bs: nonstandard IR mask" [dbrownell@users.sourceforge.net: line lengths, note issue, section ref] Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* target.cfg: use $_TARGETNAME for flashFreddie Chopin2009-10-3113-13/+13
| | | | | | | | | This gets rid of runtime warnings from the use of numbers. STM32 and LPC2103 were tested. Other LPC updates are the same, and so are safe. The CFI updates match other tested changes now in the tree. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* Olimex FT2232H JTAG adaptersDimitar Dimitrov2009-10-292-0/+22
| | | | | | | | Add interface configs for two new high speed JTAG adapters from Olimex. They need some other speed related tweaks to work well at high speed. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* Signalyzer: H2 and H4 supportOleg Seiljus2009-10-271-1/+1
| | | | | | | | | | This patch includes partial support for these new JTAG adapters. More complete support will require updates to the libftdi code, for EEPROM access. [dbrownell@users.sourceforge.net: fix whitespace, linelen, etc ] Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* Signalyzer: new config filesOleg Seiljus2009-10-273-0/+33
| | | | | | Add configs for H2, H4, LITE. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* PXA255: force reset configDavid Brownell2009-10-261-0/+4
| | | | | These chips need both SRST and TRST when debugging, and SRST doesn't gate JTAG.
* omap3530: target reset/init improvementsDavid Brownell2009-10-261-15/+25
| | | | | | | | | | | | | | | | | Now I can issue "reset halt" and have everything act smoothly; the vector_catch hardware is obviously not kicking in, but the rest of the reset sequence acts sanely. - TAP "setup" event enables the DAP, not omap3_dbginit (resolving a chicken/egg bug I noted a while back) - Remove stuff from omap3_dbginit which should never be used in event handlers - Cope better with slow clocking during reset Also, stop hard-wiring the target name: use the input params in the standard way, and set up $_TARGETNAME as an output param. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* Fix incorrect line endingsSpencer Oliver2009-10-261-17/+17
| | | | Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
* balloon3 board base configWookey2009-10-261-0/+13
| | | | | | | | | | | This is the very basic board config for the balloon3 board cpu JTAG channel. The rest of the config comprises another 14 .cfg files which I suspect openocd doesn't really want all of. I'm still not sure how to deal with this. I'll post another mail/patch to discuss. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* fix syntax of mww phys.Øyvind Harboe2009-10-255-44/+44
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* mww_phys retired. Replaced by generic mww phys in target.cØyvind Harboe2009-10-215-44/+44
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* Added the faux flash driver and target. Used for testing.Øyvind Harboe2009-10-201-0/+29
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* davinci: add watchdog reset methodDavid Brownell2009-10-191-1/+62
| | | | | | Lightly tested on dm365. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* SDRAM and clock configuration for the SAM9-L9260 board from OlimexDean Glazeski2009-10-181-6/+85
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* Fw: [PATCH] OpenRD board configurationWookey2009-10-142-0/+134
| | | | | | | | | | | | | | | | | Ofrwarded from Ron, who's not subscribed. ----- Forwarded message from Ron <ron@debian.org> ----- From: Ron <ron@debian.org> Date: Wed, 14 Oct 2009 04:50:17 +1030 To: wookey@debian.org Subject: [PATCH] OpenRD board configuration X-Spam-Status: No, score=-3.6 required=4.5 tests=BAYES_00,RCVD_IN_DNSWL_LOW autolearn=ham version=3.2.5 This piggybacks on the 'sheevaplug' layout which uses the same Kirkwood SoC. Signed-off-by: Ron Lee <ron@debian.org>
* iMX target config script's ported from Freescale BSP.Øyvind Harboe2009-10-143-65/+57
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* omap2420.cfg updatesDavid Brownell2009-10-141-5/+6
| | | | | | Remove ircapture/mask attributes. Add "srst_nogate". Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* arm11 seems to gate JTAG when srst is assertedØyvind Harboe2009-10-132-3/+2
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* Xilinx xcr3256.cfg basic config scriptWookey2009-10-121-0/+3
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* burst writes work fine. clean up junk.Øyvind Harboe2009-10-121-3/+0
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* Merge commit 'origin/master'Øyvind Harboe2009-10-121-7/+12
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| * Fix reset delays and tinker with ID'sWookey2009-10-101-7/+12
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* | Supply default reset_config statement to make target scripts useful ↵Øyvind Harboe2009-10-122-1/+4
|/ | | | standalone and provide sensible default
* Merge commit 'origin/master'Øyvind Harboe2009-10-091-3/+32
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| * make PXA255 targets enumerate sort-of-OKDavid Brownell2009-10-081-3/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Startup now mostly works, except that the initial target state is "unknown" ... previously, it refused to even start. Getting that far required fixing the ircapture value (which can never have been correct!) and the default JTAG clock rate, then providing custom reset script. The "reset" command is still iffy. DCSR updates, and loading the debug handler, report numerous DR/IR capture failures. But once that's done, "poll" reports that the CPU is halted (which it shouldn't be, this was "reset run"!), due to the rather curious reason "target-not-halted". Summary: you still can't debug these parts, but it's closer. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* | Added tip in documentation on how to translate quirky syntaxØyvind Harboe2009-10-091-0/+3
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* Function to flash SheevaPlug u-boot sectorsRabeeh Khoury2009-10-081-0/+11
| | | | | This function is used by the SheevaPlug installer to flash the erase and re-flash the U-Boot environment in the NAND Flash.
* initial builds of OSK5912 boards need srst_pulls_trstDavid Brownell2009-10-081-0/+4
| | | | | | | | | | | | This is clearly noted in the hardware spec (section 5.2.3); it works around a chip erratum: "If the MPU_RESET signal is used, it may cause the EMIFS bus to lock." I seem to have a board with such an initial build. The chip is labeled XOMAP. Presumably, parts without that "X" prefix (eXperimental) resolve this. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* make OMAP5912 resets more reliableDavid Brownell2009-10-071-0/+2
| | | | | | | Without some extra delay after releasing SRST, we seemed to be trying to talk to the TAP before it was ready to respond. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* iMX25 target supportJohn Rigby2009-10-071-0/+41
| | | | Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* first stab at imx35 reset init scriptoharboe2009-10-071-0/+272
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2817 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* remove recrusive reset invocation from reset init callbackoharboe2009-10-071-5/+0
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2816 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Add basic support for DM6446 EVM board.dbrownell2009-10-061-0/+74
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2808 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Dragonite target scriptdbrownell2009-10-061-0/+31
| | | | | | | From: Nicolas Pitre <nico@fluxnic.net> git-svn-id: svn://svn.berlios.de/openocd/trunk@2806 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* stop using targetnumoharboe2009-10-061-1/+1
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2804 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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