o Using a record for the mcu bus.

6 files changed, 277 insertions, 83 deletions

diff --git a/vhdl/ice.vhd b/vhdl/ice.vhd
new file mode 100644
index 0000000..8cbff92
--- /dev/null
+++ b/vhdl/ice.vhd
@@ -0,0 +1,42 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.mcu.all;
+
+entity ice is
+  port (
+    mcu_in              : in mcu_in;
+    bit_out             : out std_logic;
+    oe                  : in std_logic;
+    ce                  : in std_logic;
+    we                  : in std_logic
+  );
+end ice;
+
+architecture behaviour of ice is
+  signal ah             : std_logic_vector(15 downto 8);
+  signal al             : std_logic_vector(7 downto 0);
+  signal d              : std_logic_vector(7 downto 0);
+
+  signal ram_address    : std_logic_vector(14 downto 0);
+begin
+  mcu_interface : entity work.mcu_interface(behaviour) port map(
+    mcu_in,
+    bit_out,
+    ah,
+    al,
+    d,          -- d_out,
+    d           -- d_in
+  );
+
+  address : ram_address <= ah(14 downto 8) & al;
+
+  ram : entity work.as7c256a port map(
+    address => ram_address,
+    dataio => d,
+    oe_bar => oe,
+    ce_bar => ce,
+    we_bar => we
+  );
+
+end;
diff --git a/vhdl/ice_tb.vhd b/vhdl/ice_tb.vhd
new file mode 100644
index 0000000..dae94f4
--- /dev/null
+++ b/vhdl/ice_tb.vhd
@@ -0,0 +1,28 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.mcu.all;
+
+entity ice_tb is
+end;
+
+architecture behavior of ice_tb is
+  signal mcu_in         : mcu_in;
+  signal bit_out        : std_logic;
+  signal oe             : std_logic := disable;
+  signal ce             : std_logic := enable;
+  signal we             : std_logic := disable;
+begin
+  ice : entity work.ice port map(
+    mcu_in, bit_out, oe, ce, we
+  );
+
+  stimulus : process
+  begin
+    mcu_in <= mcu_in_initial;
+
+    write_ram(mcu_in, we, "10100101", "0000000000000001");
+    wait;
+  end process;
+
+end;
diff --git a/vhdl/mcu.vhd b/vhdl/mcu.vhd
new file mode 100644
index 0000000..e20f4f6
--- /dev/null
+++ b/vhdl/mcu.vhd
@@ -0,0 +1,124 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee_proposed;
+use ieee_proposed.std_logic_1164_additions.all;
+
+-- use work.mcu.all;
+
+package mcu is
+
+  type mcu_in is record
+    -- SPI interface
+    bit_in              : std_logic;
+    bit_clk             : std_logic;
+
+    -- Strobed to latch data from SPI buffer to AH, AL and Dout
+    byte_out_clk        : std_logic;
+    -- Store to latch data from D bus to Din
+    byte_in_clk         : std_logic;
+    -- Enable AH and AL, active low
+    a_oe                : std_logic; 
+    -- Enable Dout, active low
+    d_oe                : std_logic; 
+  end record;
+
+  procedure byte_out(
+    signal mcu_in       : out mcu_in;
+    byte                : in std_logic_vector(7 downto 0)
+  );
+
+  procedure byte_in(
+    signal mcu_in       : out mcu_in;
+    signal bit_out      : in std_logic;
+    signal byte         : out std_logic_vector(7 downto 0)
+  );
+
+  procedure write_ram(
+    signal mcu_in       : out mcu_in;
+    signal we           : out std_logic;
+    data                : in std_logic_vector(7 downto 0);
+    address             : in std_logic_vector(15 downto 0)
+  );
+
+  constant tClk         : time :=  100 ns;
+  constant disable      : std_logic := '1';
+  constant enable       : std_logic := '0';
+
+  constant mcu_in_initial : mcu_in := (
+    bit_in => '0',
+    bit_clk => '1',
+    byte_out_clk => '1',
+    byte_in_clk => '1',
+    a_oe => '1',
+    d_oe => '1'
+  );
+
+end mcu;
+
+package body mcu is
+
+  procedure byte_out(
+    signal mcu_in       : out mcu_in;
+    byte                : in std_logic_vector(7 downto 0)) is
+  begin
+    for i in byte'range loop
+      mcu_in.bit_in  <= byte(i);
+      mcu_in.bit_clk <= '0';
+      wait for tClk;
+
+      mcu_in.bit_clk <= '1';
+      wait for tClk;
+    end loop;
+  end;
+
+  procedure byte_in(
+    signal mcu_in       : out mcu_in;
+    signal bit_out      : in std_logic;
+    signal byte         : out std_logic_vector(7 downto 0)) is
+  begin
+    mcu_in.byte_in_clk <= '0';
+    wait for tClk;
+
+    mcu_in.byte_in_clk <= '1';
+    wait for tClk;
+
+    for i in byte'range loop
+      byte(i) <= bit_out;
+      mcu_in.bit_clk <= '0';
+      wait for tClk;
+
+      mcu_in.bit_clk <= '1';
+      wait for tClk;
+    end loop;
+  end;
+
+  procedure write_ram(
+    signal mcu_in       : out mcu_in;
+    signal we           : out std_logic;
+    data                : in std_logic_vector(7 downto 0);
+    address             : in std_logic_vector(15 downto 0)) is
+  begin
+    report "write_ram: " & to_string(data);
+
+    -- TODO: busreq + wait for busack
+    byte_out(mcu_in, data);
+    byte_out(mcu_in, address(7 downto 0));
+    byte_out(mcu_in, address(15 downto 8));
+
+    mcu_in.byte_out_clk <= '0';
+    wait for tClk;
+
+    -- Clock the data out on the A and D busses
+    mcu_in.byte_out_clk <= '1';
+    -- Enable A and D outputs
+    mcu_in.a_oe <= enable;
+    mcu_in.d_oe <= enable;
+    we <= enable;
+
+    wait for tClk;
+
+    we <= disable;
+  end;
+
+end mcu;
diff --git a/vhdl/mcu_interface.vhd b/vhdl/mcu_interface.vhd
index d8d2b56..86807a7 100644
--- a/vhdl/mcu_interface.vhd
+++ b/vhdl/mcu_interface.vhd
@@ -5,24 +5,12 @@ use ieee.std_logic_unsigned.all;
 library fmf;
 use fmf.std595;
 
-use work.all;
+use work.mcu.all;
 
 entity mcu_interface is
   port (
-    -- SPI interface
-    bit_in              : in  std_logic;
+    mcu_in              : in mcu_in;
     bit_out             : out std_logic;
-    bit_clk             : in  std_logic;
-
-    -- Strobed to latch data from SPI buffer to AH, AL and Dout
-    byte_out_clk        : in  std_logic;
-    -- Store to latch data from D bus to Din
-    byte_in_clk         : in  std_logic;
-    -- Enable AH and AL, active low
-    a_oe                : in  std_logic; 
-    -- Enable Dout, active low
-    d_oe                : in  std_logic; 
-
     ah                  : out std_logic_vector(7 downto 0);
     al                  : out std_logic_vector(7 downto 0);
     d_out               : out std_logic_vector(7 downto 0);
@@ -36,11 +24,11 @@ architecture behaviour of mcu_interface is
   signal al_out         : std_logic;
 begin
   ah_buf : entity fmf.std595(vhdl_behavioral) port map(
-    ser => bit_in,
+    ser => mcu_in.bit_in,
     qhser => ah_out,
-    sck => bit_clk,
-    rck => byte_out_clk,
-    gneg => a_oe,
+    sck => mcu_in.bit_clk,
+    rck => mcu_in.byte_out_clk,
+    gneg => mcu_in.a_oe,
     qa => ah(0),
     qb => ah(1),
     qc => ah(2),
@@ -55,9 +43,9 @@ begin
   al_buf : entity fmf.std595(vhdl_behavioral) port map(
     ser => ah_out,
     qhser => al_out,
-    sck => bit_clk,
-    rck => byte_out_clk,
-    gneg => a_oe,
+    sck => mcu_in.bit_clk,
+    rck => mcu_in.byte_out_clk,
+    gneg => mcu_in.a_oe,
     qa => al(0),
     qb => al(1),
     qc => al(2),
@@ -71,10 +59,10 @@ begin
 
   d_out_buf : entity fmf.std595(vhdl_behavioral) port map(
     ser => al_out,
---  qhser => Not connected
-    sck => bit_clk,
-    rck => byte_out_clk,
-    gneg => d_oe,
+    qhser => open,
+    sck => mcu_in.bit_clk,
+    rck => mcu_in.byte_out_clk,
+    gneg => mcu_in.d_oe,
     qa => d_out(0),
     qb => d_out(1),
     qc => d_out(2),
@@ -89,9 +77,10 @@ begin
   d_in_buf : entity fmf.std165(vhdl_behavioral) port map(
     ser => '0',
     q => bit_out,
-    clk => bit_clk,
+    qneg => open,
+    clk => mcu_in.bit_clk,
     clkinh => '0',
-    sh => byte_in_clk,
+    sh => mcu_in.byte_in_clk,
     da => d_in(0),
     db => d_in(1),
     dc => d_in(2),
diff --git a/vhdl/mcu_interface_tb.vhd b/vhdl/mcu_interface_tb.vhd
index d46df95..8fa12a9 100644
--- a/vhdl/mcu_interface_tb.vhd
+++ b/vhdl/mcu_interface_tb.vhd
@@ -1,26 +1,24 @@
 library ieee;
 use ieee.std_logic_1164.all;
-use work.all;
 
--- library std;
--- use std.textio.all;
-
--- use ieee.std_logic_textio.all;
 library ieee_proposed;
 use ieee_proposed.std_logic_1164_additions.all;
 
+use work.mcu.all;
+
 entity mcu_interface_tb is
 end mcu_interface_tb;
 
 -- The MCU has to initialize its output to these values.
 architecture behaviour of mcu_interface_tb is
-  signal bit_in         : std_logic;
+  signal mcu_in         : mcu_in;
+--  signal bit_in         : std_logic;
   signal bit_out        : std_logic;
-  signal bit_clk        : std_logic := '0';
-  signal byte_out_clk   : std_logic := '0';
-  signal byte_in_clk    : std_logic := '1'; -- active low
-  signal a_oe           : std_logic := '1';
-  signal d_oe           : std_logic := '1';
+--  signal bit_clk        : std_logic := '0';
+--  signal byte_out_clk   : std_logic := '0';
+--  signal byte_in_clk    : std_logic := '1'; -- active low
+--  signal a_oe           : std_logic := '1';
+--  signal d_oe           : std_logic := '1';
 
   signal ah             : std_logic_vector(7 downto 0);
   signal al             : std_logic_vector(7 downto 0);
@@ -29,16 +27,11 @@ architecture behaviour of mcu_interface_tb is
 
   signal byte_in_s      : std_logic_vector(7 downto 0) := "UUUUUUUU";
 
-  constant tClk         : time :=  1 ns;
+  constant tClk         : time := tClk;
 begin
   mcu_interface : entity work.mcu_interface port map(
-        bit_in,
+        mcu_in,
         bit_out,
-        bit_clk,
-        byte_out_clk,
-        byte_in_clk,
-        a_oe,
-        d_oe,
         ah,
         al,
         d_out,
@@ -51,35 +44,29 @@ begin
     procedure byte_out(byte : in std_logic_vector(7 downto 0)) is
     begin
       for i in byte'range loop
-        bit_in  <= byte(i);
-        bit_clk <= '1';
+        mcu_in.bit_in  <= byte(i);
+        mcu_in.bit_clk <= '0';
         wait for tClk;
 
-        bit_clk <= '0';
+        mcu_in.bit_clk <= '1';
         wait for tClk;
       end loop;
-
-      byte_out_clk <= '1';
-      wait for tClk;
-
-      byte_out_clk <= '0';
-      wait for tClk;
     end;
 
     procedure byte_in(byte : out std_logic_vector(7 downto 0)) is
     begin
-      byte_in_clk <= '0';
+      mcu_in.byte_in_clk <= '0';
       wait for tClk;
 
-      byte_in_clk <= '1';
+      mcu_in.byte_in_clk <= '1';
       wait for tClk;
 
       for i in byte'range loop
         byte(i) := bit_out;
-        bit_clk <= '1';
+        mcu_in.bit_clk <= '0';
         wait for tClk;
 
-        bit_clk <= '0';
+        mcu_in.bit_clk <= '1';
         wait for tClk;
       end loop;
     end;
@@ -88,18 +75,32 @@ begin
       data      : in std_logic_vector(7 downto 0);
       address   : in std_logic_vector(15 downto 0)) is
     begin
-      report "write_ram: " & to_string(data);
+      report "write_ram: " & to_string(data) & "b/0x"  & to_hex_string(data) & "@" & to_hex_string(address);
 
       -- TODO: busreq + wait for busack
       byte_out(data);
       byte_out(address(7 downto 0));
       byte_out(address(15 downto 8));
+
+      mcu_in.byte_out_clk <= '0';
+      wait for tClk;
+
+      mcu_in.byte_out_clk <= '1';
+      wait for tClk;
     end;
 
   begin
+--    mcu_in.bit_in <= '0';
+--    mcu_in.bit_clk <= '1';
+--    mcu_in.byte_out_clk <= '1';
+--    mcu_in.byte_in_clk <= '1';
+--    mcu_in.a_oe <= '1';
+--    mcu_in.d_oe <= '1';
+    mcu_in <= mcu_in_initial;
+
     write_ram("10100101", "0000000000000001");
-    d_oe <= '0';
-    a_oe <= '0';
+    mcu_in.d_oe <= '0';
+    mcu_in.a_oe <= '0';
 
     wait for tClk;
     assert ah = "00000000" report "ah failed";
diff --git a/vhdl/ram-ice.xise b/vhdl/ram-ice.xise
index a5bd50b..77f5b5a 100644
--- a/vhdl/ram-ice.xise
+++ b/vhdl/ram-ice.xise
@@ -15,14 +15,6 @@
   <version xil_pn:ise_version="14.4" xil_pn:schema_version="2"/>
 
   <files>
-    <file xil_pn:name="ice_tb.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="1"/>
-    </file>
-    <file xil_pn:name="ice.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
-    </file>
     <file xil_pn:name="fmf/conversions.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
@@ -39,12 +31,12 @@
       <library xil_pn:name="fmf"/>
     </file>
     <file xil_pn:name="fmf/ff_package.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
       <library xil_pn:name="fmf"/>
     </file>
     <file xil_pn:name="fmf/gen_utils.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
       <library xil_pn:name="fmf"/>
     </file>
@@ -59,53 +51,71 @@
       <library xil_pn:name="fmf"/>
     </file>
     <file xil_pn:name="fmf/std165.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
       <library xil_pn:name="fmf"/>
     </file>
     <file xil_pn:name="fmf/std595.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
       <library xil_pn:name="fmf"/>
     </file>
     <file xil_pn:name="mcu_interface_tb.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
       <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="37"/>
     </file>
     <file xil_pn:name="mcu_interface.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
     <file xil_pn:name="ieee_proposed/std_logic_1164_additions.vhdl" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="66"/>
       <library xil_pn:name="ieee_proposed"/>
     </file>
+    <file xil_pn:name="ice.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="57"/>
+    </file>
+    <file xil_pn:name="AS7C256A.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
+      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="59"/>
+    </file>
+    <file xil_pn:name="ice_tb.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
+      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="66"/>
+    </file>
+    <file xil_pn:name="mcu.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
+      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="67"/>
+    </file>
   </files>
 
   <properties>
+    <property xil_pn:name="Custom Waveform Configuration File Behav" xil_pn:value="ice_tb.wcfg" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Device" xil_pn:value="xc95*xl" xil_pn:valueState="default"/>
     <property xil_pn:name="Device Family" xil_pn:value="XC9500XL CPLDs" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|mcu_interface|behaviour" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top File" xil_pn:value="mcu_interface.vhd" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/mcu_interface" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|ice|behaviour" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top File" xil_pn:value="ice.vhd" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/ice" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Package" xil_pn:value="*" xil_pn:valueState="default"/>
     <property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store non-default values only" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/mcu_interface_tb" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.mcu_interface_tb" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="200 ns" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/ice_tb" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.ice_tb" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="20us" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
     <property xil_pn:name="Speed Grade" xil_pn:value="-*" xil_pn:valueState="default"/>
     <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
     <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="true" xil_pn:valueState="non-default"/>
     <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-200X" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
     <!--                                                                                  -->
     <!-- The following properties are for internal use only. These should not be modified.-->
     <!--                                                                                  -->
-    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|mcu_interface_tb|behaviour" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|ice_tb|behavior" xil_pn:valueState="non-default"/>
     <property xil_pn:name="PROP_DesignName" xil_pn:value="ram-ice" xil_pn:valueState="non-default"/>
     <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="xc9500xl" xil_pn:valueState="default"/>
     <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2013-02-10T14:06:24" xil_pn:valueState="non-default"/>