o Moving tinyprintf and stm libraries under thirdparty.

18 files changed, 0 insertions, 14577 deletions

diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/misc.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/misc.c
deleted file mode 100644
index c0a5e11..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/misc.c
+++ /dev/null
@@ -1,225 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    misc.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    11-March-2011
-  * @brief   This file provides all the miscellaneous firmware functions (add-on
-  *          to CMSIS functions).
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "misc.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Driver
-  * @{
-  */
-
-/** @defgroup MISC 
-  * @brief MISC driver modules
-  * @{
-  */
-
-/** @defgroup MISC_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */ 
-
-/** @defgroup MISC_Private_Defines
-  * @{
-  */
-
-#define AIRCR_VECTKEY_MASK    ((uint32_t)0x05FA0000)
-/**
-  * @}
-  */
-
-/** @defgroup MISC_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup MISC_Private_Variables
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup MISC_Private_FunctionPrototypes
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup MISC_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Configures the priority grouping: pre-emption priority and subpriority.
-  * @param  NVIC_PriorityGroup: specifies the priority grouping bits length. 
-  *   This parameter can be one of the following values:
-  *     @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority
-  *                                4 bits for subpriority
-  *     @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority
-  *                                3 bits for subpriority
-  *     @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority
-  *                                2 bits for subpriority
-  *     @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority
-  *                                1 bits for subpriority
-  *     @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority
-  *                                0 bits for subpriority
-  * @retval None
-  */
-void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)
-{
-  /* Check the parameters */
-  assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup));
-  
-  /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */
-  SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup;
-}
-
-/**
-  * @brief  Initializes the NVIC peripheral according to the specified
-  *         parameters in the NVIC_InitStruct.
-  * @param  NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains
-  *         the configuration information for the specified NVIC peripheral.
-  * @retval None
-  */
-void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct)
-{
-  uint32_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F;
-  
-  /* Check the parameters */
-  assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd));
-  assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority));  
-  assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority));
-    
-  if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)
-  {
-    /* Compute the Corresponding IRQ Priority --------------------------------*/    
-    tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08;
-    tmppre = (0x4 - tmppriority);
-    tmpsub = tmpsub >> tmppriority;
-
-    tmppriority = (uint32_t)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre;
-    tmppriority |=  NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub;
-    tmppriority = tmppriority << 0x04;
-        
-    NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority;
-    
-    /* Enable the Selected IRQ Channels --------------------------------------*/
-    NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
-      (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
-  }
-  else
-  {
-    /* Disable the Selected IRQ Channels -------------------------------------*/
-    NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
-      (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
-  }
-}
-
-/**
-  * @brief  Sets the vector table location and Offset.
-  * @param  NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory.
-  *   This parameter can be one of the following values:
-  *     @arg NVIC_VectTab_RAM
-  *     @arg NVIC_VectTab_FLASH
-  * @param  Offset: Vector Table base offset field. This value must be a multiple 
-  *         of 0x200.
-  * @retval None
-  */
-void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset)
-{ 
-  /* Check the parameters */
-  assert_param(IS_NVIC_VECTTAB(NVIC_VectTab));
-  assert_param(IS_NVIC_OFFSET(Offset));  
-   
-  SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80);
-}
-
-/**
-  * @brief  Selects the condition for the system to enter low power mode.
-  * @param  LowPowerMode: Specifies the new mode for the system to enter low power mode.
-  *   This parameter can be one of the following values:
-  *     @arg NVIC_LP_SEVONPEND
-  *     @arg NVIC_LP_SLEEPDEEP
-  *     @arg NVIC_LP_SLEEPONEXIT
-  * @param  NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_NVIC_LP(LowPowerMode));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));  
-  
-  if (NewState != DISABLE)
-  {
-    SCB->SCR |= LowPowerMode;
-  }
-  else
-  {
-    SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode);
-  }
-}
-
-/**
-  * @brief  Configures the SysTick clock source.
-  * @param  SysTick_CLKSource: specifies the SysTick clock source.
-  *   This parameter can be one of the following values:
-  *     @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source.
-  *     @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source.
-  * @retval None
-  */
-void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource)
-{
-  /* Check the parameters */
-  assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource));
-  if (SysTick_CLKSource == SysTick_CLKSource_HCLK)
-  {
-    SysTick->CTRL |= SysTick_CLKSource_HCLK;
-  }
-  else
-  {
-    SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8;
-  }
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_bkp.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_bkp.c
deleted file mode 100644
index 997eecc..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_bkp.c
+++ /dev/null
@@ -1,308 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f10x_bkp.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    11-March-2011
-  * @brief   This file provides all the BKP firmware functions.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_bkp.h"
-#include "stm32f10x_rcc.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Driver
-  * @{
-  */
-
-/** @defgroup BKP 
-  * @brief BKP driver modules
-  * @{
-  */
-
-/** @defgroup BKP_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup BKP_Private_Defines
-  * @{
-  */
-
-/* ------------ BKP registers bit address in the alias region --------------- */
-#define BKP_OFFSET        (BKP_BASE - PERIPH_BASE)
-
-/* --- CR Register ----*/
-
-/* Alias word address of TPAL bit */
-#define CR_OFFSET         (BKP_OFFSET + 0x30)
-#define TPAL_BitNumber    0x01
-#define CR_TPAL_BB        (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPAL_BitNumber * 4))
-
-/* Alias word address of TPE bit */
-#define TPE_BitNumber     0x00
-#define CR_TPE_BB         (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPE_BitNumber * 4))
-
-/* --- CSR Register ---*/
-
-/* Alias word address of TPIE bit */
-#define CSR_OFFSET        (BKP_OFFSET + 0x34)
-#define TPIE_BitNumber    0x02
-#define CSR_TPIE_BB       (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TPIE_BitNumber * 4))
-
-/* Alias word address of TIF bit */
-#define TIF_BitNumber     0x09
-#define CSR_TIF_BB        (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TIF_BitNumber * 4))
-
-/* Alias word address of TEF bit */
-#define TEF_BitNumber     0x08
-#define CSR_TEF_BB        (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEF_BitNumber * 4))
-
-/* ---------------------- BKP registers bit mask ------------------------ */
-
-/* RTCCR register bit mask */
-#define RTCCR_CAL_MASK    ((uint16_t)0xFF80)
-#define RTCCR_MASK        ((uint16_t)0xFC7F)
-
-/**
-  * @}
-  */ 
-
-
-/** @defgroup BKP_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup BKP_Private_Variables
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup BKP_Private_FunctionPrototypes
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup BKP_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Deinitializes the BKP peripheral registers to their default reset values.
-  * @param  None
-  * @retval None
-  */
-void BKP_DeInit(void)
-{
-  RCC_BackupResetCmd(ENABLE);
-  RCC_BackupResetCmd(DISABLE);
-}
-
-/**
-  * @brief  Configures the Tamper Pin active level.
-  * @param  BKP_TamperPinLevel: specifies the Tamper Pin active level.
-  *   This parameter can be one of the following values:
-  *     @arg BKP_TamperPinLevel_High: Tamper pin active on high level
-  *     @arg BKP_TamperPinLevel_Low: Tamper pin active on low level
-  * @retval None
-  */
-void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel)
-{
-  /* Check the parameters */
-  assert_param(IS_BKP_TAMPER_PIN_LEVEL(BKP_TamperPinLevel));
-  *(__IO uint32_t *) CR_TPAL_BB = BKP_TamperPinLevel;
-}
-
-/**
-  * @brief  Enables or disables the Tamper Pin activation.
-  * @param  NewState: new state of the Tamper Pin activation.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void BKP_TamperPinCmd(FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  *(__IO uint32_t *) CR_TPE_BB = (uint32_t)NewState;
-}
-
-/**
-  * @brief  Enables or disables the Tamper Pin Interrupt.
-  * @param  NewState: new state of the Tamper Pin Interrupt.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void BKP_ITConfig(FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  *(__IO uint32_t *) CSR_TPIE_BB = (uint32_t)NewState;
-}
-
-/**
-  * @brief  Select the RTC output source to output on the Tamper pin.
-  * @param  BKP_RTCOutputSource: specifies the RTC output source.
-  *   This parameter can be one of the following values:
-  *     @arg BKP_RTCOutputSource_None: no RTC output on the Tamper pin.
-  *     @arg BKP_RTCOutputSource_CalibClock: output the RTC clock with frequency
-  *                                          divided by 64 on the Tamper pin.
-  *     @arg BKP_RTCOutputSource_Alarm: output the RTC Alarm pulse signal on
-  *                                     the Tamper pin.
-  *     @arg BKP_RTCOutputSource_Second: output the RTC Second pulse signal on
-  *                                      the Tamper pin.  
-  * @retval None
-  */
-void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource)
-{
-  uint16_t tmpreg = 0;
-  /* Check the parameters */
-  assert_param(IS_BKP_RTC_OUTPUT_SOURCE(BKP_RTCOutputSource));
-  tmpreg = BKP->RTCCR;
-  /* Clear CCO, ASOE and ASOS bits */
-  tmpreg &= RTCCR_MASK;
-  
-  /* Set CCO, ASOE and ASOS bits according to BKP_RTCOutputSource value */
-  tmpreg |= BKP_RTCOutputSource;
-  /* Store the new value */
-  BKP->RTCCR = tmpreg;
-}
-
-/**
-  * @brief  Sets RTC Clock Calibration value.
-  * @param  CalibrationValue: specifies the RTC Clock Calibration value.
-  *   This parameter must be a number between 0 and 0x7F.
-  * @retval None
-  */
-void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue)
-{
-  uint16_t tmpreg = 0;
-  /* Check the parameters */
-  assert_param(IS_BKP_CALIBRATION_VALUE(CalibrationValue));
-  tmpreg = BKP->RTCCR;
-  /* Clear CAL[6:0] bits */
-  tmpreg &= RTCCR_CAL_MASK;
-  /* Set CAL[6:0] bits according to CalibrationValue value */
-  tmpreg |= CalibrationValue;
-  /* Store the new value */
-  BKP->RTCCR = tmpreg;
-}
-
-/**
-  * @brief  Writes user data to the specified Data Backup Register.
-  * @param  BKP_DR: specifies the Data Backup Register.
-  *   This parameter can be BKP_DRx where x:[1, 42]
-  * @param  Data: data to write
-  * @retval None
-  */
-void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data)
-{
-  __IO uint32_t tmp = 0;
-
-  /* Check the parameters */
-  assert_param(IS_BKP_DR(BKP_DR));
-
-  tmp = (uint32_t)BKP_BASE; 
-  tmp += BKP_DR;
-
-  *(__IO uint32_t *) tmp = Data;
-}
-
-/**
-  * @brief  Reads data from the specified Data Backup Register.
-  * @param  BKP_DR: specifies the Data Backup Register.
-  *   This parameter can be BKP_DRx where x:[1, 42]
-  * @retval The content of the specified Data Backup Register
-  */
-uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR)
-{
-  __IO uint32_t tmp = 0;
-
-  /* Check the parameters */
-  assert_param(IS_BKP_DR(BKP_DR));
-
-  tmp = (uint32_t)BKP_BASE; 
-  tmp += BKP_DR;
-
-  return (*(__IO uint16_t *) tmp);
-}
-
-/**
-  * @brief  Checks whether the Tamper Pin Event flag is set or not.
-  * @param  None
-  * @retval The new state of the Tamper Pin Event flag (SET or RESET).
-  */
-FlagStatus BKP_GetFlagStatus(void)
-{
-  return (FlagStatus)(*(__IO uint32_t *) CSR_TEF_BB);
-}
-
-/**
-  * @brief  Clears Tamper Pin Event pending flag.
-  * @param  None
-  * @retval None
-  */
-void BKP_ClearFlag(void)
-{
-  /* Set CTE bit to clear Tamper Pin Event flag */
-  BKP->CSR |= BKP_CSR_CTE;
-}
-
-/**
-  * @brief  Checks whether the Tamper Pin Interrupt has occurred or not.
-  * @param  None
-  * @retval The new state of the Tamper Pin Interrupt (SET or RESET).
-  */
-ITStatus BKP_GetITStatus(void)
-{
-  return (ITStatus)(*(__IO uint32_t *) CSR_TIF_BB);
-}
-
-/**
-  * @brief  Clears Tamper Pin Interrupt pending bit.
-  * @param  None
-  * @retval None
-  */
-void BKP_ClearITPendingBit(void)
-{
-  /* Set CTI bit to clear Tamper Pin Interrupt pending bit */
-  BKP->CSR |= BKP_CSR_CTI;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_can.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_can.c
deleted file mode 100644
index ec8e049..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_can.c
+++ /dev/null
@@ -1,1415 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f10x_can.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    11-March-2011
-  * @brief   This file provides all the CAN firmware functions.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_can.h"
-#include "stm32f10x_rcc.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Driver
-  * @{
-  */
-
-/** @defgroup CAN 
-  * @brief CAN driver modules
-  * @{
-  */ 
-
-/** @defgroup CAN_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup CAN_Private_Defines
-  * @{
-  */
-
-/* CAN Master Control Register bits */
-
-#define MCR_DBF      ((uint32_t)0x00010000) /* software master reset */
-
-/* CAN Mailbox Transmit Request */
-#define TMIDxR_TXRQ  ((uint32_t)0x00000001) /* Transmit mailbox request */
-
-/* CAN Filter Master Register bits */
-#define FMR_FINIT    ((uint32_t)0x00000001) /* Filter init mode */
-
-/* Time out for INAK bit */
-#define INAK_TIMEOUT        ((uint32_t)0x0000FFFF)
-/* Time out for SLAK bit */
-#define SLAK_TIMEOUT        ((uint32_t)0x0000FFFF)
-
-
-
-/* Flags in TSR register */
-#define CAN_FLAGS_TSR              ((uint32_t)0x08000000) 
-/* Flags in RF1R register */
-#define CAN_FLAGS_RF1R             ((uint32_t)0x04000000) 
-/* Flags in RF0R register */
-#define CAN_FLAGS_RF0R             ((uint32_t)0x02000000) 
-/* Flags in MSR register */
-#define CAN_FLAGS_MSR              ((uint32_t)0x01000000) 
-/* Flags in ESR register */
-#define CAN_FLAGS_ESR              ((uint32_t)0x00F00000) 
-
-/* Mailboxes definition */
-#define CAN_TXMAILBOX_0                   ((uint8_t)0x00)
-#define CAN_TXMAILBOX_1                   ((uint8_t)0x01)
-#define CAN_TXMAILBOX_2                   ((uint8_t)0x02) 
-
-
-
-#define CAN_MODE_MASK              ((uint32_t) 0x00000003)
-/**
-  * @}
-  */
-
-/** @defgroup CAN_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup CAN_Private_Variables
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup CAN_Private_FunctionPrototypes
-  * @{
-  */
-
-static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit);
-
-/**
-  * @}
-  */
-
-/** @defgroup CAN_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Deinitializes the CAN peripheral registers to their default reset values.
-  * @param  CANx: where x can be 1 or 2 to select the CAN peripheral.
-  * @retval None.
-  */
-void CAN_DeInit(CAN_TypeDef* CANx)
-{
-  /* Check the parameters */
-  assert_param(IS_CAN_ALL_PERIPH(CANx));
- 
-  if (CANx == CAN1)
-  {
-    /* Enable CAN1 reset state */
-    RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, ENABLE);
-    /* Release CAN1 from reset state */
-    RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, DISABLE);
-  }
-  else
-  {  
-    /* Enable CAN2 reset state */
-    RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, ENABLE);
-    /* Release CAN2 from reset state */
-    RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, DISABLE);
-  }
-}
-
-/**
-  * @brief  Initializes the CAN peripheral according to the specified
-  *         parameters in the CAN_InitStruct.
-  * @param  CANx:           where x can be 1 or 2 to to select the CAN 
-  *                         peripheral.
-  * @param  CAN_InitStruct: pointer to a CAN_InitTypeDef structure that
-  *                         contains the configuration information for the 
-  *                         CAN peripheral.
-  * @retval Constant indicates initialization succeed which will be 
-  *         CAN_InitStatus_Failed or CAN_InitStatus_Success.
-  */
-uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct)
-{
-  uint8_t InitStatus = CAN_InitStatus_Failed;
-  uint32_t wait_ack = 0x00000000;
-  /* Check the parameters */
-  assert_param(IS_CAN_ALL_PERIPH(CANx));
-  assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TTCM));
-  assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_ABOM));
-  assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_AWUM));
-  assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_NART));
-  assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_RFLM));
-  assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TXFP));
-  assert_param(IS_CAN_MODE(CAN_InitStruct->CAN_Mode));
-  assert_param(IS_CAN_SJW(CAN_InitStruct->CAN_SJW));
-  assert_param(IS_CAN_BS1(CAN_InitStruct->CAN_BS1));
-  assert_param(IS_CAN_BS2(CAN_InitStruct->CAN_BS2));
-  assert_param(IS_CAN_PRESCALER(CAN_InitStruct->CAN_Prescaler));
-
-  /* Exit from sleep mode */
-  CANx->MCR &= (~(uint32_t)CAN_MCR_SLEEP);
-
-  /* Request initialisation */
-  CANx->MCR |= CAN_MCR_INRQ ;
-
-  /* Wait the acknowledge */
-  while (((CANx->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) && (wait_ack != INAK_TIMEOUT))
-  {
-    wait_ack++;
-  }
-
-  /* Check acknowledge */
-  if ((CANx->MSR & CAN_MSR_INAK) != CAN_MSR_INAK)
-  {
-    InitStatus = CAN_InitStatus_Failed;
-  }
-  else 
-  {
-    /* Set the time triggered communication mode */
-    if (CAN_InitStruct->CAN_TTCM == ENABLE)
-    {
-      CANx->MCR |= CAN_MCR_TTCM;
-    }
-    else
-    {
-      CANx->MCR &= ~(uint32_t)CAN_MCR_TTCM;
-    }
-
-    /* Set the automatic bus-off management */
-    if (CAN_InitStruct->CAN_ABOM == ENABLE)
-    {
-      CANx->MCR |= CAN_MCR_ABOM;
-    }
-    else
-    {
-      CANx->MCR &= ~(uint32_t)CAN_MCR_ABOM;
-    }
-
-    /* Set the automatic wake-up mode */
-    if (CAN_InitStruct->CAN_AWUM == ENABLE)
-    {
-      CANx->MCR |= CAN_MCR_AWUM;
-    }
-    else
-    {
-      CANx->MCR &= ~(uint32_t)CAN_MCR_AWUM;
-    }
-
-    /* Set the no automatic retransmission */
-    if (CAN_InitStruct->CAN_NART == ENABLE)
-    {
-      CANx->MCR |= CAN_MCR_NART;
-    }
-    else
-    {
-      CANx->MCR &= ~(uint32_t)CAN_MCR_NART;
-    }
-
-    /* Set the receive FIFO locked mode */
-    if (CAN_InitStruct->CAN_RFLM == ENABLE)
-    {
-      CANx->MCR |= CAN_MCR_RFLM;
-    }
-    else
-    {
-      CANx->MCR &= ~(uint32_t)CAN_MCR_RFLM;
-    }
-
-    /* Set the transmit FIFO priority */
-    if (CAN_InitStruct->CAN_TXFP == ENABLE)
-    {
-      CANx->MCR |= CAN_MCR_TXFP;
-    }
-    else
-    {
-      CANx->MCR &= ~(uint32_t)CAN_MCR_TXFP;
-    }
-
-    /* Set the bit timing register */
-    CANx->BTR = (uint32_t)((uint32_t)CAN_InitStruct->CAN_Mode << 30) | \
-                ((uint32_t)CAN_InitStruct->CAN_SJW << 24) | \
-                ((uint32_t)CAN_InitStruct->CAN_BS1 << 16) | \
-                ((uint32_t)CAN_InitStruct->CAN_BS2 << 20) | \
-               ((uint32_t)CAN_InitStruct->CAN_Prescaler - 1);
-
-    /* Request leave initialisation */
-    CANx->MCR &= ~(uint32_t)CAN_MCR_INRQ;
-
-   /* Wait the acknowledge */
-   wait_ack = 0;
-
-   while (((CANx->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) && (wait_ack != INAK_TIMEOUT))
-   {
-     wait_ack++;
-   }
-
-    /* ...and check acknowledged */
-    if ((CANx->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)
-    {
-      InitStatus = CAN_InitStatus_Failed;
-    }
-    else
-    {
-      InitStatus = CAN_InitStatus_Success ;
-    }
-  }
-
-  /* At this step, return the status of initialization */
-  return InitStatus;
-}
-
-/**
-  * @brief  Initializes the CAN peripheral according to the specified
-  *         parameters in the CAN_FilterInitStruct.
-  * @param  CAN_FilterInitStruct: pointer to a CAN_FilterInitTypeDef
-  *                               structure that contains the configuration 
-  *                               information.
-  * @retval None.
-  */
-void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct)
-{
-  uint32_t filter_number_bit_pos = 0;
-  /* Check the parameters */
-  assert_param(IS_CAN_FILTER_NUMBER(CAN_FilterInitStruct->CAN_FilterNumber));
-  assert_param(IS_CAN_FILTER_MODE(CAN_FilterInitStruct->CAN_FilterMode));
-  assert_param(IS_CAN_FILTER_SCALE(CAN_FilterInitStruct->CAN_FilterScale));
-  assert_param(IS_CAN_FILTER_FIFO(CAN_FilterInitStruct->CAN_FilterFIFOAssignment));
-  assert_param(IS_FUNCTIONAL_STATE(CAN_FilterInitStruct->CAN_FilterActivation));
-
-  filter_number_bit_pos = ((uint32_t)1) << CAN_FilterInitStruct->CAN_FilterNumber;
-
-  /* Initialisation mode for the filter */
-  CAN1->FMR |= FMR_FINIT;
-
-  /* Filter Deactivation */
-  CAN1->FA1R &= ~(uint32_t)filter_number_bit_pos;
-
-  /* Filter Scale */
-  if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_16bit)
-  {
-    /* 16-bit scale for the filter */
-    CAN1->FS1R &= ~(uint32_t)filter_number_bit_pos;
-
-    /* First 16-bit identifier and First 16-bit mask */
-    /* Or First 16-bit identifier and Second 16-bit identifier */
-    CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = 
-    ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow) << 16) |
-        (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow);
-
-    /* Second 16-bit identifier and Second 16-bit mask */
-    /* Or Third 16-bit identifier and Fourth 16-bit identifier */
-    CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = 
-    ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) |
-        (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh);
-  }
-
-  if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_32bit)
-  {
-    /* 32-bit scale for the filter */
-    CAN1->FS1R |= filter_number_bit_pos;
-    /* 32-bit identifier or First 32-bit identifier */
-    CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = 
-    ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh) << 16) |
-        (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow);
-    /* 32-bit mask or Second 32-bit identifier */
-    CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = 
-    ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) |
-        (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow);
-  }
-
-  /* Filter Mode */
-  if (CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdMask)
-  {
-    /*Id/Mask mode for the filter*/
-    CAN1->FM1R &= ~(uint32_t)filter_number_bit_pos;
-  }
-  else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */
-  {
-    /*Identifier list mode for the filter*/
-    CAN1->FM1R |= (uint32_t)filter_number_bit_pos;
-  }
-
-  /* Filter FIFO assignment */
-  if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO0)
-  {
-    /* FIFO 0 assignation for the filter */
-    CAN1->FFA1R &= ~(uint32_t)filter_number_bit_pos;
-  }
-
-  if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO1)
-  {
-    /* FIFO 1 assignation for the filter */
-    CAN1->FFA1R |= (uint32_t)filter_number_bit_pos;
-  }
-  
-  /* Filter activation */
-  if (CAN_FilterInitStruct->CAN_FilterActivation == ENABLE)
-  {
-    CAN1->FA1R |= filter_number_bit_pos;
-  }
-
-  /* Leave the initialisation mode for the filter */
-  CAN1->FMR &= ~FMR_FINIT;
-}
-
-/**
-  * @brief  Fills each CAN_InitStruct member with its default value.
-  * @param  CAN_InitStruct: pointer to a CAN_InitTypeDef structure which
-  *                         will be initialized.
-  * @retval None.
-  */
-void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct)
-{
-  /* Reset CAN init structure parameters values */
-  
-  /* Initialize the time triggered communication mode */
-  CAN_InitStruct->CAN_TTCM = DISABLE;
-  
-  /* Initialize the automatic bus-off management */
-  CAN_InitStruct->CAN_ABOM = DISABLE;
-  
-  /* Initialize the automatic wake-up mode */
-  CAN_InitStruct->CAN_AWUM = DISABLE;
-  
-  /* Initialize the no automatic retransmission */
-  CAN_InitStruct->CAN_NART = DISABLE;
-  
-  /* Initialize the receive FIFO locked mode */
-  CAN_InitStruct->CAN_RFLM = DISABLE;
-  
-  /* Initialize the transmit FIFO priority */
-  CAN_InitStruct->CAN_TXFP = DISABLE;
-  
-  /* Initialize the CAN_Mode member */
-  CAN_InitStruct->CAN_Mode = CAN_Mode_Normal;
-  
-  /* Initialize the CAN_SJW member */
-  CAN_InitStruct->CAN_SJW = CAN_SJW_1tq;
-  
-  /* Initialize the CAN_BS1 member */
-  CAN_InitStruct->CAN_BS1 = CAN_BS1_4tq;
-  
-  /* Initialize the CAN_BS2 member */
-  CAN_InitStruct->CAN_BS2 = CAN_BS2_3tq;
-  
-  /* Initialize the CAN_Prescaler member */
-  CAN_InitStruct->CAN_Prescaler = 1;
-}
-
-/**
-  * @brief  Select the start bank filter for slave CAN.
-  * @note   This function applies only to STM32 Connectivity line devices.
-  * @param  CAN_BankNumber: Select the start slave bank filter from 1..27.
-  * @retval None.
-  */
-void CAN_SlaveStartBank(uint8_t CAN_BankNumber) 
-{
-  /* Check the parameters */
-  assert_param(IS_CAN_BANKNUMBER(CAN_BankNumber));
-  
-  /* Enter Initialisation mode for the filter */
-  CAN1->FMR |= FMR_FINIT;
-  
-  /* Select the start slave bank */
-  CAN1->FMR &= (uint32_t)0xFFFFC0F1 ;
-  CAN1->FMR |= (uint32_t)(CAN_BankNumber)<<8;
-  
-  /* Leave Initialisation mode for the filter */
-  CAN1->FMR &= ~FMR_FINIT;
-}
-
-/**
-  * @brief  Enables or disables the DBG Freeze for CAN.
-  * @param  CANx:     where x can be 1 or 2 to to select the CAN peripheral.
-  * @param  NewState: new state of the CAN peripheral. This parameter can 
-  *                   be: ENABLE or DISABLE.
-  * @retval None.
-  */
-void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_CAN_ALL_PERIPH(CANx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  
-  if (NewState != DISABLE)
-  {
-    /* Enable Debug Freeze  */
-    CANx->MCR |= MCR_DBF;
-  }
-  else
-  {
-    /* Disable Debug Freeze */
-    CANx->MCR &= ~MCR_DBF;
-  }
-}
-
-
-/**
-  * @brief  Enables or disabes the CAN Time TriggerOperation communication mode.
-  * @param  CANx:      where x can be 1 or 2 to to select the CAN peripheral.
-  * @param  NewState : Mode new state , can be one of @ref FunctionalState.
-  * @note   when enabled, Time stamp (TIME[15:0]) value is sent in the last 
-  *         two data bytes of the 8-byte message: TIME[7:0] in data byte 6 
-  *         and TIME[15:8] in data byte 7 
-  * @note   DLC must be programmed as 8 in order Time Stamp (2 bytes) to be 
-  *         sent over the CAN bus.  
-  * @retval None
-  */
-void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_CAN_ALL_PERIPH(CANx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  if (NewState != DISABLE)
-  {
-    /* Enable the TTCM mode */
-    CANx->MCR |= CAN_MCR_TTCM;
-
-    /* Set TGT bits */
-    CANx->sTxMailBox[0].TDTR |= ((uint32_t)CAN_TDT0R_TGT);
-    CANx->sTxMailBox[1].TDTR |= ((uint32_t)CAN_TDT1R_TGT);
-    CANx->sTxMailBox[2].TDTR |= ((uint32_t)CAN_TDT2R_TGT);
-  }
-  else
-  {
-    /* Disable the TTCM mode */
-    CANx->MCR &= (uint32_t)(~(uint32_t)CAN_MCR_TTCM);
-
-    /* Reset TGT bits */
-    CANx->sTxMailBox[0].TDTR &= ((uint32_t)~CAN_TDT0R_TGT);
-    CANx->sTxMailBox[1].TDTR &= ((uint32_t)~CAN_TDT1R_TGT);
-    CANx->sTxMailBox[2].TDTR &= ((uint32_t)~CAN_TDT2R_TGT);
-  }
-}
-/**
-  * @brief  Initiates the transmission of a message.
-  * @param  CANx:      where x can be 1 or 2 to to select the CAN peripheral.
-  * @param  TxMessage: pointer to a structure which contains CAN Id, CAN
-  *                    DLC and CAN data.
-  * @retval The number of the mailbox that is used for transmission
-  *                    or CAN_TxStatus_NoMailBox if there is no empty mailbox.
-  */
-uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage)
-{
-  uint8_t transmit_mailbox = 0;
-  /* Check the parameters */
-  assert_param(IS_CAN_ALL_PERIPH(CANx));
-  assert_param(IS_CAN_IDTYPE(TxMessage->IDE));
-  assert_param(IS_CAN_RTR(TxMessage->RTR));
-  assert_param(IS_CAN_DLC(TxMessage->DLC));
-
-  /* Select one empty transmit mailbox */
-  if ((CANx->TSR&CAN_TSR_TME0) == CAN_TSR_TME0)
-  {
-    transmit_mailbox = 0;
-  }
-  else if ((CANx->TSR&CAN_TSR_TME1) == CAN_TSR_TME1)
-  {
-    transmit_mailbox = 1;
-  }
-  else if ((CANx->TSR&CAN_TSR_TME2) == CAN_TSR_TME2)
-  {
-    transmit_mailbox = 2;
-  }
-  else
-  {
-    transmit_mailbox = CAN_TxStatus_NoMailBox;
-  }
-
-  if (transmit_mailbox != CAN_TxStatus_NoMailBox)
-  {
-    /* Set up the Id */
-    CANx->sTxMailBox[transmit_mailbox].TIR &= TMIDxR_TXRQ;
-    if (TxMessage->IDE == CAN_Id_Standard)
-    {
-      assert_param(IS_CAN_STDID(TxMessage->StdId));  
-      CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->StdId << 21) | \
-                                                  TxMessage->RTR);
-    }
-    else
-    {
-      assert_param(IS_CAN_EXTID(TxMessage->ExtId));
-      CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->ExtId << 3) | \
-                                                  TxMessage->IDE | \
-                                                  TxMessage->RTR);
-    }
-    
-    /* Set up the DLC */
-    TxMessage->DLC &= (uint8_t)0x0000000F;
-    CANx->sTxMailBox[transmit_mailbox].TDTR &= (uint32_t)0xFFFFFFF0;
-    CANx->sTxMailBox[transmit_mailbox].TDTR |= TxMessage->DLC;
-
-    /* Set up the data field */
-    CANx->sTxMailBox[transmit_mailbox].TDLR = (((uint32_t)TxMessage->Data[3] << 24) | 
-                                             ((uint32_t)TxMessage->Data[2] << 16) |
-                                             ((uint32_t)TxMessage->Data[1] << 8) | 
-                                             ((uint32_t)TxMessage->Data[0]));
-    CANx->sTxMailBox[transmit_mailbox].TDHR = (((uint32_t)TxMessage->Data[7] << 24) | 
-                                             ((uint32_t)TxMessage->Data[6] << 16) |
-                                             ((uint32_t)TxMessage->Data[5] << 8) |
-                                             ((uint32_t)TxMessage->Data[4]));
-    /* Request transmission */
-    CANx->sTxMailBox[transmit_mailbox].TIR |= TMIDxR_TXRQ;
-  }
-  return transmit_mailbox;
-}
-
-/**
-  * @brief  Checks the transmission of a message.
-  * @param  CANx:            where x can be 1 or 2 to to select the 
-  *                          CAN peripheral.
-  * @param  TransmitMailbox: the number of the mailbox that is used for 
-  *                          transmission.
-  * @retval CAN_TxStatus_Ok if the CAN driver transmits the message, CAN_TxStatus_Failed 
-  *         in an other case.
-  */
-uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox)
-{
-  uint32_t state = 0;
-
-  /* Check the parameters */
-  assert_param(IS_CAN_ALL_PERIPH(CANx));
-  assert_param(IS_CAN_TRANSMITMAILBOX(TransmitMailbox));
- 
-  switch (TransmitMailbox)
-  {
-    case (CAN_TXMAILBOX_0): 
-      state =   CANx->TSR &  (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0);
-      break;
-    case (CAN_TXMAILBOX_1): 
-      state =   CANx->TSR &  (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1);
-      break;
-    case (CAN_TXMAILBOX_2): 
-      state =   CANx->TSR &  (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2);
-      break;
-    default:
-      state = CAN_TxStatus_Failed;
-      break;
-  }
-  switch (state)
-  {
-      /* transmit pending  */
-    case (0x0): state = CAN_TxStatus_Pending;
-      break;
-      /* transmit failed  */
-     case (CAN_TSR_RQCP0 | CAN_TSR_TME0): state = CAN_TxStatus_Failed;
-      break;
-     case (CAN_TSR_RQCP1 | CAN_TSR_TME1): state = CAN_TxStatus_Failed;
-      break;
-     case (CAN_TSR_RQCP2 | CAN_TSR_TME2): state = CAN_TxStatus_Failed;
-      break;
-      /* transmit succeeded  */
-    case (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0):state = CAN_TxStatus_Ok;
-      break;
-    case (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1):state = CAN_TxStatus_Ok;
-      break;
-    case (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2):state = CAN_TxStatus_Ok;
-      break;
-    default: state = CAN_TxStatus_Failed;
-      break;
-  }
-  return (uint8_t) state;
-}
-
-/**
-  * @brief  Cancels a transmit request.
-  * @param  CANx:     where x can be 1 or 2 to to select the CAN peripheral. 
-  * @param  Mailbox:  Mailbox number.
-  * @retval None.
-  */
-void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox)
-{
-  /* Check the parameters */
-  assert_param(IS_CAN_ALL_PERIPH(CANx));
-  assert_param(IS_CAN_TRANSMITMAILBOX(Mailbox));
-  /* abort transmission */
-  switch (Mailbox)
-  {
-    case (CAN_TXMAILBOX_0): CANx->TSR |= CAN_TSR_ABRQ0;
-      break;
-    case (CAN_TXMAILBOX_1): CANx->TSR |= CAN_TSR_ABRQ1;
-      break;
-    case (CAN_TXMAILBOX_2): CANx->TSR |= CAN_TSR_ABRQ2;
-      break;
-    default:
-      break;
-  }
-}
-
-
-/**
-  * @brief  Receives a message.
-  * @param  CANx:       where x can be 1 or 2 to to select the CAN peripheral.
-  * @param  FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
-  * @param  RxMessage:  pointer to a structure receive message which contains 
-  *                     CAN Id, CAN DLC, CAN datas and FMI number.
-  * @retval None.
-  */
-void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage)
-{
-  /* Check the parameters */
-  assert_param(IS_CAN_ALL_PERIPH(CANx));
-  assert_param(IS_CAN_FIFO(FIFONumber));
-  /* Get the Id */
-  RxMessage->IDE = (uint8_t)0x04 & CANx->sFIFOMailBox[FIFONumber].RIR;
-  if (RxMessage->IDE == CAN_Id_Standard)
-  {
-    RxMessage->StdId = (uint32_t)0x000007FF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 21);
-  }
-  else
-  {
-    RxMessage->ExtId = (uint32_t)0x1FFFFFFF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 3);
-  }
-  
-  RxMessage->RTR = (uint8_t)0x02 & CANx->sFIFOMailBox[FIFONumber].RIR;
-  /* Get the DLC */
-  RxMessage->DLC = (uint8_t)0x0F & CANx->sFIFOMailBox[FIFONumber].RDTR;
-  /* Get the FMI */
-  RxMessage->FMI = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDTR >> 8);
-  /* Get the data field */
-  RxMessage->Data[0] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDLR;
-  RxMessage->Data[1] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 8);
-  RxMessage->Data[2] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 16);
-  RxMessage->Data[3] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 24);
-  RxMessage->Data[4] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDHR;
-  RxMessage->Data[5] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 8);
-  RxMessage->Data[6] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 16);
-  RxMessage->Data[7] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 24);
-  /* Release the FIFO */
-  /* Release FIFO0 */
-  if (FIFONumber == CAN_FIFO0)
-  {
-    CANx->RF0R |= CAN_RF0R_RFOM0;
-  }
-  /* Release FIFO1 */
-  else /* FIFONumber == CAN_FIFO1 */
-  {
-    CANx->RF1R |= CAN_RF1R_RFOM1;
-  }
-}
-
-/**
-  * @brief  Releases the specified FIFO.
-  * @param  CANx:       where x can be 1 or 2 to to select the CAN peripheral. 
-  * @param  FIFONumber: FIFO to release, CAN_FIFO0 or CAN_FIFO1.
-  * @retval None.
-  */
-void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber)
-{
-  /* Check the parameters */
-  assert_param(IS_CAN_ALL_PERIPH(CANx));
-  assert_param(IS_CAN_FIFO(FIFONumber));
-  /* Release FIFO0 */
-  if (FIFONumber == CAN_FIFO0)
-  {
-    CANx->RF0R |= CAN_RF0R_RFOM0;
-  }
-  /* Release FIFO1 */
-  else /* FIFONumber == CAN_FIFO1 */
-  {
-    CANx->RF1R |= CAN_RF1R_RFOM1;
-  }
-}
-
-/**
-  * @brief  Returns the number of pending messages.
-  * @param  CANx:       where x can be 1 or 2 to to select the CAN peripheral.
-  * @param  FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
-  * @retval NbMessage : which is the number of pending message.
-  */
-uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber)
-{
-  uint8_t message_pending=0;
-  /* Check the parameters */
-  assert_param(IS_CAN_ALL_PERIPH(CANx));
-  assert_param(IS_CAN_FIFO(FIFONumber));
-  if (FIFONumber == CAN_FIFO0)
-  {
-    message_pending = (uint8_t)(CANx->RF0R&(uint32_t)0x03);
-  }
-  else if (FIFONumber == CAN_FIFO1)
-  {
-    message_pending = (uint8_t)(CANx->RF1R&(uint32_t)0x03);
-  }
-  else
-  {
-    message_pending = 0;
-  }
-  return message_pending;
-}
-
-
-/**
-  * @brief   Select the CAN Operation mode.
-  * @param CAN_OperatingMode : CAN Operating Mode. This parameter can be one 
-  *                            of @ref CAN_OperatingMode_TypeDef enumeration.
-  * @retval status of the requested mode which can be 
-  *         - CAN_ModeStatus_Failed    CAN failed entering the specific mode 
-  *         - CAN_ModeStatus_Success   CAN Succeed entering the specific mode 
-
-  */
-uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode)
-{
-  uint8_t status = CAN_ModeStatus_Failed;
-  
-  /* Timeout for INAK or also for SLAK bits*/
-  uint32_t timeout = INAK_TIMEOUT; 
-
-  /* Check the parameters */
-  assert_param(IS_CAN_ALL_PERIPH(CANx));
-  assert_param(IS_CAN_OPERATING_MODE(CAN_OperatingMode));
-
-  if (CAN_OperatingMode == CAN_OperatingMode_Initialization)
-  {
-    /* Request initialisation */
-    CANx->MCR = (uint32_t)((CANx->MCR & (uint32_t)(~(uint32_t)CAN_MCR_SLEEP)) | CAN_MCR_INRQ);
-
-    /* Wait the acknowledge */
-    while (((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_INAK) && (timeout != 0))
-    {
-      timeout--;
-    }
-    if ((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_INAK)
-    {
-      status = CAN_ModeStatus_Failed;
-    }
-    else
-    {
-      status = CAN_ModeStatus_Success;
-    }
-  }
-  else  if (CAN_OperatingMode == CAN_OperatingMode_Normal)
-  {
-    /* Request leave initialisation and sleep mode  and enter Normal mode */
-    CANx->MCR &= (uint32_t)(~(CAN_MCR_SLEEP|CAN_MCR_INRQ));
-
-    /* Wait the acknowledge */
-    while (((CANx->MSR & CAN_MODE_MASK) != 0) && (timeout!=0))
-    {
-      timeout--;
-    }
-    if ((CANx->MSR & CAN_MODE_MASK) != 0)
-    {
-      status = CAN_ModeStatus_Failed;
-    }
-    else
-    {
-      status = CAN_ModeStatus_Success;
-    }
-  }
-  else  if (CAN_OperatingMode == CAN_OperatingMode_Sleep)
-  {
-    /* Request Sleep mode */
-    CANx->MCR = (uint32_t)((CANx->MCR & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP);
-
-    /* Wait the acknowledge */
-    while (((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_SLAK) && (timeout!=0))
-    {
-      timeout--;
-    }
-    if ((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_SLAK)
-    {
-      status = CAN_ModeStatus_Failed;
-    }
-    else
-    {
-      status = CAN_ModeStatus_Success;
-    }
-  }
-  else
-  {
-    status = CAN_ModeStatus_Failed;
-  }
-
-  return  (uint8_t) status;
-}
-
-/**
-  * @brief  Enters the low power mode.
-  * @param  CANx:   where x can be 1 or 2 to to select the CAN peripheral.
-  * @retval status: CAN_Sleep_Ok if sleep entered, CAN_Sleep_Failed in an 
-  *                 other case.
-  */
-uint8_t CAN_Sleep(CAN_TypeDef* CANx)
-{
-  uint8_t sleepstatus = CAN_Sleep_Failed;
-  
-  /* Check the parameters */
-  assert_param(IS_CAN_ALL_PERIPH(CANx));
-    
-  /* Request Sleep mode */
-   CANx->MCR = (((CANx->MCR) & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP);
-   
-  /* Sleep mode status */
-  if ((CANx->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) == CAN_MSR_SLAK)
-  {
-    /* Sleep mode not entered */
-    sleepstatus =  CAN_Sleep_Ok;
-  }
-  /* return sleep mode status */
-   return (uint8_t)sleepstatus;
-}
-
-/**
-  * @brief  Wakes the CAN up.
-  * @param  CANx:    where x can be 1 or 2 to to select the CAN peripheral.
-  * @retval status:  CAN_WakeUp_Ok if sleep mode left, CAN_WakeUp_Failed in an 
-  *                  other case.
-  */
-uint8_t CAN_WakeUp(CAN_TypeDef* CANx)
-{
-  uint32_t wait_slak = SLAK_TIMEOUT;
-  uint8_t wakeupstatus = CAN_WakeUp_Failed;
-  
-  /* Check the parameters */
-  assert_param(IS_CAN_ALL_PERIPH(CANx));
-    
-  /* Wake up request */
-  CANx->MCR &= ~(uint32_t)CAN_MCR_SLEEP;
-    
-  /* Sleep mode status */
-  while(((CANx->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)&&(wait_slak!=0x00))
-  {
-   wait_slak--;
-  }
-  if((CANx->MSR & CAN_MSR_SLAK) != CAN_MSR_SLAK)
-  {
-   /* wake up done : Sleep mode exited */
-    wakeupstatus = CAN_WakeUp_Ok;
-  }
-  /* return wakeup status */
-  return (uint8_t)wakeupstatus;
-}
-
-
-/**
-  * @brief  Returns the CANx's last error code (LEC).
-  * @param  CANx:          where x can be 1 or 2 to to select the CAN peripheral.  
-  * @retval CAN_ErrorCode: specifies the Error code : 
-  *                        - CAN_ERRORCODE_NoErr            No Error  
-  *                        - CAN_ERRORCODE_StuffErr         Stuff Error
-  *                        - CAN_ERRORCODE_FormErr          Form Error
-  *                        - CAN_ERRORCODE_ACKErr           Acknowledgment Error
-  *                        - CAN_ERRORCODE_BitRecessiveErr  Bit Recessive Error
-  *                        - CAN_ERRORCODE_BitDominantErr   Bit Dominant Error
-  *                        - CAN_ERRORCODE_CRCErr           CRC Error
-  *                        - CAN_ERRORCODE_SoftwareSetErr   Software Set Error  
-  */
- 
-uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx)
-{
-  uint8_t errorcode=0;
-  
-  /* Check the parameters */
-  assert_param(IS_CAN_ALL_PERIPH(CANx));
-  
-  /* Get the error code*/
-  errorcode = (((uint8_t)CANx->ESR) & (uint8_t)CAN_ESR_LEC);
-  
-  /* Return the error code*/
-  return errorcode;
-}
-/**
-  * @brief  Returns the CANx Receive Error Counter (REC).
-  * @note   In case of an error during reception, this counter is incremented 
-  *         by 1 or by 8 depending on the error condition as defined by the CAN 
-  *         standard. After every successful reception, the counter is 
-  *         decremented by 1 or reset to 120 if its value was higher than 128. 
-  *         When the counter value exceeds 127, the CAN controller enters the 
-  *         error passive state.  
-  * @param  CANx: where x can be 1 or 2 to to select the CAN peripheral.  
-  * @retval CAN Receive Error Counter. 
-  */
-uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx)
-{
-  uint8_t counter=0;
-  
-  /* Check the parameters */
-  assert_param(IS_CAN_ALL_PERIPH(CANx));
-  
-  /* Get the Receive Error Counter*/
-  counter = (uint8_t)((CANx->ESR & CAN_ESR_REC)>> 24);
-  
-  /* Return the Receive Error Counter*/
-  return counter;
-}
-
-
-/**
-  * @brief  Returns the LSB of the 9-bit CANx Transmit Error Counter(TEC).
-  * @param  CANx:   where x can be 1 or 2 to to select the CAN peripheral.  
-  * @retval LSB of the 9-bit CAN Transmit Error Counter. 
-  */
-uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx)
-{
-  uint8_t counter=0;
-  
-  /* Check the parameters */
-  assert_param(IS_CAN_ALL_PERIPH(CANx));
-  
-  /* Get the LSB of the 9-bit CANx Transmit Error Counter(TEC) */
-  counter = (uint8_t)((CANx->ESR & CAN_ESR_TEC)>> 16);
-  
-  /* Return the LSB of the 9-bit CANx Transmit Error Counter(TEC) */
-  return counter;
-}
-
-
-/**
-  * @brief  Enables or disables the specified CANx interrupts.
-  * @param  CANx:   where x can be 1 or 2 to to select the CAN peripheral.
-  * @param  CAN_IT: specifies the CAN interrupt sources to be enabled or disabled.
-  *                 This parameter can be: 
-  *                 - CAN_IT_TME, 
-  *                 - CAN_IT_FMP0, 
-  *                 - CAN_IT_FF0,
-  *                 - CAN_IT_FOV0, 
-  *                 - CAN_IT_FMP1, 
-  *                 - CAN_IT_FF1,
-  *                 - CAN_IT_FOV1, 
-  *                 - CAN_IT_EWG, 
-  *                 - CAN_IT_EPV,
-  *                 - CAN_IT_LEC, 
-  *                 - CAN_IT_ERR, 
-  *                 - CAN_IT_WKU or 
-  *                 - CAN_IT_SLK.
-  * @param  NewState: new state of the CAN interrupts.
-  *                   This parameter can be: ENABLE or DISABLE.
-  * @retval None.
-  */
-void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_CAN_ALL_PERIPH(CANx));
-  assert_param(IS_CAN_IT(CAN_IT));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-
-  if (NewState != DISABLE)
-  {
-    /* Enable the selected CANx interrupt */
-    CANx->IER |= CAN_IT;
-  }
-  else
-  {
-    /* Disable the selected CANx interrupt */
-    CANx->IER &= ~CAN_IT;
-  }
-}
-/**
-  * @brief  Checks whether the specified CAN flag is set or not.
-  * @param  CANx:     where x can be 1 or 2 to to select the CAN peripheral.
-  * @param  CAN_FLAG: specifies the flag to check.
-  *                   This parameter can be one of the following flags: 
-  *                  - CAN_FLAG_EWG
-  *                  - CAN_FLAG_EPV 
-  *                  - CAN_FLAG_BOF
-  *                  - CAN_FLAG_RQCP0
-  *                  - CAN_FLAG_RQCP1
-  *                  - CAN_FLAG_RQCP2
-  *                  - CAN_FLAG_FMP1   
-  *                  - CAN_FLAG_FF1       
-  *                  - CAN_FLAG_FOV1   
-  *                  - CAN_FLAG_FMP0   
-  *                  - CAN_FLAG_FF0       
-  *                  - CAN_FLAG_FOV0   
-  *                  - CAN_FLAG_WKU 
-  *                  - CAN_FLAG_SLAK  
-  *                  - CAN_FLAG_LEC       
-  * @retval The new state of CAN_FLAG (SET or RESET).
-  */
-FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG)
-{
-  FlagStatus bitstatus = RESET;
-  
-  /* Check the parameters */
-  assert_param(IS_CAN_ALL_PERIPH(CANx));
-  assert_param(IS_CAN_GET_FLAG(CAN_FLAG));
-  
-
-  if((CAN_FLAG & CAN_FLAGS_ESR) != (uint32_t)RESET)
-  { 
-    /* Check the status of the specified CAN flag */
-    if ((CANx->ESR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
-    { 
-      /* CAN_FLAG is set */
-      bitstatus = SET;
-    }
-    else
-    { 
-      /* CAN_FLAG is reset */
-      bitstatus = RESET;
-    }
-  }
-  else if((CAN_FLAG & CAN_FLAGS_MSR) != (uint32_t)RESET)
-  { 
-    /* Check the status of the specified CAN flag */
-    if ((CANx->MSR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
-    { 
-      /* CAN_FLAG is set */
-      bitstatus = SET;
-    }
-    else
-    { 
-      /* CAN_FLAG is reset */
-      bitstatus = RESET;
-    }
-  }
-  else if((CAN_FLAG & CAN_FLAGS_TSR) != (uint32_t)RESET)
-  { 
-    /* Check the status of the specified CAN flag */
-    if ((CANx->TSR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
-    { 
-      /* CAN_FLAG is set */
-      bitstatus = SET;
-    }
-    else
-    { 
-      /* CAN_FLAG is reset */
-      bitstatus = RESET;
-    }
-  }
-  else if((CAN_FLAG & CAN_FLAGS_RF0R) != (uint32_t)RESET)
-  { 
-    /* Check the status of the specified CAN flag */
-    if ((CANx->RF0R & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
-    { 
-      /* CAN_FLAG is set */
-      bitstatus = SET;
-    }
-    else
-    { 
-      /* CAN_FLAG is reset */
-      bitstatus = RESET;
-    }
-  }
-  else /* If(CAN_FLAG & CAN_FLAGS_RF1R != (uint32_t)RESET) */
-  { 
-    /* Check the status of the specified CAN flag */
-    if ((uint32_t)(CANx->RF1R & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
-    { 
-      /* CAN_FLAG is set */
-      bitstatus = SET;
-    }
-    else
-    { 
-      /* CAN_FLAG is reset */
-      bitstatus = RESET;
-    }
-  }
-  /* Return the CAN_FLAG status */
-  return  bitstatus;
-}
-
-/**
-  * @brief  Clears the CAN's pending flags.
-  * @param  CANx:     where x can be 1 or 2 to to select the CAN peripheral.
-  * @param  CAN_FLAG: specifies the flag to clear.
-  *                   This parameter can be one of the following flags: 
-  *                    - CAN_FLAG_RQCP0
-  *                    - CAN_FLAG_RQCP1
-  *                    - CAN_FLAG_RQCP2
-  *                    - CAN_FLAG_FF1       
-  *                    - CAN_FLAG_FOV1   
-  *                    - CAN_FLAG_FF0       
-  *                    - CAN_FLAG_FOV0   
-  *                    - CAN_FLAG_WKU   
-  *                    - CAN_FLAG_SLAK    
-  *                    - CAN_FLAG_LEC       
-  * @retval None.
-  */
-void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG)
-{
-  uint32_t flagtmp=0;
-  /* Check the parameters */
-  assert_param(IS_CAN_ALL_PERIPH(CANx));
-  assert_param(IS_CAN_CLEAR_FLAG(CAN_FLAG));
-  
-  if (CAN_FLAG == CAN_FLAG_LEC) /* ESR register */
-  {
-    /* Clear the selected CAN flags */
-    CANx->ESR = (uint32_t)RESET;
-  }
-  else /* MSR or TSR or RF0R or RF1R */
-  {
-    flagtmp = CAN_FLAG & 0x000FFFFF;
-
-    if ((CAN_FLAG & CAN_FLAGS_RF0R)!=(uint32_t)RESET)
-    {
-      /* Receive Flags */
-      CANx->RF0R = (uint32_t)(flagtmp);
-    }
-    else if ((CAN_FLAG & CAN_FLAGS_RF1R)!=(uint32_t)RESET)
-    {
-      /* Receive Flags */
-      CANx->RF1R = (uint32_t)(flagtmp);
-    }
-    else if ((CAN_FLAG & CAN_FLAGS_TSR)!=(uint32_t)RESET)
-    {
-      /* Transmit Flags */
-      CANx->TSR = (uint32_t)(flagtmp);
-    }
-    else /* If((CAN_FLAG & CAN_FLAGS_MSR)!=(uint32_t)RESET) */
-    {
-      /* Operating mode Flags */
-      CANx->MSR = (uint32_t)(flagtmp);
-    }
-  }
-}
-
-/**
-  * @brief  Checks whether the specified CANx interrupt has occurred or not.
-  * @param  CANx:    where x can be 1 or 2 to to select the CAN peripheral.
-  * @param  CAN_IT:  specifies the CAN interrupt source to check.
-  *                  This parameter can be one of the following flags: 
-  *                 -  CAN_IT_TME               
-  *                 -  CAN_IT_FMP0              
-  *                 -  CAN_IT_FF0               
-  *                 -  CAN_IT_FOV0              
-  *                 -  CAN_IT_FMP1              
-  *                 -  CAN_IT_FF1               
-  *                 -  CAN_IT_FOV1              
-  *                 -  CAN_IT_WKU  
-  *                 -  CAN_IT_SLK  
-  *                 -  CAN_IT_EWG    
-  *                 -  CAN_IT_EPV    
-  *                 -  CAN_IT_BOF    
-  *                 -  CAN_IT_LEC    
-  *                 -  CAN_IT_ERR 
-  * @retval The current state of CAN_IT (SET or RESET).
-  */
-ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT)
-{
-  ITStatus itstatus = RESET;
-  /* Check the parameters */
-  assert_param(IS_CAN_ALL_PERIPH(CANx));
-  assert_param(IS_CAN_IT(CAN_IT));
-  
-  /* check the enable interrupt bit */
- if((CANx->IER & CAN_IT) != RESET)
- {
-   /* in case the Interrupt is enabled, .... */
-    switch (CAN_IT)
-    {
-      case CAN_IT_TME:
-               /* Check CAN_TSR_RQCPx bits */
-	             itstatus = CheckITStatus(CANx->TSR, CAN_TSR_RQCP0|CAN_TSR_RQCP1|CAN_TSR_RQCP2);  
-	      break;
-      case CAN_IT_FMP0:
-               /* Check CAN_RF0R_FMP0 bit */
-	             itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FMP0);  
-	      break;
-      case CAN_IT_FF0:
-               /* Check CAN_RF0R_FULL0 bit */
-               itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FULL0);  
-	      break;
-      case CAN_IT_FOV0:
-               /* Check CAN_RF0R_FOVR0 bit */
-               itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FOVR0);  
-	      break;
-      case CAN_IT_FMP1:
-               /* Check CAN_RF1R_FMP1 bit */
-               itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FMP1);  
-	      break;
-      case CAN_IT_FF1:
-               /* Check CAN_RF1R_FULL1 bit */
-	             itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FULL1);  
-	      break;
-      case CAN_IT_FOV1:
-               /* Check CAN_RF1R_FOVR1 bit */
-	             itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FOVR1);  
-	      break;
-      case CAN_IT_WKU:
-               /* Check CAN_MSR_WKUI bit */
-               itstatus = CheckITStatus(CANx->MSR, CAN_MSR_WKUI);  
-	      break;
-      case CAN_IT_SLK:
-               /* Check CAN_MSR_SLAKI bit */
-	             itstatus = CheckITStatus(CANx->MSR, CAN_MSR_SLAKI);  
-	      break;
-      case CAN_IT_EWG:
-               /* Check CAN_ESR_EWGF bit */
-	             itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EWGF);  
-	      break;
-      case CAN_IT_EPV:
-               /* Check CAN_ESR_EPVF bit */
-	             itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EPVF);  
-	      break;
-      case CAN_IT_BOF:
-               /* Check CAN_ESR_BOFF bit */
-	             itstatus = CheckITStatus(CANx->ESR, CAN_ESR_BOFF);  
-	      break;
-      case CAN_IT_LEC:
-               /* Check CAN_ESR_LEC bit */
-	             itstatus = CheckITStatus(CANx->ESR, CAN_ESR_LEC);  
-	      break;
-      case CAN_IT_ERR:
-               /* Check CAN_MSR_ERRI bit */ 
-               itstatus = CheckITStatus(CANx->MSR, CAN_MSR_ERRI); 
-	      break;
-      default :
-               /* in case of error, return RESET */
-              itstatus = RESET;
-              break;
-    }
-  }
-  else
-  {
-   /* in case the Interrupt is not enabled, return RESET */
-    itstatus  = RESET;
-  }
-  
-  /* Return the CAN_IT status */
-  return  itstatus;
-}
-
-/**
-  * @brief  Clears the CANx's interrupt pending bits.
-  * @param  CANx:    where x can be 1 or 2 to to select the CAN peripheral.
-  * @param  CAN_IT: specifies the interrupt pending bit to clear.
-  *                  -  CAN_IT_TME                     
-  *                  -  CAN_IT_FF0               
-  *                  -  CAN_IT_FOV0                     
-  *                  -  CAN_IT_FF1               
-  *                  -  CAN_IT_FOV1              
-  *                  -  CAN_IT_WKU  
-  *                  -  CAN_IT_SLK  
-  *                  -  CAN_IT_EWG    
-  *                  -  CAN_IT_EPV    
-  *                  -  CAN_IT_BOF    
-  *                  -  CAN_IT_LEC    
-  *                  -  CAN_IT_ERR 
-  * @retval None.
-  */
-void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT)
-{
-  /* Check the parameters */
-  assert_param(IS_CAN_ALL_PERIPH(CANx));
-  assert_param(IS_CAN_CLEAR_IT(CAN_IT));
-
-  switch (CAN_IT)
-  {
-      case CAN_IT_TME:
-              /* Clear CAN_TSR_RQCPx (rc_w1)*/
-	      CANx->TSR = CAN_TSR_RQCP0|CAN_TSR_RQCP1|CAN_TSR_RQCP2;  
-	      break;
-      case CAN_IT_FF0:
-              /* Clear CAN_RF0R_FULL0 (rc_w1)*/
-	      CANx->RF0R = CAN_RF0R_FULL0; 
-	      break;
-      case CAN_IT_FOV0:
-              /* Clear CAN_RF0R_FOVR0 (rc_w1)*/
-	      CANx->RF0R = CAN_RF0R_FOVR0; 
-	      break;
-      case CAN_IT_FF1:
-              /* Clear CAN_RF1R_FULL1 (rc_w1)*/
-	      CANx->RF1R = CAN_RF1R_FULL1;  
-	      break;
-      case CAN_IT_FOV1:
-              /* Clear CAN_RF1R_FOVR1 (rc_w1)*/
-	      CANx->RF1R = CAN_RF1R_FOVR1; 
-	      break;
-      case CAN_IT_WKU:
-              /* Clear CAN_MSR_WKUI (rc_w1)*/
-	      CANx->MSR = CAN_MSR_WKUI;  
-	      break;
-      case CAN_IT_SLK:
-              /* Clear CAN_MSR_SLAKI (rc_w1)*/ 
-	      CANx->MSR = CAN_MSR_SLAKI;   
-	      break;
-      case CAN_IT_EWG:
-              /* Clear CAN_MSR_ERRI (rc_w1) */
-	      CANx->MSR = CAN_MSR_ERRI;
-              /* Note : the corresponding Flag is cleared by hardware depending 
-                        of the CAN Bus status*/ 
-	      break;
-      case CAN_IT_EPV:
-              /* Clear CAN_MSR_ERRI (rc_w1) */
-	      CANx->MSR = CAN_MSR_ERRI; 
-              /* Note : the corresponding Flag is cleared by hardware depending 
-                        of the CAN Bus status*/
-	      break;
-      case CAN_IT_BOF:
-              /* Clear CAN_MSR_ERRI (rc_w1) */ 
-	      CANx->MSR = CAN_MSR_ERRI; 
-              /* Note : the corresponding Flag is cleared by hardware depending 
-                        of the CAN Bus status*/
-	      break;
-      case CAN_IT_LEC:
-              /*  Clear LEC bits */
-	      CANx->ESR = RESET; 
-              /* Clear CAN_MSR_ERRI (rc_w1) */
-	      CANx->MSR = CAN_MSR_ERRI; 
-	      break;
-      case CAN_IT_ERR:
-              /*Clear LEC bits */
-	      CANx->ESR = RESET; 
-              /* Clear CAN_MSR_ERRI (rc_w1) */
-	      CANx->MSR = CAN_MSR_ERRI; 
-	      /* Note : BOFF, EPVF and EWGF Flags are cleared by hardware depending 
-                  of the CAN Bus status*/
-	      break;
-      default :
-	      break;
-   }
-}
-
-/**
-  * @brief  Checks whether the CAN interrupt has occurred or not.
-  * @param  CAN_Reg: specifies the CAN interrupt register to check.
-  * @param  It_Bit:  specifies the interrupt source bit to check.
-  * @retval The new state of the CAN Interrupt (SET or RESET).
-  */
-static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit)
-{
-  ITStatus pendingbitstatus = RESET;
-  
-  if ((CAN_Reg & It_Bit) != (uint32_t)RESET)
-  {
-    /* CAN_IT is set */
-    pendingbitstatus = SET;
-  }
-  else
-  {
-    /* CAN_IT is reset */
-    pendingbitstatus = RESET;
-  }
-  return pendingbitstatus;
-}
-
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_cec.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_cec.c
deleted file mode 100644
index 4dc615f..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_cec.c
+++ /dev/null
@@ -1,433 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f10x_cec.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    11-March-2011
-  * @brief   This file provides all the CEC firmware functions.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_cec.h"
-#include "stm32f10x_rcc.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Driver
-  * @{
-  */
-
-/** @defgroup CEC 
-  * @brief CEC driver modules
-  * @{
-  */
-
-/** @defgroup CEC_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-
-/** @defgroup CEC_Private_Defines
-  * @{
-  */ 
-
-/* ------------ CEC registers bit address in the alias region ----------- */
-#define CEC_OFFSET                (CEC_BASE - PERIPH_BASE)
-
-/* --- CFGR Register ---*/
-
-/* Alias word address of PE bit */
-#define CFGR_OFFSET                 (CEC_OFFSET + 0x00)
-#define PE_BitNumber                0x00
-#define CFGR_PE_BB                  (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (PE_BitNumber * 4))
-
-/* Alias word address of IE bit */
-#define IE_BitNumber                0x01
-#define CFGR_IE_BB                  (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (IE_BitNumber * 4))
-
-/* --- CSR Register ---*/
-
-/* Alias word address of TSOM bit */
-#define CSR_OFFSET                  (CEC_OFFSET + 0x10)
-#define TSOM_BitNumber              0x00
-#define CSR_TSOM_BB                 (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TSOM_BitNumber * 4))
-
-/* Alias word address of TEOM bit */
-#define TEOM_BitNumber              0x01
-#define CSR_TEOM_BB                 (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEOM_BitNumber * 4))
-  
-#define CFGR_CLEAR_Mask            (uint8_t)(0xF3)        /* CFGR register Mask */
-#define FLAG_Mask                  ((uint32_t)0x00FFFFFF) /* CEC FLAG mask */
- 
-/**
-  * @}
-  */ 
-
-
-/** @defgroup CEC_Private_Macros
-  * @{
-  */ 
-
-/**
-  * @}
-  */ 
-
-
-/** @defgroup CEC_Private_Variables
-  * @{
-  */ 
-
-/**
-  * @}
-  */ 
-
-
-/** @defgroup CEC_Private_FunctionPrototypes
-  * @{
-  */
- 
-/**
-  * @}
-  */ 
-
-
-/** @defgroup CEC_Private_Functions
-  * @{
-  */ 
-
-/**
-  * @brief  Deinitializes the CEC peripheral registers to their default reset 
-  *         values.
-  * @param  None
-  * @retval None
-  */
-void CEC_DeInit(void)
-{
-  /* Enable CEC reset state */
-  RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, ENABLE);  
-  /* Release CEC from reset state */
-  RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, DISABLE); 
-}
-
-
-/**
-  * @brief  Initializes the CEC peripheral according to the specified 
-  *         parameters in the CEC_InitStruct.
-  * @param  CEC_InitStruct: pointer to an CEC_InitTypeDef structure that
-  *         contains the configuration information for the specified
-  *         CEC peripheral.
-  * @retval None
-  */
-void CEC_Init(CEC_InitTypeDef* CEC_InitStruct)
-{
-  uint16_t tmpreg = 0;
- 
-  /* Check the parameters */
-  assert_param(IS_CEC_BIT_TIMING_ERROR_MODE(CEC_InitStruct->CEC_BitTimingMode)); 
-  assert_param(IS_CEC_BIT_PERIOD_ERROR_MODE(CEC_InitStruct->CEC_BitPeriodMode));
-     
-  /*---------------------------- CEC CFGR Configuration -----------------*/
-  /* Get the CEC CFGR value */
-  tmpreg = CEC->CFGR;
-  
-  /* Clear BTEM and BPEM bits */
-  tmpreg &= CFGR_CLEAR_Mask;
-  
-  /* Configure CEC: Bit Timing Error and Bit Period Error */
-  tmpreg |= (uint16_t)(CEC_InitStruct->CEC_BitTimingMode | CEC_InitStruct->CEC_BitPeriodMode);
-
-  /* Write to CEC CFGR  register*/
-  CEC->CFGR = tmpreg;
-  
-}
-
-/**
-  * @brief  Enables or disables the specified CEC peripheral.
-  * @param  NewState: new state of the CEC peripheral. 
-  *     This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void CEC_Cmd(FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-
-  *(__IO uint32_t *) CFGR_PE_BB = (uint32_t)NewState;
-
-  if(NewState == DISABLE)
-  {
-    /* Wait until the PE bit is cleared by hardware (Idle Line detected) */
-    while((CEC->CFGR & CEC_CFGR_PE) != (uint32_t)RESET)
-    {
-    }  
-  }  
-}
-
-/**
-  * @brief  Enables or disables the CEC interrupt.
-  * @param  NewState: new state of the CEC interrupt.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void CEC_ITConfig(FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-
-  *(__IO uint32_t *) CFGR_IE_BB = (uint32_t)NewState;
-}
-
-/**
-  * @brief  Defines the Own Address of the CEC device.
-  * @param  CEC_OwnAddress: The CEC own address
-  * @retval None
-  */
-void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress)
-{
-  /* Check the parameters */
-  assert_param(IS_CEC_ADDRESS(CEC_OwnAddress));
-
-  /* Set the CEC own address */
-  CEC->OAR = CEC_OwnAddress;
-}
-
-/**
-  * @brief  Sets the CEC prescaler value.
-  * @param  CEC_Prescaler: CEC prescaler new value
-  * @retval None
-  */
-void CEC_SetPrescaler(uint16_t CEC_Prescaler)
-{
-  /* Check the parameters */
-  assert_param(IS_CEC_PRESCALER(CEC_Prescaler));
-
-  /* Set the  Prescaler value*/
-  CEC->PRES = CEC_Prescaler;
-}
-
-/**
-  * @brief  Transmits single data through the CEC peripheral.
-  * @param  Data: the data to transmit.
-  * @retval None
-  */
-void CEC_SendDataByte(uint8_t Data)
-{  
-  /* Transmit Data */
-  CEC->TXD = Data ;
-}
-
-
-/**
-  * @brief  Returns the most recent received data by the CEC peripheral.
-  * @param  None
-  * @retval The received data.
-  */
-uint8_t CEC_ReceiveDataByte(void)
-{
-  /* Receive Data */
-  return (uint8_t)(CEC->RXD);
-}
-
-/**
-  * @brief  Starts a new message.
-  * @param  None
-  * @retval None
-  */
-void CEC_StartOfMessage(void)
-{  
-  /* Starts of new message */
-  *(__IO uint32_t *) CSR_TSOM_BB = (uint32_t)0x1;
-}
-
-/**
-  * @brief  Transmits message with or without an EOM bit.
-  * @param  NewState: new state of the CEC Tx End Of Message. 
-  *     This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void CEC_EndOfMessageCmd(FunctionalState NewState)
-{   
-  /* Check the parameters */
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  
-  /* The data byte will be transmitted with or without an EOM bit*/
-  *(__IO uint32_t *) CSR_TEOM_BB = (uint32_t)NewState;
-}
-
-/**
-  * @brief  Gets the CEC flag status
-  * @param  CEC_FLAG: specifies the CEC flag to check. 
-  *   This parameter can be one of the following values:
-  *     @arg CEC_FLAG_BTE: Bit Timing Error
-  *     @arg CEC_FLAG_BPE: Bit Period Error
-  *     @arg CEC_FLAG_RBTFE: Rx Block Transfer Finished Error
-  *     @arg CEC_FLAG_SBE: Start Bit Error
-  *     @arg CEC_FLAG_ACKE: Block Acknowledge Error
-  *     @arg CEC_FLAG_LINE: Line Error
-  *     @arg CEC_FLAG_TBTFE: Tx Block Transfer Finished Error
-  *     @arg CEC_FLAG_TEOM: Tx End Of Message 
-  *     @arg CEC_FLAG_TERR: Tx Error
-  *     @arg CEC_FLAG_TBTRF: Tx Byte Transfer Request or Block Transfer Finished
-  *     @arg CEC_FLAG_RSOM: Rx Start Of Message
-  *     @arg CEC_FLAG_REOM: Rx End Of Message
-  *     @arg CEC_FLAG_RERR: Rx Error
-  *     @arg CEC_FLAG_RBTF: Rx Byte/Block Transfer Finished
-  * @retval The new state of CEC_FLAG (SET or RESET)
-  */
-FlagStatus CEC_GetFlagStatus(uint32_t CEC_FLAG) 
-{
-  FlagStatus bitstatus = RESET;
-  uint32_t cecreg = 0, cecbase = 0;
-  
-  /* Check the parameters */
-  assert_param(IS_CEC_GET_FLAG(CEC_FLAG));
- 
-  /* Get the CEC peripheral base address */
-  cecbase = (uint32_t)(CEC_BASE);
-  
-  /* Read flag register index */
-  cecreg = CEC_FLAG >> 28;
-  
-  /* Get bit[23:0] of the flag */
-  CEC_FLAG &= FLAG_Mask;
-  
-  if(cecreg != 0)
-  {
-    /* Flag in CEC ESR Register */
-    CEC_FLAG = (uint32_t)(CEC_FLAG >> 16);
-    
-    /* Get the CEC ESR register address */
-    cecbase += 0xC;
-  }
-  else
-  {
-    /* Get the CEC CSR register address */
-    cecbase += 0x10;
-  }
-  
-  if(((*(__IO uint32_t *)cecbase) & CEC_FLAG) != (uint32_t)RESET)
-  {
-    /* CEC_FLAG is set */
-    bitstatus = SET;
-  }
-  else
-  {
-    /* CEC_FLAG is reset */
-    bitstatus = RESET;
-  }
-  
-  /* Return the CEC_FLAG status */
-  return  bitstatus;
-}
-
-/**
-  * @brief  Clears the CEC's pending flags.
-  * @param  CEC_FLAG: specifies the flag to clear. 
-  *   This parameter can be any combination of the following values:
-  *     @arg CEC_FLAG_TERR: Tx Error
-  *     @arg CEC_FLAG_TBTRF: Tx Byte Transfer Request or Block Transfer Finished
-  *     @arg CEC_FLAG_RSOM: Rx Start Of Message
-  *     @arg CEC_FLAG_REOM: Rx End Of Message
-  *     @arg CEC_FLAG_RERR: Rx Error
-  *     @arg CEC_FLAG_RBTF: Rx Byte/Block Transfer Finished
-  * @retval None
-  */
-void CEC_ClearFlag(uint32_t CEC_FLAG)
-{ 
-  uint32_t tmp = 0x0;
-  
-  /* Check the parameters */
-  assert_param(IS_CEC_CLEAR_FLAG(CEC_FLAG));
-
-  tmp = CEC->CSR & 0x2;
-       
-  /* Clear the selected CEC flags */
-  CEC->CSR &= (uint32_t)(((~(uint32_t)CEC_FLAG) & 0xFFFFFFFC) | tmp);
-}
-
-/**
-  * @brief  Checks whether the specified CEC interrupt has occurred or not.
-  * @param  CEC_IT: specifies the CEC interrupt source to check. 
-  *   This parameter can be one of the following values:
-  *     @arg CEC_IT_TERR: Tx Error
-  *     @arg CEC_IT_TBTF: Tx Block Transfer Finished
-  *     @arg CEC_IT_RERR: Rx Error
-  *     @arg CEC_IT_RBTF: Rx Block Transfer Finished
-  * @retval The new state of CEC_IT (SET or RESET).
-  */
-ITStatus CEC_GetITStatus(uint8_t CEC_IT)
-{
-  ITStatus bitstatus = RESET;
-  uint32_t enablestatus = 0;
-  
-  /* Check the parameters */
-   assert_param(IS_CEC_GET_IT(CEC_IT));
-   
-  /* Get the CEC IT enable bit status */
-  enablestatus = (CEC->CFGR & (uint8_t)CEC_CFGR_IE) ;
-  
-  /* Check the status of the specified CEC interrupt */
-  if (((CEC->CSR & CEC_IT) != (uint32_t)RESET) && enablestatus)
-  {
-    /* CEC_IT is set */
-    bitstatus = SET;
-  }
-  else
-  {
-    /* CEC_IT is reset */
-    bitstatus = RESET;
-  }
-  /* Return the CEC_IT status */
-  return  bitstatus;
-}
-
-/**
-  * @brief  Clears the CEC's interrupt pending bits.
-  * @param  CEC_IT: specifies the CEC interrupt pending bit to clear.
-  *   This parameter can be any combination of the following values:
-  *     @arg CEC_IT_TERR: Tx Error
-  *     @arg CEC_IT_TBTF: Tx Block Transfer Finished
-  *     @arg CEC_IT_RERR: Rx Error
-  *     @arg CEC_IT_RBTF: Rx Block Transfer Finished
-  * @retval None
-  */
-void CEC_ClearITPendingBit(uint16_t CEC_IT)
-{
-  uint32_t tmp = 0x0;
-  
-  /* Check the parameters */
-  assert_param(IS_CEC_GET_IT(CEC_IT));
-  
-  tmp = CEC->CSR & 0x2;
-  
-  /* Clear the selected CEC interrupt pending bits */
-  CEC->CSR &= (uint32_t)(((~(uint32_t)CEC_IT) & 0xFFFFFFFC) | tmp);
-}
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dbgmcu.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dbgmcu.c
deleted file mode 100644
index 96a8fde..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dbgmcu.c
+++ /dev/null
@@ -1,162 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f10x_dbgmcu.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    11-March-2011
-  * @brief   This file provides all the DBGMCU firmware functions.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_dbgmcu.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Driver
-  * @{
-  */
-
-/** @defgroup DBGMCU 
-  * @brief DBGMCU driver modules
-  * @{
-  */ 
-
-/** @defgroup DBGMCU_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup DBGMCU_Private_Defines
-  * @{
-  */
-
-#define IDCODE_DEVID_MASK    ((uint32_t)0x00000FFF)
-/**
-  * @}
-  */
-
-/** @defgroup DBGMCU_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup DBGMCU_Private_Variables
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup DBGMCU_Private_FunctionPrototypes
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup DBGMCU_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Returns the device revision identifier.
-  * @param  None
-  * @retval Device revision identifier
-  */
-uint32_t DBGMCU_GetREVID(void)
-{
-   return(DBGMCU->IDCODE >> 16);
-}
-
-/**
-  * @brief  Returns the device identifier.
-  * @param  None
-  * @retval Device identifier
-  */
-uint32_t DBGMCU_GetDEVID(void)
-{
-   return(DBGMCU->IDCODE & IDCODE_DEVID_MASK);
-}
-
-/**
-  * @brief  Configures the specified peripheral and low power mode behavior
-  *   when the MCU under Debug mode.
-  * @param  DBGMCU_Periph: specifies the peripheral and low power mode.
-  *   This parameter can be any combination of the following values:
-  *     @arg DBGMCU_SLEEP: Keep debugger connection during SLEEP mode              
-  *     @arg DBGMCU_STOP: Keep debugger connection during STOP mode               
-  *     @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode            
-  *     @arg DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted          
-  *     @arg DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted          
-  *     @arg DBGMCU_TIM1_STOP: TIM1 counter stopped when Core is halted          
-  *     @arg DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted          
-  *     @arg DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted          
-  *     @arg DBGMCU_TIM4_STOP: TIM4 counter stopped when Core is halted          
-  *     @arg DBGMCU_CAN1_STOP: Debug CAN2 stopped when Core is halted           
-  *     @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when Core is halted
-  *     @arg DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when Core is halted
-  *     @arg DBGMCU_TIM5_STOP: TIM5 counter stopped when Core is halted          
-  *     @arg DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted          
-  *     @arg DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted          
-  *     @arg DBGMCU_TIM8_STOP: TIM8 counter stopped when Core is halted
-  *     @arg DBGMCU_CAN2_STOP: Debug CAN2 stopped when Core is halted 
-  *     @arg DBGMCU_TIM15_STOP: TIM15 counter stopped when Core is halted
-  *     @arg DBGMCU_TIM16_STOP: TIM16 counter stopped when Core is halted
-  *     @arg DBGMCU_TIM17_STOP: TIM17 counter stopped when Core is halted                
-  *     @arg DBGMCU_TIM9_STOP: TIM9 counter stopped when Core is halted
-  *     @arg DBGMCU_TIM10_STOP: TIM10 counter stopped when Core is halted
-  *     @arg DBGMCU_TIM11_STOP: TIM11 counter stopped when Core is halted
-  *     @arg DBGMCU_TIM12_STOP: TIM12 counter stopped when Core is halted
-  *     @arg DBGMCU_TIM13_STOP: TIM13 counter stopped when Core is halted
-  *     @arg DBGMCU_TIM14_STOP: TIM14 counter stopped when Core is halted
-  * @param  NewState: new state of the specified peripheral in Debug mode.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-
-  if (NewState != DISABLE)
-  {
-    DBGMCU->CR |= DBGMCU_Periph;
-  }
-  else
-  {
-    DBGMCU->CR &= ~DBGMCU_Periph;
-  }
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dma.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dma.c
deleted file mode 100644
index bf072df..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dma.c
+++ /dev/null
@@ -1,714 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f10x_dma.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    11-March-2011
-  * @brief   This file provides all the DMA firmware functions.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_dma.h"
-#include "stm32f10x_rcc.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Driver
-  * @{
-  */
-
-/** @defgroup DMA 
-  * @brief DMA driver modules
-  * @{
-  */ 
-
-/** @defgroup DMA_Private_TypesDefinitions
-  * @{
-  */ 
-/**
-  * @}
-  */
-
-/** @defgroup DMA_Private_Defines
-  * @{
-  */
-
-
-/* DMA1 Channelx interrupt pending bit masks */
-#define DMA1_Channel1_IT_Mask    ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))
-#define DMA1_Channel2_IT_Mask    ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2))
-#define DMA1_Channel3_IT_Mask    ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3))
-#define DMA1_Channel4_IT_Mask    ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4))
-#define DMA1_Channel5_IT_Mask    ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5))
-#define DMA1_Channel6_IT_Mask    ((uint32_t)(DMA_ISR_GIF6 | DMA_ISR_TCIF6 | DMA_ISR_HTIF6 | DMA_ISR_TEIF6))
-#define DMA1_Channel7_IT_Mask    ((uint32_t)(DMA_ISR_GIF7 | DMA_ISR_TCIF7 | DMA_ISR_HTIF7 | DMA_ISR_TEIF7))
-
-/* DMA2 Channelx interrupt pending bit masks */
-#define DMA2_Channel1_IT_Mask    ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))
-#define DMA2_Channel2_IT_Mask    ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2))
-#define DMA2_Channel3_IT_Mask    ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3))
-#define DMA2_Channel4_IT_Mask    ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4))
-#define DMA2_Channel5_IT_Mask    ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5))
-
-/* DMA2 FLAG mask */
-#define FLAG_Mask                ((uint32_t)0x10000000)
-
-/* DMA registers Masks */
-#define CCR_CLEAR_Mask           ((uint32_t)0xFFFF800F)
-
-/**
-  * @}
-  */
-
-/** @defgroup DMA_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup DMA_Private_Variables
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup DMA_Private_FunctionPrototypes
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup DMA_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Deinitializes the DMAy Channelx registers to their default reset
-  *         values.
-  * @param  DMAy_Channelx: where y can be 1 or 2 to select the DMA and
-  *   x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
-  * @retval None
-  */
-void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx)
-{
-  /* Check the parameters */
-  assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
-  
-  /* Disable the selected DMAy Channelx */
-  DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN);
-  
-  /* Reset DMAy Channelx control register */
-  DMAy_Channelx->CCR  = 0;
-  
-  /* Reset DMAy Channelx remaining bytes register */
-  DMAy_Channelx->CNDTR = 0;
-  
-  /* Reset DMAy Channelx peripheral address register */
-  DMAy_Channelx->CPAR  = 0;
-  
-  /* Reset DMAy Channelx memory address register */
-  DMAy_Channelx->CMAR = 0;
-  
-  if (DMAy_Channelx == DMA1_Channel1)
-  {
-    /* Reset interrupt pending bits for DMA1 Channel1 */
-    DMA1->IFCR |= DMA1_Channel1_IT_Mask;
-  }
-  else if (DMAy_Channelx == DMA1_Channel2)
-  {
-    /* Reset interrupt pending bits for DMA1 Channel2 */
-    DMA1->IFCR |= DMA1_Channel2_IT_Mask;
-  }
-  else if (DMAy_Channelx == DMA1_Channel3)
-  {
-    /* Reset interrupt pending bits for DMA1 Channel3 */
-    DMA1->IFCR |= DMA1_Channel3_IT_Mask;
-  }
-  else if (DMAy_Channelx == DMA1_Channel4)
-  {
-    /* Reset interrupt pending bits for DMA1 Channel4 */
-    DMA1->IFCR |= DMA1_Channel4_IT_Mask;
-  }
-  else if (DMAy_Channelx == DMA1_Channel5)
-  {
-    /* Reset interrupt pending bits for DMA1 Channel5 */
-    DMA1->IFCR |= DMA1_Channel5_IT_Mask;
-  }
-  else if (DMAy_Channelx == DMA1_Channel6)
-  {
-    /* Reset interrupt pending bits for DMA1 Channel6 */
-    DMA1->IFCR |= DMA1_Channel6_IT_Mask;
-  }
-  else if (DMAy_Channelx == DMA1_Channel7)
-  {
-    /* Reset interrupt pending bits for DMA1 Channel7 */
-    DMA1->IFCR |= DMA1_Channel7_IT_Mask;
-  }
-  else if (DMAy_Channelx == DMA2_Channel1)
-  {
-    /* Reset interrupt pending bits for DMA2 Channel1 */
-    DMA2->IFCR |= DMA2_Channel1_IT_Mask;
-  }
-  else if (DMAy_Channelx == DMA2_Channel2)
-  {
-    /* Reset interrupt pending bits for DMA2 Channel2 */
-    DMA2->IFCR |= DMA2_Channel2_IT_Mask;
-  }
-  else if (DMAy_Channelx == DMA2_Channel3)
-  {
-    /* Reset interrupt pending bits for DMA2 Channel3 */
-    DMA2->IFCR |= DMA2_Channel3_IT_Mask;
-  }
-  else if (DMAy_Channelx == DMA2_Channel4)
-  {
-    /* Reset interrupt pending bits for DMA2 Channel4 */
-    DMA2->IFCR |= DMA2_Channel4_IT_Mask;
-  }
-  else
-  { 
-    if (DMAy_Channelx == DMA2_Channel5)
-    {
-      /* Reset interrupt pending bits for DMA2 Channel5 */
-      DMA2->IFCR |= DMA2_Channel5_IT_Mask;
-    }
-  }
-}
-
-/**
-  * @brief  Initializes the DMAy Channelx according to the specified
-  *         parameters in the DMA_InitStruct.
-  * @param  DMAy_Channelx: where y can be 1 or 2 to select the DMA and 
-  *   x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
-  * @param  DMA_InitStruct: pointer to a DMA_InitTypeDef structure that
-  *         contains the configuration information for the specified DMA Channel.
-  * @retval None
-  */
-void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct)
-{
-  uint32_t tmpreg = 0;
-
-  /* Check the parameters */
-  assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
-  assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_DIR));
-  assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize));
-  assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc));
-  assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc));   
-  assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize));
-  assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize));
-  assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode));
-  assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority));
-  assert_param(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M));
-
-/*--------------------------- DMAy Channelx CCR Configuration -----------------*/
-  /* Get the DMAy_Channelx CCR value */
-  tmpreg = DMAy_Channelx->CCR;
-  /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */
-  tmpreg &= CCR_CLEAR_Mask;
-  /* Configure DMAy Channelx: data transfer, data size, priority level and mode */
-  /* Set DIR bit according to DMA_DIR value */
-  /* Set CIRC bit according to DMA_Mode value */
-  /* Set PINC bit according to DMA_PeripheralInc value */
-  /* Set MINC bit according to DMA_MemoryInc value */
-  /* Set PSIZE bits according to DMA_PeripheralDataSize value */
-  /* Set MSIZE bits according to DMA_MemoryDataSize value */
-  /* Set PL bits according to DMA_Priority value */
-  /* Set the MEM2MEM bit according to DMA_M2M value */
-  tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode |
-            DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |
-            DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |
-            DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M;
-
-  /* Write to DMAy Channelx CCR */
-  DMAy_Channelx->CCR = tmpreg;
-
-/*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/
-  /* Write to DMAy Channelx CNDTR */
-  DMAy_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize;
-
-/*--------------------------- DMAy Channelx CPAR Configuration ----------------*/
-  /* Write to DMAy Channelx CPAR */
-  DMAy_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr;
-
-/*--------------------------- DMAy Channelx CMAR Configuration ----------------*/
-  /* Write to DMAy Channelx CMAR */
-  DMAy_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr;
-}
-
-/**
-  * @brief  Fills each DMA_InitStruct member with its default value.
-  * @param  DMA_InitStruct : pointer to a DMA_InitTypeDef structure which will
-  *         be initialized.
-  * @retval None
-  */
-void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct)
-{
-/*-------------- Reset DMA init structure parameters values ------------------*/
-  /* Initialize the DMA_PeripheralBaseAddr member */
-  DMA_InitStruct->DMA_PeripheralBaseAddr = 0;
-  /* Initialize the DMA_MemoryBaseAddr member */
-  DMA_InitStruct->DMA_MemoryBaseAddr = 0;
-  /* Initialize the DMA_DIR member */
-  DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC;
-  /* Initialize the DMA_BufferSize member */
-  DMA_InitStruct->DMA_BufferSize = 0;
-  /* Initialize the DMA_PeripheralInc member */
-  DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable;
-  /* Initialize the DMA_MemoryInc member */
-  DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable;
-  /* Initialize the DMA_PeripheralDataSize member */
-  DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
-  /* Initialize the DMA_MemoryDataSize member */
-  DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
-  /* Initialize the DMA_Mode member */
-  DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;
-  /* Initialize the DMA_Priority member */
-  DMA_InitStruct->DMA_Priority = DMA_Priority_Low;
-  /* Initialize the DMA_M2M member */
-  DMA_InitStruct->DMA_M2M = DMA_M2M_Disable;
-}
-
-/**
-  * @brief  Enables or disables the specified DMAy Channelx.
-  * @param  DMAy_Channelx: where y can be 1 or 2 to select the DMA and 
-  *   x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
-  * @param  NewState: new state of the DMAy Channelx. 
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-
-  if (NewState != DISABLE)
-  {
-    /* Enable the selected DMAy Channelx */
-    DMAy_Channelx->CCR |= DMA_CCR1_EN;
-  }
-  else
-  {
-    /* Disable the selected DMAy Channelx */
-    DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN);
-  }
-}
-
-/**
-  * @brief  Enables or disables the specified DMAy Channelx interrupts.
-  * @param  DMAy_Channelx: where y can be 1 or 2 to select the DMA and 
-  *   x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
-  * @param  DMA_IT: specifies the DMA interrupts sources to be enabled
-  *   or disabled. 
-  *   This parameter can be any combination of the following values:
-  *     @arg DMA_IT_TC:  Transfer complete interrupt mask
-  *     @arg DMA_IT_HT:  Half transfer interrupt mask
-  *     @arg DMA_IT_TE:  Transfer error interrupt mask
-  * @param  NewState: new state of the specified DMA interrupts.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
-  assert_param(IS_DMA_CONFIG_IT(DMA_IT));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  if (NewState != DISABLE)
-  {
-    /* Enable the selected DMA interrupts */
-    DMAy_Channelx->CCR |= DMA_IT;
-  }
-  else
-  {
-    /* Disable the selected DMA interrupts */
-    DMAy_Channelx->CCR &= ~DMA_IT;
-  }
-}
-
-/**
-  * @brief  Sets the number of data units in the current DMAy Channelx transfer.
-  * @param  DMAy_Channelx: where y can be 1 or 2 to select the DMA and 
-  *         x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
-  * @param  DataNumber: The number of data units in the current DMAy Channelx
-  *         transfer.   
-  * @note   This function can only be used when the DMAy_Channelx is disabled.                 
-  * @retval None.
-  */
-void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber)
-{
-  /* Check the parameters */
-  assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
-  
-/*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/
-  /* Write to DMAy Channelx CNDTR */
-  DMAy_Channelx->CNDTR = DataNumber;  
-}
-
-/**
-  * @brief  Returns the number of remaining data units in the current
-  *         DMAy Channelx transfer.
-  * @param  DMAy_Channelx: where y can be 1 or 2 to select the DMA and 
-  *   x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
-  * @retval The number of remaining data units in the current DMAy Channelx
-  *         transfer.
-  */
-uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx)
-{
-  /* Check the parameters */
-  assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
-  /* Return the number of remaining data units for DMAy Channelx */
-  return ((uint16_t)(DMAy_Channelx->CNDTR));
-}
-
-/**
-  * @brief  Checks whether the specified DMAy Channelx flag is set or not.
-  * @param  DMAy_FLAG: specifies the flag to check.
-  *   This parameter can be one of the following values:
-  *     @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.
-  *     @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
-  *     @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
-  *     @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
-  *     @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.
-  *     @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
-  *     @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
-  *     @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
-  *     @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.
-  *     @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
-  *     @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
-  *     @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
-  *     @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.
-  *     @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
-  *     @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
-  *     @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
-  *     @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.
-  *     @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
-  *     @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
-  *     @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
-  *     @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.
-  *     @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
-  *     @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
-  *     @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.
-  *     @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.
-  *     @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
-  *     @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
-  *     @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.
-  *     @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag.
-  *     @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.
-  *     @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.
-  *     @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.
-  *     @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag.
-  *     @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.
-  *     @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.
-  *     @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.
-  *     @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag.
-  *     @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.
-  *     @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.
-  *     @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.
-  *     @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag.
-  *     @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.
-  *     @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.
-  *     @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.
-  *     @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag.
-  *     @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.
-  *     @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.
-  *     @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.
-  * @retval The new state of DMAy_FLAG (SET or RESET).
-  */
-FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG)
-{
-  FlagStatus bitstatus = RESET;
-  uint32_t tmpreg = 0;
-  
-  /* Check the parameters */
-  assert_param(IS_DMA_GET_FLAG(DMAy_FLAG));
-
-  /* Calculate the used DMAy */
-  if ((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET)
-  {
-    /* Get DMA2 ISR register value */
-    tmpreg = DMA2->ISR ;
-  }
-  else
-  {
-    /* Get DMA1 ISR register value */
-    tmpreg = DMA1->ISR ;
-  }
-
-  /* Check the status of the specified DMAy flag */
-  if ((tmpreg & DMAy_FLAG) != (uint32_t)RESET)
-  {
-    /* DMAy_FLAG is set */
-    bitstatus = SET;
-  }
-  else
-  {
-    /* DMAy_FLAG is reset */
-    bitstatus = RESET;
-  }
-  
-  /* Return the DMAy_FLAG status */
-  return  bitstatus;
-}
-
-/**
-  * @brief  Clears the DMAy Channelx's pending flags.
-  * @param  DMAy_FLAG: specifies the flag to clear.
-  *   This parameter can be any combination (for the same DMA) of the following values:
-  *     @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.
-  *     @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
-  *     @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
-  *     @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
-  *     @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.
-  *     @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
-  *     @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
-  *     @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
-  *     @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.
-  *     @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
-  *     @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
-  *     @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
-  *     @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.
-  *     @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
-  *     @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
-  *     @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
-  *     @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.
-  *     @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
-  *     @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
-  *     @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
-  *     @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.
-  *     @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
-  *     @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
-  *     @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.
-  *     @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.
-  *     @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
-  *     @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
-  *     @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.
-  *     @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag.
-  *     @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.
-  *     @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.
-  *     @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.
-  *     @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag.
-  *     @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.
-  *     @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.
-  *     @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.
-  *     @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag.
-  *     @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.
-  *     @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.
-  *     @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.
-  *     @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag.
-  *     @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.
-  *     @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.
-  *     @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.
-  *     @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag.
-  *     @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.
-  *     @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.
-  *     @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.
-  * @retval None
-  */
-void DMA_ClearFlag(uint32_t DMAy_FLAG)
-{
-  /* Check the parameters */
-  assert_param(IS_DMA_CLEAR_FLAG(DMAy_FLAG));
-
-  /* Calculate the used DMAy */
-  if ((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET)
-  {
-    /* Clear the selected DMAy flags */
-    DMA2->IFCR = DMAy_FLAG;
-  }
-  else
-  {
-    /* Clear the selected DMAy flags */
-    DMA1->IFCR = DMAy_FLAG;
-  }
-}
-
-/**
-  * @brief  Checks whether the specified DMAy Channelx interrupt has occurred or not.
-  * @param  DMAy_IT: specifies the DMAy interrupt source to check. 
-  *   This parameter can be one of the following values:
-  *     @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.
-  *     @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
-  *     @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
-  *     @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
-  *     @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.
-  *     @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
-  *     @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
-  *     @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
-  *     @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.
-  *     @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
-  *     @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
-  *     @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
-  *     @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.
-  *     @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
-  *     @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
-  *     @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
-  *     @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.
-  *     @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
-  *     @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
-  *     @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
-  *     @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt.
-  *     @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.
-  *     @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.
-  *     @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.
-  *     @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt.
-  *     @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.
-  *     @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.
-  *     @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.
-  *     @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt.
-  *     @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt.
-  *     @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt.
-  *     @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt.
-  *     @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt.
-  *     @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt.
-  *     @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt.
-  *     @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt.
-  *     @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt.
-  *     @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt.
-  *     @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt.
-  *     @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt.
-  *     @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt.
-  *     @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt.
-  *     @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt.
-  *     @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt.
-  *     @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt.
-  *     @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt.
-  *     @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt.
-  *     @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt.
-  * @retval The new state of DMAy_IT (SET or RESET).
-  */
-ITStatus DMA_GetITStatus(uint32_t DMAy_IT)
-{
-  ITStatus bitstatus = RESET;
-  uint32_t tmpreg = 0;
-
-  /* Check the parameters */
-  assert_param(IS_DMA_GET_IT(DMAy_IT));
-
-  /* Calculate the used DMA */
-  if ((DMAy_IT & FLAG_Mask) != (uint32_t)RESET)
-  {
-    /* Get DMA2 ISR register value */
-    tmpreg = DMA2->ISR;
-  }
-  else
-  {
-    /* Get DMA1 ISR register value */
-    tmpreg = DMA1->ISR;
-  }
-
-  /* Check the status of the specified DMAy interrupt */
-  if ((tmpreg & DMAy_IT) != (uint32_t)RESET)
-  {
-    /* DMAy_IT is set */
-    bitstatus = SET;
-  }
-  else
-  {
-    /* DMAy_IT is reset */
-    bitstatus = RESET;
-  }
-  /* Return the DMA_IT status */
-  return  bitstatus;
-}
-
-/**
-  * @brief  Clears the DMAy Channelx's interrupt pending bits.
-  * @param  DMAy_IT: specifies the DMAy interrupt pending bit to clear.
-  *   This parameter can be any combination (for the same DMA) of the following values:
-  *     @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.
-  *     @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
-  *     @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
-  *     @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
-  *     @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.
-  *     @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
-  *     @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
-  *     @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
-  *     @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.
-  *     @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
-  *     @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
-  *     @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
-  *     @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.
-  *     @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
-  *     @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
-  *     @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
-  *     @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.
-  *     @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
-  *     @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
-  *     @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
-  *     @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt.
-  *     @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.
-  *     @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.
-  *     @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.
-  *     @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt.
-  *     @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.
-  *     @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.
-  *     @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.
-  *     @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt.
-  *     @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt.
-  *     @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt.
-  *     @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt.
-  *     @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt.
-  *     @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt.
-  *     @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt.
-  *     @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt.
-  *     @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt.
-  *     @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt.
-  *     @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt.
-  *     @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt.
-  *     @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt.
-  *     @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt.
-  *     @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt.
-  *     @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt.
-  *     @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt.
-  *     @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt.
-  *     @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt.
-  *     @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt.
-  * @retval None
-  */
-void DMA_ClearITPendingBit(uint32_t DMAy_IT)
-{
-  /* Check the parameters */
-  assert_param(IS_DMA_CLEAR_IT(DMAy_IT));
-
-  /* Calculate the used DMAy */
-  if ((DMAy_IT & FLAG_Mask) != (uint32_t)RESET)
-  {
-    /* Clear the selected DMAy interrupt pending bits */
-    DMA2->IFCR = DMAy_IT;
-  }
-  else
-  {
-    /* Clear the selected DMAy interrupt pending bits */
-    DMA1->IFCR = DMAy_IT;
-  }
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_exti.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_exti.c
deleted file mode 100644
index b6290d5..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_exti.c
+++ /dev/null
@@ -1,269 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f10x_exti.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    11-March-2011
-  * @brief   This file provides all the EXTI firmware functions.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_exti.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Driver
-  * @{
-  */
-
-/** @defgroup EXTI 
-  * @brief EXTI driver modules
-  * @{
-  */
-
-/** @defgroup EXTI_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup EXTI_Private_Defines
-  * @{
-  */
-
-#define EXTI_LINENONE    ((uint32_t)0x00000)  /* No interrupt selected */
-
-/**
-  * @}
-  */
-
-/** @defgroup EXTI_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup EXTI_Private_Variables
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup EXTI_Private_FunctionPrototypes
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup EXTI_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Deinitializes the EXTI peripheral registers to their default reset values.
-  * @param  None
-  * @retval None
-  */
-void EXTI_DeInit(void)
-{
-  EXTI->IMR = 0x00000000;
-  EXTI->EMR = 0x00000000;
-  EXTI->RTSR = 0x00000000; 
-  EXTI->FTSR = 0x00000000; 
-  EXTI->PR = 0x000FFFFF;
-}
-
-/**
-  * @brief  Initializes the EXTI peripheral according to the specified
-  *         parameters in the EXTI_InitStruct.
-  * @param  EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure
-  *         that contains the configuration information for the EXTI peripheral.
-  * @retval None
-  */
-void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct)
-{
-  uint32_t tmp = 0;
-
-  /* Check the parameters */
-  assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode));
-  assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger));
-  assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line));  
-  assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd));
-
-  tmp = (uint32_t)EXTI_BASE;
-     
-  if (EXTI_InitStruct->EXTI_LineCmd != DISABLE)
-  {
-    /* Clear EXTI line configuration */
-    EXTI->IMR &= ~EXTI_InitStruct->EXTI_Line;
-    EXTI->EMR &= ~EXTI_InitStruct->EXTI_Line;
-    
-    tmp += EXTI_InitStruct->EXTI_Mode;
-
-    *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;
-
-    /* Clear Rising Falling edge configuration */
-    EXTI->RTSR &= ~EXTI_InitStruct->EXTI_Line;
-    EXTI->FTSR &= ~EXTI_InitStruct->EXTI_Line;
-    
-    /* Select the trigger for the selected external interrupts */
-    if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling)
-    {
-      /* Rising Falling edge */
-      EXTI->RTSR |= EXTI_InitStruct->EXTI_Line;
-      EXTI->FTSR |= EXTI_InitStruct->EXTI_Line;
-    }
-    else
-    {
-      tmp = (uint32_t)EXTI_BASE;
-      tmp += EXTI_InitStruct->EXTI_Trigger;
-
-      *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;
-    }
-  }
-  else
-  {
-    tmp += EXTI_InitStruct->EXTI_Mode;
-
-    /* Disable the selected external lines */
-    *(__IO uint32_t *) tmp &= ~EXTI_InitStruct->EXTI_Line;
-  }
-}
-
-/**
-  * @brief  Fills each EXTI_InitStruct member with its reset value.
-  * @param  EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will
-  *         be initialized.
-  * @retval None
-  */
-void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct)
-{
-  EXTI_InitStruct->EXTI_Line = EXTI_LINENONE;
-  EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt;
-  EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling;
-  EXTI_InitStruct->EXTI_LineCmd = DISABLE;
-}
-
-/**
-  * @brief  Generates a Software interrupt.
-  * @param  EXTI_Line: specifies the EXTI lines to be enabled or disabled.
-  *   This parameter can be any combination of EXTI_Linex where x can be (0..19).
-  * @retval None
-  */
-void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line)
-{
-  /* Check the parameters */
-  assert_param(IS_EXTI_LINE(EXTI_Line));
-  
-  EXTI->SWIER |= EXTI_Line;
-}
-
-/**
-  * @brief  Checks whether the specified EXTI line flag is set or not.
-  * @param  EXTI_Line: specifies the EXTI line flag to check.
-  *   This parameter can be:
-  *     @arg EXTI_Linex: External interrupt line x where x(0..19)
-  * @retval The new state of EXTI_Line (SET or RESET).
-  */
-FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line)
-{
-  FlagStatus bitstatus = RESET;
-  /* Check the parameters */
-  assert_param(IS_GET_EXTI_LINE(EXTI_Line));
-  
-  if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET)
-  {
-    bitstatus = SET;
-  }
-  else
-  {
-    bitstatus = RESET;
-  }
-  return bitstatus;
-}
-
-/**
-  * @brief  Clears the EXTI's line pending flags.
-  * @param  EXTI_Line: specifies the EXTI lines flags to clear.
-  *   This parameter can be any combination of EXTI_Linex where x can be (0..19).
-  * @retval None
-  */
-void EXTI_ClearFlag(uint32_t EXTI_Line)
-{
-  /* Check the parameters */
-  assert_param(IS_EXTI_LINE(EXTI_Line));
-  
-  EXTI->PR = EXTI_Line;
-}
-
-/**
-  * @brief  Checks whether the specified EXTI line is asserted or not.
-  * @param  EXTI_Line: specifies the EXTI line to check.
-  *   This parameter can be:
-  *     @arg EXTI_Linex: External interrupt line x where x(0..19)
-  * @retval The new state of EXTI_Line (SET or RESET).
-  */
-ITStatus EXTI_GetITStatus(uint32_t EXTI_Line)
-{
-  ITStatus bitstatus = RESET;
-  uint32_t enablestatus = 0;
-  /* Check the parameters */
-  assert_param(IS_GET_EXTI_LINE(EXTI_Line));
-  
-  enablestatus =  EXTI->IMR & EXTI_Line;
-  if (((EXTI->PR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))
-  {
-    bitstatus = SET;
-  }
-  else
-  {
-    bitstatus = RESET;
-  }
-  return bitstatus;
-}
-
-/**
-  * @brief  Clears the EXTI's line pending bits.
-  * @param  EXTI_Line: specifies the EXTI lines to clear.
-  *   This parameter can be any combination of EXTI_Linex where x can be (0..19).
-  * @retval None
-  */
-void EXTI_ClearITPendingBit(uint32_t EXTI_Line)
-{
-  /* Check the parameters */
-  assert_param(IS_EXTI_LINE(EXTI_Line));
-  
-  EXTI->PR = EXTI_Line;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.c
deleted file mode 100644
index cdff9e9..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.c
+++ /dev/null
@@ -1,1684 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f10x_flash.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    11-March-2011
-  * @brief   This file provides all the FLASH firmware functions.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_flash.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Driver
-  * @{
-  */
-
-/** @defgroup FLASH 
-  * @brief FLASH driver modules
-  * @{
-  */ 
-
-/** @defgroup FLASH_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */ 
-
-/** @defgroup FLASH_Private_Defines
-  * @{
-  */ 
-
-/* Flash Access Control Register bits */
-#define ACR_LATENCY_Mask         ((uint32_t)0x00000038)
-#define ACR_HLFCYA_Mask          ((uint32_t)0xFFFFFFF7)
-#define ACR_PRFTBE_Mask          ((uint32_t)0xFFFFFFEF)
-
-/* Flash Access Control Register bits */
-#define ACR_PRFTBS_Mask          ((uint32_t)0x00000020) 
-
-/* Flash Control Register bits */
-#define CR_PG_Set                ((uint32_t)0x00000001)
-#define CR_PG_Reset              ((uint32_t)0x00001FFE) 
-#define CR_PER_Set               ((uint32_t)0x00000002)
-#define CR_PER_Reset             ((uint32_t)0x00001FFD)
-#define CR_MER_Set               ((uint32_t)0x00000004)
-#define CR_MER_Reset             ((uint32_t)0x00001FFB)
-#define CR_OPTPG_Set             ((uint32_t)0x00000010)
-#define CR_OPTPG_Reset           ((uint32_t)0x00001FEF)
-#define CR_OPTER_Set             ((uint32_t)0x00000020)
-#define CR_OPTER_Reset           ((uint32_t)0x00001FDF)
-#define CR_STRT_Set              ((uint32_t)0x00000040)
-#define CR_LOCK_Set              ((uint32_t)0x00000080)
-
-/* FLASH Mask */
-#define RDPRT_Mask               ((uint32_t)0x00000002)
-#define WRP0_Mask                ((uint32_t)0x000000FF)
-#define WRP1_Mask                ((uint32_t)0x0000FF00)
-#define WRP2_Mask                ((uint32_t)0x00FF0000)
-#define WRP3_Mask                ((uint32_t)0xFF000000)
-#define OB_USER_BFB2             ((uint16_t)0x0008)
-
-/* FLASH Keys */
-#define RDP_Key                  ((uint16_t)0x00A5)
-#define FLASH_KEY1               ((uint32_t)0x45670123)
-#define FLASH_KEY2               ((uint32_t)0xCDEF89AB)
-
-/* FLASH BANK address */
-#define FLASH_BANK1_END_ADDRESS   ((uint32_t)0x807FFFF)
-
-/* Delay definition */   
-#define EraseTimeout          ((uint32_t)0x000B0000)
-#define ProgramTimeout        ((uint32_t)0x00002000)
-/**
-  * @}
-  */ 
-
-/** @defgroup FLASH_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */ 
-
-/** @defgroup FLASH_Private_Variables
-  * @{
-  */
-
-/**
-  * @}
-  */ 
-
-/** @defgroup FLASH_Private_FunctionPrototypes
-  * @{
-  */
-  
-/**
-  * @}
-  */
-
-/** @defgroup FLASH_Private_Functions
-  * @{
-  */
-
-/**
-@code  
- 
- This driver provides functions to configure and program the Flash memory of all STM32F10x devices,
- including the latest STM32F10x_XL density devices. 
-
- STM32F10x_XL devices feature up to 1 Mbyte with dual bank architecture for read-while-write (RWW) capability:
-    - bank1: fixed size of 512 Kbytes (256 pages of 2Kbytes each)
-    - bank2: up to 512 Kbytes (up to 256 pages of 2Kbytes each)
- While other STM32F10x devices features only one bank with memory up to 512 Kbytes.
-
- In version V3.3.0, some functions were updated and new ones were added to support
- STM32F10x_XL devices. Thus some functions manages all devices, while other are 
- dedicated for XL devices only.
- 
- The table below presents the list of available functions depending on the used STM32F10x devices.  
-      
-   ***************************************************
-   * Legacy functions used for all STM32F10x devices *
-   ***************************************************
-   +----------------------------------------------------------------------------------------------------------------------------------+
-   |       Functions prototypes         |STM32F10x_XL|Other STM32F10x|    Comments                                                    |
-   |                                    |   devices  |  devices      |                                                                |
-   |----------------------------------------------------------------------------------------------------------------------------------|
-   |FLASH_SetLatency                    |    Yes     |      Yes      | No change                                                      |
-   |----------------------------------------------------------------------------------------------------------------------------------|
-   |FLASH_HalfCycleAccessCmd            |    Yes     |      Yes      | No change                                                      |
-   |----------------------------------------------------------------------------------------------------------------------------------|
-   |FLASH_PrefetchBufferCmd             |    Yes     |      Yes      | No change                                                      |
-   |----------------------------------------------------------------------------------------------------------------------------------|
-   |FLASH_Unlock                        |    Yes     |      Yes      | - For STM32F10X_XL devices: unlock Bank1 and Bank2.            |
-   |                                    |            |               | - For other devices: unlock Bank1 and it is equivalent         |
-   |                                    |            |               |   to FLASH_UnlockBank1 function.                               |
-   |----------------------------------------------------------------------------------------------------------------------------------|
-   |FLASH_Lock                          |    Yes     |      Yes      | - For STM32F10X_XL devices: lock Bank1 and Bank2.              |
-   |                                    |            |               | - For other devices: lock Bank1 and it is equivalent           |
-   |                                    |            |               |   to FLASH_LockBank1 function.                                 |
-   |----------------------------------------------------------------------------------------------------------------------------------|
-   |FLASH_ErasePage                     |    Yes     |      Yes      | - For STM32F10x_XL devices: erase a page in Bank1 and Bank2    |
-   |                                    |            |               | - For other devices: erase a page in Bank1                     |
-   |----------------------------------------------------------------------------------------------------------------------------------|
-   |FLASH_EraseAllPages                 |    Yes     |      Yes      | - For STM32F10x_XL devices: erase all pages in Bank1 and Bank2 |
-   |                                    |            |               | - For other devices: erase all pages in Bank1                  |
-   |----------------------------------------------------------------------------------------------------------------------------------|
-   |FLASH_EraseOptionBytes              |    Yes     |      Yes      | No change                                                      |
-   |----------------------------------------------------------------------------------------------------------------------------------|
-   |FLASH_ProgramWord                   |    Yes     |      Yes      | Updated to program up to 1MByte (depending on the used device) |
-   |----------------------------------------------------------------------------------------------------------------------------------|
-   |FLASH_ProgramHalfWord               |    Yes     |      Yes      | Updated to program up to 1MByte (depending on the used device) |
-   |----------------------------------------------------------------------------------------------------------------------------------|
-   |FLASH_ProgramOptionByteData         |    Yes     |      Yes      | No change                                                      |
-   |----------------------------------------------------------------------------------------------------------------------------------|
-   |FLASH_EnableWriteProtection         |    Yes     |      Yes      | No change                                                      |
-   |----------------------------------------------------------------------------------------------------------------------------------|
-   |FLASH_ReadOutProtection             |    Yes     |      Yes      | No change                                                      |
-   |----------------------------------------------------------------------------------------------------------------------------------|
-   |FLASH_UserOptionByteConfig          |    Yes     |      Yes      | No change                                                      |
-   |----------------------------------------------------------------------------------------------------------------------------------|
-   |FLASH_GetUserOptionByte             |    Yes     |      Yes      | No change                                                      |
-   |----------------------------------------------------------------------------------------------------------------------------------|
-   |FLASH_GetWriteProtectionOptionByte  |    Yes     |      Yes      | No change                                                      |
-   |----------------------------------------------------------------------------------------------------------------------------------|
-   |FLASH_GetReadOutProtectionStatus    |    Yes     |      Yes      | No change                                                      |
-   |----------------------------------------------------------------------------------------------------------------------------------|
-   |FLASH_GetPrefetchBufferStatus       |    Yes     |      Yes      | No change                                                      |
-   |----------------------------------------------------------------------------------------------------------------------------------|
-   |FLASH_ITConfig                      |    Yes     |      Yes      | - For STM32F10x_XL devices: enable Bank1 and Bank2's interrupts|
-   |                                    |            |               | - For other devices: enable Bank1's interrupts                 |
-   |----------------------------------------------------------------------------------------------------------------------------------|
-   |FLASH_GetFlagStatus                 |    Yes     |      Yes      | - For STM32F10x_XL devices: return Bank1 and Bank2's flag status|
-   |                                    |            |               | - For other devices: return Bank1's flag status                |
-   |----------------------------------------------------------------------------------------------------------------------------------|
-   |FLASH_ClearFlag                     |    Yes     |      Yes      | - For STM32F10x_XL devices: clear Bank1 and Bank2's flag       |
-   |                                    |            |               | - For other devices: clear Bank1's flag                        |
-   |----------------------------------------------------------------------------------------------------------------------------------|
-   |FLASH_GetStatus                     |    Yes     |      Yes      | - Return the status of Bank1 (for all devices)                 |
-   |                                    |            |               |   equivalent to FLASH_GetBank1Status function                  |
-   |----------------------------------------------------------------------------------------------------------------------------------|
-   |FLASH_WaitForLastOperation          |    Yes     |      Yes      | - Wait for Bank1 last operation (for all devices)              |
-   |                                    |            |               |   equivalent to: FLASH_WaitForLastBank1Operation function      |
-   +----------------------------------------------------------------------------------------------------------------------------------+
-
-   ************************************************************************************************************************
-   * New functions used for all STM32F10x devices to manage Bank1:                                                        *
-   *   - These functions are mainly useful for STM32F10x_XL density devices, to have separate control for Bank1 and bank2 *
-   *   - For other devices, these functions are optional (covered by functions listed above)                              *
-   ************************************************************************************************************************
-   +----------------------------------------------------------------------------------------------------------------------------------+
-   |       Functions prototypes         |STM32F10x_XL|Other STM32F10x|    Comments                                                    |
-   |                                    |   devices  |  devices      |                                                                |
-   |----------------------------------------------------------------------------------------------------------------------------------|
-   | FLASH_UnlockBank1                  |    Yes     |      Yes      | - Unlock Bank1                                                 |
-   |----------------------------------------------------------------------------------------------------------------------------------|
-   |FLASH_LockBank1                     |    Yes     |      Yes      | - Lock Bank1                                                   |
-   |----------------------------------------------------------------------------------------------------------------------------------|
-   | FLASH_EraseAllBank1Pages           |    Yes     |      Yes      | - Erase all pages in Bank1                                     |
-   |----------------------------------------------------------------------------------------------------------------------------------|
-   | FLASH_GetBank1Status               |    Yes     |      Yes      | - Return the status of Bank1                                   |
-   |----------------------------------------------------------------------------------------------------------------------------------|
-   | FLASH_WaitForLastBank1Operation    |    Yes     |      Yes      | - Wait for Bank1 last operation                                |
-   +----------------------------------------------------------------------------------------------------------------------------------+
-
-   *****************************************************************************
-   * New Functions used only with STM32F10x_XL density devices to manage Bank2 *
-   *****************************************************************************
-   +----------------------------------------------------------------------------------------------------------------------------------+
-   |       Functions prototypes         |STM32F10x_XL|Other STM32F10x|    Comments                                                    |
-   |                                    |   devices  |  devices      |                                                                |
-   |----------------------------------------------------------------------------------------------------------------------------------|
-   | FLASH_UnlockBank2                  |    Yes     |      No       | - Unlock Bank2                                                 |
-   |----------------------------------------------------------------------------------------------------------------------------------|
-   |FLASH_LockBank2                     |    Yes     |      No       | - Lock Bank2                                                   |
-   |----------------------------------------------------------------------------------------------------------------------------------|
-   | FLASH_EraseAllBank2Pages           |    Yes     |      No       | - Erase all pages in Bank2                                     |
-   |----------------------------------------------------------------------------------------------------------------------------------|
-   | FLASH_GetBank2Status               |    Yes     |      No       | - Return the status of Bank2                                   |
-   |----------------------------------------------------------------------------------------------------------------------------------|
-   | FLASH_WaitForLastBank2Operation    |    Yes     |      No       | - Wait for Bank2 last operation                                |
-   |----------------------------------------------------------------------------------------------------------------------------------|
-   | FLASH_BootConfig                   |    Yes     |      No       | - Configure to boot from Bank1 or Bank2                        |
-   +----------------------------------------------------------------------------------------------------------------------------------+
-@endcode
-*/
-
-
-/**
-  * @brief  Sets the code latency value.
-  * @note   This function can be used for all STM32F10x devices.
-  * @param  FLASH_Latency: specifies the FLASH Latency value.
-  *   This parameter can be one of the following values:
-  *     @arg FLASH_Latency_0: FLASH Zero Latency cycle
-  *     @arg FLASH_Latency_1: FLASH One Latency cycle
-  *     @arg FLASH_Latency_2: FLASH Two Latency cycles
-  * @retval None
-  */
-void FLASH_SetLatency(uint32_t FLASH_Latency)
-{
-  uint32_t tmpreg = 0;
-  
-  /* Check the parameters */
-  assert_param(IS_FLASH_LATENCY(FLASH_Latency));
-  
-  /* Read the ACR register */
-  tmpreg = FLASH->ACR;  
-  
-  /* Sets the Latency value */
-  tmpreg &= ACR_LATENCY_Mask;
-  tmpreg |= FLASH_Latency;
-  
-  /* Write the ACR register */
-  FLASH->ACR = tmpreg;
-}
-
-/**
-  * @brief  Enables or disables the Half cycle flash access.
-  * @note   This function can be used for all STM32F10x devices.
-  * @param  FLASH_HalfCycleAccess: specifies the FLASH Half cycle Access mode.
-  *   This parameter can be one of the following values:
-  *     @arg FLASH_HalfCycleAccess_Enable: FLASH Half Cycle Enable
-  *     @arg FLASH_HalfCycleAccess_Disable: FLASH Half Cycle Disable
-  * @retval None
-  */
-void FLASH_HalfCycleAccessCmd(uint32_t FLASH_HalfCycleAccess)
-{
-  /* Check the parameters */
-  assert_param(IS_FLASH_HALFCYCLEACCESS_STATE(FLASH_HalfCycleAccess));
-  
-  /* Enable or disable the Half cycle access */
-  FLASH->ACR &= ACR_HLFCYA_Mask;
-  FLASH->ACR |= FLASH_HalfCycleAccess;
-}
-
-/**
-  * @brief  Enables or disables the Prefetch Buffer.
-  * @note   This function can be used for all STM32F10x devices.
-  * @param  FLASH_PrefetchBuffer: specifies the Prefetch buffer status.
-  *   This parameter can be one of the following values:
-  *     @arg FLASH_PrefetchBuffer_Enable: FLASH Prefetch Buffer Enable
-  *     @arg FLASH_PrefetchBuffer_Disable: FLASH Prefetch Buffer Disable
-  * @retval None
-  */
-void FLASH_PrefetchBufferCmd(uint32_t FLASH_PrefetchBuffer)
-{
-  /* Check the parameters */
-  assert_param(IS_FLASH_PREFETCHBUFFER_STATE(FLASH_PrefetchBuffer));
-  
-  /* Enable or disable the Prefetch Buffer */
-  FLASH->ACR &= ACR_PRFTBE_Mask;
-  FLASH->ACR |= FLASH_PrefetchBuffer;
-}
-
-/**
-  * @brief  Unlocks the FLASH Program Erase Controller.
-  * @note   This function can be used for all STM32F10x devices.
-  *         - For STM32F10X_XL devices this function unlocks Bank1 and Bank2.
-  *         - For all other devices it unlocks Bank1 and it is equivalent 
-  *           to FLASH_UnlockBank1 function.. 
-  * @param  None
-  * @retval None
-  */
-void FLASH_Unlock(void)
-{
-  /* Authorize the FPEC of Bank1 Access */
-  FLASH->KEYR = FLASH_KEY1;
-  FLASH->KEYR = FLASH_KEY2;
-
-#ifdef STM32F10X_XL
-  /* Authorize the FPEC of Bank2 Access */
-  FLASH->KEYR2 = FLASH_KEY1;
-  FLASH->KEYR2 = FLASH_KEY2;
-#endif /* STM32F10X_XL */
-}
-/**
-  * @brief  Unlocks the FLASH Bank1 Program Erase Controller.
-  * @note   This function can be used for all STM32F10x devices.
-  *         - For STM32F10X_XL devices this function unlocks Bank1.
-  *         - For all other devices it unlocks Bank1 and it is 
-  *           equivalent to FLASH_Unlock function.
-  * @param  None
-  * @retval None
-  */
-void FLASH_UnlockBank1(void)
-{
-  /* Authorize the FPEC of Bank1 Access */
-  FLASH->KEYR = FLASH_KEY1;
-  FLASH->KEYR = FLASH_KEY2;
-}
-
-#ifdef STM32F10X_XL
-/**
-  * @brief  Unlocks the FLASH Bank2 Program Erase Controller.
-  * @note   This function can be used only for STM32F10X_XL density devices.
-  * @param  None
-  * @retval None
-  */
-void FLASH_UnlockBank2(void)
-{
-  /* Authorize the FPEC of Bank2 Access */
-  FLASH->KEYR2 = FLASH_KEY1;
-  FLASH->KEYR2 = FLASH_KEY2;
-
-}
-#endif /* STM32F10X_XL */
-
-/**
-  * @brief  Locks the FLASH Program Erase Controller.
-  * @note   This function can be used for all STM32F10x devices.
-  *         - For STM32F10X_XL devices this function Locks Bank1 and Bank2.
-  *         - For all other devices it Locks Bank1 and it is equivalent 
-  *           to FLASH_LockBank1 function.
-  * @param  None
-  * @retval None
-  */
-void FLASH_Lock(void)
-{
-  /* Set the Lock Bit to lock the FPEC and the CR of  Bank1 */
-  FLASH->CR |= CR_LOCK_Set;
-
-#ifdef STM32F10X_XL
-  /* Set the Lock Bit to lock the FPEC and the CR of  Bank2 */
-  FLASH->CR2 |= CR_LOCK_Set;
-#endif /* STM32F10X_XL */
-}
-
-/**
-  * @brief  Locks the FLASH Bank1 Program Erase Controller.
-  * @note   this function can be used for all STM32F10x devices.
-  *         - For STM32F10X_XL devices this function Locks Bank1.
-  *         - For all other devices it Locks Bank1 and it is equivalent 
-  *           to FLASH_Lock function.
-  * @param  None
-  * @retval None
-  */
-void FLASH_LockBank1(void)
-{
-  /* Set the Lock Bit to lock the FPEC and the CR of  Bank1 */
-  FLASH->CR |= CR_LOCK_Set;
-}
-
-#ifdef STM32F10X_XL
-/**
-  * @brief  Locks the FLASH Bank2 Program Erase Controller.
-  * @note   This function can be used only for STM32F10X_XL density devices.
-  * @param  None
-  * @retval None
-  */
-void FLASH_LockBank2(void)
-{
-  /* Set the Lock Bit to lock the FPEC and the CR of  Bank2 */
-  FLASH->CR2 |= CR_LOCK_Set;
-}
-#endif /* STM32F10X_XL */
-
-/**
-  * @brief  Erases a specified FLASH page.
-  * @note   This function can be used for all STM32F10x devices.
-  * @param  Page_Address: The page address to be erased.
-  * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
-  *         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
-  */
-FLASH_Status FLASH_ErasePage(uint32_t Page_Address)
-{
-  FLASH_Status status = FLASH_COMPLETE;
-  /* Check the parameters */
-  assert_param(IS_FLASH_ADDRESS(Page_Address));
-
-#ifdef STM32F10X_XL
-  if(Page_Address < FLASH_BANK1_END_ADDRESS)  
-  {
-    /* Wait for last operation to be completed */
-    status = FLASH_WaitForLastBank1Operation(EraseTimeout);
-    if(status == FLASH_COMPLETE)
-    { 
-      /* if the previous operation is completed, proceed to erase the page */
-      FLASH->CR|= CR_PER_Set;
-      FLASH->AR = Page_Address; 
-      FLASH->CR|= CR_STRT_Set;
-    
-      /* Wait for last operation to be completed */
-      status = FLASH_WaitForLastBank1Operation(EraseTimeout);
-
-      /* Disable the PER Bit */
-      FLASH->CR &= CR_PER_Reset;
-    }
-  }
-  else
-  {
-    /* Wait for last operation to be completed */
-    status = FLASH_WaitForLastBank2Operation(EraseTimeout);
-    if(status == FLASH_COMPLETE)
-    { 
-      /* if the previous operation is completed, proceed to erase the page */
-      FLASH->CR2|= CR_PER_Set;
-      FLASH->AR2 = Page_Address; 
-      FLASH->CR2|= CR_STRT_Set;
-    
-      /* Wait for last operation to be completed */
-      status = FLASH_WaitForLastBank2Operation(EraseTimeout);
-      
-      /* Disable the PER Bit */
-      FLASH->CR2 &= CR_PER_Reset;
-    }
-  }
-#else
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation(EraseTimeout);
-  
-  if(status == FLASH_COMPLETE)
-  { 
-    /* if the previous operation is completed, proceed to erase the page */
-    FLASH->CR|= CR_PER_Set;
-    FLASH->AR = Page_Address; 
-    FLASH->CR|= CR_STRT_Set;
-    
-    /* Wait for last operation to be completed */
-    status = FLASH_WaitForLastOperation(EraseTimeout);
-    
-    /* Disable the PER Bit */
-    FLASH->CR &= CR_PER_Reset;
-  }
-#endif /* STM32F10X_XL */
-
-  /* Return the Erase Status */
-  return status;
-}
-
-/**
-  * @brief  Erases all FLASH pages.
-  * @note   This function can be used for all STM32F10x devices.
-  * @param  None
-  * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
-  *         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
-  */
-FLASH_Status FLASH_EraseAllPages(void)
-{
-  FLASH_Status status = FLASH_COMPLETE;
-
-#ifdef STM32F10X_XL
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastBank1Operation(EraseTimeout);
-  
-  if(status == FLASH_COMPLETE)
-  {
-    /* if the previous operation is completed, proceed to erase all pages */
-     FLASH->CR |= CR_MER_Set;
-     FLASH->CR |= CR_STRT_Set;
-    
-    /* Wait for last operation to be completed */
-    status = FLASH_WaitForLastBank1Operation(EraseTimeout);
-    
-    /* Disable the MER Bit */
-    FLASH->CR &= CR_MER_Reset;
-  }    
-  if(status == FLASH_COMPLETE)
-  {
-    /* if the previous operation is completed, proceed to erase all pages */
-     FLASH->CR2 |= CR_MER_Set;
-     FLASH->CR2 |= CR_STRT_Set;
-    
-    /* Wait for last operation to be completed */
-    status = FLASH_WaitForLastBank2Operation(EraseTimeout);
-    
-    /* Disable the MER Bit */
-    FLASH->CR2 &= CR_MER_Reset;
-  }
-#else
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation(EraseTimeout);
-  if(status == FLASH_COMPLETE)
-  {
-    /* if the previous operation is completed, proceed to erase all pages */
-     FLASH->CR |= CR_MER_Set;
-     FLASH->CR |= CR_STRT_Set;
-    
-    /* Wait for last operation to be completed */
-    status = FLASH_WaitForLastOperation(EraseTimeout);
-
-    /* Disable the MER Bit */
-    FLASH->CR &= CR_MER_Reset;
-  }
-#endif /* STM32F10X_XL */
-
-  /* Return the Erase Status */
-  return status;
-}
-
-/**
-  * @brief  Erases all Bank1 FLASH pages.
-  * @note   This function can be used for all STM32F10x devices.
-  *         - For STM32F10X_XL devices this function erases all Bank1 pages.
-  *         - For all other devices it erases all Bank1 pages and it is equivalent 
-  *           to FLASH_EraseAllPages function.
-  * @param  None
-  * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
-  *         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
-  */
-FLASH_Status FLASH_EraseAllBank1Pages(void)
-{
-  FLASH_Status status = FLASH_COMPLETE;
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastBank1Operation(EraseTimeout);
-  
-  if(status == FLASH_COMPLETE)
-  {
-    /* if the previous operation is completed, proceed to erase all pages */
-     FLASH->CR |= CR_MER_Set;
-     FLASH->CR |= CR_STRT_Set;
-    
-    /* Wait for last operation to be completed */
-    status = FLASH_WaitForLastBank1Operation(EraseTimeout);
-    
-    /* Disable the MER Bit */
-    FLASH->CR &= CR_MER_Reset;
-  }    
-  /* Return the Erase Status */
-  return status;
-}
-
-#ifdef STM32F10X_XL
-/**
-  * @brief  Erases all Bank2 FLASH pages.
-  * @note   This function can be used only for STM32F10x_XL density devices.
-  * @param  None
-  * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
-  *         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
-  */
-FLASH_Status FLASH_EraseAllBank2Pages(void)
-{
-  FLASH_Status status = FLASH_COMPLETE;
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastBank2Operation(EraseTimeout);
-  
-  if(status == FLASH_COMPLETE)
-  {
-    /* if the previous operation is completed, proceed to erase all pages */
-     FLASH->CR2 |= CR_MER_Set;
-     FLASH->CR2 |= CR_STRT_Set;
-    
-    /* Wait for last operation to be completed */
-    status = FLASH_WaitForLastBank2Operation(EraseTimeout);
-
-    /* Disable the MER Bit */
-    FLASH->CR2 &= CR_MER_Reset;
-  }    
-  /* Return the Erase Status */
-  return status;
-}
-#endif /* STM32F10X_XL */
-
-/**
-  * @brief  Erases the FLASH option bytes.
-  * @note   This functions erases all option bytes except the Read protection (RDP). 
-  * @note   This function can be used for all STM32F10x devices.
-  * @param  None
-  * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
-  *         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
-  */
-FLASH_Status FLASH_EraseOptionBytes(void)
-{
-  uint16_t rdptmp = RDP_Key;
-
-  FLASH_Status status = FLASH_COMPLETE;
-
-  /* Get the actual read protection Option Byte value */ 
-  if(FLASH_GetReadOutProtectionStatus() != RESET)
-  {
-    rdptmp = 0x00;  
-  }
-
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation(EraseTimeout);
-  if(status == FLASH_COMPLETE)
-  {
-    /* Authorize the small information block programming */
-    FLASH->OPTKEYR = FLASH_KEY1;
-    FLASH->OPTKEYR = FLASH_KEY2;
-    
-    /* if the previous operation is completed, proceed to erase the option bytes */
-    FLASH->CR |= CR_OPTER_Set;
-    FLASH->CR |= CR_STRT_Set;
-    /* Wait for last operation to be completed */
-    status = FLASH_WaitForLastOperation(EraseTimeout);
-    
-    if(status == FLASH_COMPLETE)
-    {
-      /* if the erase operation is completed, disable the OPTER Bit */
-      FLASH->CR &= CR_OPTER_Reset;
-       
-      /* Enable the Option Bytes Programming operation */
-      FLASH->CR |= CR_OPTPG_Set;
-      /* Restore the last read protection Option Byte value */
-      OB->RDP = (uint16_t)rdptmp; 
-      /* Wait for last operation to be completed */
-      status = FLASH_WaitForLastOperation(ProgramTimeout);
- 
-      if(status != FLASH_TIMEOUT)
-      {
-        /* if the program operation is completed, disable the OPTPG Bit */
-        FLASH->CR &= CR_OPTPG_Reset;
-      }
-    }
-    else
-    {
-      if (status != FLASH_TIMEOUT)
-      {
-        /* Disable the OPTPG Bit */
-        FLASH->CR &= CR_OPTPG_Reset;
-      }
-    }  
-  }
-  /* Return the erase status */
-  return status;
-}
-
-/**
-  * @brief  Programs a word at a specified address.
-  * @note   This function can be used for all STM32F10x devices.
-  * @param  Address: specifies the address to be programmed.
-  * @param  Data: specifies the data to be programmed.
-  * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
-  *         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. 
-  */
-FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data)
-{
-  FLASH_Status status = FLASH_COMPLETE;
-  __IO uint32_t tmp = 0;
-
-  /* Check the parameters */
-  assert_param(IS_FLASH_ADDRESS(Address));
-
-#ifdef STM32F10X_XL
-  if(Address < FLASH_BANK1_END_ADDRESS - 2)
-  { 
-    /* Wait for last operation to be completed */
-    status = FLASH_WaitForLastBank1Operation(ProgramTimeout); 
-    if(status == FLASH_COMPLETE)
-    {
-      /* if the previous operation is completed, proceed to program the new first 
-        half word */
-      FLASH->CR |= CR_PG_Set;
-  
-      *(__IO uint16_t*)Address = (uint16_t)Data;
-      /* Wait for last operation to be completed */
-      status = FLASH_WaitForLastOperation(ProgramTimeout);
- 
-      if(status == FLASH_COMPLETE)
-      {
-        /* if the previous operation is completed, proceed to program the new second 
-        half word */
-        tmp = Address + 2;
-
-        *(__IO uint16_t*) tmp = Data >> 16;
-    
-        /* Wait for last operation to be completed */
-        status = FLASH_WaitForLastOperation(ProgramTimeout);
-        
-        /* Disable the PG Bit */
-        FLASH->CR &= CR_PG_Reset;
-      }
-      else
-      {
-        /* Disable the PG Bit */
-        FLASH->CR &= CR_PG_Reset;
-       }
-    }
-  }
-  else if(Address == (FLASH_BANK1_END_ADDRESS - 1))
-  {
-    /* Wait for last operation to be completed */
-    status = FLASH_WaitForLastBank1Operation(ProgramTimeout);
-
-    if(status == FLASH_COMPLETE)
-    {
-      /* if the previous operation is completed, proceed to program the new first 
-        half word */
-      FLASH->CR |= CR_PG_Set;
-  
-      *(__IO uint16_t*)Address = (uint16_t)Data;
-
-      /* Wait for last operation to be completed */
-      status = FLASH_WaitForLastBank1Operation(ProgramTimeout);
-      
-	  /* Disable the PG Bit */
-      FLASH->CR &= CR_PG_Reset;
-    }
-    else
-    {
-      /* Disable the PG Bit */
-      FLASH->CR &= CR_PG_Reset;
-    }
-
-    /* Wait for last operation to be completed */
-    status = FLASH_WaitForLastBank2Operation(ProgramTimeout);
-
-    if(status == FLASH_COMPLETE)
-    {
-      /* if the previous operation is completed, proceed to program the new second 
-      half word */
-      FLASH->CR2 |= CR_PG_Set;
-      tmp = Address + 2;
-
-      *(__IO uint16_t*) tmp = Data >> 16;
-    
-      /* Wait for last operation to be completed */
-      status = FLASH_WaitForLastBank2Operation(ProgramTimeout);
-        
-      /* Disable the PG Bit */
-      FLASH->CR2 &= CR_PG_Reset;
-    }
-    else
-    {
-      /* Disable the PG Bit */
-      FLASH->CR2 &= CR_PG_Reset;
-    }
-  }
-  else
-  {
-    /* Wait for last operation to be completed */
-    status = FLASH_WaitForLastBank2Operation(ProgramTimeout);
-
-    if(status == FLASH_COMPLETE)
-    {
-      /* if the previous operation is completed, proceed to program the new first 
-        half word */
-      FLASH->CR2 |= CR_PG_Set;
-  
-      *(__IO uint16_t*)Address = (uint16_t)Data;
-      /* Wait for last operation to be completed */
-      status = FLASH_WaitForLastBank2Operation(ProgramTimeout);
- 
-      if(status == FLASH_COMPLETE)
-      {
-        /* if the previous operation is completed, proceed to program the new second 
-        half word */
-        tmp = Address + 2;
-
-        *(__IO uint16_t*) tmp = Data >> 16;
-    
-        /* Wait for last operation to be completed */
-        status = FLASH_WaitForLastBank2Operation(ProgramTimeout);
-        
-        /* Disable the PG Bit */
-        FLASH->CR2 &= CR_PG_Reset;
-      }
-      else
-      {
-        /* Disable the PG Bit */
-        FLASH->CR2 &= CR_PG_Reset;
-      }
-    }
-  }
-#else
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation(ProgramTimeout);
-  
-  if(status == FLASH_COMPLETE)
-  {
-    /* if the previous operation is completed, proceed to program the new first 
-    half word */
-    FLASH->CR |= CR_PG_Set;
-  
-    *(__IO uint16_t*)Address = (uint16_t)Data;
-    /* Wait for last operation to be completed */
-    status = FLASH_WaitForLastOperation(ProgramTimeout);
- 
-    if(status == FLASH_COMPLETE)
-    {
-      /* if the previous operation is completed, proceed to program the new second 
-      half word */
-      tmp = Address + 2;
-
-      *(__IO uint16_t*) tmp = Data >> 16;
-    
-      /* Wait for last operation to be completed */
-      status = FLASH_WaitForLastOperation(ProgramTimeout);
-        
-      /* Disable the PG Bit */
-      FLASH->CR &= CR_PG_Reset;
-    }
-    else
-    {
-      /* Disable the PG Bit */
-      FLASH->CR &= CR_PG_Reset;
-    }
-  }         
-#endif /* STM32F10X_XL */
-   
-  /* Return the Program Status */
-  return status;
-}
-
-/**
-  * @brief  Programs a half word at a specified address.
-  * @note   This function can be used for all STM32F10x devices.
-  * @param  Address: specifies the address to be programmed.
-  * @param  Data: specifies the data to be programmed.
-  * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
-  *         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. 
-  */
-FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data)
-{
-  FLASH_Status status = FLASH_COMPLETE;
-  /* Check the parameters */
-  assert_param(IS_FLASH_ADDRESS(Address));
-
-#ifdef STM32F10X_XL
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation(ProgramTimeout);
-  
-  if(Address < FLASH_BANK1_END_ADDRESS)
-  {
-    if(status == FLASH_COMPLETE)
-    {
-      /* if the previous operation is completed, proceed to program the new data */
-      FLASH->CR |= CR_PG_Set;
-  
-      *(__IO uint16_t*)Address = Data;
-      /* Wait for last operation to be completed */
-      status = FLASH_WaitForLastBank1Operation(ProgramTimeout);
-
-      /* Disable the PG Bit */
-      FLASH->CR &= CR_PG_Reset;
-    }
-  }
-  else
-  {
-    if(status == FLASH_COMPLETE)
-    {
-      /* if the previous operation is completed, proceed to program the new data */
-      FLASH->CR2 |= CR_PG_Set;
-  
-      *(__IO uint16_t*)Address = Data;
-      /* Wait for last operation to be completed */
-      status = FLASH_WaitForLastBank2Operation(ProgramTimeout);
-
-      /* Disable the PG Bit */
-      FLASH->CR2 &= CR_PG_Reset;
-    }
-  }
-#else
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation(ProgramTimeout);
-  
-  if(status == FLASH_COMPLETE)
-  {
-    /* if the previous operation is completed, proceed to program the new data */
-    FLASH->CR |= CR_PG_Set;
-  
-    *(__IO uint16_t*)Address = Data;
-    /* Wait for last operation to be completed */
-    status = FLASH_WaitForLastOperation(ProgramTimeout);
-    
-    /* Disable the PG Bit */
-    FLASH->CR &= CR_PG_Reset;
-  } 
-#endif  /* STM32F10X_XL */
-  
-  /* Return the Program Status */
-  return status;
-}
-
-/**
-  * @brief  Programs a half word at a specified Option Byte Data address.
-  * @note   This function can be used for all STM32F10x devices.
-  * @param  Address: specifies the address to be programmed.
-  *   This parameter can be 0x1FFFF804 or 0x1FFFF806. 
-  * @param  Data: specifies the data to be programmed.
-  * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
-  *         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. 
-  */
-FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data)
-{
-  FLASH_Status status = FLASH_COMPLETE;
-  /* Check the parameters */
-  assert_param(IS_OB_DATA_ADDRESS(Address));
-  status = FLASH_WaitForLastOperation(ProgramTimeout);
-
-  if(status == FLASH_COMPLETE)
-  {
-    /* Authorize the small information block programming */
-    FLASH->OPTKEYR = FLASH_KEY1;
-    FLASH->OPTKEYR = FLASH_KEY2;
-    /* Enables the Option Bytes Programming operation */
-    FLASH->CR |= CR_OPTPG_Set; 
-    *(__IO uint16_t*)Address = Data;
-    
-    /* Wait for last operation to be completed */
-    status = FLASH_WaitForLastOperation(ProgramTimeout);
-    if(status != FLASH_TIMEOUT)
-    {
-      /* if the program operation is completed, disable the OPTPG Bit */
-      FLASH->CR &= CR_OPTPG_Reset;
-    }
-  }
-  /* Return the Option Byte Data Program Status */
-  return status;
-}
-
-/**
-  * @brief  Write protects the desired pages
-  * @note   This function can be used for all STM32F10x devices.
-  * @param  FLASH_Pages: specifies the address of the pages to be write protected.
-  *   This parameter can be:
-  *     @arg For @b STM32_Low-density_devices: value between FLASH_WRProt_Pages0to3 and FLASH_WRProt_Pages28to31  
-  *     @arg For @b STM32_Medium-density_devices: value between FLASH_WRProt_Pages0to3
-  *       and FLASH_WRProt_Pages124to127
-  *     @arg For @b STM32_High-density_devices: value between FLASH_WRProt_Pages0to1 and
-  *       FLASH_WRProt_Pages60to61 or FLASH_WRProt_Pages62to255
-  *     @arg For @b STM32_Connectivity_line_devices: value between FLASH_WRProt_Pages0to1 and
-  *       FLASH_WRProt_Pages60to61 or FLASH_WRProt_Pages62to127    
-  *     @arg For @b STM32_XL-density_devices: value between FLASH_WRProt_Pages0to1 and
-  *       FLASH_WRProt_Pages60to61 or FLASH_WRProt_Pages62to511
-  *     @arg FLASH_WRProt_AllPages
-  * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
-  *         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
-  */
-FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages)
-{
-  uint16_t WRP0_Data = 0xFFFF, WRP1_Data = 0xFFFF, WRP2_Data = 0xFFFF, WRP3_Data = 0xFFFF;
-  
-  FLASH_Status status = FLASH_COMPLETE;
-  
-  /* Check the parameters */
-  assert_param(IS_FLASH_WRPROT_PAGE(FLASH_Pages));
-  
-  FLASH_Pages = (uint32_t)(~FLASH_Pages);
-  WRP0_Data = (uint16_t)(FLASH_Pages & WRP0_Mask);
-  WRP1_Data = (uint16_t)((FLASH_Pages & WRP1_Mask) >> 8);
-  WRP2_Data = (uint16_t)((FLASH_Pages & WRP2_Mask) >> 16);
-  WRP3_Data = (uint16_t)((FLASH_Pages & WRP3_Mask) >> 24);
-  
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation(ProgramTimeout);
-  
-  if(status == FLASH_COMPLETE)
-  {
-    /* Authorizes the small information block programming */
-    FLASH->OPTKEYR = FLASH_KEY1;
-    FLASH->OPTKEYR = FLASH_KEY2;
-    FLASH->CR |= CR_OPTPG_Set;
-    if(WRP0_Data != 0xFF)
-    {
-      OB->WRP0 = WRP0_Data;
-      
-      /* Wait for last operation to be completed */
-      status = FLASH_WaitForLastOperation(ProgramTimeout);
-    }
-    if((status == FLASH_COMPLETE) && (WRP1_Data != 0xFF))
-    {
-      OB->WRP1 = WRP1_Data;
-      
-      /* Wait for last operation to be completed */
-      status = FLASH_WaitForLastOperation(ProgramTimeout);
-    }
-    if((status == FLASH_COMPLETE) && (WRP2_Data != 0xFF))
-    {
-      OB->WRP2 = WRP2_Data;
-      
-      /* Wait for last operation to be completed */
-      status = FLASH_WaitForLastOperation(ProgramTimeout);
-    }
-    
-    if((status == FLASH_COMPLETE)&& (WRP3_Data != 0xFF))
-    {
-      OB->WRP3 = WRP3_Data;
-     
-      /* Wait for last operation to be completed */
-      status = FLASH_WaitForLastOperation(ProgramTimeout);
-    }
-          
-    if(status != FLASH_TIMEOUT)
-    {
-      /* if the program operation is completed, disable the OPTPG Bit */
-      FLASH->CR &= CR_OPTPG_Reset;
-    }
-  } 
-  /* Return the write protection operation Status */
-  return status;       
-}
-
-/**
-  * @brief  Enables or disables the read out protection.
-  * @note   If the user has already programmed the other option bytes before calling 
-  *   this function, he must re-program them since this function erases all option bytes.
-  * @note   This function can be used for all STM32F10x devices.
-  * @param  Newstate: new state of the ReadOut Protection.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
-  *         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
-  */
-FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState)
-{
-  FLASH_Status status = FLASH_COMPLETE;
-  /* Check the parameters */
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  status = FLASH_WaitForLastOperation(EraseTimeout);
-  if(status == FLASH_COMPLETE)
-  {
-    /* Authorizes the small information block programming */
-    FLASH->OPTKEYR = FLASH_KEY1;
-    FLASH->OPTKEYR = FLASH_KEY2;
-    FLASH->CR |= CR_OPTER_Set;
-    FLASH->CR |= CR_STRT_Set;
-    /* Wait for last operation to be completed */
-    status = FLASH_WaitForLastOperation(EraseTimeout);
-    if(status == FLASH_COMPLETE)
-    {
-      /* if the erase operation is completed, disable the OPTER Bit */
-      FLASH->CR &= CR_OPTER_Reset;
-      /* Enable the Option Bytes Programming operation */
-      FLASH->CR |= CR_OPTPG_Set; 
-      if(NewState != DISABLE)
-      {
-        OB->RDP = 0x00;
-      }
-      else
-      {
-        OB->RDP = RDP_Key;  
-      }
-      /* Wait for last operation to be completed */
-      status = FLASH_WaitForLastOperation(EraseTimeout); 
-    
-      if(status != FLASH_TIMEOUT)
-      {
-        /* if the program operation is completed, disable the OPTPG Bit */
-        FLASH->CR &= CR_OPTPG_Reset;
-      }
-    }
-    else 
-    {
-      if(status != FLASH_TIMEOUT)
-      {
-        /* Disable the OPTER Bit */
-        FLASH->CR &= CR_OPTER_Reset;
-      }
-    }
-  }
-  /* Return the protection operation Status */
-  return status;       
-}
-
-/**
-  * @brief  Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.
-  * @note   This function can be used for all STM32F10x devices.
-  * @param  OB_IWDG: Selects the IWDG mode
-  *   This parameter can be one of the following values:
-  *     @arg OB_IWDG_SW: Software IWDG selected
-  *     @arg OB_IWDG_HW: Hardware IWDG selected
-  * @param  OB_STOP: Reset event when entering STOP mode.
-  *   This parameter can be one of the following values:
-  *     @arg OB_STOP_NoRST: No reset generated when entering in STOP
-  *     @arg OB_STOP_RST: Reset generated when entering in STOP
-  * @param  OB_STDBY: Reset event when entering Standby mode.
-  *   This parameter can be one of the following values:
-  *     @arg OB_STDBY_NoRST: No reset generated when entering in STANDBY
-  *     @arg OB_STDBY_RST: Reset generated when entering in STANDBY
-  * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, 
-  *         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
-  */
-FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY)
-{
-  FLASH_Status status = FLASH_COMPLETE; 
-
-  /* Check the parameters */
-  assert_param(IS_OB_IWDG_SOURCE(OB_IWDG));
-  assert_param(IS_OB_STOP_SOURCE(OB_STOP));
-  assert_param(IS_OB_STDBY_SOURCE(OB_STDBY));
-
-  /* Authorize the small information block programming */
-  FLASH->OPTKEYR = FLASH_KEY1;
-  FLASH->OPTKEYR = FLASH_KEY2;
-  
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation(ProgramTimeout);
-  
-  if(status == FLASH_COMPLETE)
-  {  
-    /* Enable the Option Bytes Programming operation */
-    FLASH->CR |= CR_OPTPG_Set; 
-           
-    OB->USER = OB_IWDG | (uint16_t)(OB_STOP | (uint16_t)(OB_STDBY | ((uint16_t)0xF8))); 
-  
-    /* Wait for last operation to be completed */
-    status = FLASH_WaitForLastOperation(ProgramTimeout);
-    if(status != FLASH_TIMEOUT)
-    {
-      /* if the program operation is completed, disable the OPTPG Bit */
-      FLASH->CR &= CR_OPTPG_Reset;
-    }
-  }    
-  /* Return the Option Byte program Status */
-  return status;
-}
-
-#ifdef STM32F10X_XL
-/**
-  * @brief  Configures to boot from Bank1 or Bank2.  
-  * @note   This function can be used only for STM32F10x_XL density devices.
-  * @param  FLASH_BOOT: select the FLASH Bank to boot from.
-  *   This parameter can be one of the following values:
-  *     @arg FLASH_BOOT_Bank1: At startup, if boot pins are set in boot from user Flash
-  *        position and this parameter is selected the device will boot from Bank1(Default).
-  *     @arg FLASH_BOOT_Bank2: At startup, if boot pins are set in boot from user Flash
-  *        position and this parameter is selected the device will boot from Bank2 or Bank1,
-  *        depending on the activation of the bank. The active banks are checked in
-  *        the following order: Bank2, followed by Bank1.
-  *        The active bank is recognized by the value programmed at the base address
-  *        of the respective bank (corresponding to the initial stack pointer value
-  *        in the interrupt vector table).
-  *        For more information, please refer to AN2606 from www.st.com.    
-  * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, 
-  *         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
-  */
-FLASH_Status FLASH_BootConfig(uint16_t FLASH_BOOT)
-{ 
-  FLASH_Status status = FLASH_COMPLETE; 
-  assert_param(IS_FLASH_BOOT(FLASH_BOOT));
-  /* Authorize the small information block programming */
-  FLASH->OPTKEYR = FLASH_KEY1;
-  FLASH->OPTKEYR = FLASH_KEY2;
-  
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation(ProgramTimeout);
-  
-  if(status == FLASH_COMPLETE)
-  {  
-    /* Enable the Option Bytes Programming operation */
-    FLASH->CR |= CR_OPTPG_Set; 
-
-    if(FLASH_BOOT == FLASH_BOOT_Bank1)
-    {
-      OB->USER |= OB_USER_BFB2;
-    }
-    else
-    {
-      OB->USER &= (uint16_t)(~(uint16_t)(OB_USER_BFB2));
-    }
-    /* Wait for last operation to be completed */
-    status = FLASH_WaitForLastOperation(ProgramTimeout);
-    if(status != FLASH_TIMEOUT)
-    {
-      /* if the program operation is completed, disable the OPTPG Bit */
-      FLASH->CR &= CR_OPTPG_Reset;
-    }
-  }    
-  /* Return the Option Byte program Status */
-  return status;
-}
-#endif /* STM32F10X_XL */
-
-/**
-  * @brief  Returns the FLASH User Option Bytes values.
-  * @note   This function can be used for all STM32F10x devices.
-  * @param  None
-  * @retval The FLASH User Option Bytes values:IWDG_SW(Bit0), RST_STOP(Bit1)
-  *         and RST_STDBY(Bit2).
-  */
-uint32_t FLASH_GetUserOptionByte(void)
-{
-  /* Return the User Option Byte */
-  return (uint32_t)(FLASH->OBR >> 2);
-}
-
-/**
-  * @brief  Returns the FLASH Write Protection Option Bytes Register value.
-  * @note   This function can be used for all STM32F10x devices.
-  * @param  None
-  * @retval The FLASH Write Protection  Option Bytes Register value
-  */
-uint32_t FLASH_GetWriteProtectionOptionByte(void)
-{
-  /* Return the Flash write protection Register value */
-  return (uint32_t)(FLASH->WRPR);
-}
-
-/**
-  * @brief  Checks whether the FLASH Read Out Protection Status is set or not.
-  * @note   This function can be used for all STM32F10x devices.
-  * @param  None
-  * @retval FLASH ReadOut Protection Status(SET or RESET)
-  */
-FlagStatus FLASH_GetReadOutProtectionStatus(void)
-{
-  FlagStatus readoutstatus = RESET;
-  if ((FLASH->OBR & RDPRT_Mask) != (uint32_t)RESET)
-  {
-    readoutstatus = SET;
-  }
-  else
-  {
-    readoutstatus = RESET;
-  }
-  return readoutstatus;
-}
-
-/**
-  * @brief  Checks whether the FLASH Prefetch Buffer status is set or not.
-  * @note   This function can be used for all STM32F10x devices.
-  * @param  None
-  * @retval FLASH Prefetch Buffer Status (SET or RESET).
-  */
-FlagStatus FLASH_GetPrefetchBufferStatus(void)
-{
-  FlagStatus bitstatus = RESET;
-  
-  if ((FLASH->ACR & ACR_PRFTBS_Mask) != (uint32_t)RESET)
-  {
-    bitstatus = SET;
-  }
-  else
-  {
-    bitstatus = RESET;
-  }
-  /* Return the new state of FLASH Prefetch Buffer Status (SET or RESET) */
-  return bitstatus; 
-}
-
-/**
-  * @brief  Enables or disables the specified FLASH interrupts.
-  * @note   This function can be used for all STM32F10x devices.
-  *         - For STM32F10X_XL devices, enables or disables the specified FLASH interrupts
-              for Bank1 and Bank2.
-  *         - For other devices it enables or disables the specified FLASH interrupts for Bank1.
-  * @param  FLASH_IT: specifies the FLASH interrupt sources to be enabled or disabled.
-  *   This parameter can be any combination of the following values:
-  *     @arg FLASH_IT_ERROR: FLASH Error Interrupt
-  *     @arg FLASH_IT_EOP: FLASH end of operation Interrupt
-  * @param  NewState: new state of the specified Flash interrupts.
-  *   This parameter can be: ENABLE or DISABLE.      
-  * @retval None 
-  */
-void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState)
-{
-#ifdef STM32F10X_XL
-  /* Check the parameters */
-  assert_param(IS_FLASH_IT(FLASH_IT)); 
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-
-  if((FLASH_IT & 0x80000000) != 0x0)
-  {
-    if(NewState != DISABLE)
-    {
-      /* Enable the interrupt sources */
-      FLASH->CR2 |= (FLASH_IT & 0x7FFFFFFF);
-    }
-    else
-    {
-      /* Disable the interrupt sources */
-      FLASH->CR2 &= ~(uint32_t)(FLASH_IT & 0x7FFFFFFF);
-    }
-  }
-  else
-  {
-    if(NewState != DISABLE)
-    {
-      /* Enable the interrupt sources */
-      FLASH->CR |= FLASH_IT;
-    }
-    else
-    {
-      /* Disable the interrupt sources */
-      FLASH->CR &= ~(uint32_t)FLASH_IT;
-    }
-  }
-#else
-  /* Check the parameters */
-  assert_param(IS_FLASH_IT(FLASH_IT)); 
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-
-  if(NewState != DISABLE)
-  {
-    /* Enable the interrupt sources */
-    FLASH->CR |= FLASH_IT;
-  }
-  else
-  {
-    /* Disable the interrupt sources */
-    FLASH->CR &= ~(uint32_t)FLASH_IT;
-  }
-#endif /* STM32F10X_XL */
-}
-
-/**
-  * @brief  Checks whether the specified FLASH flag is set or not.
-  * @note   This function can be used for all STM32F10x devices.
-  *         - For STM32F10X_XL devices, this function checks whether the specified 
-  *           Bank1 or Bank2 flag is set or not.
-  *         - For other devices, it checks whether the specified Bank1 flag is 
-  *           set or not.
-  * @param  FLASH_FLAG: specifies the FLASH flag to check.
-  *   This parameter can be one of the following values:
-  *     @arg FLASH_FLAG_BSY: FLASH Busy flag           
-  *     @arg FLASH_FLAG_PGERR: FLASH Program error flag       
-  *     @arg FLASH_FLAG_WRPRTERR: FLASH Write protected error flag      
-  *     @arg FLASH_FLAG_EOP: FLASH End of Operation flag           
-  *     @arg FLASH_FLAG_OPTERR:  FLASH Option Byte error flag     
-  * @retval The new state of FLASH_FLAG (SET or RESET).
-  */
-FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG)
-{
-  FlagStatus bitstatus = RESET;
-
-#ifdef STM32F10X_XL
-  /* Check the parameters */
-  assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG)) ;
-  if(FLASH_FLAG == FLASH_FLAG_OPTERR) 
-  {
-    if((FLASH->OBR & FLASH_FLAG_OPTERR) != (uint32_t)RESET)
-    {
-      bitstatus = SET;
-    }
-    else
-    {
-      bitstatus = RESET;
-    }
-  }
-  else
-  {
-    if((FLASH_FLAG & 0x80000000) != 0x0)
-    {
-      if((FLASH->SR2 & FLASH_FLAG) != (uint32_t)RESET)
-      {
-        bitstatus = SET;
-      }
-      else
-      {
-        bitstatus = RESET;
-      }
-    }
-    else
-    {
-      if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET)
-      {
-        bitstatus = SET;
-      }
-      else
-      {
-        bitstatus = RESET;
-      }
-    }
-  }
-#else
-  /* Check the parameters */
-  assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG)) ;
-  if(FLASH_FLAG == FLASH_FLAG_OPTERR) 
-  {
-    if((FLASH->OBR & FLASH_FLAG_OPTERR) != (uint32_t)RESET)
-    {
-      bitstatus = SET;
-    }
-    else
-    {
-      bitstatus = RESET;
-    }
-  }
-  else
-  {
-   if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET)
-    {
-      bitstatus = SET;
-    }
-    else
-    {
-      bitstatus = RESET;
-    }
-  }
-#endif /* STM32F10X_XL */
-
-  /* Return the new state of FLASH_FLAG (SET or RESET) */
-  return bitstatus;
-}
-
-/**
-  * @brief  Clears the FLASH's pending flags.
-  * @note   This function can be used for all STM32F10x devices.
-  *         - For STM32F10X_XL devices, this function clears Bank1 or Bank2’s pending flags
-  *         - For other devices, it clears Bank1’s pending flags.
-  * @param  FLASH_FLAG: specifies the FLASH flags to clear.
-  *   This parameter can be any combination of the following values:         
-  *     @arg FLASH_FLAG_PGERR: FLASH Program error flag       
-  *     @arg FLASH_FLAG_WRPRTERR: FLASH Write protected error flag      
-  *     @arg FLASH_FLAG_EOP: FLASH End of Operation flag           
-  * @retval None
-  */
-void FLASH_ClearFlag(uint32_t FLASH_FLAG)
-{
-#ifdef STM32F10X_XL
-  /* Check the parameters */
-  assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG)) ;
-
-  if((FLASH_FLAG & 0x80000000) != 0x0)
-  {
-    /* Clear the flags */
-    FLASH->SR2 = FLASH_FLAG;
-  }
-  else
-  {
-    /* Clear the flags */
-    FLASH->SR = FLASH_FLAG;
-  }  
-
-#else
-  /* Check the parameters */
-  assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG)) ;
-  
-  /* Clear the flags */
-  FLASH->SR = FLASH_FLAG;
-#endif /* STM32F10X_XL */
-}
-
-/**
-  * @brief  Returns the FLASH Status.
-  * @note   This function can be used for all STM32F10x devices, it is equivalent
-  *         to FLASH_GetBank1Status function.
-  * @param  None
-  * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
-  *         FLASH_ERROR_WRP or FLASH_COMPLETE
-  */
-FLASH_Status FLASH_GetStatus(void)
-{
-  FLASH_Status flashstatus = FLASH_COMPLETE;
-  
-  if((FLASH->SR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY) 
-  {
-    flashstatus = FLASH_BUSY;
-  }
-  else 
-  {  
-    if((FLASH->SR & FLASH_FLAG_PGERR) != 0)
-    { 
-      flashstatus = FLASH_ERROR_PG;
-    }
-    else 
-    {
-      if((FLASH->SR & FLASH_FLAG_WRPRTERR) != 0 )
-      {
-        flashstatus = FLASH_ERROR_WRP;
-      }
-      else
-      {
-        flashstatus = FLASH_COMPLETE;
-      }
-    }
-  }
-  /* Return the Flash Status */
-  return flashstatus;
-}
-
-/**
-  * @brief  Returns the FLASH Bank1 Status.
-  * @note   This function can be used for all STM32F10x devices, it is equivalent
-  *         to FLASH_GetStatus function.
-  * @param  None
-  * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
-  *         FLASH_ERROR_WRP or FLASH_COMPLETE
-  */
-FLASH_Status FLASH_GetBank1Status(void)
-{
-  FLASH_Status flashstatus = FLASH_COMPLETE;
-  
-  if((FLASH->SR & FLASH_FLAG_BANK1_BSY) == FLASH_FLAG_BSY) 
-  {
-    flashstatus = FLASH_BUSY;
-  }
-  else 
-  {  
-    if((FLASH->SR & FLASH_FLAG_BANK1_PGERR) != 0)
-    { 
-      flashstatus = FLASH_ERROR_PG;
-    }
-    else 
-    {
-      if((FLASH->SR & FLASH_FLAG_BANK1_WRPRTERR) != 0 )
-      {
-        flashstatus = FLASH_ERROR_WRP;
-      }
-      else
-      {
-        flashstatus = FLASH_COMPLETE;
-      }
-    }
-  }
-  /* Return the Flash Status */
-  return flashstatus;
-}
-
-#ifdef STM32F10X_XL
-/**
-  * @brief  Returns the FLASH Bank2 Status.
-  * @note   This function can be used for STM32F10x_XL density devices.
-  * @param  None
-  * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
-  *        FLASH_ERROR_WRP or FLASH_COMPLETE
-  */
-FLASH_Status FLASH_GetBank2Status(void)
-{
-  FLASH_Status flashstatus = FLASH_COMPLETE;
-  
-  if((FLASH->SR2 & (FLASH_FLAG_BANK2_BSY & 0x7FFFFFFF)) == (FLASH_FLAG_BANK2_BSY & 0x7FFFFFFF)) 
-  {
-    flashstatus = FLASH_BUSY;
-  }
-  else 
-  {  
-    if((FLASH->SR2 & (FLASH_FLAG_BANK2_PGERR & 0x7FFFFFFF)) != 0)
-    { 
-      flashstatus = FLASH_ERROR_PG;
-    }
-    else 
-    {
-      if((FLASH->SR2 & (FLASH_FLAG_BANK2_WRPRTERR & 0x7FFFFFFF)) != 0 )
-      {
-        flashstatus = FLASH_ERROR_WRP;
-      }
-      else
-      {
-        flashstatus = FLASH_COMPLETE;
-      }
-    }
-  }
-  /* Return the Flash Status */
-  return flashstatus;
-}
-#endif /* STM32F10X_XL */
-/**
-  * @brief  Waits for a Flash operation to complete or a TIMEOUT to occur.
-  * @note   This function can be used for all STM32F10x devices, 
-  *         it is equivalent to FLASH_WaitForLastBank1Operation.
-  *         - For STM32F10X_XL devices this function waits for a Bank1 Flash operation
-  *           to complete or a TIMEOUT to occur.
-  *         - For all other devices it waits for a Flash operation to complete 
-  *           or a TIMEOUT to occur.
-  * @param  Timeout: FLASH programming Timeout
-  * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
-  *         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
-  */
-FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout)
-{ 
-  FLASH_Status status = FLASH_COMPLETE;
-   
-  /* Check for the Flash Status */
-  status = FLASH_GetBank1Status();
-  /* Wait for a Flash operation to complete or a TIMEOUT to occur */
-  while((status == FLASH_BUSY) && (Timeout != 0x00))
-  {
-    status = FLASH_GetBank1Status();
-    Timeout--;
-  }
-  if(Timeout == 0x00 )
-  {
-    status = FLASH_TIMEOUT;
-  }
-  /* Return the operation status */
-  return status;
-}
-
-/**
-  * @brief  Waits for a Flash operation on Bank1 to complete or a TIMEOUT to occur.
-  * @note   This function can be used for all STM32F10x devices, 
-  *         it is equivalent to FLASH_WaitForLastOperation.
-  * @param  Timeout: FLASH programming Timeout
-  * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
-  *         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
-  */
-FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout)
-{ 
-  FLASH_Status status = FLASH_COMPLETE;
-   
-  /* Check for the Flash Status */
-  status = FLASH_GetBank1Status();
-  /* Wait for a Flash operation to complete or a TIMEOUT to occur */
-  while((status == FLASH_FLAG_BANK1_BSY) && (Timeout != 0x00))
-  {
-    status = FLASH_GetBank1Status();
-    Timeout--;
-  }
-  if(Timeout == 0x00 )
-  {
-    status = FLASH_TIMEOUT;
-  }
-  /* Return the operation status */
-  return status;
-}
-
-#ifdef STM32F10X_XL
-/**
-  * @brief  Waits for a Flash operation on Bank2 to complete or a TIMEOUT to occur.
-  * @note   This function can be used only for STM32F10x_XL density devices.
-  * @param  Timeout: FLASH programming Timeout
-  * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
-  *         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
-  */
-FLASH_Status FLASH_WaitForLastBank2Operation(uint32_t Timeout)
-{ 
-  FLASH_Status status = FLASH_COMPLETE;
-   
-  /* Check for the Flash Status */
-  status = FLASH_GetBank2Status();
-  /* Wait for a Flash operation to complete or a TIMEOUT to occur */
-  while((status == (FLASH_FLAG_BANK2_BSY & 0x7FFFFFFF)) && (Timeout != 0x00))
-  {
-    status = FLASH_GetBank2Status();
-    Timeout--;
-  }
-  if(Timeout == 0x00 )
-  {
-    status = FLASH_TIMEOUT;
-  }
-  /* Return the operation status */
-  return status;
-}
-#endif /* STM32F10X_XL */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c
deleted file mode 100644
index 457ff11..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c
+++ /dev/null
@@ -1,650 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f10x_gpio.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    11-March-2011
-  * @brief   This file provides all the GPIO firmware functions.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_gpio.h"
-#include "stm32f10x_rcc.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Driver
-  * @{
-  */
-
-/** @defgroup GPIO 
-  * @brief GPIO driver modules
-  * @{
-  */ 
-
-/** @defgroup GPIO_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup GPIO_Private_Defines
-  * @{
-  */
-
-/* ------------ RCC registers bit address in the alias region ----------------*/
-#define AFIO_OFFSET                 (AFIO_BASE - PERIPH_BASE)
-
-/* --- EVENTCR Register -----*/
-
-/* Alias word address of EVOE bit */
-#define EVCR_OFFSET                 (AFIO_OFFSET + 0x00)
-#define EVOE_BitNumber              ((uint8_t)0x07)
-#define EVCR_EVOE_BB                (PERIPH_BB_BASE + (EVCR_OFFSET * 32) + (EVOE_BitNumber * 4))
-
-
-/* ---  MAPR Register ---*/ 
-/* Alias word address of MII_RMII_SEL bit */ 
-#define MAPR_OFFSET                 (AFIO_OFFSET + 0x04) 
-#define MII_RMII_SEL_BitNumber      ((u8)0x17) 
-#define MAPR_MII_RMII_SEL_BB        (PERIPH_BB_BASE + (MAPR_OFFSET * 32) + (MII_RMII_SEL_BitNumber * 4))
-
-
-#define EVCR_PORTPINCONFIG_MASK     ((uint16_t)0xFF80)
-#define LSB_MASK                    ((uint16_t)0xFFFF)
-#define DBGAFR_POSITION_MASK        ((uint32_t)0x000F0000)
-#define DBGAFR_SWJCFG_MASK          ((uint32_t)0xF0FFFFFF)
-#define DBGAFR_LOCATION_MASK        ((uint32_t)0x00200000)
-#define DBGAFR_NUMBITS_MASK         ((uint32_t)0x00100000)
-/**
-  * @}
-  */
-
-/** @defgroup GPIO_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup GPIO_Private_Variables
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup GPIO_Private_FunctionPrototypes
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup GPIO_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Deinitializes the GPIOx peripheral registers to their default reset values.
-  * @param  GPIOx: where x can be (A..G) to select the GPIO peripheral.
-  * @retval None
-  */
-void GPIO_DeInit(GPIO_TypeDef* GPIOx)
-{
-  /* Check the parameters */
-  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
-  
-  if (GPIOx == GPIOA)
-  {
-    RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, ENABLE);
-    RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, DISABLE);
-  }
-  else if (GPIOx == GPIOB)
-  {
-    RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, ENABLE);
-    RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, DISABLE);
-  }
-  else if (GPIOx == GPIOC)
-  {
-    RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, ENABLE);
-    RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, DISABLE);
-  }
-  else if (GPIOx == GPIOD)
-  {
-    RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, ENABLE);
-    RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, DISABLE);
-  }    
-  else if (GPIOx == GPIOE)
-  {
-    RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, ENABLE);
-    RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, DISABLE);
-  } 
-  else if (GPIOx == GPIOF)
-  {
-    RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOF, ENABLE);
-    RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOF, DISABLE);
-  }
-  else
-  {
-    if (GPIOx == GPIOG)
-    {
-      RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOG, ENABLE);
-      RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOG, DISABLE);
-    }
-  }
-}
-
-/**
-  * @brief  Deinitializes the Alternate Functions (remap, event control
-  *   and EXTI configuration) registers to their default reset values.
-  * @param  None
-  * @retval None
-  */
-void GPIO_AFIODeInit(void)
-{
-  RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, ENABLE);
-  RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, DISABLE);
-}
-
-/**
-  * @brief  Initializes the GPIOx peripheral according to the specified
-  *         parameters in the GPIO_InitStruct.
-  * @param  GPIOx: where x can be (A..G) to select the GPIO peripheral.
-  * @param  GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that
-  *         contains the configuration information for the specified GPIO peripheral.
-  * @retval None
-  */
-void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)
-{
-  uint32_t currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00;
-  uint32_t tmpreg = 0x00, pinmask = 0x00;
-  /* Check the parameters */
-  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
-  assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode));
-  assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin));  
-  
-/*---------------------------- GPIO Mode Configuration -----------------------*/
-  currentmode = ((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x0F);
-  if ((((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x10)) != 0x00)
-  { 
-    /* Check the parameters */
-    assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed));
-    /* Output mode */
-    currentmode |= (uint32_t)GPIO_InitStruct->GPIO_Speed;
-  }
-/*---------------------------- GPIO CRL Configuration ------------------------*/
-  /* Configure the eight low port pins */
-  if (((uint32_t)GPIO_InitStruct->GPIO_Pin & ((uint32_t)0x00FF)) != 0x00)
-  {
-    tmpreg = GPIOx->CRL;
-    for (pinpos = 0x00; pinpos < 0x08; pinpos++)
-    {
-      pos = ((uint32_t)0x01) << pinpos;
-      /* Get the port pins position */
-      currentpin = (GPIO_InitStruct->GPIO_Pin) & pos;
-      if (currentpin == pos)
-      {
-        pos = pinpos << 2;
-        /* Clear the corresponding low control register bits */
-        pinmask = ((uint32_t)0x0F) << pos;
-        tmpreg &= ~pinmask;
-        /* Write the mode configuration in the corresponding bits */
-        tmpreg |= (currentmode << pos);
-        /* Reset the corresponding ODR bit */
-        if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)
-        {
-          GPIOx->BRR = (((uint32_t)0x01) << pinpos);
-        }
-        else
-        {
-          /* Set the corresponding ODR bit */
-          if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)
-          {
-            GPIOx->BSRR = (((uint32_t)0x01) << pinpos);
-          }
-        }
-      }
-    }
-    GPIOx->CRL = tmpreg;
-  }
-/*---------------------------- GPIO CRH Configuration ------------------------*/
-  /* Configure the eight high port pins */
-  if (GPIO_InitStruct->GPIO_Pin > 0x00FF)
-  {
-    tmpreg = GPIOx->CRH;
-    for (pinpos = 0x00; pinpos < 0x08; pinpos++)
-    {
-      pos = (((uint32_t)0x01) << (pinpos + 0x08));
-      /* Get the port pins position */
-      currentpin = ((GPIO_InitStruct->GPIO_Pin) & pos);
-      if (currentpin == pos)
-      {
-        pos = pinpos << 2;
-        /* Clear the corresponding high control register bits */
-        pinmask = ((uint32_t)0x0F) << pos;
-        tmpreg &= ~pinmask;
-        /* Write the mode configuration in the corresponding bits */
-        tmpreg |= (currentmode << pos);
-        /* Reset the corresponding ODR bit */
-        if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)
-        {
-          GPIOx->BRR = (((uint32_t)0x01) << (pinpos + 0x08));
-        }
-        /* Set the corresponding ODR bit */
-        if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)
-        {
-          GPIOx->BSRR = (((uint32_t)0x01) << (pinpos + 0x08));
-        }
-      }
-    }
-    GPIOx->CRH = tmpreg;
-  }
-}
-
-/**
-  * @brief  Fills each GPIO_InitStruct member with its default value.
-  * @param  GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure which will
-  *         be initialized.
-  * @retval None
-  */
-void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct)
-{
-  /* Reset GPIO init structure parameters values */
-  GPIO_InitStruct->GPIO_Pin  = GPIO_Pin_All;
-  GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz;
-  GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN_FLOATING;
-}
-
-/**
-  * @brief  Reads the specified input port pin.
-  * @param  GPIOx: where x can be (A..G) to select the GPIO peripheral.
-  * @param  GPIO_Pin:  specifies the port bit to read.
-  *   This parameter can be GPIO_Pin_x where x can be (0..15).
-  * @retval The input port pin value.
-  */
-uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
-  uint8_t bitstatus = 0x00;
-  
-  /* Check the parameters */
-  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
-  assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); 
-  
-  if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET)
-  {
-    bitstatus = (uint8_t)Bit_SET;
-  }
-  else
-  {
-    bitstatus = (uint8_t)Bit_RESET;
-  }
-  return bitstatus;
-}
-
-/**
-  * @brief  Reads the specified GPIO input data port.
-  * @param  GPIOx: where x can be (A..G) to select the GPIO peripheral.
-  * @retval GPIO input data port value.
-  */
-uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx)
-{
-  /* Check the parameters */
-  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
-  
-  return ((uint16_t)GPIOx->IDR);
-}
-
-/**
-  * @brief  Reads the specified output data port bit.
-  * @param  GPIOx: where x can be (A..G) to select the GPIO peripheral.
-  * @param  GPIO_Pin:  specifies the port bit to read.
-  *   This parameter can be GPIO_Pin_x where x can be (0..15).
-  * @retval The output port pin value.
-  */
-uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
-  uint8_t bitstatus = 0x00;
-  /* Check the parameters */
-  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
-  assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); 
-  
-  if ((GPIOx->ODR & GPIO_Pin) != (uint32_t)Bit_RESET)
-  {
-    bitstatus = (uint8_t)Bit_SET;
-  }
-  else
-  {
-    bitstatus = (uint8_t)Bit_RESET;
-  }
-  return bitstatus;
-}
-
-/**
-  * @brief  Reads the specified GPIO output data port.
-  * @param  GPIOx: where x can be (A..G) to select the GPIO peripheral.
-  * @retval GPIO output data port value.
-  */
-uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx)
-{
-  /* Check the parameters */
-  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
-    
-  return ((uint16_t)GPIOx->ODR);
-}
-
-/**
-  * @brief  Sets the selected data port bits.
-  * @param  GPIOx: where x can be (A..G) to select the GPIO peripheral.
-  * @param  GPIO_Pin: specifies the port bits to be written.
-  *   This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
-  * @retval None
-  */
-void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
-  /* Check the parameters */
-  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
-  assert_param(IS_GPIO_PIN(GPIO_Pin));
-  
-  GPIOx->BSRR = GPIO_Pin;
-}
-
-/**
-  * @brief  Clears the selected data port bits.
-  * @param  GPIOx: where x can be (A..G) to select the GPIO peripheral.
-  * @param  GPIO_Pin: specifies the port bits to be written.
-  *   This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
-  * @retval None
-  */
-void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
-  /* Check the parameters */
-  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
-  assert_param(IS_GPIO_PIN(GPIO_Pin));
-  
-  GPIOx->BRR = GPIO_Pin;
-}
-
-/**
-  * @brief  Sets or clears the selected data port bit.
-  * @param  GPIOx: where x can be (A..G) to select the GPIO peripheral.
-  * @param  GPIO_Pin: specifies the port bit to be written.
-  *   This parameter can be one of GPIO_Pin_x where x can be (0..15).
-  * @param  BitVal: specifies the value to be written to the selected bit.
-  *   This parameter can be one of the BitAction enum values:
-  *     @arg Bit_RESET: to clear the port pin
-  *     @arg Bit_SET: to set the port pin
-  * @retval None
-  */
-void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal)
-{
-  /* Check the parameters */
-  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
-  assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
-  assert_param(IS_GPIO_BIT_ACTION(BitVal)); 
-  
-  if (BitVal != Bit_RESET)
-  {
-    GPIOx->BSRR = GPIO_Pin;
-  }
-  else
-  {
-    GPIOx->BRR = GPIO_Pin;
-  }
-}
-
-/**
-  * @brief  Writes data to the specified GPIO data port.
-  * @param  GPIOx: where x can be (A..G) to select the GPIO peripheral.
-  * @param  PortVal: specifies the value to be written to the port output data register.
-  * @retval None
-  */
-void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal)
-{
-  /* Check the parameters */
-  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
-  
-  GPIOx->ODR = PortVal;
-}
-
-/**
-  * @brief  Locks GPIO Pins configuration registers.
-  * @param  GPIOx: where x can be (A..G) to select the GPIO peripheral.
-  * @param  GPIO_Pin: specifies the port bit to be written.
-  *   This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
-  * @retval None
-  */
-void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
-  uint32_t tmp = 0x00010000;
-  
-  /* Check the parameters */
-  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
-  assert_param(IS_GPIO_PIN(GPIO_Pin));
-  
-  tmp |= GPIO_Pin;
-  /* Set LCKK bit */
-  GPIOx->LCKR = tmp;
-  /* Reset LCKK bit */
-  GPIOx->LCKR =  GPIO_Pin;
-  /* Set LCKK bit */
-  GPIOx->LCKR = tmp;
-  /* Read LCKK bit*/
-  tmp = GPIOx->LCKR;
-  /* Read LCKK bit*/
-  tmp = GPIOx->LCKR;
-}
-
-/**
-  * @brief  Selects the GPIO pin used as Event output.
-  * @param  GPIO_PortSource: selects the GPIO port to be used as source
-  *   for Event output.
-  *   This parameter can be GPIO_PortSourceGPIOx where x can be (A..E).
-  * @param  GPIO_PinSource: specifies the pin for the Event output.
-  *   This parameter can be GPIO_PinSourcex where x can be (0..15).
-  * @retval None
-  */
-void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource)
-{
-  uint32_t tmpreg = 0x00;
-  /* Check the parameters */
-  assert_param(IS_GPIO_EVENTOUT_PORT_SOURCE(GPIO_PortSource));
-  assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource));
-    
-  tmpreg = AFIO->EVCR;
-  /* Clear the PORT[6:4] and PIN[3:0] bits */
-  tmpreg &= EVCR_PORTPINCONFIG_MASK;
-  tmpreg |= (uint32_t)GPIO_PortSource << 0x04;
-  tmpreg |= GPIO_PinSource;
-  AFIO->EVCR = tmpreg;
-}
-
-/**
-  * @brief  Enables or disables the Event Output.
-  * @param  NewState: new state of the Event output.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void GPIO_EventOutputCmd(FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  
-  *(__IO uint32_t *) EVCR_EVOE_BB = (uint32_t)NewState;
-}
-
-/**
-  * @brief  Changes the mapping of the specified pin.
-  * @param  GPIO_Remap: selects the pin to remap.
-  *   This parameter can be one of the following values:
-  *     @arg GPIO_Remap_SPI1             : SPI1 Alternate Function mapping
-  *     @arg GPIO_Remap_I2C1             : I2C1 Alternate Function mapping
-  *     @arg GPIO_Remap_USART1           : USART1 Alternate Function mapping
-  *     @arg GPIO_Remap_USART2           : USART2 Alternate Function mapping
-  *     @arg GPIO_PartialRemap_USART3    : USART3 Partial Alternate Function mapping
-  *     @arg GPIO_FullRemap_USART3       : USART3 Full Alternate Function mapping
-  *     @arg GPIO_PartialRemap_TIM1      : TIM1 Partial Alternate Function mapping
-  *     @arg GPIO_FullRemap_TIM1         : TIM1 Full Alternate Function mapping
-  *     @arg GPIO_PartialRemap1_TIM2     : TIM2 Partial1 Alternate Function mapping
-  *     @arg GPIO_PartialRemap2_TIM2     : TIM2 Partial2 Alternate Function mapping
-  *     @arg GPIO_FullRemap_TIM2         : TIM2 Full Alternate Function mapping
-  *     @arg GPIO_PartialRemap_TIM3      : TIM3 Partial Alternate Function mapping
-  *     @arg GPIO_FullRemap_TIM3         : TIM3 Full Alternate Function mapping
-  *     @arg GPIO_Remap_TIM4             : TIM4 Alternate Function mapping
-  *     @arg GPIO_Remap1_CAN1            : CAN1 Alternate Function mapping
-  *     @arg GPIO_Remap2_CAN1            : CAN1 Alternate Function mapping
-  *     @arg GPIO_Remap_PD01             : PD01 Alternate Function mapping
-  *     @arg GPIO_Remap_TIM5CH4_LSI      : LSI connected to TIM5 Channel4 input capture for calibration
-  *     @arg GPIO_Remap_ADC1_ETRGINJ     : ADC1 External Trigger Injected Conversion remapping
-  *     @arg GPIO_Remap_ADC1_ETRGREG     : ADC1 External Trigger Regular Conversion remapping
-  *     @arg GPIO_Remap_ADC2_ETRGINJ     : ADC2 External Trigger Injected Conversion remapping
-  *     @arg GPIO_Remap_ADC2_ETRGREG     : ADC2 External Trigger Regular Conversion remapping
-  *     @arg GPIO_Remap_ETH              : Ethernet remapping (only for Connectivity line devices)
-  *     @arg GPIO_Remap_CAN2             : CAN2 remapping (only for Connectivity line devices)
-  *     @arg GPIO_Remap_SWJ_NoJTRST      : Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST
-  *     @arg GPIO_Remap_SWJ_JTAGDisable  : JTAG-DP Disabled and SW-DP Enabled
-  *     @arg GPIO_Remap_SWJ_Disable      : Full SWJ Disabled (JTAG-DP + SW-DP)
-  *     @arg GPIO_Remap_SPI3             : SPI3/I2S3 Alternate Function mapping (only for Connectivity line devices)
-  *                                        When the SPI3/I2S3 is remapped using this function, the SWJ is configured
-  *                                        to Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST.   
-  *     @arg GPIO_Remap_TIM2ITR1_PTP_SOF : Ethernet PTP output or USB OTG SOF (Start of Frame) connected
-  *                                        to TIM2 Internal Trigger 1 for calibration (only for Connectivity line devices)
-  *                                        If the GPIO_Remap_TIM2ITR1_PTP_SOF is enabled the TIM2 ITR1 is connected to 
-  *                                        Ethernet PTP output. When Reset TIM2 ITR1 is connected to USB OTG SOF output.    
-  *     @arg GPIO_Remap_PTP_PPS          : Ethernet MAC PPS_PTS output on PB05 (only for Connectivity line devices)
-  *     @arg GPIO_Remap_TIM15            : TIM15 Alternate Function mapping (only for Value line devices)
-  *     @arg GPIO_Remap_TIM16            : TIM16 Alternate Function mapping (only for Value line devices)
-  *     @arg GPIO_Remap_TIM17            : TIM17 Alternate Function mapping (only for Value line devices)
-  *     @arg GPIO_Remap_CEC              : CEC Alternate Function mapping (only for Value line devices)
-  *     @arg GPIO_Remap_TIM1_DMA         : TIM1 DMA requests mapping (only for Value line devices)
-  *     @arg GPIO_Remap_TIM9             : TIM9 Alternate Function mapping (only for XL-density devices)
-  *     @arg GPIO_Remap_TIM10            : TIM10 Alternate Function mapping (only for XL-density devices)
-  *     @arg GPIO_Remap_TIM11            : TIM11 Alternate Function mapping (only for XL-density devices)
-  *     @arg GPIO_Remap_TIM13            : TIM13 Alternate Function mapping (only for High density Value line and XL-density devices)
-  *     @arg GPIO_Remap_TIM14            : TIM14 Alternate Function mapping (only for High density Value line and XL-density devices)
-  *     @arg GPIO_Remap_FSMC_NADV        : FSMC_NADV Alternate Function mapping (only for High density Value line and XL-density devices)
-  *     @arg GPIO_Remap_TIM67_DAC_DMA    : TIM6/TIM7 and DAC DMA requests remapping (only for High density Value line devices)
-  *     @arg GPIO_Remap_TIM12            : TIM12 Alternate Function mapping (only for High density Value line devices)
-  *     @arg GPIO_Remap_MISC             : Miscellaneous Remap (DMA2 Channel5 Position and DAC Trigger remapping, 
-  *                                        only for High density Value line devices)     
-  * @param  NewState: new state of the port pin remapping.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState)
-{
-  uint32_t tmp = 0x00, tmp1 = 0x00, tmpreg = 0x00, tmpmask = 0x00;
-
-  /* Check the parameters */
-  assert_param(IS_GPIO_REMAP(GPIO_Remap));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));  
-  
-  if((GPIO_Remap & 0x80000000) == 0x80000000)
-  {
-    tmpreg = AFIO->MAPR2;
-  }
-  else
-  {
-    tmpreg = AFIO->MAPR;
-  }
-
-  tmpmask = (GPIO_Remap & DBGAFR_POSITION_MASK) >> 0x10;
-  tmp = GPIO_Remap & LSB_MASK;
-
-  if ((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK))
-  {
-    tmpreg &= DBGAFR_SWJCFG_MASK;
-    AFIO->MAPR &= DBGAFR_SWJCFG_MASK;
-  }
-  else if ((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK)
-  {
-    tmp1 = ((uint32_t)0x03) << tmpmask;
-    tmpreg &= ~tmp1;
-    tmpreg |= ~DBGAFR_SWJCFG_MASK;
-  }
-  else
-  {
-    tmpreg &= ~(tmp << ((GPIO_Remap >> 0x15)*0x10));
-    tmpreg |= ~DBGAFR_SWJCFG_MASK;
-  }
-
-  if (NewState != DISABLE)
-  {
-    tmpreg |= (tmp << ((GPIO_Remap >> 0x15)*0x10));
-  }
-
-  if((GPIO_Remap & 0x80000000) == 0x80000000)
-  {
-    AFIO->MAPR2 = tmpreg;
-  }
-  else
-  {
-    AFIO->MAPR = tmpreg;
-  }  
-}
-
-/**
-  * @brief  Selects the GPIO pin used as EXTI Line.
-  * @param  GPIO_PortSource: selects the GPIO port to be used as source for EXTI lines.
-  *   This parameter can be GPIO_PortSourceGPIOx where x can be (A..G).
-  * @param  GPIO_PinSource: specifies the EXTI line to be configured.
-  *   This parameter can be GPIO_PinSourcex where x can be (0..15).
-  * @retval None
-  */
-void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource)
-{
-  uint32_t tmp = 0x00;
-  /* Check the parameters */
-  assert_param(IS_GPIO_EXTI_PORT_SOURCE(GPIO_PortSource));
-  assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource));
-  
-  tmp = ((uint32_t)0x0F) << (0x04 * (GPIO_PinSource & (uint8_t)0x03));
-  AFIO->EXTICR[GPIO_PinSource >> 0x02] &= ~tmp;
-  AFIO->EXTICR[GPIO_PinSource >> 0x02] |= (((uint32_t)GPIO_PortSource) << (0x04 * (GPIO_PinSource & (uint8_t)0x03)));
-}
-
-/**
-  * @brief  Selects the Ethernet media interface.
-  * @note   This function applies only to STM32 Connectivity line devices.  
-  * @param  GPIO_ETH_MediaInterface: specifies the Media Interface mode.
-  *   This parameter can be one of the following values:
-  *     @arg GPIO_ETH_MediaInterface_MII: MII mode
-  *     @arg GPIO_ETH_MediaInterface_RMII: RMII mode    
-  * @retval None
-  */
-void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface) 
-{ 
-  assert_param(IS_GPIO_ETH_MEDIA_INTERFACE(GPIO_ETH_MediaInterface)); 
-
-  /* Configure MII_RMII selection bit */ 
-  *(__IO uint32_t *) MAPR_MII_RMII_SEL_BB = GPIO_ETH_MediaInterface; 
-}
-  
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.c
deleted file mode 100644
index 4ea321c..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.c
+++ /dev/null
@@ -1,1331 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f10x_i2c.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    11-March-2011
-  * @brief   This file provides all the I2C firmware functions.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_rcc.h"
-
-
-/** @addtogroup STM32F10x_StdPeriph_Driver
-  * @{
-  */
-
-/** @defgroup I2C 
-  * @brief I2C driver modules
-  * @{
-  */ 
-
-/** @defgroup I2C_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup I2C_Private_Defines
-  * @{
-  */
-
-/* I2C SPE mask */
-#define CR1_PE_Set              ((uint16_t)0x0001)
-#define CR1_PE_Reset            ((uint16_t)0xFFFE)
-
-/* I2C START mask */
-#define CR1_START_Set           ((uint16_t)0x0100)
-#define CR1_START_Reset         ((uint16_t)0xFEFF)
-
-/* I2C STOP mask */
-#define CR1_STOP_Set            ((uint16_t)0x0200)
-#define CR1_STOP_Reset          ((uint16_t)0xFDFF)
-
-/* I2C ACK mask */
-#define CR1_ACK_Set             ((uint16_t)0x0400)
-#define CR1_ACK_Reset           ((uint16_t)0xFBFF)
-
-/* I2C ENGC mask */
-#define CR1_ENGC_Set            ((uint16_t)0x0040)
-#define CR1_ENGC_Reset          ((uint16_t)0xFFBF)
-
-/* I2C SWRST mask */
-#define CR1_SWRST_Set           ((uint16_t)0x8000)
-#define CR1_SWRST_Reset         ((uint16_t)0x7FFF)
-
-/* I2C PEC mask */
-#define CR1_PEC_Set             ((uint16_t)0x1000)
-#define CR1_PEC_Reset           ((uint16_t)0xEFFF)
-
-/* I2C ENPEC mask */
-#define CR1_ENPEC_Set           ((uint16_t)0x0020)
-#define CR1_ENPEC_Reset         ((uint16_t)0xFFDF)
-
-/* I2C ENARP mask */
-#define CR1_ENARP_Set           ((uint16_t)0x0010)
-#define CR1_ENARP_Reset         ((uint16_t)0xFFEF)
-
-/* I2C NOSTRETCH mask */
-#define CR1_NOSTRETCH_Set       ((uint16_t)0x0080)
-#define CR1_NOSTRETCH_Reset     ((uint16_t)0xFF7F)
-
-/* I2C registers Masks */
-#define CR1_CLEAR_Mask          ((uint16_t)0xFBF5)
-
-/* I2C DMAEN mask */
-#define CR2_DMAEN_Set           ((uint16_t)0x0800)
-#define CR2_DMAEN_Reset         ((uint16_t)0xF7FF)
-
-/* I2C LAST mask */
-#define CR2_LAST_Set            ((uint16_t)0x1000)
-#define CR2_LAST_Reset          ((uint16_t)0xEFFF)
-
-/* I2C FREQ mask */
-#define CR2_FREQ_Reset          ((uint16_t)0xFFC0)
-
-/* I2C ADD0 mask */
-#define OAR1_ADD0_Set           ((uint16_t)0x0001)
-#define OAR1_ADD0_Reset         ((uint16_t)0xFFFE)
-
-/* I2C ENDUAL mask */
-#define OAR2_ENDUAL_Set         ((uint16_t)0x0001)
-#define OAR2_ENDUAL_Reset       ((uint16_t)0xFFFE)
-
-/* I2C ADD2 mask */
-#define OAR2_ADD2_Reset         ((uint16_t)0xFF01)
-
-/* I2C F/S mask */
-#define CCR_FS_Set              ((uint16_t)0x8000)
-
-/* I2C CCR mask */
-#define CCR_CCR_Set             ((uint16_t)0x0FFF)
-
-/* I2C FLAG mask */
-#define FLAG_Mask               ((uint32_t)0x00FFFFFF)
-
-/* I2C Interrupt Enable mask */
-#define ITEN_Mask               ((uint32_t)0x07000000)
-
-/**
-  * @}
-  */
-
-/** @defgroup I2C_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup I2C_Private_Variables
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup I2C_Private_FunctionPrototypes
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup I2C_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Deinitializes the I2Cx peripheral registers to their default reset values.
-  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-  * @retval None
-  */
-void I2C_DeInit(I2C_TypeDef* I2Cx)
-{
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-
-  if (I2Cx == I2C1)
-  {
-    /* Enable I2C1 reset state */
-    RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, ENABLE);
-    /* Release I2C1 from reset state */
-    RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, DISABLE);
-  }
-  else
-  {
-    /* Enable I2C2 reset state */
-    RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, ENABLE);
-    /* Release I2C2 from reset state */
-    RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, DISABLE);
-  }
-}
-
-/**
-  * @brief  Initializes the I2Cx peripheral according to the specified 
-  *   parameters in the I2C_InitStruct.
-  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-  * @param  I2C_InitStruct: pointer to a I2C_InitTypeDef structure that
-  *   contains the configuration information for the specified I2C peripheral.
-  * @retval None
-  */
-void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct)
-{
-  uint16_t tmpreg = 0, freqrange = 0;
-  uint16_t result = 0x04;
-  uint32_t pclk1 = 8000000;
-  RCC_ClocksTypeDef  rcc_clocks;
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-  assert_param(IS_I2C_CLOCK_SPEED(I2C_InitStruct->I2C_ClockSpeed));
-  assert_param(IS_I2C_MODE(I2C_InitStruct->I2C_Mode));
-  assert_param(IS_I2C_DUTY_CYCLE(I2C_InitStruct->I2C_DutyCycle));
-  assert_param(IS_I2C_OWN_ADDRESS1(I2C_InitStruct->I2C_OwnAddress1));
-  assert_param(IS_I2C_ACK_STATE(I2C_InitStruct->I2C_Ack));
-  assert_param(IS_I2C_ACKNOWLEDGE_ADDRESS(I2C_InitStruct->I2C_AcknowledgedAddress));
-
-/*---------------------------- I2Cx CR2 Configuration ------------------------*/
-  /* Get the I2Cx CR2 value */
-  tmpreg = I2Cx->CR2;
-  /* Clear frequency FREQ[5:0] bits */
-  tmpreg &= CR2_FREQ_Reset;
-  /* Get pclk1 frequency value */
-  RCC_GetClocksFreq(&rcc_clocks);
-  pclk1 = rcc_clocks.PCLK1_Frequency;
-  /* Set frequency bits depending on pclk1 value */
-  freqrange = (uint16_t)(pclk1 / 1000000);
-  tmpreg |= freqrange;
-  /* Write to I2Cx CR2 */
-  I2Cx->CR2 = tmpreg;
-
-/*---------------------------- I2Cx CCR Configuration ------------------------*/
-  /* Disable the selected I2C peripheral to configure TRISE */
-  I2Cx->CR1 &= CR1_PE_Reset;
-  /* Reset tmpreg value */
-  /* Clear F/S, DUTY and CCR[11:0] bits */
-  tmpreg = 0;
-
-  /* Configure speed in standard mode */
-  if (I2C_InitStruct->I2C_ClockSpeed <= 100000)
-  {
-    /* Standard mode speed calculate */
-    result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed << 1));
-    /* Test if CCR value is under 0x4*/
-    if (result < 0x04)
-    {
-      /* Set minimum allowed value */
-      result = 0x04;  
-    }
-    /* Set speed value for standard mode */
-    tmpreg |= result;	  
-    /* Set Maximum Rise Time for standard mode */
-    I2Cx->TRISE = freqrange + 1; 
-  }
-  /* Configure speed in fast mode */
-  else /*(I2C_InitStruct->I2C_ClockSpeed <= 400000)*/
-  {
-    if (I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_2)
-    {
-      /* Fast mode speed calculate: Tlow/Thigh = 2 */
-      result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 3));
-    }
-    else /*I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_16_9*/
-    {
-      /* Fast mode speed calculate: Tlow/Thigh = 16/9 */
-      result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 25));
-      /* Set DUTY bit */
-      result |= I2C_DutyCycle_16_9;
-    }
-
-    /* Test if CCR value is under 0x1*/
-    if ((result & CCR_CCR_Set) == 0)
-    {
-      /* Set minimum allowed value */
-      result |= (uint16_t)0x0001;  
-    }
-    /* Set speed value and set F/S bit for fast mode */
-    tmpreg |= (uint16_t)(result | CCR_FS_Set);
-    /* Set Maximum Rise Time for fast mode */
-    I2Cx->TRISE = (uint16_t)(((freqrange * (uint16_t)300) / (uint16_t)1000) + (uint16_t)1);  
-  }
-
-  /* Write to I2Cx CCR */
-  I2Cx->CCR = tmpreg;
-  /* Enable the selected I2C peripheral */
-  I2Cx->CR1 |= CR1_PE_Set;
-
-/*---------------------------- I2Cx CR1 Configuration ------------------------*/
-  /* Get the I2Cx CR1 value */
-  tmpreg = I2Cx->CR1;
-  /* Clear ACK, SMBTYPE and  SMBUS bits */
-  tmpreg &= CR1_CLEAR_Mask;
-  /* Configure I2Cx: mode and acknowledgement */
-  /* Set SMBTYPE and SMBUS bits according to I2C_Mode value */
-  /* Set ACK bit according to I2C_Ack value */
-  tmpreg |= (uint16_t)((uint32_t)I2C_InitStruct->I2C_Mode | I2C_InitStruct->I2C_Ack);
-  /* Write to I2Cx CR1 */
-  I2Cx->CR1 = tmpreg;
-
-/*---------------------------- I2Cx OAR1 Configuration -----------------------*/
-  /* Set I2Cx Own Address1 and acknowledged address */
-  I2Cx->OAR1 = (I2C_InitStruct->I2C_AcknowledgedAddress | I2C_InitStruct->I2C_OwnAddress1);
-}
-
-/**
-  * @brief  Fills each I2C_InitStruct member with its default value.
-  * @param  I2C_InitStruct: pointer to an I2C_InitTypeDef structure which will be initialized.
-  * @retval None
-  */
-void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct)
-{
-/*---------------- Reset I2C init structure parameters values ----------------*/
-  /* initialize the I2C_ClockSpeed member */
-  I2C_InitStruct->I2C_ClockSpeed = 5000;
-  /* Initialize the I2C_Mode member */
-  I2C_InitStruct->I2C_Mode = I2C_Mode_I2C;
-  /* Initialize the I2C_DutyCycle member */
-  I2C_InitStruct->I2C_DutyCycle = I2C_DutyCycle_2;
-  /* Initialize the I2C_OwnAddress1 member */
-  I2C_InitStruct->I2C_OwnAddress1 = 0;
-  /* Initialize the I2C_Ack member */
-  I2C_InitStruct->I2C_Ack = I2C_Ack_Disable;
-  /* Initialize the I2C_AcknowledgedAddress member */
-  I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;
-}
-
-/**
-  * @brief  Enables or disables the specified I2C peripheral.
-  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-  * @param  NewState: new state of the I2Cx peripheral. 
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  if (NewState != DISABLE)
-  {
-    /* Enable the selected I2C peripheral */
-    I2Cx->CR1 |= CR1_PE_Set;
-  }
-  else
-  {
-    /* Disable the selected I2C peripheral */
-    I2Cx->CR1 &= CR1_PE_Reset;
-  }
-}
-
-/**
-  * @brief  Enables or disables the specified I2C DMA requests.
-  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-  * @param  NewState: new state of the I2C DMA transfer.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  if (NewState != DISABLE)
-  {
-    /* Enable the selected I2C DMA requests */
-    I2Cx->CR2 |= CR2_DMAEN_Set;
-  }
-  else
-  {
-    /* Disable the selected I2C DMA requests */
-    I2Cx->CR2 &= CR2_DMAEN_Reset;
-  }
-}
-
-/**
-  * @brief  Specifies if the next DMA transfer will be the last one.
-  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-  * @param  NewState: new state of the I2C DMA last transfer.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  if (NewState != DISABLE)
-  {
-    /* Next DMA transfer is the last transfer */
-    I2Cx->CR2 |= CR2_LAST_Set;
-  }
-  else
-  {
-    /* Next DMA transfer is not the last transfer */
-    I2Cx->CR2 &= CR2_LAST_Reset;
-  }
-}
-
-/**
-  * @brief  Generates I2Cx communication START condition.
-  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-  * @param  NewState: new state of the I2C START condition generation.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None.
-  */
-void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  if (NewState != DISABLE)
-  {
-    /* Generate a START condition */
-    I2Cx->CR1 |= CR1_START_Set;
-  }
-  else
-  {
-    /* Disable the START condition generation */
-    I2Cx->CR1 &= CR1_START_Reset;
-  }
-}
-
-/**
-  * @brief  Generates I2Cx communication STOP condition.
-  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-  * @param  NewState: new state of the I2C STOP condition generation.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None.
-  */
-void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  if (NewState != DISABLE)
-  {
-    /* Generate a STOP condition */
-    I2Cx->CR1 |= CR1_STOP_Set;
-  }
-  else
-  {
-    /* Disable the STOP condition generation */
-    I2Cx->CR1 &= CR1_STOP_Reset;
-  }
-}
-
-/**
-  * @brief  Enables or disables the specified I2C acknowledge feature.
-  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-  * @param  NewState: new state of the I2C Acknowledgement.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None.
-  */
-void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  if (NewState != DISABLE)
-  {
-    /* Enable the acknowledgement */
-    I2Cx->CR1 |= CR1_ACK_Set;
-  }
-  else
-  {
-    /* Disable the acknowledgement */
-    I2Cx->CR1 &= CR1_ACK_Reset;
-  }
-}
-
-/**
-  * @brief  Configures the specified I2C own address2.
-  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-  * @param  Address: specifies the 7bit I2C own address2.
-  * @retval None.
-  */
-void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address)
-{
-  uint16_t tmpreg = 0;
-
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-
-  /* Get the old register value */
-  tmpreg = I2Cx->OAR2;
-
-  /* Reset I2Cx Own address2 bit [7:1] */
-  tmpreg &= OAR2_ADD2_Reset;
-
-  /* Set I2Cx Own address2 */
-  tmpreg |= (uint16_t)((uint16_t)Address & (uint16_t)0x00FE);
-
-  /* Store the new register value */
-  I2Cx->OAR2 = tmpreg;
-}
-
-/**
-  * @brief  Enables or disables the specified I2C dual addressing mode.
-  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-  * @param  NewState: new state of the I2C dual addressing mode.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  if (NewState != DISABLE)
-  {
-    /* Enable dual addressing mode */
-    I2Cx->OAR2 |= OAR2_ENDUAL_Set;
-  }
-  else
-  {
-    /* Disable dual addressing mode */
-    I2Cx->OAR2 &= OAR2_ENDUAL_Reset;
-  }
-}
-
-/**
-  * @brief  Enables or disables the specified I2C general call feature.
-  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-  * @param  NewState: new state of the I2C General call.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  if (NewState != DISABLE)
-  {
-    /* Enable generall call */
-    I2Cx->CR1 |= CR1_ENGC_Set;
-  }
-  else
-  {
-    /* Disable generall call */
-    I2Cx->CR1 &= CR1_ENGC_Reset;
-  }
-}
-
-/**
-  * @brief  Enables or disables the specified I2C interrupts.
-  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-  * @param  I2C_IT: specifies the I2C interrupts sources to be enabled or disabled. 
-  *   This parameter can be any combination of the following values:
-  *     @arg I2C_IT_BUF: Buffer interrupt mask
-  *     @arg I2C_IT_EVT: Event interrupt mask
-  *     @arg I2C_IT_ERR: Error interrupt mask
-  * @param  NewState: new state of the specified I2C interrupts.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  assert_param(IS_I2C_CONFIG_IT(I2C_IT));
-  
-  if (NewState != DISABLE)
-  {
-    /* Enable the selected I2C interrupts */
-    I2Cx->CR2 |= I2C_IT;
-  }
-  else
-  {
-    /* Disable the selected I2C interrupts */
-    I2Cx->CR2 &= (uint16_t)~I2C_IT;
-  }
-}
-
-/**
-  * @brief  Sends a data byte through the I2Cx peripheral.
-  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-  * @param  Data: Byte to be transmitted..
-  * @retval None
-  */
-void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data)
-{
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-  /* Write in the DR register the data to be sent */
-  I2Cx->DR = Data;
-}
-
-/**
-  * @brief  Returns the most recent received data by the I2Cx peripheral.
-  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-  * @retval The value of the received data.
-  */
-uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx)
-{
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-  /* Return the data in the DR register */
-  return (uint8_t)I2Cx->DR;
-}
-
-/**
-  * @brief  Transmits the address byte to select the slave device.
-  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-  * @param  Address: specifies the slave address which will be transmitted
-  * @param  I2C_Direction: specifies whether the I2C device will be a
-  *   Transmitter or a Receiver. This parameter can be one of the following values
-  *     @arg I2C_Direction_Transmitter: Transmitter mode
-  *     @arg I2C_Direction_Receiver: Receiver mode
-  * @retval None.
-  */
-void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction)
-{
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-  assert_param(IS_I2C_DIRECTION(I2C_Direction));
-  /* Test on the direction to set/reset the read/write bit */
-  if (I2C_Direction != I2C_Direction_Transmitter)
-  {
-    /* Set the address bit0 for read */
-    Address |= OAR1_ADD0_Set;
-  }
-  else
-  {
-    /* Reset the address bit0 for write */
-    Address &= OAR1_ADD0_Reset;
-  }
-  /* Send the address */
-  I2Cx->DR = Address;
-}
-
-/**
-  * @brief  Reads the specified I2C register and returns its value.
-  * @param  I2C_Register: specifies the register to read.
-  *   This parameter can be one of the following values:
-  *     @arg I2C_Register_CR1:  CR1 register.
-  *     @arg I2C_Register_CR2:   CR2 register.
-  *     @arg I2C_Register_OAR1:  OAR1 register.
-  *     @arg I2C_Register_OAR2:  OAR2 register.
-  *     @arg I2C_Register_DR:    DR register.
-  *     @arg I2C_Register_SR1:   SR1 register.
-  *     @arg I2C_Register_SR2:   SR2 register.
-  *     @arg I2C_Register_CCR:   CCR register.
-  *     @arg I2C_Register_TRISE: TRISE register.
-  * @retval The value of the read register.
-  */
-uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register)
-{
-  __IO uint32_t tmp = 0;
-
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-  assert_param(IS_I2C_REGISTER(I2C_Register));
-
-  tmp = (uint32_t) I2Cx;
-  tmp += I2C_Register;
-
-  /* Return the selected register value */
-  return (*(__IO uint16_t *) tmp);
-}
-
-/**
-  * @brief  Enables or disables the specified I2C software reset.
-  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-  * @param  NewState: new state of the I2C software reset.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  if (NewState != DISABLE)
-  {
-    /* Peripheral under reset */
-    I2Cx->CR1 |= CR1_SWRST_Set;
-  }
-  else
-  {
-    /* Peripheral not under reset */
-    I2Cx->CR1 &= CR1_SWRST_Reset;
-  }
-}
-
-/**
-  * @brief  Selects the specified I2C NACK position in master receiver mode.
-  *         This function is useful in I2C Master Receiver mode when the number
-  *         of data to be received is equal to 2. In this case, this function 
-  *         should be called (with parameter I2C_NACKPosition_Next) before data 
-  *         reception starts,as described in the 2-byte reception procedure 
-  *         recommended in Reference Manual in Section: Master receiver.                
-  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-  * @param  I2C_NACKPosition: specifies the NACK position. 
-  *   This parameter can be one of the following values:
-  *     @arg I2C_NACKPosition_Next: indicates that the next byte will be the last
-  *          received byte.  
-  *     @arg I2C_NACKPosition_Current: indicates that current byte is the last 
-  *          received byte.
-  *            
-  * @note    This function configures the same bit (POS) as I2C_PECPositionConfig() 
-  *          but is intended to be used in I2C mode while I2C_PECPositionConfig() 
-  *          is intended to used in SMBUS mode. 
-  *            
-  * @retval None
-  */
-void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition)
-{
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-  assert_param(IS_I2C_NACK_POSITION(I2C_NACKPosition));
-  
-  /* Check the input parameter */
-  if (I2C_NACKPosition == I2C_NACKPosition_Next)
-  {
-    /* Next byte in shift register is the last received byte */
-    I2Cx->CR1 |= I2C_NACKPosition_Next;
-  }
-  else
-  {
-    /* Current byte in shift register is the last received byte */
-    I2Cx->CR1 &= I2C_NACKPosition_Current;
-  }
-}
-
-/**
-  * @brief  Drives the SMBusAlert pin high or low for the specified I2C.
-  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-  * @param  I2C_SMBusAlert: specifies SMBAlert pin level. 
-  *   This parameter can be one of the following values:
-  *     @arg I2C_SMBusAlert_Low: SMBAlert pin driven low
-  *     @arg I2C_SMBusAlert_High: SMBAlert pin driven high
-  * @retval None
-  */
-void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert)
-{
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-  assert_param(IS_I2C_SMBUS_ALERT(I2C_SMBusAlert));
-  if (I2C_SMBusAlert == I2C_SMBusAlert_Low)
-  {
-    /* Drive the SMBusAlert pin Low */
-    I2Cx->CR1 |= I2C_SMBusAlert_Low;
-  }
-  else
-  {
-    /* Drive the SMBusAlert pin High  */
-    I2Cx->CR1 &= I2C_SMBusAlert_High;
-  }
-}
-
-/**
-  * @brief  Enables or disables the specified I2C PEC transfer.
-  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-  * @param  NewState: new state of the I2C PEC transmission.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  if (NewState != DISABLE)
-  {
-    /* Enable the selected I2C PEC transmission */
-    I2Cx->CR1 |= CR1_PEC_Set;
-  }
-  else
-  {
-    /* Disable the selected I2C PEC transmission */
-    I2Cx->CR1 &= CR1_PEC_Reset;
-  }
-}
-
-/**
-  * @brief  Selects the specified I2C PEC position.
-  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-  * @param  I2C_PECPosition: specifies the PEC position. 
-  *   This parameter can be one of the following values:
-  *     @arg I2C_PECPosition_Next: indicates that the next byte is PEC
-  *     @arg I2C_PECPosition_Current: indicates that current byte is PEC
-  *       
-  * @note    This function configures the same bit (POS) as I2C_NACKPositionConfig()
-  *          but is intended to be used in SMBUS mode while I2C_NACKPositionConfig() 
-  *          is intended to used in I2C mode.
-  *               
-  * @retval None
-  */
-void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition)
-{
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-  assert_param(IS_I2C_PEC_POSITION(I2C_PECPosition));
-  if (I2C_PECPosition == I2C_PECPosition_Next)
-  {
-    /* Next byte in shift register is PEC */
-    I2Cx->CR1 |= I2C_PECPosition_Next;
-  }
-  else
-  {
-    /* Current byte in shift register is PEC */
-    I2Cx->CR1 &= I2C_PECPosition_Current;
-  }
-}
-
-/**
-  * @brief  Enables or disables the PEC value calculation of the transferred bytes.
-  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-  * @param  NewState: new state of the I2Cx PEC value calculation.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  if (NewState != DISABLE)
-  {
-    /* Enable the selected I2C PEC calculation */
-    I2Cx->CR1 |= CR1_ENPEC_Set;
-  }
-  else
-  {
-    /* Disable the selected I2C PEC calculation */
-    I2Cx->CR1 &= CR1_ENPEC_Reset;
-  }
-}
-
-/**
-  * @brief  Returns the PEC value for the specified I2C.
-  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-  * @retval The PEC value.
-  */
-uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx)
-{
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-  /* Return the selected I2C PEC value */
-  return ((I2Cx->SR2) >> 8);
-}
-
-/**
-  * @brief  Enables or disables the specified I2C ARP.
-  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-  * @param  NewState: new state of the I2Cx ARP. 
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  if (NewState != DISABLE)
-  {
-    /* Enable the selected I2C ARP */
-    I2Cx->CR1 |= CR1_ENARP_Set;
-  }
-  else
-  {
-    /* Disable the selected I2C ARP */
-    I2Cx->CR1 &= CR1_ENARP_Reset;
-  }
-}
-
-/**
-  * @brief  Enables or disables the specified I2C Clock stretching.
-  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-  * @param  NewState: new state of the I2Cx Clock stretching.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  if (NewState == DISABLE)
-  {
-    /* Enable the selected I2C Clock stretching */
-    I2Cx->CR1 |= CR1_NOSTRETCH_Set;
-  }
-  else
-  {
-    /* Disable the selected I2C Clock stretching */
-    I2Cx->CR1 &= CR1_NOSTRETCH_Reset;
-  }
-}
-
-/**
-  * @brief  Selects the specified I2C fast mode duty cycle.
-  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-  * @param  I2C_DutyCycle: specifies the fast mode duty cycle.
-  *   This parameter can be one of the following values:
-  *     @arg I2C_DutyCycle_2: I2C fast mode Tlow/Thigh = 2
-  *     @arg I2C_DutyCycle_16_9: I2C fast mode Tlow/Thigh = 16/9
-  * @retval None
-  */
-void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle)
-{
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-  assert_param(IS_I2C_DUTY_CYCLE(I2C_DutyCycle));
-  if (I2C_DutyCycle != I2C_DutyCycle_16_9)
-  {
-    /* I2C fast mode Tlow/Thigh=2 */
-    I2Cx->CCR &= I2C_DutyCycle_2;
-  }
-  else
-  {
-    /* I2C fast mode Tlow/Thigh=16/9 */
-    I2Cx->CCR |= I2C_DutyCycle_16_9;
-  }
-}
-
-
-
-/**
- * @brief
- ****************************************************************************************
- *
- *                         I2C State Monitoring Functions
- *                       
- ****************************************************************************************   
- * This I2C driver provides three different ways for I2C state monitoring
- *  depending on the application requirements and constraints:
- *        
- *  
- * 1) Basic state monitoring:
- *    Using I2C_CheckEvent() function:
- *    It compares the status registers (SR1 and SR2) content to a given event
- *    (can be the combination of one or more flags).
- *    It returns SUCCESS if the current status includes the given flags 
- *    and returns ERROR if one or more flags are missing in the current status.
- *    - When to use:
- *      - This function is suitable for most applications as well as for startup 
- *      activity since the events are fully described in the product reference manual 
- *      (RM0008).
- *      - It is also suitable for users who need to define their own events.
- *    - Limitations:
- *      - If an error occurs (ie. error flags are set besides to the monitored flags),
- *        the I2C_CheckEvent() function may return SUCCESS despite the communication
- *        hold or corrupted real state. 
- *        In this case, it is advised to use error interrupts to monitor the error
- *        events and handle them in the interrupt IRQ handler.
- *        
- *        @note 
- *        For error management, it is advised to use the following functions:
- *          - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR).
- *          - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs.
- *            Where x is the peripheral instance (I2C1, I2C2 ...)
- *          - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into I2Cx_ER_IRQHandler() 
- *            in order to determine which error occured.
- *          - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd()
- *            and/or I2C_GenerateStop() in order to clear the error flag and source,
- *            and return to correct communication status.
- *            
- *
- *  2) Advanced state monitoring:
- *     Using the function I2C_GetLastEvent() which returns the image of both status 
- *     registers in a single word (uint32_t) (Status Register 2 value is shifted left 
- *     by 16 bits and concatenated to Status Register 1).
- *     - When to use:
- *       - This function is suitable for the same applications above but it allows to
- *         overcome the mentioned limitation of I2C_GetFlagStatus() function.
- *         The returned value could be compared to events already defined in the 
- *         library (stm32f10x_i2c.h) or to custom values defined by user.
- *       - This function is suitable when multiple flags are monitored at the same time.
- *       - At the opposite of I2C_CheckEvent() function, this function allows user to
- *         choose when an event is accepted (when all events flags are set and no 
- *         other flags are set or just when the needed flags are set like 
- *         I2C_CheckEvent() function).
- *     - Limitations:
- *       - User may need to define his own events.
- *       - Same remark concerning the error management is applicable for this 
- *         function if user decides to check only regular communication flags (and 
- *         ignores error flags).
- *     
- *
- *  3) Flag-based state monitoring:
- *     Using the function I2C_GetFlagStatus() which simply returns the status of 
- *     one single flag (ie. I2C_FLAG_RXNE ...). 
- *     - When to use:
- *        - This function could be used for specific applications or in debug phase.
- *        - It is suitable when only one flag checking is needed (most I2C events 
- *          are monitored through multiple flags).
- *     - Limitations: 
- *        - When calling this function, the Status register is accessed. Some flags are
- *          cleared when the status register is accessed. So checking the status
- *          of one Flag, may clear other ones.
- *        - Function may need to be called twice or more in order to monitor one 
- *          single event.
- *
- *  For detailed description of Events, please refer to section I2C_Events in 
- *  stm32f10x_i2c.h file.
- *  
- */
-
-/**
- * 
- *  1) Basic state monitoring
- *******************************************************************************
- */
-
-/**
-  * @brief  Checks whether the last I2Cx Event is equal to the one passed
-  *   as parameter.
-  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-  * @param  I2C_EVENT: specifies the event to be checked. 
-  *   This parameter can be one of the following values:
-  *     @arg I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED           : EV1
-  *     @arg I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED              : EV1
-  *     @arg I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED     : EV1
-  *     @arg I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED        : EV1
-  *     @arg I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED            : EV1
-  *     @arg I2C_EVENT_SLAVE_BYTE_RECEIVED                         : EV2
-  *     @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF)      : EV2
-  *     @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL)    : EV2
-  *     @arg I2C_EVENT_SLAVE_BYTE_TRANSMITTED                      : EV3
-  *     @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF)   : EV3
-  *     @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL) : EV3
-  *     @arg I2C_EVENT_SLAVE_ACK_FAILURE                           : EV3_2
-  *     @arg I2C_EVENT_SLAVE_STOP_DETECTED                         : EV4
-  *     @arg I2C_EVENT_MASTER_MODE_SELECT                          : EV5
-  *     @arg I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED            : EV6     
-  *     @arg I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED               : EV6
-  *     @arg I2C_EVENT_MASTER_BYTE_RECEIVED                        : EV7
-  *     @arg I2C_EVENT_MASTER_BYTE_TRANSMITTING                    : EV8
-  *     @arg I2C_EVENT_MASTER_BYTE_TRANSMITTED                     : EV8_2
-  *     @arg I2C_EVENT_MASTER_MODE_ADDRESS10                       : EV9
-  *     
-  * @note: For detailed description of Events, please refer to section 
-  *    I2C_Events in stm32f10x_i2c.h file.
-  *    
-  * @retval An ErrorStatus enumeration value:
-  * - SUCCESS: Last event is equal to the I2C_EVENT
-  * - ERROR: Last event is different from the I2C_EVENT
-  */
-ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT)
-{
-  uint32_t lastevent = 0;
-  uint32_t flag1 = 0, flag2 = 0;
-  ErrorStatus status = ERROR;
-
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-  assert_param(IS_I2C_EVENT(I2C_EVENT));
-
-  /* Read the I2Cx status register */
-  flag1 = I2Cx->SR1;
-  flag2 = I2Cx->SR2;
-  flag2 = flag2 << 16;
-
-  /* Get the last event value from I2C status register */
-  lastevent = (flag1 | flag2) & FLAG_Mask;
-
-  /* Check whether the last event contains the I2C_EVENT */
-  if ((lastevent & I2C_EVENT) == I2C_EVENT)
-  {
-    /* SUCCESS: last event is equal to I2C_EVENT */
-    status = SUCCESS;
-  }
-  else
-  {
-    /* ERROR: last event is different from I2C_EVENT */
-    status = ERROR;
-  }
-  /* Return status */
-  return status;
-}
-
-/**
- * 
- *  2) Advanced state monitoring
- *******************************************************************************
- */
-
-/**
-  * @brief  Returns the last I2Cx Event.
-  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-  *     
-  * @note: For detailed description of Events, please refer to section 
-  *    I2C_Events in stm32f10x_i2c.h file.
-  *    
-  * @retval The last event
-  */
-uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx)
-{
-  uint32_t lastevent = 0;
-  uint32_t flag1 = 0, flag2 = 0;
-
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-
-  /* Read the I2Cx status register */
-  flag1 = I2Cx->SR1;
-  flag2 = I2Cx->SR2;
-  flag2 = flag2 << 16;
-
-  /* Get the last event value from I2C status register */
-  lastevent = (flag1 | flag2) & FLAG_Mask;
-
-  /* Return status */
-  return lastevent;
-}
-
-/**
- * 
- *  3) Flag-based state monitoring
- *******************************************************************************
- */
-
-/**
-  * @brief  Checks whether the specified I2C flag is set or not.
-  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-  * @param  I2C_FLAG: specifies the flag to check. 
-  *   This parameter can be one of the following values:
-  *     @arg I2C_FLAG_DUALF: Dual flag (Slave mode)
-  *     @arg I2C_FLAG_SMBHOST: SMBus host header (Slave mode)
-  *     @arg I2C_FLAG_SMBDEFAULT: SMBus default header (Slave mode)
-  *     @arg I2C_FLAG_GENCALL: General call header flag (Slave mode)
-  *     @arg I2C_FLAG_TRA: Transmitter/Receiver flag
-  *     @arg I2C_FLAG_BUSY: Bus busy flag
-  *     @arg I2C_FLAG_MSL: Master/Slave flag
-  *     @arg I2C_FLAG_SMBALERT: SMBus Alert flag
-  *     @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
-  *     @arg I2C_FLAG_PECERR: PEC error in reception flag
-  *     @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)
-  *     @arg I2C_FLAG_AF: Acknowledge failure flag
-  *     @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode)
-  *     @arg I2C_FLAG_BERR: Bus error flag
-  *     @arg I2C_FLAG_TXE: Data register empty flag (Transmitter)
-  *     @arg I2C_FLAG_RXNE: Data register not empty (Receiver) flag
-  *     @arg I2C_FLAG_STOPF: Stop detection flag (Slave mode)
-  *     @arg I2C_FLAG_ADD10: 10-bit header sent flag (Master mode)
-  *     @arg I2C_FLAG_BTF: Byte transfer finished flag
-  *     @arg I2C_FLAG_ADDR: Address sent flag (Master mode) "ADSL"
-  *   Address matched flag (Slave mode)"ENDA"
-  *     @arg I2C_FLAG_SB: Start bit flag (Master mode)
-  * @retval The new state of I2C_FLAG (SET or RESET).
-  */
-FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG)
-{
-  FlagStatus bitstatus = RESET;
-  __IO uint32_t i2creg = 0, i2cxbase = 0;
-
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-  assert_param(IS_I2C_GET_FLAG(I2C_FLAG));
-
-  /* Get the I2Cx peripheral base address */
-  i2cxbase = (uint32_t)I2Cx;
-  
-  /* Read flag register index */
-  i2creg = I2C_FLAG >> 28;
-  
-  /* Get bit[23:0] of the flag */
-  I2C_FLAG &= FLAG_Mask;
-  
-  if(i2creg != 0)
-  {
-    /* Get the I2Cx SR1 register address */
-    i2cxbase += 0x14;
-  }
-  else
-  {
-    /* Flag in I2Cx SR2 Register */
-    I2C_FLAG = (uint32_t)(I2C_FLAG >> 16);
-    /* Get the I2Cx SR2 register address */
-    i2cxbase += 0x18;
-  }
-  
-  if(((*(__IO uint32_t *)i2cxbase) & I2C_FLAG) != (uint32_t)RESET)
-  {
-    /* I2C_FLAG is set */
-    bitstatus = SET;
-  }
-  else
-  {
-    /* I2C_FLAG is reset */
-    bitstatus = RESET;
-  }
-  
-  /* Return the I2C_FLAG status */
-  return  bitstatus;
-}
-
-
-
-/**
-  * @brief  Clears the I2Cx's pending flags.
-  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-  * @param  I2C_FLAG: specifies the flag to clear. 
-  *   This parameter can be any combination of the following values:
-  *     @arg I2C_FLAG_SMBALERT: SMBus Alert flag
-  *     @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
-  *     @arg I2C_FLAG_PECERR: PEC error in reception flag
-  *     @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)
-  *     @arg I2C_FLAG_AF: Acknowledge failure flag
-  *     @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode)
-  *     @arg I2C_FLAG_BERR: Bus error flag
-  *   
-  * @note
-  *   - STOPF (STOP detection) is cleared by software sequence: a read operation 
-  *     to I2C_SR1 register (I2C_GetFlagStatus()) followed by a write operation 
-  *     to I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral).
-  *   - ADD10 (10-bit header sent) is cleared by software sequence: a read 
-  *     operation to I2C_SR1 (I2C_GetFlagStatus()) followed by writing the 
-  *     second byte of the address in DR register.
-  *   - BTF (Byte Transfer Finished) is cleared by software sequence: a read 
-  *     operation to I2C_SR1 register (I2C_GetFlagStatus()) followed by a 
-  *     read/write to I2C_DR register (I2C_SendData()).
-  *   - ADDR (Address sent) is cleared by software sequence: a read operation to 
-  *     I2C_SR1 register (I2C_GetFlagStatus()) followed by a read operation to 
-  *     I2C_SR2 register ((void)(I2Cx->SR2)).
-  *   - SB (Start Bit) is cleared software sequence: a read operation to I2C_SR1
-  *     register (I2C_GetFlagStatus()) followed by a write operation to I2C_DR
-  *     register  (I2C_SendData()).
-  * @retval None
-  */
-void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG)
-{
-  uint32_t flagpos = 0;
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-  assert_param(IS_I2C_CLEAR_FLAG(I2C_FLAG));
-  /* Get the I2C flag position */
-  flagpos = I2C_FLAG & FLAG_Mask;
-  /* Clear the selected I2C flag */
-  I2Cx->SR1 = (uint16_t)~flagpos;
-}
-
-/**
-  * @brief  Checks whether the specified I2C interrupt has occurred or not.
-  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-  * @param  I2C_IT: specifies the interrupt source to check. 
-  *   This parameter can be one of the following values:
-  *     @arg I2C_IT_SMBALERT: SMBus Alert flag
-  *     @arg I2C_IT_TIMEOUT: Timeout or Tlow error flag
-  *     @arg I2C_IT_PECERR: PEC error in reception flag
-  *     @arg I2C_IT_OVR: Overrun/Underrun flag (Slave mode)
-  *     @arg I2C_IT_AF: Acknowledge failure flag
-  *     @arg I2C_IT_ARLO: Arbitration lost flag (Master mode)
-  *     @arg I2C_IT_BERR: Bus error flag
-  *     @arg I2C_IT_TXE: Data register empty flag (Transmitter)
-  *     @arg I2C_IT_RXNE: Data register not empty (Receiver) flag
-  *     @arg I2C_IT_STOPF: Stop detection flag (Slave mode)
-  *     @arg I2C_IT_ADD10: 10-bit header sent flag (Master mode)
-  *     @arg I2C_IT_BTF: Byte transfer finished flag
-  *     @arg I2C_IT_ADDR: Address sent flag (Master mode) "ADSL"
-  *                       Address matched flag (Slave mode)"ENDAD"
-  *     @arg I2C_IT_SB: Start bit flag (Master mode)
-  * @retval The new state of I2C_IT (SET or RESET).
-  */
-ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT)
-{
-  ITStatus bitstatus = RESET;
-  uint32_t enablestatus = 0;
-
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-  assert_param(IS_I2C_GET_IT(I2C_IT));
-
-  /* Check if the interrupt source is enabled or not */
-  enablestatus = (uint32_t)(((I2C_IT & ITEN_Mask) >> 16) & (I2Cx->CR2)) ;
-  
-  /* Get bit[23:0] of the flag */
-  I2C_IT &= FLAG_Mask;
-
-  /* Check the status of the specified I2C flag */
-  if (((I2Cx->SR1 & I2C_IT) != (uint32_t)RESET) && enablestatus)
-  {
-    /* I2C_IT is set */
-    bitstatus = SET;
-  }
-  else
-  {
-    /* I2C_IT is reset */
-    bitstatus = RESET;
-  }
-  /* Return the I2C_IT status */
-  return  bitstatus;
-}
-
-/**
-  * @brief  Clears the I2Cx’s interrupt pending bits.
-  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-  * @param  I2C_IT: specifies the interrupt pending bit to clear. 
-  *   This parameter can be any combination of the following values:
-  *     @arg I2C_IT_SMBALERT: SMBus Alert interrupt
-  *     @arg I2C_IT_TIMEOUT: Timeout or Tlow error interrupt
-  *     @arg I2C_IT_PECERR: PEC error in reception  interrupt
-  *     @arg I2C_IT_OVR: Overrun/Underrun interrupt (Slave mode)
-  *     @arg I2C_IT_AF: Acknowledge failure interrupt
-  *     @arg I2C_IT_ARLO: Arbitration lost interrupt (Master mode)
-  *     @arg I2C_IT_BERR: Bus error interrupt
-  *   
-  * @note
-  *   - STOPF (STOP detection) is cleared by software sequence: a read operation 
-  *     to I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to 
-  *     I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral).
-  *   - ADD10 (10-bit header sent) is cleared by software sequence: a read 
-  *     operation to I2C_SR1 (I2C_GetITStatus()) followed by writing the second 
-  *     byte of the address in I2C_DR register.
-  *   - BTF (Byte Transfer Finished) is cleared by software sequence: a read 
-  *     operation to I2C_SR1 register (I2C_GetITStatus()) followed by a 
-  *     read/write to I2C_DR register (I2C_SendData()).
-  *   - ADDR (Address sent) is cleared by software sequence: a read operation to 
-  *     I2C_SR1 register (I2C_GetITStatus()) followed by a read operation to 
-  *     I2C_SR2 register ((void)(I2Cx->SR2)).
-  *   - SB (Start Bit) is cleared by software sequence: a read operation to 
-  *     I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to 
-  *     I2C_DR register (I2C_SendData()).
-  * @retval None
-  */
-void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT)
-{
-  uint32_t flagpos = 0;
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-  assert_param(IS_I2C_CLEAR_IT(I2C_IT));
-  /* Get the I2C flag position */
-  flagpos = I2C_IT & FLAG_Mask;
-  /* Clear the selected I2C flag */
-  I2Cx->SR1 = (uint16_t)~flagpos;
-}
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_iwdg.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_iwdg.c
deleted file mode 100644
index c7cbf7e..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_iwdg.c
+++ /dev/null
@@ -1,190 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f10x_iwdg.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    11-March-2011
-  * @brief   This file provides all the IWDG firmware functions.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_iwdg.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Driver
-  * @{
-  */
-
-/** @defgroup IWDG 
-  * @brief IWDG driver modules
-  * @{
-  */ 
-
-/** @defgroup IWDG_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup IWDG_Private_Defines
-  * @{
-  */ 
-
-/* ---------------------- IWDG registers bit mask ----------------------------*/
-
-/* KR register bit mask */
-#define KR_KEY_Reload    ((uint16_t)0xAAAA)
-#define KR_KEY_Enable    ((uint16_t)0xCCCC)
-
-/**
-  * @}
-  */ 
-
-/** @defgroup IWDG_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup IWDG_Private_Variables
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup IWDG_Private_FunctionPrototypes
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup IWDG_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Enables or disables write access to IWDG_PR and IWDG_RLR registers.
-  * @param  IWDG_WriteAccess: new state of write access to IWDG_PR and IWDG_RLR registers.
-  *   This parameter can be one of the following values:
-  *     @arg IWDG_WriteAccess_Enable: Enable write access to IWDG_PR and IWDG_RLR registers
-  *     @arg IWDG_WriteAccess_Disable: Disable write access to IWDG_PR and IWDG_RLR registers
-  * @retval None
-  */
-void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess)
-{
-  /* Check the parameters */
-  assert_param(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess));
-  IWDG->KR = IWDG_WriteAccess;
-}
-
-/**
-  * @brief  Sets IWDG Prescaler value.
-  * @param  IWDG_Prescaler: specifies the IWDG Prescaler value.
-  *   This parameter can be one of the following values:
-  *     @arg IWDG_Prescaler_4: IWDG prescaler set to 4
-  *     @arg IWDG_Prescaler_8: IWDG prescaler set to 8
-  *     @arg IWDG_Prescaler_16: IWDG prescaler set to 16
-  *     @arg IWDG_Prescaler_32: IWDG prescaler set to 32
-  *     @arg IWDG_Prescaler_64: IWDG prescaler set to 64
-  *     @arg IWDG_Prescaler_128: IWDG prescaler set to 128
-  *     @arg IWDG_Prescaler_256: IWDG prescaler set to 256
-  * @retval None
-  */
-void IWDG_SetPrescaler(uint8_t IWDG_Prescaler)
-{
-  /* Check the parameters */
-  assert_param(IS_IWDG_PRESCALER(IWDG_Prescaler));
-  IWDG->PR = IWDG_Prescaler;
-}
-
-/**
-  * @brief  Sets IWDG Reload value.
-  * @param  Reload: specifies the IWDG Reload value.
-  *   This parameter must be a number between 0 and 0x0FFF.
-  * @retval None
-  */
-void IWDG_SetReload(uint16_t Reload)
-{
-  /* Check the parameters */
-  assert_param(IS_IWDG_RELOAD(Reload));
-  IWDG->RLR = Reload;
-}
-
-/**
-  * @brief  Reloads IWDG counter with value defined in the reload register
-  *   (write access to IWDG_PR and IWDG_RLR registers disabled).
-  * @param  None
-  * @retval None
-  */
-void IWDG_ReloadCounter(void)
-{
-  IWDG->KR = KR_KEY_Reload;
-}
-
-/**
-  * @brief  Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled).
-  * @param  None
-  * @retval None
-  */
-void IWDG_Enable(void)
-{
-  IWDG->KR = KR_KEY_Enable;
-}
-
-/**
-  * @brief  Checks whether the specified IWDG flag is set or not.
-  * @param  IWDG_FLAG: specifies the flag to check.
-  *   This parameter can be one of the following values:
-  *     @arg IWDG_FLAG_PVU: Prescaler Value Update on going
-  *     @arg IWDG_FLAG_RVU: Reload Value Update on going
-  * @retval The new state of IWDG_FLAG (SET or RESET).
-  */
-FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG)
-{
-  FlagStatus bitstatus = RESET;
-  /* Check the parameters */
-  assert_param(IS_IWDG_FLAG(IWDG_FLAG));
-  if ((IWDG->SR & IWDG_FLAG) != (uint32_t)RESET)
-  {
-    bitstatus = SET;
-  }
-  else
-  {
-    bitstatus = RESET;
-  }
-  /* Return the flag status */
-  return bitstatus;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_pwr.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_pwr.c
deleted file mode 100644
index a5a5c57..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_pwr.c
+++ /dev/null
@@ -1,307 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f10x_pwr.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    11-March-2011
-  * @brief   This file provides all the PWR firmware functions.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_pwr.h"
-#include "stm32f10x_rcc.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Driver
-  * @{
-  */
-
-/** @defgroup PWR 
-  * @brief PWR driver modules
-  * @{
-  */ 
-
-/** @defgroup PWR_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup PWR_Private_Defines
-  * @{
-  */
-
-/* --------- PWR registers bit address in the alias region ---------- */
-#define PWR_OFFSET               (PWR_BASE - PERIPH_BASE)
-
-/* --- CR Register ---*/
-
-/* Alias word address of DBP bit */
-#define CR_OFFSET                (PWR_OFFSET + 0x00)
-#define DBP_BitNumber            0x08
-#define CR_DBP_BB                (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4))
-
-/* Alias word address of PVDE bit */
-#define PVDE_BitNumber           0x04
-#define CR_PVDE_BB               (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4))
-
-/* --- CSR Register ---*/
-
-/* Alias word address of EWUP bit */
-#define CSR_OFFSET               (PWR_OFFSET + 0x04)
-#define EWUP_BitNumber           0x08
-#define CSR_EWUP_BB              (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4))
-
-/* ------------------ PWR registers bit mask ------------------------ */
-
-/* CR register bit mask */
-#define CR_DS_MASK               ((uint32_t)0xFFFFFFFC)
-#define CR_PLS_MASK              ((uint32_t)0xFFFFFF1F)
-
-
-/**
-  * @}
-  */
-
-/** @defgroup PWR_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup PWR_Private_Variables
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup PWR_Private_FunctionPrototypes
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup PWR_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Deinitializes the PWR peripheral registers to their default reset values.
-  * @param  None
-  * @retval None
-  */
-void PWR_DeInit(void)
-{
-  RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE);
-  RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE);
-}
-
-/**
-  * @brief  Enables or disables access to the RTC and backup registers.
-  * @param  NewState: new state of the access to the RTC and backup registers.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void PWR_BackupAccessCmd(FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  *(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState;
-}
-
-/**
-  * @brief  Enables or disables the Power Voltage Detector(PVD).
-  * @param  NewState: new state of the PVD.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void PWR_PVDCmd(FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)NewState;
-}
-
-/**
-  * @brief  Configures the voltage threshold detected by the Power Voltage Detector(PVD).
-  * @param  PWR_PVDLevel: specifies the PVD detection level
-  *   This parameter can be one of the following values:
-  *     @arg PWR_PVDLevel_2V2: PVD detection level set to 2.2V
-  *     @arg PWR_PVDLevel_2V3: PVD detection level set to 2.3V
-  *     @arg PWR_PVDLevel_2V4: PVD detection level set to 2.4V
-  *     @arg PWR_PVDLevel_2V5: PVD detection level set to 2.5V
-  *     @arg PWR_PVDLevel_2V6: PVD detection level set to 2.6V
-  *     @arg PWR_PVDLevel_2V7: PVD detection level set to 2.7V
-  *     @arg PWR_PVDLevel_2V8: PVD detection level set to 2.8V
-  *     @arg PWR_PVDLevel_2V9: PVD detection level set to 2.9V
-  * @retval None
-  */
-void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)
-{
-  uint32_t tmpreg = 0;
-  /* Check the parameters */
-  assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel));
-  tmpreg = PWR->CR;
-  /* Clear PLS[7:5] bits */
-  tmpreg &= CR_PLS_MASK;
-  /* Set PLS[7:5] bits according to PWR_PVDLevel value */
-  tmpreg |= PWR_PVDLevel;
-  /* Store the new value */
-  PWR->CR = tmpreg;
-}
-
-/**
-  * @brief  Enables or disables the WakeUp Pin functionality.
-  * @param  NewState: new state of the WakeUp Pin functionality.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void PWR_WakeUpPinCmd(FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  *(__IO uint32_t *) CSR_EWUP_BB = (uint32_t)NewState;
-}
-
-/**
-  * @brief  Enters STOP mode.
-  * @param  PWR_Regulator: specifies the regulator state in STOP mode.
-  *   This parameter can be one of the following values:
-  *     @arg PWR_Regulator_ON: STOP mode with regulator ON
-  *     @arg PWR_Regulator_LowPower: STOP mode with regulator in low power mode
-  * @param  PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction.
-  *   This parameter can be one of the following values:
-  *     @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction
-  *     @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction
-  * @retval None
-  */
-void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
-{
-  uint32_t tmpreg = 0;
-  /* Check the parameters */
-  assert_param(IS_PWR_REGULATOR(PWR_Regulator));
-  assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry));
-  
-  /* Select the regulator state in STOP mode ---------------------------------*/
-  tmpreg = PWR->CR;
-  /* Clear PDDS and LPDS bits */
-  tmpreg &= CR_DS_MASK;
-  /* Set LPDS bit according to PWR_Regulator value */
-  tmpreg |= PWR_Regulator;
-  /* Store the new value */
-  PWR->CR = tmpreg;
-  /* Set SLEEPDEEP bit of Cortex System Control Register */
-  SCB->SCR |= SCB_SCR_SLEEPDEEP;
-  
-  /* Select STOP mode entry --------------------------------------------------*/
-  if(PWR_STOPEntry == PWR_STOPEntry_WFI)
-  {   
-    /* Request Wait For Interrupt */
-    __WFI();
-  }
-  else
-  {
-    /* Request Wait For Event */
-    __WFE();
-  }
-  
-  /* Reset SLEEPDEEP bit of Cortex System Control Register */
-  SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP);  
-}
-
-/**
-  * @brief  Enters STANDBY mode.
-  * @param  None
-  * @retval None
-  */
-void PWR_EnterSTANDBYMode(void)
-{
-  /* Clear Wake-up flag */
-  PWR->CR |= PWR_CR_CWUF;
-  /* Select STANDBY mode */
-  PWR->CR |= PWR_CR_PDDS;
-  /* Set SLEEPDEEP bit of Cortex System Control Register */
-  SCB->SCR |= SCB_SCR_SLEEPDEEP;
-/* This option is used to ensure that store operations are completed */
-#if defined ( __CC_ARM   )
-  __force_stores();
-#endif
-  /* Request Wait For Interrupt */
-  __WFI();
-}
-
-/**
-  * @brief  Checks whether the specified PWR flag is set or not.
-  * @param  PWR_FLAG: specifies the flag to check.
-  *   This parameter can be one of the following values:
-  *     @arg PWR_FLAG_WU: Wake Up flag
-  *     @arg PWR_FLAG_SB: StandBy flag
-  *     @arg PWR_FLAG_PVDO: PVD Output
-  * @retval The new state of PWR_FLAG (SET or RESET).
-  */
-FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)
-{
-  FlagStatus bitstatus = RESET;
-  /* Check the parameters */
-  assert_param(IS_PWR_GET_FLAG(PWR_FLAG));
-  
-  if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET)
-  {
-    bitstatus = SET;
-  }
-  else
-  {
-    bitstatus = RESET;
-  }
-  /* Return the flag status */
-  return bitstatus;
-}
-
-/**
-  * @brief  Clears the PWR's pending flags.
-  * @param  PWR_FLAG: specifies the flag to clear.
-  *   This parameter can be one of the following values:
-  *     @arg PWR_FLAG_WU: Wake Up flag
-  *     @arg PWR_FLAG_SB: StandBy flag
-  * @retval None
-  */
-void PWR_ClearFlag(uint32_t PWR_FLAG)
-{
-  /* Check the parameters */
-  assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG));
-         
-  PWR->CR |=  PWR_FLAG << 2;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c
deleted file mode 100644
index a29034b..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c
+++ /dev/null
@@ -1,1470 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f10x_rcc.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    11-March-2011
-  * @brief   This file provides all the RCC firmware functions.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_rcc.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Driver
-  * @{
-  */
-
-/** @defgroup RCC 
-  * @brief RCC driver modules
-  * @{
-  */ 
-
-/** @defgroup RCC_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_Private_Defines
-  * @{
-  */
-
-/* ------------ RCC registers bit address in the alias region ----------- */
-#define RCC_OFFSET                (RCC_BASE - PERIPH_BASE)
-
-/* --- CR Register ---*/
-
-/* Alias word address of HSION bit */
-#define CR_OFFSET                 (RCC_OFFSET + 0x00)
-#define HSION_BitNumber           0x00
-#define CR_HSION_BB               (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4))
-
-/* Alias word address of PLLON bit */
-#define PLLON_BitNumber           0x18
-#define CR_PLLON_BB               (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4))
-
-#ifdef STM32F10X_CL
- /* Alias word address of PLL2ON bit */
- #define PLL2ON_BitNumber          0x1A
- #define CR_PLL2ON_BB              (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLL2ON_BitNumber * 4))
-
- /* Alias word address of PLL3ON bit */
- #define PLL3ON_BitNumber          0x1C
- #define CR_PLL3ON_BB              (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLL3ON_BitNumber * 4))
-#endif /* STM32F10X_CL */ 
-
-/* Alias word address of CSSON bit */
-#define CSSON_BitNumber           0x13
-#define CR_CSSON_BB               (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4))
-
-/* --- CFGR Register ---*/
-
-/* Alias word address of USBPRE bit */
-#define CFGR_OFFSET               (RCC_OFFSET + 0x04)
-
-#ifndef STM32F10X_CL
- #define USBPRE_BitNumber          0x16
- #define CFGR_USBPRE_BB            (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (USBPRE_BitNumber * 4))
-#else
- #define OTGFSPRE_BitNumber        0x16
- #define CFGR_OTGFSPRE_BB          (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (OTGFSPRE_BitNumber * 4))
-#endif /* STM32F10X_CL */ 
-
-/* --- BDCR Register ---*/
-
-/* Alias word address of RTCEN bit */
-#define BDCR_OFFSET               (RCC_OFFSET + 0x20)
-#define RTCEN_BitNumber           0x0F
-#define BDCR_RTCEN_BB             (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4))
-
-/* Alias word address of BDRST bit */
-#define BDRST_BitNumber           0x10
-#define BDCR_BDRST_BB             (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4))
-
-/* --- CSR Register ---*/
-
-/* Alias word address of LSION bit */
-#define CSR_OFFSET                (RCC_OFFSET + 0x24)
-#define LSION_BitNumber           0x00
-#define CSR_LSION_BB              (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4))
-
-#ifdef STM32F10X_CL
-/* --- CFGR2 Register ---*/
-
- /* Alias word address of I2S2SRC bit */
- #define CFGR2_OFFSET              (RCC_OFFSET + 0x2C)
- #define I2S2SRC_BitNumber         0x11
- #define CFGR2_I2S2SRC_BB          (PERIPH_BB_BASE + (CFGR2_OFFSET * 32) + (I2S2SRC_BitNumber * 4))
-
- /* Alias word address of I2S3SRC bit */
- #define I2S3SRC_BitNumber         0x12
- #define CFGR2_I2S3SRC_BB          (PERIPH_BB_BASE + (CFGR2_OFFSET * 32) + (I2S3SRC_BitNumber * 4))
-#endif /* STM32F10X_CL */
-
-/* ---------------------- RCC registers bit mask ------------------------ */
-
-/* CR register bit mask */
-#define CR_HSEBYP_Reset           ((uint32_t)0xFFFBFFFF)
-#define CR_HSEBYP_Set             ((uint32_t)0x00040000)
-#define CR_HSEON_Reset            ((uint32_t)0xFFFEFFFF)
-#define CR_HSEON_Set              ((uint32_t)0x00010000)
-#define CR_HSITRIM_Mask           ((uint32_t)0xFFFFFF07)
-
-/* CFGR register bit mask */
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL) 
- #define CFGR_PLL_Mask            ((uint32_t)0xFFC2FFFF)
-#else
- #define CFGR_PLL_Mask            ((uint32_t)0xFFC0FFFF)
-#endif /* STM32F10X_CL */ 
-
-#define CFGR_PLLMull_Mask         ((uint32_t)0x003C0000)
-#define CFGR_PLLSRC_Mask          ((uint32_t)0x00010000)
-#define CFGR_PLLXTPRE_Mask        ((uint32_t)0x00020000)
-#define CFGR_SWS_Mask             ((uint32_t)0x0000000C)
-#define CFGR_SW_Mask              ((uint32_t)0xFFFFFFFC)
-#define CFGR_HPRE_Reset_Mask      ((uint32_t)0xFFFFFF0F)
-#define CFGR_HPRE_Set_Mask        ((uint32_t)0x000000F0)
-#define CFGR_PPRE1_Reset_Mask     ((uint32_t)0xFFFFF8FF)
-#define CFGR_PPRE1_Set_Mask       ((uint32_t)0x00000700)
-#define CFGR_PPRE2_Reset_Mask     ((uint32_t)0xFFFFC7FF)
-#define CFGR_PPRE2_Set_Mask       ((uint32_t)0x00003800)
-#define CFGR_ADCPRE_Reset_Mask    ((uint32_t)0xFFFF3FFF)
-#define CFGR_ADCPRE_Set_Mask      ((uint32_t)0x0000C000)
-
-/* CSR register bit mask */
-#define CSR_RMVF_Set              ((uint32_t)0x01000000)
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL) 
-/* CFGR2 register bit mask */
- #define CFGR2_PREDIV1SRC         ((uint32_t)0x00010000)
- #define CFGR2_PREDIV1            ((uint32_t)0x0000000F)
-#endif
-#ifdef STM32F10X_CL
- #define CFGR2_PREDIV2            ((uint32_t)0x000000F0)
- #define CFGR2_PLL2MUL            ((uint32_t)0x00000F00)
- #define CFGR2_PLL3MUL            ((uint32_t)0x0000F000)
-#endif /* STM32F10X_CL */ 
-
-/* RCC Flag Mask */
-#define FLAG_Mask                 ((uint8_t)0x1F)
-
-/* CIR register byte 2 (Bits[15:8]) base address */
-#define CIR_BYTE2_ADDRESS         ((uint32_t)0x40021009)
-
-/* CIR register byte 3 (Bits[23:16]) base address */
-#define CIR_BYTE3_ADDRESS         ((uint32_t)0x4002100A)
-
-/* CFGR register byte 4 (Bits[31:24]) base address */
-#define CFGR_BYTE4_ADDRESS        ((uint32_t)0x40021007)
-
-/* BDCR register base address */
-#define BDCR_ADDRESS              (PERIPH_BASE + BDCR_OFFSET)
-
-/**
-  * @}
-  */ 
-
-/** @defgroup RCC_Private_Macros
-  * @{
-  */ 
-
-/**
-  * @}
-  */ 
-
-/** @defgroup RCC_Private_Variables
-  * @{
-  */ 
-
-static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
-static __I uint8_t ADCPrescTable[4] = {2, 4, 6, 8};
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_Private_FunctionPrototypes
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Resets the RCC clock configuration to the default reset state.
-  * @param  None
-  * @retval None
-  */
-void RCC_DeInit(void)
-{
-  /* Set HSION bit */
-  RCC->CR |= (uint32_t)0x00000001;
-
-  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
-#ifndef STM32F10X_CL
-  RCC->CFGR &= (uint32_t)0xF8FF0000;
-#else
-  RCC->CFGR &= (uint32_t)0xF0FF0000;
-#endif /* STM32F10X_CL */   
-  
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFFF;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
-  RCC->CFGR &= (uint32_t)0xFF80FFFF;
-
-#ifdef STM32F10X_CL
-  /* Reset PLL2ON and PLL3ON bits */
-  RCC->CR &= (uint32_t)0xEBFFFFFF;
-
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x00FF0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;      
-#else
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-#endif /* STM32F10X_CL */
-
-}
-
-/**
-  * @brief  Configures the External High Speed oscillator (HSE).
-  * @note   HSE can not be stopped if it is used directly or through the PLL as system clock.
-  * @param  RCC_HSE: specifies the new state of the HSE.
-  *   This parameter can be one of the following values:
-  *     @arg RCC_HSE_OFF: HSE oscillator OFF
-  *     @arg RCC_HSE_ON: HSE oscillator ON
-  *     @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock
-  * @retval None
-  */
-void RCC_HSEConfig(uint32_t RCC_HSE)
-{
-  /* Check the parameters */
-  assert_param(IS_RCC_HSE(RCC_HSE));
-  /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/
-  /* Reset HSEON bit */
-  RCC->CR &= CR_HSEON_Reset;
-  /* Reset HSEBYP bit */
-  RCC->CR &= CR_HSEBYP_Reset;
-  /* Configure HSE (RCC_HSE_OFF is already covered by the code section above) */
-  switch(RCC_HSE)
-  {
-    case RCC_HSE_ON:
-      /* Set HSEON bit */
-      RCC->CR |= CR_HSEON_Set;
-      break;
-      
-    case RCC_HSE_Bypass:
-      /* Set HSEBYP and HSEON bits */
-      RCC->CR |= CR_HSEBYP_Set | CR_HSEON_Set;
-      break;
-      
-    default:
-      break;
-  }
-}
-
-/**
-  * @brief  Waits for HSE start-up.
-  * @param  None
-  * @retval An ErrorStatus enumuration value:
-  * - SUCCESS: HSE oscillator is stable and ready to use
-  * - ERROR: HSE oscillator not yet ready
-  */
-ErrorStatus RCC_WaitForHSEStartUp(void)
-{
-  __IO uint32_t StartUpCounter = 0;
-  ErrorStatus status = ERROR;
-  FlagStatus HSEStatus = RESET;
-  
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY);
-    StartUpCounter++;  
-  } while((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET));
-  
-  if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET)
-  {
-    status = SUCCESS;
-  }
-  else
-  {
-    status = ERROR;
-  }  
-  return (status);
-}
-
-/**
-  * @brief  Adjusts the Internal High Speed oscillator (HSI) calibration value.
-  * @param  HSICalibrationValue: specifies the calibration trimming value.
-  *   This parameter must be a number between 0 and 0x1F.
-  * @retval None
-  */
-void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)
-{
-  uint32_t tmpreg = 0;
-  /* Check the parameters */
-  assert_param(IS_RCC_CALIBRATION_VALUE(HSICalibrationValue));
-  tmpreg = RCC->CR;
-  /* Clear HSITRIM[4:0] bits */
-  tmpreg &= CR_HSITRIM_Mask;
-  /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */
-  tmpreg |= (uint32_t)HSICalibrationValue << 3;
-  /* Store the new value */
-  RCC->CR = tmpreg;
-}
-
-/**
-  * @brief  Enables or disables the Internal High Speed oscillator (HSI).
-  * @note   HSI can not be stopped if it is used directly or through the PLL as system clock.
-  * @param  NewState: new state of the HSI. This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void RCC_HSICmd(FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  *(__IO uint32_t *) CR_HSION_BB = (uint32_t)NewState;
-}
-
-/**
-  * @brief  Configures the PLL clock source and multiplication factor.
-  * @note   This function must be used only when the PLL is disabled.
-  * @param  RCC_PLLSource: specifies the PLL entry clock source.
-  *   For @b STM32_Connectivity_line_devices or @b STM32_Value_line_devices, 
-  *   this parameter can be one of the following values:
-  *     @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock divided by 2 selected as PLL clock entry
-  *     @arg RCC_PLLSource_PREDIV1: PREDIV1 clock selected as PLL clock entry
-  *   For @b other_STM32_devices, this parameter can be one of the following values:
-  *     @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock divided by 2 selected as PLL clock entry
-  *     @arg RCC_PLLSource_HSE_Div1: HSE oscillator clock selected as PLL clock entry
-  *     @arg RCC_PLLSource_HSE_Div2: HSE oscillator clock divided by 2 selected as PLL clock entry 
-  * @param  RCC_PLLMul: specifies the PLL multiplication factor.
-  *   For @b STM32_Connectivity_line_devices, this parameter can be RCC_PLLMul_x where x:{[4,9], 6_5}
-  *   For @b other_STM32_devices, this parameter can be RCC_PLLMul_x where x:[2,16]  
-  * @retval None
-  */
-void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul)
-{
-  uint32_t tmpreg = 0;
-
-  /* Check the parameters */
-  assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource));
-  assert_param(IS_RCC_PLL_MUL(RCC_PLLMul));
-
-  tmpreg = RCC->CFGR;
-  /* Clear PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
-  tmpreg &= CFGR_PLL_Mask;
-  /* Set the PLL configuration bits */
-  tmpreg |= RCC_PLLSource | RCC_PLLMul;
-  /* Store the new value */
-  RCC->CFGR = tmpreg;
-}
-
-/**
-  * @brief  Enables or disables the PLL.
-  * @note   The PLL can not be disabled if it is used as system clock.
-  * @param  NewState: new state of the PLL. This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void RCC_PLLCmd(FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-
-  *(__IO uint32_t *) CR_PLLON_BB = (uint32_t)NewState;
-}
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL)
-/**
-  * @brief  Configures the PREDIV1 division factor.
-  * @note 
-  *   - This function must be used only when the PLL is disabled.
-  *   - This function applies only to STM32 Connectivity line and Value line 
-  *     devices.
-  * @param  RCC_PREDIV1_Source: specifies the PREDIV1 clock source.
-  *   This parameter can be one of the following values:
-  *     @arg RCC_PREDIV1_Source_HSE: HSE selected as PREDIV1 clock
-  *     @arg RCC_PREDIV1_Source_PLL2: PLL2 selected as PREDIV1 clock
-  * @note 
-  *   For @b STM32_Value_line_devices this parameter is always RCC_PREDIV1_Source_HSE  
-  * @param  RCC_PREDIV1_Div: specifies the PREDIV1 clock division factor.
-  *   This parameter can be RCC_PREDIV1_Divx where x:[1,16]
-  * @retval None
-  */
-void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source, uint32_t RCC_PREDIV1_Div)
-{
-  uint32_t tmpreg = 0;
-  
-  /* Check the parameters */
-  assert_param(IS_RCC_PREDIV1_SOURCE(RCC_PREDIV1_Source));
-  assert_param(IS_RCC_PREDIV1(RCC_PREDIV1_Div));
-
-  tmpreg = RCC->CFGR2;
-  /* Clear PREDIV1[3:0] and PREDIV1SRC bits */
-  tmpreg &= ~(CFGR2_PREDIV1 | CFGR2_PREDIV1SRC);
-  /* Set the PREDIV1 clock source and division factor */
-  tmpreg |= RCC_PREDIV1_Source | RCC_PREDIV1_Div ;
-  /* Store the new value */
-  RCC->CFGR2 = tmpreg;
-}
-#endif
-
-#ifdef STM32F10X_CL
-/**
-  * @brief  Configures the PREDIV2 division factor.
-  * @note 
-  *   - This function must be used only when both PLL2 and PLL3 are disabled.
-  *   - This function applies only to STM32 Connectivity line devices.
-  * @param  RCC_PREDIV2_Div: specifies the PREDIV2 clock division factor.
-  *   This parameter can be RCC_PREDIV2_Divx where x:[1,16]
-  * @retval None
-  */
-void RCC_PREDIV2Config(uint32_t RCC_PREDIV2_Div)
-{
-  uint32_t tmpreg = 0;
-
-  /* Check the parameters */
-  assert_param(IS_RCC_PREDIV2(RCC_PREDIV2_Div));
-
-  tmpreg = RCC->CFGR2;
-  /* Clear PREDIV2[3:0] bits */
-  tmpreg &= ~CFGR2_PREDIV2;
-  /* Set the PREDIV2 division factor */
-  tmpreg |= RCC_PREDIV2_Div;
-  /* Store the new value */
-  RCC->CFGR2 = tmpreg;
-}
-
-/**
-  * @brief  Configures the PLL2 multiplication factor.
-  * @note
-  *   - This function must be used only when the PLL2 is disabled.
-  *   - This function applies only to STM32 Connectivity line devices.
-  * @param  RCC_PLL2Mul: specifies the PLL2 multiplication factor.
-  *   This parameter can be RCC_PLL2Mul_x where x:{[8,14], 16, 20}
-  * @retval None
-  */
-void RCC_PLL2Config(uint32_t RCC_PLL2Mul)
-{
-  uint32_t tmpreg = 0;
-
-  /* Check the parameters */
-  assert_param(IS_RCC_PLL2_MUL(RCC_PLL2Mul));
-
-  tmpreg = RCC->CFGR2;
-  /* Clear PLL2Mul[3:0] bits */
-  tmpreg &= ~CFGR2_PLL2MUL;
-  /* Set the PLL2 configuration bits */
-  tmpreg |= RCC_PLL2Mul;
-  /* Store the new value */
-  RCC->CFGR2 = tmpreg;
-}
-
-
-/**
-  * @brief  Enables or disables the PLL2.
-  * @note 
-  *   - The PLL2 can not be disabled if it is used indirectly as system clock
-  *     (i.e. it is used as PLL clock entry that is used as System clock).
-  *   - This function applies only to STM32 Connectivity line devices.
-  * @param  NewState: new state of the PLL2. This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void RCC_PLL2Cmd(FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-
-  *(__IO uint32_t *) CR_PLL2ON_BB = (uint32_t)NewState;
-}
-
-
-/**
-  * @brief  Configures the PLL3 multiplication factor.
-  * @note 
-  *   - This function must be used only when the PLL3 is disabled.
-  *   - This function applies only to STM32 Connectivity line devices.
-  * @param  RCC_PLL3Mul: specifies the PLL3 multiplication factor.
-  *   This parameter can be RCC_PLL3Mul_x where x:{[8,14], 16, 20}
-  * @retval None
-  */
-void RCC_PLL3Config(uint32_t RCC_PLL3Mul)
-{
-  uint32_t tmpreg = 0;
-
-  /* Check the parameters */
-  assert_param(IS_RCC_PLL3_MUL(RCC_PLL3Mul));
-
-  tmpreg = RCC->CFGR2;
-  /* Clear PLL3Mul[3:0] bits */
-  tmpreg &= ~CFGR2_PLL3MUL;
-  /* Set the PLL3 configuration bits */
-  tmpreg |= RCC_PLL3Mul;
-  /* Store the new value */
-  RCC->CFGR2 = tmpreg;
-}
-
-
-/**
-  * @brief  Enables or disables the PLL3.
-  * @note   This function applies only to STM32 Connectivity line devices.
-  * @param  NewState: new state of the PLL3. This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void RCC_PLL3Cmd(FunctionalState NewState)
-{
-  /* Check the parameters */
-
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  *(__IO uint32_t *) CR_PLL3ON_BB = (uint32_t)NewState;
-}
-#endif /* STM32F10X_CL */
-
-/**
-  * @brief  Configures the system clock (SYSCLK).
-  * @param  RCC_SYSCLKSource: specifies the clock source used as system clock.
-  *   This parameter can be one of the following values:
-  *     @arg RCC_SYSCLKSource_HSI: HSI selected as system clock
-  *     @arg RCC_SYSCLKSource_HSE: HSE selected as system clock
-  *     @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock
-  * @retval None
-  */
-void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)
-{
-  uint32_t tmpreg = 0;
-  /* Check the parameters */
-  assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource));
-  tmpreg = RCC->CFGR;
-  /* Clear SW[1:0] bits */
-  tmpreg &= CFGR_SW_Mask;
-  /* Set SW[1:0] bits according to RCC_SYSCLKSource value */
-  tmpreg |= RCC_SYSCLKSource;
-  /* Store the new value */
-  RCC->CFGR = tmpreg;
-}
-
-/**
-  * @brief  Returns the clock source used as system clock.
-  * @param  None
-  * @retval The clock source used as system clock. The returned value can
-  *   be one of the following:
-  *     - 0x00: HSI used as system clock
-  *     - 0x04: HSE used as system clock
-  *     - 0x08: PLL used as system clock
-  */
-uint8_t RCC_GetSYSCLKSource(void)
-{
-  return ((uint8_t)(RCC->CFGR & CFGR_SWS_Mask));
-}
-
-/**
-  * @brief  Configures the AHB clock (HCLK).
-  * @param  RCC_SYSCLK: defines the AHB clock divider. This clock is derived from 
-  *   the system clock (SYSCLK).
-  *   This parameter can be one of the following values:
-  *     @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK
-  *     @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2
-  *     @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4
-  *     @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8
-  *     @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16
-  *     @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64
-  *     @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128
-  *     @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256
-  *     @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512
-  * @retval None
-  */
-void RCC_HCLKConfig(uint32_t RCC_SYSCLK)
-{
-  uint32_t tmpreg = 0;
-  /* Check the parameters */
-  assert_param(IS_RCC_HCLK(RCC_SYSCLK));
-  tmpreg = RCC->CFGR;
-  /* Clear HPRE[3:0] bits */
-  tmpreg &= CFGR_HPRE_Reset_Mask;
-  /* Set HPRE[3:0] bits according to RCC_SYSCLK value */
-  tmpreg |= RCC_SYSCLK;
-  /* Store the new value */
-  RCC->CFGR = tmpreg;
-}
-
-/**
-  * @brief  Configures the Low Speed APB clock (PCLK1).
-  * @param  RCC_HCLK: defines the APB1 clock divider. This clock is derived from 
-  *   the AHB clock (HCLK).
-  *   This parameter can be one of the following values:
-  *     @arg RCC_HCLK_Div1: APB1 clock = HCLK
-  *     @arg RCC_HCLK_Div2: APB1 clock = HCLK/2
-  *     @arg RCC_HCLK_Div4: APB1 clock = HCLK/4
-  *     @arg RCC_HCLK_Div8: APB1 clock = HCLK/8
-  *     @arg RCC_HCLK_Div16: APB1 clock = HCLK/16
-  * @retval None
-  */
-void RCC_PCLK1Config(uint32_t RCC_HCLK)
-{
-  uint32_t tmpreg = 0;
-  /* Check the parameters */
-  assert_param(IS_RCC_PCLK(RCC_HCLK));
-  tmpreg = RCC->CFGR;
-  /* Clear PPRE1[2:0] bits */
-  tmpreg &= CFGR_PPRE1_Reset_Mask;
-  /* Set PPRE1[2:0] bits according to RCC_HCLK value */
-  tmpreg |= RCC_HCLK;
-  /* Store the new value */
-  RCC->CFGR = tmpreg;
-}
-
-/**
-  * @brief  Configures the High Speed APB clock (PCLK2).
-  * @param  RCC_HCLK: defines the APB2 clock divider. This clock is derived from 
-  *   the AHB clock (HCLK).
-  *   This parameter can be one of the following values:
-  *     @arg RCC_HCLK_Div1: APB2 clock = HCLK
-  *     @arg RCC_HCLK_Div2: APB2 clock = HCLK/2
-  *     @arg RCC_HCLK_Div4: APB2 clock = HCLK/4
-  *     @arg RCC_HCLK_Div8: APB2 clock = HCLK/8
-  *     @arg RCC_HCLK_Div16: APB2 clock = HCLK/16
-  * @retval None
-  */
-void RCC_PCLK2Config(uint32_t RCC_HCLK)
-{
-  uint32_t tmpreg = 0;
-  /* Check the parameters */
-  assert_param(IS_RCC_PCLK(RCC_HCLK));
-  tmpreg = RCC->CFGR;
-  /* Clear PPRE2[2:0] bits */
-  tmpreg &= CFGR_PPRE2_Reset_Mask;
-  /* Set PPRE2[2:0] bits according to RCC_HCLK value */
-  tmpreg |= RCC_HCLK << 3;
-  /* Store the new value */
-  RCC->CFGR = tmpreg;
-}
-
-/**
-  * @brief  Enables or disables the specified RCC interrupts.
-  * @param  RCC_IT: specifies the RCC interrupt sources to be enabled or disabled.
-  * 
-  *   For @b STM32_Connectivity_line_devices, this parameter can be any combination
-  *   of the following values        
-  *     @arg RCC_IT_LSIRDY: LSI ready interrupt
-  *     @arg RCC_IT_LSERDY: LSE ready interrupt
-  *     @arg RCC_IT_HSIRDY: HSI ready interrupt
-  *     @arg RCC_IT_HSERDY: HSE ready interrupt
-  *     @arg RCC_IT_PLLRDY: PLL ready interrupt
-  *     @arg RCC_IT_PLL2RDY: PLL2 ready interrupt
-  *     @arg RCC_IT_PLL3RDY: PLL3 ready interrupt
-  * 
-  *   For @b other_STM32_devices, this parameter can be any combination of the 
-  *   following values        
-  *     @arg RCC_IT_LSIRDY: LSI ready interrupt
-  *     @arg RCC_IT_LSERDY: LSE ready interrupt
-  *     @arg RCC_IT_HSIRDY: HSI ready interrupt
-  *     @arg RCC_IT_HSERDY: HSE ready interrupt
-  *     @arg RCC_IT_PLLRDY: PLL ready interrupt
-  *       
-  * @param  NewState: new state of the specified RCC interrupts.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_RCC_IT(RCC_IT));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  if (NewState != DISABLE)
-  {
-    /* Perform Byte access to RCC_CIR bits to enable the selected interrupts */
-    *(__IO uint8_t *) CIR_BYTE2_ADDRESS |= RCC_IT;
-  }
-  else
-  {
-    /* Perform Byte access to RCC_CIR bits to disable the selected interrupts */
-    *(__IO uint8_t *) CIR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT;
-  }
-}
-
-#ifndef STM32F10X_CL
-/**
-  * @brief  Configures the USB clock (USBCLK).
-  * @param  RCC_USBCLKSource: specifies the USB clock source. This clock is 
-  *   derived from the PLL output.
-  *   This parameter can be one of the following values:
-  *     @arg RCC_USBCLKSource_PLLCLK_1Div5: PLL clock divided by 1,5 selected as USB 
-  *                                     clock source
-  *     @arg RCC_USBCLKSource_PLLCLK_Div1: PLL clock selected as USB clock source
-  * @retval None
-  */
-void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource)
-{
-  /* Check the parameters */
-  assert_param(IS_RCC_USBCLK_SOURCE(RCC_USBCLKSource));
-
-  *(__IO uint32_t *) CFGR_USBPRE_BB = RCC_USBCLKSource;
-}
-#else
-/**
-  * @brief  Configures the USB OTG FS clock (OTGFSCLK).
-  *   This function applies only to STM32 Connectivity line devices.
-  * @param  RCC_OTGFSCLKSource: specifies the USB OTG FS clock source.
-  *   This clock is derived from the PLL output.
-  *   This parameter can be one of the following values:
-  *     @arg  RCC_OTGFSCLKSource_PLLVCO_Div3: PLL VCO clock divided by 2 selected as USB OTG FS clock source
-  *     @arg  RCC_OTGFSCLKSource_PLLVCO_Div2: PLL VCO clock divided by 2 selected as USB OTG FS clock source
-  * @retval None
-  */
-void RCC_OTGFSCLKConfig(uint32_t RCC_OTGFSCLKSource)
-{
-  /* Check the parameters */
-  assert_param(IS_RCC_OTGFSCLK_SOURCE(RCC_OTGFSCLKSource));
-
-  *(__IO uint32_t *) CFGR_OTGFSPRE_BB = RCC_OTGFSCLKSource;
-}
-#endif /* STM32F10X_CL */ 
-
-/**
-  * @brief  Configures the ADC clock (ADCCLK).
-  * @param  RCC_PCLK2: defines the ADC clock divider. This clock is derived from 
-  *   the APB2 clock (PCLK2).
-  *   This parameter can be one of the following values:
-  *     @arg RCC_PCLK2_Div2: ADC clock = PCLK2/2
-  *     @arg RCC_PCLK2_Div4: ADC clock = PCLK2/4
-  *     @arg RCC_PCLK2_Div6: ADC clock = PCLK2/6
-  *     @arg RCC_PCLK2_Div8: ADC clock = PCLK2/8
-  * @retval None
-  */
-void RCC_ADCCLKConfig(uint32_t RCC_PCLK2)
-{
-  uint32_t tmpreg = 0;
-  /* Check the parameters */
-  assert_param(IS_RCC_ADCCLK(RCC_PCLK2));
-  tmpreg = RCC->CFGR;
-  /* Clear ADCPRE[1:0] bits */
-  tmpreg &= CFGR_ADCPRE_Reset_Mask;
-  /* Set ADCPRE[1:0] bits according to RCC_PCLK2 value */
-  tmpreg |= RCC_PCLK2;
-  /* Store the new value */
-  RCC->CFGR = tmpreg;
-}
-
-#ifdef STM32F10X_CL
-/**
-  * @brief  Configures the I2S2 clock source(I2S2CLK).
-  * @note
-  *   - This function must be called before enabling I2S2 APB clock.
-  *   - This function applies only to STM32 Connectivity line devices.
-  * @param  RCC_I2S2CLKSource: specifies the I2S2 clock source.
-  *   This parameter can be one of the following values:
-  *     @arg RCC_I2S2CLKSource_SYSCLK: system clock selected as I2S2 clock entry
-  *     @arg RCC_I2S2CLKSource_PLL3_VCO: PLL3 VCO clock selected as I2S2 clock entry
-  * @retval None
-  */
-void RCC_I2S2CLKConfig(uint32_t RCC_I2S2CLKSource)
-{
-  /* Check the parameters */
-  assert_param(IS_RCC_I2S2CLK_SOURCE(RCC_I2S2CLKSource));
-
-  *(__IO uint32_t *) CFGR2_I2S2SRC_BB = RCC_I2S2CLKSource;
-}
-
-/**
-  * @brief  Configures the I2S3 clock source(I2S2CLK).
-  * @note
-  *   - This function must be called before enabling I2S3 APB clock.
-  *   - This function applies only to STM32 Connectivity line devices.
-  * @param  RCC_I2S3CLKSource: specifies the I2S3 clock source.
-  *   This parameter can be one of the following values:
-  *     @arg RCC_I2S3CLKSource_SYSCLK: system clock selected as I2S3 clock entry
-  *     @arg RCC_I2S3CLKSource_PLL3_VCO: PLL3 VCO clock selected as I2S3 clock entry
-  * @retval None
-  */
-void RCC_I2S3CLKConfig(uint32_t RCC_I2S3CLKSource)
-{
-  /* Check the parameters */
-  assert_param(IS_RCC_I2S3CLK_SOURCE(RCC_I2S3CLKSource));
-
-  *(__IO uint32_t *) CFGR2_I2S3SRC_BB = RCC_I2S3CLKSource;
-}
-#endif /* STM32F10X_CL */
-
-/**
-  * @brief  Configures the External Low Speed oscillator (LSE).
-  * @param  RCC_LSE: specifies the new state of the LSE.
-  *   This parameter can be one of the following values:
-  *     @arg RCC_LSE_OFF: LSE oscillator OFF
-  *     @arg RCC_LSE_ON: LSE oscillator ON
-  *     @arg RCC_LSE_Bypass: LSE oscillator bypassed with external clock
-  * @retval None
-  */
-void RCC_LSEConfig(uint8_t RCC_LSE)
-{
-  /* Check the parameters */
-  assert_param(IS_RCC_LSE(RCC_LSE));
-  /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/
-  /* Reset LSEON bit */
-  *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF;
-  /* Reset LSEBYP bit */
-  *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF;
-  /* Configure LSE (RCC_LSE_OFF is already covered by the code section above) */
-  switch(RCC_LSE)
-  {
-    case RCC_LSE_ON:
-      /* Set LSEON bit */
-      *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_ON;
-      break;
-      
-    case RCC_LSE_Bypass:
-      /* Set LSEBYP and LSEON bits */
-      *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON;
-      break;            
-      
-    default:
-      break;      
-  }
-}
-
-/**
-  * @brief  Enables or disables the Internal Low Speed oscillator (LSI).
-  * @note   LSI can not be disabled if the IWDG is running.
-  * @param  NewState: new state of the LSI. This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void RCC_LSICmd(FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  *(__IO uint32_t *) CSR_LSION_BB = (uint32_t)NewState;
-}
-
-/**
-  * @brief  Configures the RTC clock (RTCCLK).
-  * @note   Once the RTC clock is selected it can't be changed unless the Backup domain is reset.
-  * @param  RCC_RTCCLKSource: specifies the RTC clock source.
-  *   This parameter can be one of the following values:
-  *     @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock
-  *     @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock
-  *     @arg RCC_RTCCLKSource_HSE_Div128: HSE clock divided by 128 selected as RTC clock
-  * @retval None
-  */
-void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource)
-{
-  /* Check the parameters */
-  assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource));
-  /* Select the RTC clock source */
-  RCC->BDCR |= RCC_RTCCLKSource;
-}
-
-/**
-  * @brief  Enables or disables the RTC clock.
-  * @note   This function must be used only after the RTC clock was selected using the RCC_RTCCLKConfig function.
-  * @param  NewState: new state of the RTC clock. This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void RCC_RTCCLKCmd(FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  *(__IO uint32_t *) BDCR_RTCEN_BB = (uint32_t)NewState;
-}
-
-/**
-  * @brief  Returns the frequencies of different on chip clocks.
-  * @param  RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold
-  *         the clocks frequencies.
-  * @note   The result of this function could be not correct when using 
-  *         fractional value for HSE crystal.  
-  * @retval None
-  */
-void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
-{
-  uint32_t tmp = 0, pllmull = 0, pllsource = 0, presc = 0;
-
-#ifdef  STM32F10X_CL
-  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
-#endif /* STM32F10X_CL */
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-  uint32_t prediv1factor = 0;
-#endif
-    
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & CFGR_SWS_Mask;
-  
-  switch (tmp)
-  {
-    case 0x00:  /* HSI used as system clock */
-      RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
-      break;
-    case 0x04:  /* HSE used as system clock */
-      RCC_Clocks->SYSCLK_Frequency = HSE_VALUE;
-      break;
-    case 0x08:  /* PLL used as system clock */
-
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmull = RCC->CFGR & CFGR_PLLMull_Mask;
-      pllsource = RCC->CFGR & CFGR_PLLSRC_Mask;
-      
-#ifndef STM32F10X_CL      
-      pllmull = ( pllmull >> 18) + 2;
-      
-      if (pllsource == 0x00)
-      {/* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {
- #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-       prediv1factor = (RCC->CFGR2 & CFGR2_PREDIV1) + 1;
-       /* HSE oscillator clock selected as PREDIV1 clock entry */
-       RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE / prediv1factor) * pllmull; 
- #else
-        /* HSE selected as PLL clock entry */
-        if ((RCC->CFGR & CFGR_PLLXTPRE_Mask) != (uint32_t)RESET)
-        {/* HSE oscillator clock divided by 2 */
-          RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE >> 1) * pllmull;
-        }
-        else
-        {
-          RCC_Clocks->SYSCLK_Frequency = HSE_VALUE * pllmull;
-        }
- #endif
-      }
-#else
-      pllmull = pllmull >> 18;
-      
-      if (pllmull != 0x0D)
-      {
-         pllmull += 2;
-      }
-      else
-      { /* PLL multiplication factor = PLL input clock * 6.5 */
-        pllmull = 13 / 2; 
-      }
-            
-      if (pllsource == 0x00)
-      {/* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {/* PREDIV1 selected as PLL clock entry */
-        
-        /* Get PREDIV1 clock source and division factor */
-        prediv1source = RCC->CFGR2 & CFGR2_PREDIV1SRC;
-        prediv1factor = (RCC->CFGR2 & CFGR2_PREDIV1) + 1;
-        
-        if (prediv1source == 0)
-        { /* HSE oscillator clock selected as PREDIV1 clock entry */
-          RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE / prediv1factor) * pllmull;          
-        }
-        else
-        {/* PLL2 clock selected as PREDIV1 clock entry */
-          
-          /* Get PREDIV2 division factor and PLL2 multiplication factor */
-          prediv2factor = ((RCC->CFGR2 & CFGR2_PREDIV2) >> 4) + 1;
-          pll2mull = ((RCC->CFGR2 & CFGR2_PLL2MUL) >> 8 ) + 2; 
-          RCC_Clocks->SYSCLK_Frequency = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
-        }
-      }
-#endif /* STM32F10X_CL */ 
-      break;
-
-    default:
-      RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
-      break;
-  }
-
-  /* Compute HCLK, PCLK1, PCLK2 and ADCCLK clocks frequencies ----------------*/
-  /* Get HCLK prescaler */
-  tmp = RCC->CFGR & CFGR_HPRE_Set_Mask;
-  tmp = tmp >> 4;
-  presc = APBAHBPrescTable[tmp];
-  /* HCLK clock frequency */
-  RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;
-  /* Get PCLK1 prescaler */
-  tmp = RCC->CFGR & CFGR_PPRE1_Set_Mask;
-  tmp = tmp >> 8;
-  presc = APBAHBPrescTable[tmp];
-  /* PCLK1 clock frequency */
-  RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
-  /* Get PCLK2 prescaler */
-  tmp = RCC->CFGR & CFGR_PPRE2_Set_Mask;
-  tmp = tmp >> 11;
-  presc = APBAHBPrescTable[tmp];
-  /* PCLK2 clock frequency */
-  RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
-  /* Get ADCCLK prescaler */
-  tmp = RCC->CFGR & CFGR_ADCPRE_Set_Mask;
-  tmp = tmp >> 14;
-  presc = ADCPrescTable[tmp];
-  /* ADCCLK clock frequency */
-  RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc;
-}
-
-/**
-  * @brief  Enables or disables the AHB peripheral clock.
-  * @param  RCC_AHBPeriph: specifies the AHB peripheral to gates its clock.
-  *   
-  *   For @b STM32_Connectivity_line_devices, this parameter can be any combination
-  *   of the following values:        
-  *     @arg RCC_AHBPeriph_DMA1
-  *     @arg RCC_AHBPeriph_DMA2
-  *     @arg RCC_AHBPeriph_SRAM
-  *     @arg RCC_AHBPeriph_FLITF
-  *     @arg RCC_AHBPeriph_CRC
-  *     @arg RCC_AHBPeriph_OTG_FS    
-  *     @arg RCC_AHBPeriph_ETH_MAC   
-  *     @arg RCC_AHBPeriph_ETH_MAC_Tx
-  *     @arg RCC_AHBPeriph_ETH_MAC_Rx
-  * 
-  *   For @b other_STM32_devices, this parameter can be any combination of the 
-  *   following values:        
-  *     @arg RCC_AHBPeriph_DMA1
-  *     @arg RCC_AHBPeriph_DMA2
-  *     @arg RCC_AHBPeriph_SRAM
-  *     @arg RCC_AHBPeriph_FLITF
-  *     @arg RCC_AHBPeriph_CRC
-  *     @arg RCC_AHBPeriph_FSMC
-  *     @arg RCC_AHBPeriph_SDIO
-  *   
-  * @note SRAM and FLITF clock can be disabled only during sleep mode.
-  * @param  NewState: new state of the specified peripheral clock.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-
-  if (NewState != DISABLE)
-  {
-    RCC->AHBENR |= RCC_AHBPeriph;
-  }
-  else
-  {
-    RCC->AHBENR &= ~RCC_AHBPeriph;
-  }
-}
-
-/**
-  * @brief  Enables or disables the High Speed APB (APB2) peripheral clock.
-  * @param  RCC_APB2Periph: specifies the APB2 peripheral to gates its clock.
-  *   This parameter can be any combination of the following values:
-  *     @arg RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB,
-  *          RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE,
-  *          RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, RCC_APB2Periph_ADC1,
-  *          RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1,
-  *          RCC_APB2Periph_TIM8, RCC_APB2Periph_USART1, RCC_APB2Periph_ADC3,
-  *          RCC_APB2Periph_TIM15, RCC_APB2Periph_TIM16, RCC_APB2Periph_TIM17,
-  *          RCC_APB2Periph_TIM9, RCC_APB2Periph_TIM10, RCC_APB2Periph_TIM11     
-  * @param  NewState: new state of the specified peripheral clock.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  if (NewState != DISABLE)
-  {
-    RCC->APB2ENR |= RCC_APB2Periph;
-  }
-  else
-  {
-    RCC->APB2ENR &= ~RCC_APB2Periph;
-  }
-}
-
-/**
-  * @brief  Enables or disables the Low Speed APB (APB1) peripheral clock.
-  * @param  RCC_APB1Periph: specifies the APB1 peripheral to gates its clock.
-  *   This parameter can be any combination of the following values:
-  *     @arg RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4,
-  *          RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7,
-  *          RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3,
-  *          RCC_APB1Periph_USART2, RCC_APB1Periph_USART3, RCC_APB1Periph_USART4, 
-  *          RCC_APB1Periph_USART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2,
-  *          RCC_APB1Periph_USB, RCC_APB1Periph_CAN1, RCC_APB1Periph_BKP,
-  *          RCC_APB1Periph_PWR, RCC_APB1Periph_DAC, RCC_APB1Periph_CEC,
-  *          RCC_APB1Periph_TIM12, RCC_APB1Periph_TIM13, RCC_APB1Periph_TIM14
-  * @param  NewState: new state of the specified peripheral clock.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  if (NewState != DISABLE)
-  {
-    RCC->APB1ENR |= RCC_APB1Periph;
-  }
-  else
-  {
-    RCC->APB1ENR &= ~RCC_APB1Periph;
-  }
-}
-
-#ifdef STM32F10X_CL
-/**
-  * @brief  Forces or releases AHB peripheral reset.
-  * @note   This function applies only to STM32 Connectivity line devices.
-  * @param  RCC_AHBPeriph: specifies the AHB peripheral to reset.
-  *   This parameter can be any combination of the following values:
-  *     @arg RCC_AHBPeriph_OTG_FS 
-  *     @arg RCC_AHBPeriph_ETH_MAC
-  * @param  NewState: new state of the specified peripheral reset.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_RCC_AHB_PERIPH_RESET(RCC_AHBPeriph));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-
-  if (NewState != DISABLE)
-  {
-    RCC->AHBRSTR |= RCC_AHBPeriph;
-  }
-  else
-  {
-    RCC->AHBRSTR &= ~RCC_AHBPeriph;
-  }
-}
-#endif /* STM32F10X_CL */ 
-
-/**
-  * @brief  Forces or releases High Speed APB (APB2) peripheral reset.
-  * @param  RCC_APB2Periph: specifies the APB2 peripheral to reset.
-  *   This parameter can be any combination of the following values:
-  *     @arg RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB,
-  *          RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE,
-  *          RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, RCC_APB2Periph_ADC1,
-  *          RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1,
-  *          RCC_APB2Periph_TIM8, RCC_APB2Periph_USART1, RCC_APB2Periph_ADC3,
-  *          RCC_APB2Periph_TIM15, RCC_APB2Periph_TIM16, RCC_APB2Periph_TIM17,
-  *          RCC_APB2Periph_TIM9, RCC_APB2Periph_TIM10, RCC_APB2Periph_TIM11  
-  * @param  NewState: new state of the specified peripheral reset.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  if (NewState != DISABLE)
-  {
-    RCC->APB2RSTR |= RCC_APB2Periph;
-  }
-  else
-  {
-    RCC->APB2RSTR &= ~RCC_APB2Periph;
-  }
-}
-
-/**
-  * @brief  Forces or releases Low Speed APB (APB1) peripheral reset.
-  * @param  RCC_APB1Periph: specifies the APB1 peripheral to reset.
-  *   This parameter can be any combination of the following values:
-  *     @arg RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4,
-  *          RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7,
-  *          RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3,
-  *          RCC_APB1Periph_USART2, RCC_APB1Periph_USART3, RCC_APB1Periph_USART4, 
-  *          RCC_APB1Periph_USART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2,
-  *          RCC_APB1Periph_USB, RCC_APB1Periph_CAN1, RCC_APB1Periph_BKP,
-  *          RCC_APB1Periph_PWR, RCC_APB1Periph_DAC, RCC_APB1Periph_CEC,
-  *          RCC_APB1Periph_TIM12, RCC_APB1Periph_TIM13, RCC_APB1Periph_TIM14  
-  * @param  NewState: new state of the specified peripheral clock.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  if (NewState != DISABLE)
-  {
-    RCC->APB1RSTR |= RCC_APB1Periph;
-  }
-  else
-  {
-    RCC->APB1RSTR &= ~RCC_APB1Periph;
-  }
-}
-
-/**
-  * @brief  Forces or releases the Backup domain reset.
-  * @param  NewState: new state of the Backup domain reset.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void RCC_BackupResetCmd(FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  *(__IO uint32_t *) BDCR_BDRST_BB = (uint32_t)NewState;
-}
-
-/**
-  * @brief  Enables or disables the Clock Security System.
-  * @param  NewState: new state of the Clock Security System..
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void RCC_ClockSecuritySystemCmd(FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)NewState;
-}
-
-/**
-  * @brief  Selects the clock source to output on MCO pin.
-  * @param  RCC_MCO: specifies the clock source to output.
-  *   
-  *   For @b STM32_Connectivity_line_devices, this parameter can be one of the
-  *   following values:       
-  *     @arg RCC_MCO_NoClock: No clock selected
-  *     @arg RCC_MCO_SYSCLK: System clock selected
-  *     @arg RCC_MCO_HSI: HSI oscillator clock selected
-  *     @arg RCC_MCO_HSE: HSE oscillator clock selected
-  *     @arg RCC_MCO_PLLCLK_Div2: PLL clock divided by 2 selected
-  *     @arg RCC_MCO_PLL2CLK: PLL2 clock selected                     
-  *     @arg RCC_MCO_PLL3CLK_Div2: PLL3 clock divided by 2 selected   
-  *     @arg RCC_MCO_XT1: External 3-25 MHz oscillator clock selected  
-  *     @arg RCC_MCO_PLL3CLK: PLL3 clock selected 
-  * 
-  *   For  @b other_STM32_devices, this parameter can be one of the following values:        
-  *     @arg RCC_MCO_NoClock: No clock selected
-  *     @arg RCC_MCO_SYSCLK: System clock selected
-  *     @arg RCC_MCO_HSI: HSI oscillator clock selected
-  *     @arg RCC_MCO_HSE: HSE oscillator clock selected
-  *     @arg RCC_MCO_PLLCLK_Div2: PLL clock divided by 2 selected
-  *   
-  * @retval None
-  */
-void RCC_MCOConfig(uint8_t RCC_MCO)
-{
-  /* Check the parameters */
-  assert_param(IS_RCC_MCO(RCC_MCO));
-
-  /* Perform Byte access to MCO bits to select the MCO source */
-  *(__IO uint8_t *) CFGR_BYTE4_ADDRESS = RCC_MCO;
-}
-
-/**
-  * @brief  Checks whether the specified RCC flag is set or not.
-  * @param  RCC_FLAG: specifies the flag to check.
-  *   
-  *   For @b STM32_Connectivity_line_devices, this parameter can be one of the
-  *   following values:
-  *     @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
-  *     @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
-  *     @arg RCC_FLAG_PLLRDY: PLL clock ready
-  *     @arg RCC_FLAG_PLL2RDY: PLL2 clock ready      
-  *     @arg RCC_FLAG_PLL3RDY: PLL3 clock ready                           
-  *     @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
-  *     @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
-  *     @arg RCC_FLAG_PINRST: Pin reset
-  *     @arg RCC_FLAG_PORRST: POR/PDR reset
-  *     @arg RCC_FLAG_SFTRST: Software reset
-  *     @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
-  *     @arg RCC_FLAG_WWDGRST: Window Watchdog reset
-  *     @arg RCC_FLAG_LPWRRST: Low Power reset
-  * 
-  *   For @b other_STM32_devices, this parameter can be one of the following values:        
-  *     @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
-  *     @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
-  *     @arg RCC_FLAG_PLLRDY: PLL clock ready
-  *     @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
-  *     @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
-  *     @arg RCC_FLAG_PINRST: Pin reset
-  *     @arg RCC_FLAG_PORRST: POR/PDR reset
-  *     @arg RCC_FLAG_SFTRST: Software reset
-  *     @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
-  *     @arg RCC_FLAG_WWDGRST: Window Watchdog reset
-  *     @arg RCC_FLAG_LPWRRST: Low Power reset
-  *   
-  * @retval The new state of RCC_FLAG (SET or RESET).
-  */
-FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG)
-{
-  uint32_t tmp = 0;
-  uint32_t statusreg = 0;
-  FlagStatus bitstatus = RESET;
-  /* Check the parameters */
-  assert_param(IS_RCC_FLAG(RCC_FLAG));
-
-  /* Get the RCC register index */
-  tmp = RCC_FLAG >> 5;
-  if (tmp == 1)               /* The flag to check is in CR register */
-  {
-    statusreg = RCC->CR;
-  }
-  else if (tmp == 2)          /* The flag to check is in BDCR register */
-  {
-    statusreg = RCC->BDCR;
-  }
-  else                       /* The flag to check is in CSR register */
-  {
-    statusreg = RCC->CSR;
-  }
-
-  /* Get the flag position */
-  tmp = RCC_FLAG & FLAG_Mask;
-  if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET)
-  {
-    bitstatus = SET;
-  }
-  else
-  {
-    bitstatus = RESET;
-  }
-
-  /* Return the flag status */
-  return bitstatus;
-}
-
-/**
-  * @brief  Clears the RCC reset flags.
-  * @note   The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,
-  *   RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
-  * @param  None
-  * @retval None
-  */
-void RCC_ClearFlag(void)
-{
-  /* Set RMVF bit to clear the reset flags */
-  RCC->CSR |= CSR_RMVF_Set;
-}
-
-/**
-  * @brief  Checks whether the specified RCC interrupt has occurred or not.
-  * @param  RCC_IT: specifies the RCC interrupt source to check.
-  *   
-  *   For @b STM32_Connectivity_line_devices, this parameter can be one of the
-  *   following values:
-  *     @arg RCC_IT_LSIRDY: LSI ready interrupt
-  *     @arg RCC_IT_LSERDY: LSE ready interrupt
-  *     @arg RCC_IT_HSIRDY: HSI ready interrupt
-  *     @arg RCC_IT_HSERDY: HSE ready interrupt
-  *     @arg RCC_IT_PLLRDY: PLL ready interrupt
-  *     @arg RCC_IT_PLL2RDY: PLL2 ready interrupt 
-  *     @arg RCC_IT_PLL3RDY: PLL3 ready interrupt                      
-  *     @arg RCC_IT_CSS: Clock Security System interrupt
-  * 
-  *   For @b other_STM32_devices, this parameter can be one of the following values:        
-  *     @arg RCC_IT_LSIRDY: LSI ready interrupt
-  *     @arg RCC_IT_LSERDY: LSE ready interrupt
-  *     @arg RCC_IT_HSIRDY: HSI ready interrupt
-  *     @arg RCC_IT_HSERDY: HSE ready interrupt
-  *     @arg RCC_IT_PLLRDY: PLL ready interrupt
-  *     @arg RCC_IT_CSS: Clock Security System interrupt
-  *   
-  * @retval The new state of RCC_IT (SET or RESET).
-  */
-ITStatus RCC_GetITStatus(uint8_t RCC_IT)
-{
-  ITStatus bitstatus = RESET;
-  /* Check the parameters */
-  assert_param(IS_RCC_GET_IT(RCC_IT));
-
-  /* Check the status of the specified RCC interrupt */
-  if ((RCC->CIR & RCC_IT) != (uint32_t)RESET)
-  {
-    bitstatus = SET;
-  }
-  else
-  {
-    bitstatus = RESET;
-  }
-
-  /* Return the RCC_IT status */
-  return  bitstatus;
-}
-
-/**
-  * @brief  Clears the RCC's interrupt pending bits.
-  * @param  RCC_IT: specifies the interrupt pending bit to clear.
-  *   
-  *   For @b STM32_Connectivity_line_devices, this parameter can be any combination
-  *   of the following values:
-  *     @arg RCC_IT_LSIRDY: LSI ready interrupt
-  *     @arg RCC_IT_LSERDY: LSE ready interrupt
-  *     @arg RCC_IT_HSIRDY: HSI ready interrupt
-  *     @arg RCC_IT_HSERDY: HSE ready interrupt
-  *     @arg RCC_IT_PLLRDY: PLL ready interrupt
-  *     @arg RCC_IT_PLL2RDY: PLL2 ready interrupt 
-  *     @arg RCC_IT_PLL3RDY: PLL3 ready interrupt                      
-  *     @arg RCC_IT_CSS: Clock Security System interrupt
-  * 
-  *   For @b other_STM32_devices, this parameter can be any combination of the
-  *   following values:        
-  *     @arg RCC_IT_LSIRDY: LSI ready interrupt
-  *     @arg RCC_IT_LSERDY: LSE ready interrupt
-  *     @arg RCC_IT_HSIRDY: HSI ready interrupt
-  *     @arg RCC_IT_HSERDY: HSE ready interrupt
-  *     @arg RCC_IT_PLLRDY: PLL ready interrupt
-  *   
-  *     @arg RCC_IT_CSS: Clock Security System interrupt
-  * @retval None
-  */
-void RCC_ClearITPendingBit(uint8_t RCC_IT)
-{
-  /* Check the parameters */
-  assert_param(IS_RCC_CLEAR_IT(RCC_IT));
-
-  /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt
-     pending bits */
-  *(__IO uint8_t *) CIR_BYTE3_ADDRESS = RCC_IT;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rtc.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rtc.c
deleted file mode 100644
index f05aef5..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rtc.c
+++ /dev/null
@@ -1,339 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f10x_rtc.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    11-March-2011
-  * @brief   This file provides all the RTC firmware functions.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_rtc.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Driver
-  * @{
-  */
-
-/** @defgroup RTC 
-  * @brief RTC driver modules
-  * @{
-  */
-
-/** @defgroup RTC_Private_TypesDefinitions
-  * @{
-  */ 
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Private_Defines
-  * @{
-  */
-#define RTC_LSB_MASK     ((uint32_t)0x0000FFFF)  /*!< RTC LSB Mask */
-#define PRLH_MSB_MASK    ((uint32_t)0x000F0000)  /*!< RTC Prescaler MSB Mask */
-
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Private_Variables
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Private_FunctionPrototypes
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Enables or disables the specified RTC interrupts.
-  * @param  RTC_IT: specifies the RTC interrupts sources to be enabled or disabled.
-  *   This parameter can be any combination of the following values:
-  *     @arg RTC_IT_OW: Overflow interrupt
-  *     @arg RTC_IT_ALR: Alarm interrupt
-  *     @arg RTC_IT_SEC: Second interrupt
-  * @param  NewState: new state of the specified RTC interrupts.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_RTC_IT(RTC_IT));  
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  
-  if (NewState != DISABLE)
-  {
-    RTC->CRH |= RTC_IT;
-  }
-  else
-  {
-    RTC->CRH &= (uint16_t)~RTC_IT;
-  }
-}
-
-/**
-  * @brief  Enters the RTC configuration mode.
-  * @param  None
-  * @retval None
-  */
-void RTC_EnterConfigMode(void)
-{
-  /* Set the CNF flag to enter in the Configuration Mode */
-  RTC->CRL |= RTC_CRL_CNF;
-}
-
-/**
-  * @brief  Exits from the RTC configuration mode.
-  * @param  None
-  * @retval None
-  */
-void RTC_ExitConfigMode(void)
-{
-  /* Reset the CNF flag to exit from the Configuration Mode */
-  RTC->CRL &= (uint16_t)~((uint16_t)RTC_CRL_CNF); 
-}
-
-/**
-  * @brief  Gets the RTC counter value.
-  * @param  None
-  * @retval RTC counter value.
-  */
-uint32_t RTC_GetCounter(void)
-{
-  uint16_t tmp = 0;
-  tmp = RTC->CNTL;
-  return (((uint32_t)RTC->CNTH << 16 ) | tmp) ;
-}
-
-/**
-  * @brief  Sets the RTC counter value.
-  * @param  CounterValue: RTC counter new value.
-  * @retval None
-  */
-void RTC_SetCounter(uint32_t CounterValue)
-{ 
-  RTC_EnterConfigMode();
-  /* Set RTC COUNTER MSB word */
-  RTC->CNTH = CounterValue >> 16;
-  /* Set RTC COUNTER LSB word */
-  RTC->CNTL = (CounterValue & RTC_LSB_MASK);
-  RTC_ExitConfigMode();
-}
-
-/**
-  * @brief  Sets the RTC prescaler value.
-  * @param  PrescalerValue: RTC prescaler new value.
-  * @retval None
-  */
-void RTC_SetPrescaler(uint32_t PrescalerValue)
-{
-  /* Check the parameters */
-  assert_param(IS_RTC_PRESCALER(PrescalerValue));
-  
-  RTC_EnterConfigMode();
-  /* Set RTC PRESCALER MSB word */
-  RTC->PRLH = (PrescalerValue & PRLH_MSB_MASK) >> 16;
-  /* Set RTC PRESCALER LSB word */
-  RTC->PRLL = (PrescalerValue & RTC_LSB_MASK);
-  RTC_ExitConfigMode();
-}
-
-/**
-  * @brief  Sets the RTC alarm value.
-  * @param  AlarmValue: RTC alarm new value.
-  * @retval None
-  */
-void RTC_SetAlarm(uint32_t AlarmValue)
-{  
-  RTC_EnterConfigMode();
-  /* Set the ALARM MSB word */
-  RTC->ALRH = AlarmValue >> 16;
-  /* Set the ALARM LSB word */
-  RTC->ALRL = (AlarmValue & RTC_LSB_MASK);
-  RTC_ExitConfigMode();
-}
-
-/**
-  * @brief  Gets the RTC divider value.
-  * @param  None
-  * @retval RTC Divider value.
-  */
-uint32_t RTC_GetDivider(void)
-{
-  uint32_t tmp = 0x00;
-  tmp = ((uint32_t)RTC->DIVH & (uint32_t)0x000F) << 16;
-  tmp |= RTC->DIVL;
-  return tmp;
-}
-
-/**
-  * @brief  Waits until last write operation on RTC registers has finished.
-  * @note   This function must be called before any write to RTC registers.
-  * @param  None
-  * @retval None
-  */
-void RTC_WaitForLastTask(void)
-{
-  /* Loop until RTOFF flag is set */
-  while ((RTC->CRL & RTC_FLAG_RTOFF) == (uint16_t)RESET)
-  {
-  }
-}
-
-/**
-  * @brief  Waits until the RTC registers (RTC_CNT, RTC_ALR and RTC_PRL)
-  *   are synchronized with RTC APB clock.
-  * @note   This function must be called before any read operation after an APB reset
-  *   or an APB clock stop.
-  * @param  None
-  * @retval None
-  */
-void RTC_WaitForSynchro(void)
-{
-  /* Clear RSF flag */
-  RTC->CRL &= (uint16_t)~RTC_FLAG_RSF;
-  /* Loop until RSF flag is set */
-  while ((RTC->CRL & RTC_FLAG_RSF) == (uint16_t)RESET)
-  {
-  }
-}
-
-/**
-  * @brief  Checks whether the specified RTC flag is set or not.
-  * @param  RTC_FLAG: specifies the flag to check.
-  *   This parameter can be one the following values:
-  *     @arg RTC_FLAG_RTOFF: RTC Operation OFF flag
-  *     @arg RTC_FLAG_RSF: Registers Synchronized flag
-  *     @arg RTC_FLAG_OW: Overflow flag
-  *     @arg RTC_FLAG_ALR: Alarm flag
-  *     @arg RTC_FLAG_SEC: Second flag
-  * @retval The new state of RTC_FLAG (SET or RESET).
-  */
-FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG)
-{
-  FlagStatus bitstatus = RESET;
-  
-  /* Check the parameters */
-  assert_param(IS_RTC_GET_FLAG(RTC_FLAG)); 
-  
-  if ((RTC->CRL & RTC_FLAG) != (uint16_t)RESET)
-  {
-    bitstatus = SET;
-  }
-  else
-  {
-    bitstatus = RESET;
-  }
-  return bitstatus;
-}
-
-/**
-  * @brief  Clears the RTC's pending flags.
-  * @param  RTC_FLAG: specifies the flag to clear.
-  *   This parameter can be any combination of the following values:
-  *     @arg RTC_FLAG_RSF: Registers Synchronized flag. This flag is cleared only after
-  *                        an APB reset or an APB Clock stop.
-  *     @arg RTC_FLAG_OW: Overflow flag
-  *     @arg RTC_FLAG_ALR: Alarm flag
-  *     @arg RTC_FLAG_SEC: Second flag
-  * @retval None
-  */
-void RTC_ClearFlag(uint16_t RTC_FLAG)
-{
-  /* Check the parameters */
-  assert_param(IS_RTC_CLEAR_FLAG(RTC_FLAG)); 
-    
-  /* Clear the corresponding RTC flag */
-  RTC->CRL &= (uint16_t)~RTC_FLAG;
-}
-
-/**
-  * @brief  Checks whether the specified RTC interrupt has occurred or not.
-  * @param  RTC_IT: specifies the RTC interrupts sources to check.
-  *   This parameter can be one of the following values:
-  *     @arg RTC_IT_OW: Overflow interrupt
-  *     @arg RTC_IT_ALR: Alarm interrupt
-  *     @arg RTC_IT_SEC: Second interrupt
-  * @retval The new state of the RTC_IT (SET or RESET).
-  */
-ITStatus RTC_GetITStatus(uint16_t RTC_IT)
-{
-  ITStatus bitstatus = RESET;
-  /* Check the parameters */
-  assert_param(IS_RTC_GET_IT(RTC_IT)); 
-  
-  bitstatus = (ITStatus)(RTC->CRL & RTC_IT);
-  if (((RTC->CRH & RTC_IT) != (uint16_t)RESET) && (bitstatus != (uint16_t)RESET))
-  {
-    bitstatus = SET;
-  }
-  else
-  {
-    bitstatus = RESET;
-  }
-  return bitstatus;
-}
-
-/**
-  * @brief  Clears the RTC's interrupt pending bits.
-  * @param  RTC_IT: specifies the interrupt pending bit to clear.
-  *   This parameter can be any combination of the following values:
-  *     @arg RTC_IT_OW: Overflow interrupt
-  *     @arg RTC_IT_ALR: Alarm interrupt
-  *     @arg RTC_IT_SEC: Second interrupt
-  * @retval None
-  */
-void RTC_ClearITPendingBit(uint16_t RTC_IT)
-{
-  /* Check the parameters */
-  assert_param(IS_RTC_IT(RTC_IT));  
-  
-  /* Clear the corresponding RTC pending bit */
-  RTC->CRL &= (uint16_t)~RTC_IT;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c
deleted file mode 100644
index 4ec65b2..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c
+++ /dev/null
@@ -1,908 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f10x_spi.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    11-March-2011
-  * @brief   This file provides all the SPI firmware functions.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_spi.h"
-#include "stm32f10x_rcc.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Driver
-  * @{
-  */
-
-/** @defgroup SPI 
-  * @brief SPI driver modules
-  * @{
-  */ 
-
-/** @defgroup SPI_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */ 
-
-
-/** @defgroup SPI_Private_Defines
-  * @{
-  */
-
-/* SPI SPE mask */
-#define CR1_SPE_Set          ((uint16_t)0x0040)
-#define CR1_SPE_Reset        ((uint16_t)0xFFBF)
-
-/* I2S I2SE mask */
-#define I2SCFGR_I2SE_Set     ((uint16_t)0x0400)
-#define I2SCFGR_I2SE_Reset   ((uint16_t)0xFBFF)
-
-/* SPI CRCNext mask */
-#define CR1_CRCNext_Set      ((uint16_t)0x1000)
-
-/* SPI CRCEN mask */
-#define CR1_CRCEN_Set        ((uint16_t)0x2000)
-#define CR1_CRCEN_Reset      ((uint16_t)0xDFFF)
-
-/* SPI SSOE mask */
-#define CR2_SSOE_Set         ((uint16_t)0x0004)
-#define CR2_SSOE_Reset       ((uint16_t)0xFFFB)
-
-/* SPI registers Masks */
-#define CR1_CLEAR_Mask       ((uint16_t)0x3040)
-#define I2SCFGR_CLEAR_Mask   ((uint16_t)0xF040)
-
-/* SPI or I2S mode selection masks */
-#define SPI_Mode_Select      ((uint16_t)0xF7FF)
-#define I2S_Mode_Select      ((uint16_t)0x0800) 
-
-/* I2S clock source selection masks */
-#define I2S2_CLOCK_SRC       ((uint32_t)(0x00020000))
-#define I2S3_CLOCK_SRC       ((uint32_t)(0x00040000))
-#define I2S_MUL_MASK         ((uint32_t)(0x0000F000))
-#define I2S_DIV_MASK         ((uint32_t)(0x000000F0))
-
-/**
-  * @}
-  */
-
-/** @defgroup SPI_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup SPI_Private_Variables
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup SPI_Private_FunctionPrototypes
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup SPI_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Deinitializes the SPIx peripheral registers to their default
-  *         reset values (Affects also the I2Ss).
-  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
-  * @retval None
-  */
-void SPI_I2S_DeInit(SPI_TypeDef* SPIx)
-{
-  /* Check the parameters */
-  assert_param(IS_SPI_ALL_PERIPH(SPIx));
-
-  if (SPIx == SPI1)
-  {
-    /* Enable SPI1 reset state */
-    RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE);
-    /* Release SPI1 from reset state */
-    RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE);
-  }
-  else if (SPIx == SPI2)
-  {
-    /* Enable SPI2 reset state */
-    RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE);
-    /* Release SPI2 from reset state */
-    RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE);
-  }
-  else
-  {
-    if (SPIx == SPI3)
-    {
-      /* Enable SPI3 reset state */
-      RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE);
-      /* Release SPI3 from reset state */
-      RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, DISABLE);
-    }
-  }
-}
-
-/**
-  * @brief  Initializes the SPIx peripheral according to the specified 
-  *         parameters in the SPI_InitStruct.
-  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
-  * @param  SPI_InitStruct: pointer to a SPI_InitTypeDef structure that
-  *         contains the configuration information for the specified SPI peripheral.
-  * @retval None
-  */
-void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct)
-{
-  uint16_t tmpreg = 0;
-  
-  /* check the parameters */
-  assert_param(IS_SPI_ALL_PERIPH(SPIx));   
-  
-  /* Check the SPI parameters */
-  assert_param(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction));
-  assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode));
-  assert_param(IS_SPI_DATASIZE(SPI_InitStruct->SPI_DataSize));
-  assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL));
-  assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA));
-  assert_param(IS_SPI_NSS(SPI_InitStruct->SPI_NSS));
-  assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler));
-  assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit));
-  assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->SPI_CRCPolynomial));
-
-/*---------------------------- SPIx CR1 Configuration ------------------------*/
-  /* Get the SPIx CR1 value */
-  tmpreg = SPIx->CR1;
-  /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */
-  tmpreg &= CR1_CLEAR_Mask;
-  /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler
-     master/salve mode, CPOL and CPHA */
-  /* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */
-  /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */
-  /* Set LSBFirst bit according to SPI_FirstBit value */
-  /* Set BR bits according to SPI_BaudRatePrescaler value */
-  /* Set CPOL bit according to SPI_CPOL value */
-  /* Set CPHA bit according to SPI_CPHA value */
-  tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode |
-                  SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL |  
-                  SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS |  
-                  SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit);
-  /* Write to SPIx CR1 */
-  SPIx->CR1 = tmpreg;
-  
-  /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
-  SPIx->I2SCFGR &= SPI_Mode_Select;		
-
-/*---------------------------- SPIx CRCPOLY Configuration --------------------*/
-  /* Write to SPIx CRCPOLY */
-  SPIx->CRCPR = SPI_InitStruct->SPI_CRCPolynomial;
-}
-
-/**
-  * @brief  Initializes the SPIx peripheral according to the specified 
-  *         parameters in the I2S_InitStruct.
-  * @param  SPIx: where x can be  2 or 3 to select the SPI peripheral
-  *         (configured in I2S mode).
-  * @param  I2S_InitStruct: pointer to an I2S_InitTypeDef structure that
-  *         contains the configuration information for the specified SPI peripheral
-  *         configured in I2S mode.
-  * @note
-  *  The function calculates the optimal prescaler needed to obtain the most 
-  *  accurate audio frequency (depending on the I2S clock source, the PLL values 
-  *  and the product configuration). But in case the prescaler value is greater 
-  *  than 511, the default value (0x02) will be configured instead.  *   
-  * @retval None
-  */
-void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct)
-{
-  uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1;
-  uint32_t tmp = 0;
-  RCC_ClocksTypeDef RCC_Clocks;
-  uint32_t sourceclock = 0;
-  
-  /* Check the I2S parameters */
-  assert_param(IS_SPI_23_PERIPH(SPIx));
-  assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode));
-  assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard));
-  assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat));
-  assert_param(IS_I2S_MCLK_OUTPUT(I2S_InitStruct->I2S_MCLKOutput));
-  assert_param(IS_I2S_AUDIO_FREQ(I2S_InitStruct->I2S_AudioFreq));
-  assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL));  
-
-/*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/
-  /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
-  SPIx->I2SCFGR &= I2SCFGR_CLEAR_Mask; 
-  SPIx->I2SPR = 0x0002;
-  
-  /* Get the I2SCFGR register value */
-  tmpreg = SPIx->I2SCFGR;
-  
-  /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/
-  if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default)
-  {
-    i2sodd = (uint16_t)0;
-    i2sdiv = (uint16_t)2;   
-  }
-  /* If the requested audio frequency is not the default, compute the prescaler */
-  else
-  {
-    /* Check the frame length (For the Prescaler computing) */
-    if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b)
-    {
-      /* Packet length is 16 bits */
-      packetlength = 1;
-    }
-    else
-    {
-      /* Packet length is 32 bits */
-      packetlength = 2;
-    }
-
-    /* Get the I2S clock source mask depending on the peripheral number */
-    if(((uint32_t)SPIx) == SPI2_BASE)
-    {
-      /* The mask is relative to I2S2 */
-      tmp = I2S2_CLOCK_SRC;
-    }
-    else 
-    {
-      /* The mask is relative to I2S3 */      
-      tmp = I2S3_CLOCK_SRC;
-    }
-
-    /* Check the I2S clock source configuration depending on the Device:
-       Only Connectivity line devices have the PLL3 VCO clock */
-#ifdef STM32F10X_CL
-    if((RCC->CFGR2 & tmp) != 0)
-    {
-      /* Get the configuration bits of RCC PLL3 multiplier */
-      tmp = (uint32_t)((RCC->CFGR2 & I2S_MUL_MASK) >> 12);
-
-      /* Get the value of the PLL3 multiplier */      
-      if((tmp > 5) && (tmp < 15))
-      {
-        /* Multiplier is between 8 and 14 (value 15 is forbidden) */
-        tmp += 2;
-      }
-      else
-      {
-        if (tmp == 15)
-        {
-          /* Multiplier is 20 */
-          tmp = 20;
-        }
-      }      
-      /* Get the PREDIV2 value */
-      sourceclock = (uint32_t)(((RCC->CFGR2 & I2S_DIV_MASK) >> 4) + 1);
-      
-      /* Calculate the Source Clock frequency based on PLL3 and PREDIV2 values */
-      sourceclock = (uint32_t) ((HSE_Value / sourceclock) * tmp * 2); 
-    }
-    else
-    {
-      /* I2S Clock source is System clock: Get System Clock frequency */
-      RCC_GetClocksFreq(&RCC_Clocks);      
-      
-      /* Get the source clock value: based on System Clock value */
-      sourceclock = RCC_Clocks.SYSCLK_Frequency;
-    }        
-#else /* STM32F10X_HD */
-    /* I2S Clock source is System clock: Get System Clock frequency */
-    RCC_GetClocksFreq(&RCC_Clocks);      
-      
-    /* Get the source clock value: based on System Clock value */
-    sourceclock = RCC_Clocks.SYSCLK_Frequency;    
-#endif /* STM32F10X_CL */    
-
-    /* Compute the Real divider depending on the MCLK output state with a floating point */
-    if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable)
-    {
-      /* MCLK output is enabled */
-      tmp = (uint16_t)(((((sourceclock / 256) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5);
-    }
-    else
-    {
-      /* MCLK output is disabled */
-      tmp = (uint16_t)(((((sourceclock / (32 * packetlength)) *10 ) / I2S_InitStruct->I2S_AudioFreq)) + 5);
-    }
-    
-    /* Remove the floating point */
-    tmp = tmp / 10;  
-      
-    /* Check the parity of the divider */
-    i2sodd = (uint16_t)(tmp & (uint16_t)0x0001);
-   
-    /* Compute the i2sdiv prescaler */
-    i2sdiv = (uint16_t)((tmp - i2sodd) / 2);
-   
-    /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
-    i2sodd = (uint16_t) (i2sodd << 8);
-  }
-  
-  /* Test if the divider is 1 or 0 or greater than 0xFF */
-  if ((i2sdiv < 2) || (i2sdiv > 0xFF))
-  {
-    /* Set the default values */
-    i2sdiv = 2;
-    i2sodd = 0;
-  }
-
-  /* Write to SPIx I2SPR register the computed value */
-  SPIx->I2SPR = (uint16_t)(i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->I2S_MCLKOutput));  
- 
-  /* Configure the I2S with the SPI_InitStruct values */
-  tmpreg |= (uint16_t)(I2S_Mode_Select | (uint16_t)(I2S_InitStruct->I2S_Mode | \
-                  (uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | \
-                  (uint16_t)I2S_InitStruct->I2S_CPOL))));
- 
-  /* Write to SPIx I2SCFGR */  
-  SPIx->I2SCFGR = tmpreg;   
-}
-
-/**
-  * @brief  Fills each SPI_InitStruct member with its default value.
-  * @param  SPI_InitStruct : pointer to a SPI_InitTypeDef structure which will be initialized.
-  * @retval None
-  */
-void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct)
-{
-/*--------------- Reset SPI init structure parameters values -----------------*/
-  /* Initialize the SPI_Direction member */
-  SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex;
-  /* initialize the SPI_Mode member */
-  SPI_InitStruct->SPI_Mode = SPI_Mode_Slave;
-  /* initialize the SPI_DataSize member */
-  SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b;
-  /* Initialize the SPI_CPOL member */
-  SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low;
-  /* Initialize the SPI_CPHA member */
-  SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge;
-  /* Initialize the SPI_NSS member */
-  SPI_InitStruct->SPI_NSS = SPI_NSS_Hard;
-  /* Initialize the SPI_BaudRatePrescaler member */
-  SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
-  /* Initialize the SPI_FirstBit member */
-  SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB;
-  /* Initialize the SPI_CRCPolynomial member */
-  SPI_InitStruct->SPI_CRCPolynomial = 7;
-}
-
-/**
-  * @brief  Fills each I2S_InitStruct member with its default value.
-  * @param  I2S_InitStruct : pointer to a I2S_InitTypeDef structure which will be initialized.
-  * @retval None
-  */
-void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct)
-{
-/*--------------- Reset I2S init structure parameters values -----------------*/
-  /* Initialize the I2S_Mode member */
-  I2S_InitStruct->I2S_Mode = I2S_Mode_SlaveTx;
-  
-  /* Initialize the I2S_Standard member */
-  I2S_InitStruct->I2S_Standard = I2S_Standard_Phillips;
-  
-  /* Initialize the I2S_DataFormat member */
-  I2S_InitStruct->I2S_DataFormat = I2S_DataFormat_16b;
-  
-  /* Initialize the I2S_MCLKOutput member */
-  I2S_InitStruct->I2S_MCLKOutput = I2S_MCLKOutput_Disable;
-  
-  /* Initialize the I2S_AudioFreq member */
-  I2S_InitStruct->I2S_AudioFreq = I2S_AudioFreq_Default;
-  
-  /* Initialize the I2S_CPOL member */
-  I2S_InitStruct->I2S_CPOL = I2S_CPOL_Low;
-}
-
-/**
-  * @brief  Enables or disables the specified SPI peripheral.
-  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
-  * @param  NewState: new state of the SPIx peripheral. 
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_SPI_ALL_PERIPH(SPIx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  if (NewState != DISABLE)
-  {
-    /* Enable the selected SPI peripheral */
-    SPIx->CR1 |= CR1_SPE_Set;
-  }
-  else
-  {
-    /* Disable the selected SPI peripheral */
-    SPIx->CR1 &= CR1_SPE_Reset;
-  }
-}
-
-/**
-  * @brief  Enables or disables the specified SPI peripheral (in I2S mode).
-  * @param  SPIx: where x can be 2 or 3 to select the SPI peripheral.
-  * @param  NewState: new state of the SPIx peripheral. 
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_SPI_23_PERIPH(SPIx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  if (NewState != DISABLE)
-  {
-    /* Enable the selected SPI peripheral (in I2S mode) */
-    SPIx->I2SCFGR |= I2SCFGR_I2SE_Set;
-  }
-  else
-  {
-    /* Disable the selected SPI peripheral (in I2S mode) */
-    SPIx->I2SCFGR &= I2SCFGR_I2SE_Reset;
-  }
-}
-
-/**
-  * @brief  Enables or disables the specified SPI/I2S interrupts.
-  * @param  SPIx: where x can be
-  *   - 1, 2 or 3 in SPI mode 
-  *   - 2 or 3 in I2S mode
-  * @param  SPI_I2S_IT: specifies the SPI/I2S interrupt source to be enabled or disabled. 
-  *   This parameter can be one of the following values:
-  *     @arg SPI_I2S_IT_TXE: Tx buffer empty interrupt mask
-  *     @arg SPI_I2S_IT_RXNE: Rx buffer not empty interrupt mask
-  *     @arg SPI_I2S_IT_ERR: Error interrupt mask
-  * @param  NewState: new state of the specified SPI/I2S interrupt.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState)
-{
-  uint16_t itpos = 0, itmask = 0 ;
-  /* Check the parameters */
-  assert_param(IS_SPI_ALL_PERIPH(SPIx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  assert_param(IS_SPI_I2S_CONFIG_IT(SPI_I2S_IT));
-
-  /* Get the SPI/I2S IT index */
-  itpos = SPI_I2S_IT >> 4;
-
-  /* Set the IT mask */
-  itmask = (uint16_t)1 << (uint16_t)itpos;
-
-  if (NewState != DISABLE)
-  {
-    /* Enable the selected SPI/I2S interrupt */
-    SPIx->CR2 |= itmask;
-  }
-  else
-  {
-    /* Disable the selected SPI/I2S interrupt */
-    SPIx->CR2 &= (uint16_t)~itmask;
-  }
-}
-
-/**
-  * @brief  Enables or disables the SPIx/I2Sx DMA interface.
-  * @param  SPIx: where x can be
-  *   - 1, 2 or 3 in SPI mode 
-  *   - 2 or 3 in I2S mode
-  * @param  SPI_I2S_DMAReq: specifies the SPI/I2S DMA transfer request to be enabled or disabled. 
-  *   This parameter can be any combination of the following values:
-  *     @arg SPI_I2S_DMAReq_Tx: Tx buffer DMA transfer request
-  *     @arg SPI_I2S_DMAReq_Rx: Rx buffer DMA transfer request
-  * @param  NewState: new state of the selected SPI/I2S DMA transfer request.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_SPI_ALL_PERIPH(SPIx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  assert_param(IS_SPI_I2S_DMAREQ(SPI_I2S_DMAReq));
-  if (NewState != DISABLE)
-  {
-    /* Enable the selected SPI/I2S DMA requests */
-    SPIx->CR2 |= SPI_I2S_DMAReq;
-  }
-  else
-  {
-    /* Disable the selected SPI/I2S DMA requests */
-    SPIx->CR2 &= (uint16_t)~SPI_I2S_DMAReq;
-  }
-}
-
-/**
-  * @brief  Transmits a Data through the SPIx/I2Sx peripheral.
-  * @param  SPIx: where x can be
-  *   - 1, 2 or 3 in SPI mode 
-  *   - 2 or 3 in I2S mode
-  * @param  Data : Data to be transmitted.
-  * @retval None
-  */
-void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data)
-{
-  /* Check the parameters */
-  assert_param(IS_SPI_ALL_PERIPH(SPIx));
-  
-  /* Write in the DR register the data to be sent */
-  SPIx->DR = Data;
-}
-
-/**
-  * @brief  Returns the most recent received data by the SPIx/I2Sx peripheral. 
-  * @param  SPIx: where x can be
-  *   - 1, 2 or 3 in SPI mode 
-  *   - 2 or 3 in I2S mode
-  * @retval The value of the received data.
-  */
-uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx)
-{
-  /* Check the parameters */
-  assert_param(IS_SPI_ALL_PERIPH(SPIx));
-  
-  /* Return the data in the DR register */
-  return SPIx->DR;
-}
-
-/**
-  * @brief  Configures internally by software the NSS pin for the selected SPI.
-  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
-  * @param  SPI_NSSInternalSoft: specifies the SPI NSS internal state.
-  *   This parameter can be one of the following values:
-  *     @arg SPI_NSSInternalSoft_Set: Set NSS pin internally
-  *     @arg SPI_NSSInternalSoft_Reset: Reset NSS pin internally
-  * @retval None
-  */
-void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft)
-{
-  /* Check the parameters */
-  assert_param(IS_SPI_ALL_PERIPH(SPIx));
-  assert_param(IS_SPI_NSS_INTERNAL(SPI_NSSInternalSoft));
-  if (SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset)
-  {
-    /* Set NSS pin internally by software */
-    SPIx->CR1 |= SPI_NSSInternalSoft_Set;
-  }
-  else
-  {
-    /* Reset NSS pin internally by software */
-    SPIx->CR1 &= SPI_NSSInternalSoft_Reset;
-  }
-}
-
-/**
-  * @brief  Enables or disables the SS output for the selected SPI.
-  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
-  * @param  NewState: new state of the SPIx SS output. 
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_SPI_ALL_PERIPH(SPIx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  if (NewState != DISABLE)
-  {
-    /* Enable the selected SPI SS output */
-    SPIx->CR2 |= CR2_SSOE_Set;
-  }
-  else
-  {
-    /* Disable the selected SPI SS output */
-    SPIx->CR2 &= CR2_SSOE_Reset;
-  }
-}
-
-/**
-  * @brief  Configures the data size for the selected SPI.
-  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
-  * @param  SPI_DataSize: specifies the SPI data size.
-  *   This parameter can be one of the following values:
-  *     @arg SPI_DataSize_16b: Set data frame format to 16bit
-  *     @arg SPI_DataSize_8b: Set data frame format to 8bit
-  * @retval None
-  */
-void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize)
-{
-  /* Check the parameters */
-  assert_param(IS_SPI_ALL_PERIPH(SPIx));
-  assert_param(IS_SPI_DATASIZE(SPI_DataSize));
-  /* Clear DFF bit */
-  SPIx->CR1 &= (uint16_t)~SPI_DataSize_16b;
-  /* Set new DFF bit value */
-  SPIx->CR1 |= SPI_DataSize;
-}
-
-/**
-  * @brief  Transmit the SPIx CRC value.
-  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
-  * @retval None
-  */
-void SPI_TransmitCRC(SPI_TypeDef* SPIx)
-{
-  /* Check the parameters */
-  assert_param(IS_SPI_ALL_PERIPH(SPIx));
-  
-  /* Enable the selected SPI CRC transmission */
-  SPIx->CR1 |= CR1_CRCNext_Set;
-}
-
-/**
-  * @brief  Enables or disables the CRC value calculation of the transferred bytes.
-  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
-  * @param  NewState: new state of the SPIx CRC value calculation.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_SPI_ALL_PERIPH(SPIx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  if (NewState != DISABLE)
-  {
-    /* Enable the selected SPI CRC calculation */
-    SPIx->CR1 |= CR1_CRCEN_Set;
-  }
-  else
-  {
-    /* Disable the selected SPI CRC calculation */
-    SPIx->CR1 &= CR1_CRCEN_Reset;
-  }
-}
-
-/**
-  * @brief  Returns the transmit or the receive CRC register value for the specified SPI.
-  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
-  * @param  SPI_CRC: specifies the CRC register to be read.
-  *   This parameter can be one of the following values:
-  *     @arg SPI_CRC_Tx: Selects Tx CRC register
-  *     @arg SPI_CRC_Rx: Selects Rx CRC register
-  * @retval The selected CRC register value..
-  */
-uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC)
-{
-  uint16_t crcreg = 0;
-  /* Check the parameters */
-  assert_param(IS_SPI_ALL_PERIPH(SPIx));
-  assert_param(IS_SPI_CRC(SPI_CRC));
-  if (SPI_CRC != SPI_CRC_Rx)
-  {
-    /* Get the Tx CRC register */
-    crcreg = SPIx->TXCRCR;
-  }
-  else
-  {
-    /* Get the Rx CRC register */
-    crcreg = SPIx->RXCRCR;
-  }
-  /* Return the selected CRC register */
-  return crcreg;
-}
-
-/**
-  * @brief  Returns the CRC Polynomial register value for the specified SPI.
-  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
-  * @retval The CRC Polynomial register value.
-  */
-uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx)
-{
-  /* Check the parameters */
-  assert_param(IS_SPI_ALL_PERIPH(SPIx));
-  
-  /* Return the CRC polynomial register */
-  return SPIx->CRCPR;
-}
-
-/**
-  * @brief  Selects the data transfer direction in bi-directional mode for the specified SPI.
-  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
-  * @param  SPI_Direction: specifies the data transfer direction in bi-directional mode. 
-  *   This parameter can be one of the following values:
-  *     @arg SPI_Direction_Tx: Selects Tx transmission direction
-  *     @arg SPI_Direction_Rx: Selects Rx receive direction
-  * @retval None
-  */
-void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction)
-{
-  /* Check the parameters */
-  assert_param(IS_SPI_ALL_PERIPH(SPIx));
-  assert_param(IS_SPI_DIRECTION(SPI_Direction));
-  if (SPI_Direction == SPI_Direction_Tx)
-  {
-    /* Set the Tx only mode */
-    SPIx->CR1 |= SPI_Direction_Tx;
-  }
-  else
-  {
-    /* Set the Rx only mode */
-    SPIx->CR1 &= SPI_Direction_Rx;
-  }
-}
-
-/**
-  * @brief  Checks whether the specified SPI/I2S flag is set or not.
-  * @param  SPIx: where x can be
-  *   - 1, 2 or 3 in SPI mode 
-  *   - 2 or 3 in I2S mode
-  * @param  SPI_I2S_FLAG: specifies the SPI/I2S flag to check. 
-  *   This parameter can be one of the following values:
-  *     @arg SPI_I2S_FLAG_TXE: Transmit buffer empty flag.
-  *     @arg SPI_I2S_FLAG_RXNE: Receive buffer not empty flag.
-  *     @arg SPI_I2S_FLAG_BSY: Busy flag.
-  *     @arg SPI_I2S_FLAG_OVR: Overrun flag.
-  *     @arg SPI_FLAG_MODF: Mode Fault flag.
-  *     @arg SPI_FLAG_CRCERR: CRC Error flag.
-  *     @arg I2S_FLAG_UDR: Underrun Error flag.
-  *     @arg I2S_FLAG_CHSIDE: Channel Side flag.
-  * @retval The new state of SPI_I2S_FLAG (SET or RESET).
-  */
-FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)
-{
-  FlagStatus bitstatus = RESET;
-  /* Check the parameters */
-  assert_param(IS_SPI_ALL_PERIPH(SPIx));
-  assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG));
-  /* Check the status of the specified SPI/I2S flag */
-  if ((SPIx->SR & SPI_I2S_FLAG) != (uint16_t)RESET)
-  {
-    /* SPI_I2S_FLAG is set */
-    bitstatus = SET;
-  }
-  else
-  {
-    /* SPI_I2S_FLAG is reset */
-    bitstatus = RESET;
-  }
-  /* Return the SPI_I2S_FLAG status */
-  return  bitstatus;
-}
-
-/**
-  * @brief  Clears the SPIx CRC Error (CRCERR) flag.
-  * @param  SPIx: where x can be
-  *   - 1, 2 or 3 in SPI mode 
-  * @param  SPI_I2S_FLAG: specifies the SPI flag to clear. 
-  *   This function clears only CRCERR flag.
-  * @note
-  *   - OVR (OverRun error) flag is cleared by software sequence: a read 
-  *     operation to SPI_DR register (SPI_I2S_ReceiveData()) followed by a read 
-  *     operation to SPI_SR register (SPI_I2S_GetFlagStatus()).
-  *   - UDR (UnderRun error) flag is cleared by a read operation to 
-  *     SPI_SR register (SPI_I2S_GetFlagStatus()).
-  *   - MODF (Mode Fault) flag is cleared by software sequence: a read/write 
-  *     operation to SPI_SR register (SPI_I2S_GetFlagStatus()) followed by a 
-  *     write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI).
-  * @retval None
-  */
-void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)
-{
-  /* Check the parameters */
-  assert_param(IS_SPI_ALL_PERIPH(SPIx));
-  assert_param(IS_SPI_I2S_CLEAR_FLAG(SPI_I2S_FLAG));
-    
-    /* Clear the selected SPI CRC Error (CRCERR) flag */
-    SPIx->SR = (uint16_t)~SPI_I2S_FLAG;
-}
-
-/**
-  * @brief  Checks whether the specified SPI/I2S interrupt has occurred or not.
-  * @param  SPIx: where x can be
-  *   - 1, 2 or 3 in SPI mode 
-  *   - 2 or 3 in I2S mode
-  * @param  SPI_I2S_IT: specifies the SPI/I2S interrupt source to check. 
-  *   This parameter can be one of the following values:
-  *     @arg SPI_I2S_IT_TXE: Transmit buffer empty interrupt.
-  *     @arg SPI_I2S_IT_RXNE: Receive buffer not empty interrupt.
-  *     @arg SPI_I2S_IT_OVR: Overrun interrupt.
-  *     @arg SPI_IT_MODF: Mode Fault interrupt.
-  *     @arg SPI_IT_CRCERR: CRC Error interrupt.
-  *     @arg I2S_IT_UDR: Underrun Error interrupt.
-  * @retval The new state of SPI_I2S_IT (SET or RESET).
-  */
-ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT)
-{
-  ITStatus bitstatus = RESET;
-  uint16_t itpos = 0, itmask = 0, enablestatus = 0;
-
-  /* Check the parameters */
-  assert_param(IS_SPI_ALL_PERIPH(SPIx));
-  assert_param(IS_SPI_I2S_GET_IT(SPI_I2S_IT));
-
-  /* Get the SPI/I2S IT index */
-  itpos = 0x01 << (SPI_I2S_IT & 0x0F);
-
-  /* Get the SPI/I2S IT mask */
-  itmask = SPI_I2S_IT >> 4;
-
-  /* Set the IT mask */
-  itmask = 0x01 << itmask;
-
-  /* Get the SPI_I2S_IT enable bit status */
-  enablestatus = (SPIx->CR2 & itmask) ;
-
-  /* Check the status of the specified SPI/I2S interrupt */
-  if (((SPIx->SR & itpos) != (uint16_t)RESET) && enablestatus)
-  {
-    /* SPI_I2S_IT is set */
-    bitstatus = SET;
-  }
-  else
-  {
-    /* SPI_I2S_IT is reset */
-    bitstatus = RESET;
-  }
-  /* Return the SPI_I2S_IT status */
-  return bitstatus;
-}
-
-/**
-  * @brief  Clears the SPIx CRC Error (CRCERR) interrupt pending bit.
-  * @param  SPIx: where x can be
-  *   - 1, 2 or 3 in SPI mode 
-  * @param  SPI_I2S_IT: specifies the SPI interrupt pending bit to clear.
-  *   This function clears only CRCERR interrupt pending bit.   
-  * @note
-  *   - OVR (OverRun Error) interrupt pending bit is cleared by software 
-  *     sequence: a read operation to SPI_DR register (SPI_I2S_ReceiveData()) 
-  *     followed by a read operation to SPI_SR register (SPI_I2S_GetITStatus()).
-  *   - UDR (UnderRun Error) interrupt pending bit is cleared by a read 
-  *     operation to SPI_SR register (SPI_I2S_GetITStatus()).
-  *   - MODF (Mode Fault) interrupt pending bit is cleared by software sequence:
-  *     a read/write operation to SPI_SR register (SPI_I2S_GetITStatus()) 
-  *     followed by a write operation to SPI_CR1 register (SPI_Cmd() to enable 
-  *     the SPI).
-  * @retval None
-  */
-void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT)
-{
-  uint16_t itpos = 0;
-  /* Check the parameters */
-  assert_param(IS_SPI_ALL_PERIPH(SPIx));
-  assert_param(IS_SPI_I2S_CLEAR_IT(SPI_I2S_IT));
-
-  /* Get the SPI IT index */
-  itpos = 0x01 << (SPI_I2S_IT & 0x0F);
-
-  /* Clear the selected SPI CRC Error (CRCERR) interrupt pending bit */
-  SPIx->SR = (uint16_t)~itpos;
-}
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.c
deleted file mode 100644
index bfb4dd1..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.c
+++ /dev/null
@@ -1,2890 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f10x_tim.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    11-March-2011
-  * @brief   This file provides all the TIM firmware functions.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_tim.h"
-#include "stm32f10x_rcc.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Driver
-  * @{
-  */
-
-/** @defgroup TIM 
-  * @brief TIM driver modules
-  * @{
-  */
-
-/** @defgroup TIM_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Private_Defines
-  * @{
-  */
-
-/* ---------------------- TIM registers bit mask ------------------------ */
-#define SMCR_ETR_Mask               ((uint16_t)0x00FF) 
-#define CCMR_Offset                 ((uint16_t)0x0018)
-#define CCER_CCE_Set                ((uint16_t)0x0001)  
-#define	CCER_CCNE_Set               ((uint16_t)0x0004) 
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Private_Variables
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Private_FunctionPrototypes
-  * @{
-  */
-
-static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
-                       uint16_t TIM_ICFilter);
-static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
-                       uint16_t TIM_ICFilter);
-static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
-                       uint16_t TIM_ICFilter);
-static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
-                       uint16_t TIM_ICFilter);
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Private_Variables
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Private_FunctionPrototypes
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Deinitializes the TIMx peripheral registers to their default reset values.
-  * @param  TIMx: where x can be 1 to 17 to select the TIM peripheral.
-  * @retval None
-  */
-void TIM_DeInit(TIM_TypeDef* TIMx)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_ALL_PERIPH(TIMx)); 
- 
-  if (TIMx == TIM1)
-  {
-    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE);
-    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE);  
-  }     
-  else if (TIMx == TIM2)
-  {
-    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE);
-    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE);
-  }
-  else if (TIMx == TIM3)
-  {
-    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE);
-    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE);
-  }
-  else if (TIMx == TIM4)
-  {
-    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE);
-    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE);
-  } 
-  else if (TIMx == TIM5)
-  {
-    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, ENABLE);
-    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, DISABLE);
-  } 
-  else if (TIMx == TIM6)
-  {
-    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE);
-    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE);
-  } 
-  else if (TIMx == TIM7)
-  {
-    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE);
-    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE);
-  } 
-  else if (TIMx == TIM8)
-  {
-    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, ENABLE);
-    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, DISABLE);
-  }
-  else if (TIMx == TIM9)
-  {      
-    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, ENABLE);
-    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, DISABLE);  
-   }  
-  else if (TIMx == TIM10)
-  {      
-    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, ENABLE);
-    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, DISABLE);  
-  }  
-  else if (TIMx == TIM11) 
-  {     
-    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, ENABLE);
-    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, DISABLE);  
-  }  
-  else if (TIMx == TIM12)
-  {      
-    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, ENABLE);
-    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, DISABLE);  
-  }  
-  else if (TIMx == TIM13) 
-  {       
-    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, ENABLE);
-    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, DISABLE);  
-  }
-  else if (TIMx == TIM14) 
-  {       
-    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, ENABLE);
-    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, DISABLE);  
-  }        
-  else if (TIMx == TIM15)
-  {
-    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, ENABLE);
-    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, DISABLE);
-  } 
-  else if (TIMx == TIM16)
-  {
-    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, ENABLE);
-    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, DISABLE);
-  } 
-  else
-  {
-    if (TIMx == TIM17)
-    {
-      RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, ENABLE);
-      RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, DISABLE);
-    }  
-  }
-}
-
-/**
-  * @brief  Initializes the TIMx Time Base Unit peripheral according to 
-  *         the specified parameters in the TIM_TimeBaseInitStruct.
-  * @param  TIMx: where x can be 1 to 17 to select the TIM peripheral.
-  * @param  TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef
-  *         structure that contains the configuration information for the 
-  *         specified TIM peripheral.
-  * @retval None
-  */
-void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
-{
-  uint16_t tmpcr1 = 0;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_ALL_PERIPH(TIMx)); 
-  assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode));
-  assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision));
-
-  tmpcr1 = TIMx->CR1;  
-
-  if((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM2) || (TIMx == TIM3)||
-     (TIMx == TIM4) || (TIMx == TIM5)) 
-  {
-    /* Select the Counter Mode */
-    tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS)));
-    tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode;
-  }
- 
-  if((TIMx != TIM6) && (TIMx != TIM7))
-  {
-    /* Set the clock division */
-    tmpcr1 &= (uint16_t)(~((uint16_t)TIM_CR1_CKD));
-    tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision;
-  }
-
-  TIMx->CR1 = tmpcr1;
-
-  /* Set the Autoreload value */
-  TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ;
- 
-  /* Set the Prescaler value */
-  TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler;
-    
-  if ((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM15)|| (TIMx == TIM16) || (TIMx == TIM17))  
-  {
-    /* Set the Repetition Counter value */
-    TIMx->RCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter;
-  }
-
-  /* Generate an update event to reload the Prescaler and the Repetition counter
-     values immediately */
-  TIMx->EGR = TIM_PSCReloadMode_Immediate;           
-}
-
-/**
-  * @brief  Initializes the TIMx Channel1 according to the specified
-  *         parameters in the TIM_OCInitStruct.
-  * @param  TIMx: where x can be  1 to 17 except 6 and 7 to select the TIM peripheral.
-  * @param  TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
-  *         that contains the configuration information for the specified TIM peripheral.
-  * @retval None
-  */
-void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
-{
-  uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
-   
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST8_PERIPH(TIMx));
-  assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
-  assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
-  assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));   
- /* Disable the Channel 1: Reset the CC1E Bit */
-  TIMx->CCER &= (uint16_t)(~(uint16_t)TIM_CCER_CC1E);
-  /* Get the TIMx CCER register value */
-  tmpccer = TIMx->CCER;
-  /* Get the TIMx CR2 register value */
-  tmpcr2 =  TIMx->CR2;
-  
-  /* Get the TIMx CCMR1 register value */
-  tmpccmrx = TIMx->CCMR1;
-    
-  /* Reset the Output Compare Mode Bits */
-  tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC1M));
-  tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC1S));
-
-  /* Select the Output Compare Mode */
-  tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
-  
-  /* Reset the Output Polarity level */
-  tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1P));
-  /* Set the Output Compare Polarity */
-  tmpccer |= TIM_OCInitStruct->TIM_OCPolarity;
-  
-  /* Set the Output State */
-  tmpccer |= TIM_OCInitStruct->TIM_OutputState;
-    
-  if((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM15)||
-     (TIMx == TIM16)|| (TIMx == TIM17))
-  {
-    assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
-    assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
-    assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
-    assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
-    
-    /* Reset the Output N Polarity level */
-    tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1NP));
-    /* Set the Output N Polarity */
-    tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity;
-    
-    /* Reset the Output N State */
-    tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1NE));    
-    /* Set the Output N State */
-    tmpccer |= TIM_OCInitStruct->TIM_OutputNState;
-    
-    /* Reset the Output Compare and Output Compare N IDLE State */
-    tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS1));
-    tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS1N));
-    
-    /* Set the Output Idle state */
-    tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState;
-    /* Set the Output N Idle state */
-    tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState;
-  }
-  /* Write to TIMx CR2 */
-  TIMx->CR2 = tmpcr2;
-  
-  /* Write to TIMx CCMR1 */
-  TIMx->CCMR1 = tmpccmrx;
-
-  /* Set the Capture Compare Register value */
-  TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse; 
- 
-  /* Write to TIMx CCER */
-  TIMx->CCER = tmpccer;
-}
-
-/**
-  * @brief  Initializes the TIMx Channel2 according to the specified
-  *         parameters in the TIM_OCInitStruct.
-  * @param  TIMx: where x can be  1, 2, 3, 4, 5, 8, 9, 12 or 15 to select 
-  *         the TIM peripheral.
-  * @param  TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
-  *         that contains the configuration information for the specified TIM peripheral.
-  * @retval None
-  */
-void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
-{
-  uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
-   
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST6_PERIPH(TIMx)); 
-  assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
-  assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
-  assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));   
-   /* Disable the Channel 2: Reset the CC2E Bit */
-  TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC2E));
-  
-  /* Get the TIMx CCER register value */  
-  tmpccer = TIMx->CCER;
-  /* Get the TIMx CR2 register value */
-  tmpcr2 =  TIMx->CR2;
-  
-  /* Get the TIMx CCMR1 register value */
-  tmpccmrx = TIMx->CCMR1;
-    
-  /* Reset the Output Compare mode and Capture/Compare selection Bits */
-  tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC2M));
-  tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S));
-  
-  /* Select the Output Compare Mode */
-  tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);
-  
-  /* Reset the Output Polarity level */
-  tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2P));
-  /* Set the Output Compare Polarity */
-  tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4);
-  
-  /* Set the Output State */
-  tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4);
-    
-  if((TIMx == TIM1) || (TIMx == TIM8))
-  {
-    assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
-    assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
-    assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
-    assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
-    
-    /* Reset the Output N Polarity level */
-    tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2NP));
-    /* Set the Output N Polarity */
-    tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4);
-    
-    /* Reset the Output N State */
-    tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2NE));    
-    /* Set the Output N State */
-    tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4);
-    
-    /* Reset the Output Compare and Output Compare N IDLE State */
-    tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS2));
-    tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS2N));
-    
-    /* Set the Output Idle state */
-    tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2);
-    /* Set the Output N Idle state */
-    tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2);
-  }
-  /* Write to TIMx CR2 */
-  TIMx->CR2 = tmpcr2;
-  
-  /* Write to TIMx CCMR1 */
-  TIMx->CCMR1 = tmpccmrx;
-
-  /* Set the Capture Compare Register value */
-  TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse;
-  
-  /* Write to TIMx CCER */
-  TIMx->CCER = tmpccer;
-}
-
-/**
-  * @brief  Initializes the TIMx Channel3 according to the specified
-  *         parameters in the TIM_OCInitStruct.
-  * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
-  * @param  TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
-  *         that contains the configuration information for the specified TIM peripheral.
-  * @retval None
-  */
-void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
-{
-  uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
-   
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST3_PERIPH(TIMx)); 
-  assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
-  assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
-  assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));   
-  /* Disable the Channel 2: Reset the CC2E Bit */
-  TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC3E));
-  
-  /* Get the TIMx CCER register value */
-  tmpccer = TIMx->CCER;
-  /* Get the TIMx CR2 register value */
-  tmpcr2 =  TIMx->CR2;
-  
-  /* Get the TIMx CCMR2 register value */
-  tmpccmrx = TIMx->CCMR2;
-    
-  /* Reset the Output Compare mode and Capture/Compare selection Bits */
-  tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC3M));
-  tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_CC3S));  
-  /* Select the Output Compare Mode */
-  tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
-  
-  /* Reset the Output Polarity level */
-  tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3P));
-  /* Set the Output Compare Polarity */
-  tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8);
-  
-  /* Set the Output State */
-  tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8);
-    
-  if((TIMx == TIM1) || (TIMx == TIM8))
-  {
-    assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
-    assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
-    assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
-    assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
-    
-    /* Reset the Output N Polarity level */
-    tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3NP));
-    /* Set the Output N Polarity */
-    tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8);
-    /* Reset the Output N State */
-    tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3NE));
-    
-    /* Set the Output N State */
-    tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8);
-    /* Reset the Output Compare and Output Compare N IDLE State */
-    tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS3));
-    tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS3N));
-    /* Set the Output Idle state */
-    tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4);
-    /* Set the Output N Idle state */
-    tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4);
-  }
-  /* Write to TIMx CR2 */
-  TIMx->CR2 = tmpcr2;
-  
-  /* Write to TIMx CCMR2 */
-  TIMx->CCMR2 = tmpccmrx;
-
-  /* Set the Capture Compare Register value */
-  TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse;
-  
-  /* Write to TIMx CCER */
-  TIMx->CCER = tmpccer;
-}
-
-/**
-  * @brief  Initializes the TIMx Channel4 according to the specified
-  *         parameters in the TIM_OCInitStruct.
-  * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
-  * @param  TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
-  *         that contains the configuration information for the specified TIM peripheral.
-  * @retval None
-  */
-void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
-{
-  uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
-   
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST3_PERIPH(TIMx)); 
-  assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
-  assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
-  assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));   
-  /* Disable the Channel 2: Reset the CC4E Bit */
-  TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC4E));
-  
-  /* Get the TIMx CCER register value */
-  tmpccer = TIMx->CCER;
-  /* Get the TIMx CR2 register value */
-  tmpcr2 =  TIMx->CR2;
-  
-  /* Get the TIMx CCMR2 register value */
-  tmpccmrx = TIMx->CCMR2;
-    
-  /* Reset the Output Compare mode and Capture/Compare selection Bits */
-  tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC4M));
-  tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_CC4S));
-  
-  /* Select the Output Compare Mode */
-  tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);
-  
-  /* Reset the Output Polarity level */
-  tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC4P));
-  /* Set the Output Compare Polarity */
-  tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12);
-  
-  /* Set the Output State */
-  tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12);
-    
-  if((TIMx == TIM1) || (TIMx == TIM8))
-  {
-    assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
-    /* Reset the Output Compare IDLE State */
-    tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS4));
-    /* Set the Output Idle state */
-    tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6);
-  }
-  /* Write to TIMx CR2 */
-  TIMx->CR2 = tmpcr2;
-  
-  /* Write to TIMx CCMR2 */  
-  TIMx->CCMR2 = tmpccmrx;
-
-  /* Set the Capture Compare Register value */
-  TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse;
-  
-  /* Write to TIMx CCER */
-  TIMx->CCER = tmpccer;
-}
-
-/**
-  * @brief  Initializes the TIM peripheral according to the specified
-  *         parameters in the TIM_ICInitStruct.
-  * @param  TIMx: where x can be  1 to 17 except 6 and 7 to select the TIM peripheral.
-  * @param  TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure
-  *         that contains the configuration information for the specified TIM peripheral.
-  * @retval None
-  */
-void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CHANNEL(TIM_ICInitStruct->TIM_Channel));  
-  assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection));
-  assert_param(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler));
-  assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter));
-  
-  if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) ||
-     (TIMx == TIM4) ||(TIMx == TIM5))
-  {
-    assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity));
-  }
-  else
-  {
-    assert_param(IS_TIM_IC_POLARITY_LITE(TIM_ICInitStruct->TIM_ICPolarity));
-  }
-  if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
-  {
-    assert_param(IS_TIM_LIST8_PERIPH(TIMx));
-    /* TI1 Configuration */
-    TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
-               TIM_ICInitStruct->TIM_ICSelection,
-               TIM_ICInitStruct->TIM_ICFilter);
-    /* Set the Input Capture Prescaler value */
-    TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
-  }
-  else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2)
-  {
-    assert_param(IS_TIM_LIST6_PERIPH(TIMx));
-    /* TI2 Configuration */
-    TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
-               TIM_ICInitStruct->TIM_ICSelection,
-               TIM_ICInitStruct->TIM_ICFilter);
-    /* Set the Input Capture Prescaler value */
-    TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
-  }
-  else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3)
-  {
-    assert_param(IS_TIM_LIST3_PERIPH(TIMx));
-    /* TI3 Configuration */
-    TI3_Config(TIMx,  TIM_ICInitStruct->TIM_ICPolarity,
-               TIM_ICInitStruct->TIM_ICSelection,
-               TIM_ICInitStruct->TIM_ICFilter);
-    /* Set the Input Capture Prescaler value */
-    TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
-  }
-  else
-  {
-    assert_param(IS_TIM_LIST3_PERIPH(TIMx));
-    /* TI4 Configuration */
-    TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
-               TIM_ICInitStruct->TIM_ICSelection,
-               TIM_ICInitStruct->TIM_ICFilter);
-    /* Set the Input Capture Prescaler value */
-    TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
-  }
-}
-
-/**
-  * @brief  Configures the TIM peripheral according to the specified
-  *         parameters in the TIM_ICInitStruct to measure an external PWM signal.
-  * @param  TIMx: where x can be  1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
-  * @param  TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure
-  *         that contains the configuration information for the specified TIM peripheral.
-  * @retval None
-  */
-void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
-{
-  uint16_t icoppositepolarity = TIM_ICPolarity_Rising;
-  uint16_t icoppositeselection = TIM_ICSelection_DirectTI;
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST6_PERIPH(TIMx));
-  /* Select the Opposite Input Polarity */
-  if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising)
-  {
-    icoppositepolarity = TIM_ICPolarity_Falling;
-  }
-  else
-  {
-    icoppositepolarity = TIM_ICPolarity_Rising;
-  }
-  /* Select the Opposite Input */
-  if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI)
-  {
-    icoppositeselection = TIM_ICSelection_IndirectTI;
-  }
-  else
-  {
-    icoppositeselection = TIM_ICSelection_DirectTI;
-  }
-  if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
-  {
-    /* TI1 Configuration */
-    TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
-               TIM_ICInitStruct->TIM_ICFilter);
-    /* Set the Input Capture Prescaler value */
-    TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
-    /* TI2 Configuration */
-    TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
-    /* Set the Input Capture Prescaler value */
-    TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
-  }
-  else
-  { 
-    /* TI2 Configuration */
-    TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
-               TIM_ICInitStruct->TIM_ICFilter);
-    /* Set the Input Capture Prescaler value */
-    TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
-    /* TI1 Configuration */
-    TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
-    /* Set the Input Capture Prescaler value */
-    TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
-  }
-}
-
-/**
-  * @brief  Configures the: Break feature, dead time, Lock level, the OSSI,
-  *         the OSSR State and the AOE(automatic output enable).
-  * @param  TIMx: where x can be  1 or 8 to select the TIM 
-  * @param  TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure that
-  *         contains the BDTR Register configuration  information for the TIM peripheral.
-  * @retval None
-  */
-void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST2_PERIPH(TIMx));
-  assert_param(IS_TIM_OSSR_STATE(TIM_BDTRInitStruct->TIM_OSSRState));
-  assert_param(IS_TIM_OSSI_STATE(TIM_BDTRInitStruct->TIM_OSSIState));
-  assert_param(IS_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->TIM_LOCKLevel));
-  assert_param(IS_TIM_BREAK_STATE(TIM_BDTRInitStruct->TIM_Break));
-  assert_param(IS_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->TIM_BreakPolarity));
-  assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->TIM_AutomaticOutput));
-  /* Set the Lock level, the Break enable Bit and the Ploarity, the OSSR State,
-     the OSSI State, the dead time value and the Automatic Output Enable Bit */
-  TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState |
-             TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime |
-             TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity |
-             TIM_BDTRInitStruct->TIM_AutomaticOutput;
-}
-
-/**
-  * @brief  Fills each TIM_TimeBaseInitStruct member with its default value.
-  * @param  TIM_TimeBaseInitStruct : pointer to a TIM_TimeBaseInitTypeDef
-  *         structure which will be initialized.
-  * @retval None
-  */
-void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
-{
-  /* Set the default configuration */
-  TIM_TimeBaseInitStruct->TIM_Period = 0xFFFF;
-  TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000;
-  TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1;
-  TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up;
-  TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000;
-}
-
-/**
-  * @brief  Fills each TIM_OCInitStruct member with its default value.
-  * @param  TIM_OCInitStruct : pointer to a TIM_OCInitTypeDef structure which will
-  *         be initialized.
-  * @retval None
-  */
-void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct)
-{
-  /* Set the default configuration */
-  TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing;
-  TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable;
-  TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable;
-  TIM_OCInitStruct->TIM_Pulse = 0x0000;
-  TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High;
-  TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High;
-  TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset;
-  TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset;
-}
-
-/**
-  * @brief  Fills each TIM_ICInitStruct member with its default value.
-  * @param  TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure which will
-  *         be initialized.
-  * @retval None
-  */
-void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct)
-{
-  /* Set the default configuration */
-  TIM_ICInitStruct->TIM_Channel = TIM_Channel_1;
-  TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising;
-  TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI;
-  TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1;
-  TIM_ICInitStruct->TIM_ICFilter = 0x00;
-}
-
-/**
-  * @brief  Fills each TIM_BDTRInitStruct member with its default value.
-  * @param  TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure which
-  *         will be initialized.
-  * @retval None
-  */
-void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct)
-{
-  /* Set the default configuration */
-  TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable;
-  TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable;
-  TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF;
-  TIM_BDTRInitStruct->TIM_DeadTime = 0x00;
-  TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable;
-  TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low;
-  TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable;
-}
-
-/**
-  * @brief  Enables or disables the specified TIM peripheral.
-  * @param  TIMx: where x can be 1 to 17 to select the TIMx peripheral.
-  * @param  NewState: new state of the TIMx peripheral.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_ALL_PERIPH(TIMx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  
-  if (NewState != DISABLE)
-  {
-    /* Enable the TIM Counter */
-    TIMx->CR1 |= TIM_CR1_CEN;
-  }
-  else
-  {
-    /* Disable the TIM Counter */
-    TIMx->CR1 &= (uint16_t)(~((uint16_t)TIM_CR1_CEN));
-  }
-}
-
-/**
-  * @brief  Enables or disables the TIM peripheral Main Outputs.
-  * @param  TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIMx peripheral.
-  * @param  NewState: new state of the TIM peripheral Main Outputs.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST2_PERIPH(TIMx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  if (NewState != DISABLE)
-  {
-    /* Enable the TIM Main Output */
-    TIMx->BDTR |= TIM_BDTR_MOE;
-  }
-  else
-  {
-    /* Disable the TIM Main Output */
-    TIMx->BDTR &= (uint16_t)(~((uint16_t)TIM_BDTR_MOE));
-  }  
-}
-
-/**
-  * @brief  Enables or disables the specified TIM interrupts.
-  * @param  TIMx: where x can be 1 to 17 to select the TIMx peripheral.
-  * @param  TIM_IT: specifies the TIM interrupts sources to be enabled or disabled.
-  *   This parameter can be any combination of the following values:
-  *     @arg TIM_IT_Update: TIM update Interrupt source
-  *     @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
-  *     @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
-  *     @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
-  *     @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
-  *     @arg TIM_IT_COM: TIM Commutation Interrupt source
-  *     @arg TIM_IT_Trigger: TIM Trigger Interrupt source
-  *     @arg TIM_IT_Break: TIM Break Interrupt source
-  * @note 
-  *   - TIM6 and TIM7 can only generate an update interrupt.
-  *   - TIM9, TIM12 and TIM15 can have only TIM_IT_Update, TIM_IT_CC1,
-  *      TIM_IT_CC2 or TIM_IT_Trigger. 
-  *   - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1.   
-  *   - TIM_IT_Break is used only with TIM1, TIM8 and TIM15. 
-  *   - TIM_IT_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17.    
-  * @param  NewState: new state of the TIM interrupts.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState)
-{  
-  /* Check the parameters */
-  assert_param(IS_TIM_ALL_PERIPH(TIMx));
-  assert_param(IS_TIM_IT(TIM_IT));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  
-  if (NewState != DISABLE)
-  {
-    /* Enable the Interrupt sources */
-    TIMx->DIER |= TIM_IT;
-  }
-  else
-  {
-    /* Disable the Interrupt sources */
-    TIMx->DIER &= (uint16_t)~TIM_IT;
-  }
-}
-
-/**
-  * @brief  Configures the TIMx event to be generate by software.
-  * @param  TIMx: where x can be 1 to 17 to select the TIM peripheral.
-  * @param  TIM_EventSource: specifies the event source.
-  *   This parameter can be one or more of the following values:	   
-  *     @arg TIM_EventSource_Update: Timer update Event source
-  *     @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source
-  *     @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source
-  *     @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source
-  *     @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source
-  *     @arg TIM_EventSource_COM: Timer COM event source  
-  *     @arg TIM_EventSource_Trigger: Timer Trigger Event source
-  *     @arg TIM_EventSource_Break: Timer Break event source
-  * @note 
-  *   - TIM6 and TIM7 can only generate an update event. 
-  *   - TIM_EventSource_COM and TIM_EventSource_Break are used only with TIM1 and TIM8.      
-  * @retval None
-  */
-void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource)
-{ 
-  /* Check the parameters */
-  assert_param(IS_TIM_ALL_PERIPH(TIMx));
-  assert_param(IS_TIM_EVENT_SOURCE(TIM_EventSource));
-  
-  /* Set the event sources */
-  TIMx->EGR = TIM_EventSource;
-}
-
-/**
-  * @brief  Configures the TIMx's DMA interface.
-  * @param  TIMx: where x can be  1, 2, 3, 4, 5, 8, 15, 16 or 17 to select 
-  *   the TIM peripheral.
-  * @param  TIM_DMABase: DMA Base address.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_DMABase_CR, TIM_DMABase_CR2, TIM_DMABase_SMCR,
-  *          TIM_DMABase_DIER, TIM1_DMABase_SR, TIM_DMABase_EGR,
-  *          TIM_DMABase_CCMR1, TIM_DMABase_CCMR2, TIM_DMABase_CCER,
-  *          TIM_DMABase_CNT, TIM_DMABase_PSC, TIM_DMABase_ARR,
-  *          TIM_DMABase_RCR, TIM_DMABase_CCR1, TIM_DMABase_CCR2,
-  *          TIM_DMABase_CCR3, TIM_DMABase_CCR4, TIM_DMABase_BDTR,
-  *          TIM_DMABase_DCR.
-  * @param  TIM_DMABurstLength: DMA Burst length.
-  *   This parameter can be one value between:
-  *   TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.
-  * @retval None
-  */
-void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST4_PERIPH(TIMx));
-  assert_param(IS_TIM_DMA_BASE(TIM_DMABase));
-  assert_param(IS_TIM_DMA_LENGTH(TIM_DMABurstLength));
-  /* Set the DMA Base and the DMA Burst Length */
-  TIMx->DCR = TIM_DMABase | TIM_DMABurstLength;
-}
-
-/**
-  * @brief  Enables or disables the TIMx's DMA Requests.
-  * @param  TIMx: where x can be  1, 2, 3, 4, 5, 6, 7, 8, 15, 16 or 17 
-  *   to select the TIM peripheral. 
-  * @param  TIM_DMASource: specifies the DMA Request sources.
-  *   This parameter can be any combination of the following values:
-  *     @arg TIM_DMA_Update: TIM update Interrupt source
-  *     @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
-  *     @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
-  *     @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
-  *     @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
-  *     @arg TIM_DMA_COM: TIM Commutation DMA source
-  *     @arg TIM_DMA_Trigger: TIM Trigger DMA source
-  * @param  NewState: new state of the DMA Request sources.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState)
-{ 
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST9_PERIPH(TIMx));
-  assert_param(IS_TIM_DMA_SOURCE(TIM_DMASource));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  
-  if (NewState != DISABLE)
-  {
-    /* Enable the DMA sources */
-    TIMx->DIER |= TIM_DMASource; 
-  }
-  else
-  {
-    /* Disable the DMA sources */
-    TIMx->DIER &= (uint16_t)~TIM_DMASource;
-  }
-}
-
-/**
-  * @brief  Configures the TIMx internal Clock
-  * @param  TIMx: where x can be  1, 2, 3, 4, 5, 8, 9, 12 or 15
-  *         to select the TIM peripheral.
-  * @retval None
-  */
-void TIM_InternalClockConfig(TIM_TypeDef* TIMx)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST6_PERIPH(TIMx));
-  /* Disable slave mode to clock the prescaler directly with the internal clock */
-  TIMx->SMCR &=  (uint16_t)(~((uint16_t)TIM_SMCR_SMS));
-}
-
-/**
-  * @brief  Configures the TIMx Internal Trigger as External Clock
-  * @param  TIMx: where x can be  1, 2, 3, 4, 5, 9, 12 or 15 to select the TIM peripheral.
-  * @param  TIM_ITRSource: Trigger source.
-  *   This parameter can be one of the following values:
-  * @param  TIM_TS_ITR0: Internal Trigger 0
-  * @param  TIM_TS_ITR1: Internal Trigger 1
-  * @param  TIM_TS_ITR2: Internal Trigger 2
-  * @param  TIM_TS_ITR3: Internal Trigger 3
-  * @retval None
-  */
-void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST6_PERIPH(TIMx));
-  assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource));
-  /* Select the Internal Trigger */
-  TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource);
-  /* Select the External clock mode1 */
-  TIMx->SMCR |= TIM_SlaveMode_External1;
-}
-
-/**
-  * @brief  Configures the TIMx Trigger as External Clock
-  * @param  TIMx: where x can be  1, 2, 3, 4, 5, 9, 12 or 15 to select the TIM peripheral.
-  * @param  TIM_TIxExternalCLKSource: Trigger source.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector
-  *     @arg TIM_TIxExternalCLK1Source_TI1: Filtered Timer Input 1
-  *     @arg TIM_TIxExternalCLK1Source_TI2: Filtered Timer Input 2
-  * @param  TIM_ICPolarity: specifies the TIx Polarity.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_ICPolarity_Rising
-  *     @arg TIM_ICPolarity_Falling
-  * @param  ICFilter : specifies the filter value.
-  *   This parameter must be a value between 0x0 and 0xF.
-  * @retval None
-  */
-void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,
-                                uint16_t TIM_ICPolarity, uint16_t ICFilter)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST6_PERIPH(TIMx));
-  assert_param(IS_TIM_TIXCLK_SOURCE(TIM_TIxExternalCLKSource));
-  assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity));
-  assert_param(IS_TIM_IC_FILTER(ICFilter));
-  /* Configure the Timer Input Clock Source */
-  if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2)
-  {
-    TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
-  }
-  else
-  {
-    TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
-  }
-  /* Select the Trigger source */
-  TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource);
-  /* Select the External clock mode1 */
-  TIMx->SMCR |= TIM_SlaveMode_External1;
-}
-
-/**
-  * @brief  Configures the External clock Mode1
-  * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
-  * @param  TIM_ExtTRGPrescaler: The external Trigger Prescaler.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
-  *     @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
-  *     @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
-  *     @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
-  * @param  TIM_ExtTRGPolarity: The external Trigger Polarity.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
-  *     @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
-  * @param  ExtTRGFilter: External Trigger Filter.
-  *   This parameter must be a value between 0x00 and 0x0F
-  * @retval None
-  */
-void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
-                             uint16_t ExtTRGFilter)
-{
-  uint16_t tmpsmcr = 0;
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
-  assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
-  assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
-  assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
-  /* Configure the ETR Clock source */
-  TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
-  
-  /* Get the TIMx SMCR register value */
-  tmpsmcr = TIMx->SMCR;
-  /* Reset the SMS Bits */
-  tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS));
-  /* Select the External clock mode1 */
-  tmpsmcr |= TIM_SlaveMode_External1;
-  /* Select the Trigger selection : ETRF */
-  tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS));
-  tmpsmcr |= TIM_TS_ETRF;
-  /* Write to TIMx SMCR */
-  TIMx->SMCR = tmpsmcr;
-}
-
-/**
-  * @brief  Configures the External clock Mode2
-  * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
-  * @param  TIM_ExtTRGPrescaler: The external Trigger Prescaler.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
-  *     @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
-  *     @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
-  *     @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
-  * @param  TIM_ExtTRGPolarity: The external Trigger Polarity.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
-  *     @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
-  * @param  ExtTRGFilter: External Trigger Filter.
-  *   This parameter must be a value between 0x00 and 0x0F
-  * @retval None
-  */
-void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, 
-                             uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
-  assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
-  assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
-  assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
-  /* Configure the ETR Clock source */
-  TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
-  /* Enable the External clock mode2 */
-  TIMx->SMCR |= TIM_SMCR_ECE;
-}
-
-/**
-  * @brief  Configures the TIMx External Trigger (ETR).
-  * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
-  * @param  TIM_ExtTRGPrescaler: The external Trigger Prescaler.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
-  *     @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
-  *     @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
-  *     @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
-  * @param  TIM_ExtTRGPolarity: The external Trigger Polarity.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
-  *     @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
-  * @param  ExtTRGFilter: External Trigger Filter.
-  *   This parameter must be a value between 0x00 and 0x0F
-  * @retval None
-  */
-void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
-                   uint16_t ExtTRGFilter)
-{
-  uint16_t tmpsmcr = 0;
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
-  assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
-  assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
-  assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
-  tmpsmcr = TIMx->SMCR;
-  /* Reset the ETR Bits */
-  tmpsmcr &= SMCR_ETR_Mask;
-  /* Set the Prescaler, the Filter value and the Polarity */
-  tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8)));
-  /* Write to TIMx SMCR */
-  TIMx->SMCR = tmpsmcr;
-}
-
-/**
-  * @brief  Configures the TIMx Prescaler.
-  * @param  TIMx: where x can be 1 to 17 to select the TIM peripheral.
-  * @param  Prescaler: specifies the Prescaler Register value
-  * @param  TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode
-  *   This parameter can be one of the following values:
-  *     @arg TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event.
-  *     @arg TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediately.
-  * @retval None
-  */
-void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_ALL_PERIPH(TIMx));
-  assert_param(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode));
-  /* Set the Prescaler value */
-  TIMx->PSC = Prescaler;
-  /* Set or reset the UG Bit */
-  TIMx->EGR = TIM_PSCReloadMode;
-}
-
-/**
-  * @brief  Specifies the TIMx Counter Mode to be used.
-  * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
-  * @param  TIM_CounterMode: specifies the Counter Mode to be used
-  *   This parameter can be one of the following values:
-  *     @arg TIM_CounterMode_Up: TIM Up Counting Mode
-  *     @arg TIM_CounterMode_Down: TIM Down Counting Mode
-  *     @arg TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1
-  *     @arg TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2
-  *     @arg TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3
-  * @retval None
-  */
-void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode)
-{
-  uint16_t tmpcr1 = 0;
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
-  assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode));
-  tmpcr1 = TIMx->CR1;
-  /* Reset the CMS and DIR Bits */
-  tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS)));
-  /* Set the Counter Mode */
-  tmpcr1 |= TIM_CounterMode;
-  /* Write to TIMx CR1 register */
-  TIMx->CR1 = tmpcr1;
-}
-
-/**
-  * @brief  Selects the Input Trigger source
-  * @param  TIMx: where x can be  1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
-  * @param  TIM_InputTriggerSource: The Input Trigger source.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_TS_ITR0: Internal Trigger 0
-  *     @arg TIM_TS_ITR1: Internal Trigger 1
-  *     @arg TIM_TS_ITR2: Internal Trigger 2
-  *     @arg TIM_TS_ITR3: Internal Trigger 3
-  *     @arg TIM_TS_TI1F_ED: TI1 Edge Detector
-  *     @arg TIM_TS_TI1FP1: Filtered Timer Input 1
-  *     @arg TIM_TS_TI2FP2: Filtered Timer Input 2
-  *     @arg TIM_TS_ETRF: External Trigger input
-  * @retval None
-  */
-void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)
-{
-  uint16_t tmpsmcr = 0;
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST6_PERIPH(TIMx));
-  assert_param(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource));
-  /* Get the TIMx SMCR register value */
-  tmpsmcr = TIMx->SMCR;
-  /* Reset the TS Bits */
-  tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS));
-  /* Set the Input Trigger source */
-  tmpsmcr |= TIM_InputTriggerSource;
-  /* Write to TIMx SMCR */
-  TIMx->SMCR = tmpsmcr;
-}
-
-/**
-  * @brief  Configures the TIMx Encoder Interface.
-  * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
-  * @param  TIM_EncoderMode: specifies the TIMx Encoder Mode.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level.
-  *     @arg TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level.
-  *     @arg TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending
-  *                                on the level of the other input.
-  * @param  TIM_IC1Polarity: specifies the IC1 Polarity
-  *   This parameter can be one of the following values:
-  *     @arg TIM_ICPolarity_Falling: IC Falling edge.
-  *     @arg TIM_ICPolarity_Rising: IC Rising edge.
-  * @param  TIM_IC2Polarity: specifies the IC2 Polarity
-  *   This parameter can be one of the following values:
-  *     @arg TIM_ICPolarity_Falling: IC Falling edge.
-  *     @arg TIM_ICPolarity_Rising: IC Rising edge.
-  * @retval None
-  */
-void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
-                                uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity)
-{
-  uint16_t tmpsmcr = 0;
-  uint16_t tmpccmr1 = 0;
-  uint16_t tmpccer = 0;
-    
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST5_PERIPH(TIMx));
-  assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode));
-  assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity));
-  assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity));
-
-  /* Get the TIMx SMCR register value */
-  tmpsmcr = TIMx->SMCR;
-  
-  /* Get the TIMx CCMR1 register value */
-  tmpccmr1 = TIMx->CCMR1;
-  
-  /* Get the TIMx CCER register value */
-  tmpccer = TIMx->CCER;
-  
-  /* Set the encoder Mode */
-  tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS));
-  tmpsmcr |= TIM_EncoderMode;
-  
-  /* Select the Capture Compare 1 and the Capture Compare 2 as input */
-  tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S)));
-  tmpccmr1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0;
-  
-  /* Set the TI1 and the TI2 Polarities */
-  tmpccer &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCER_CC1P)) & ((uint16_t)~((uint16_t)TIM_CCER_CC2P)));
-  tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4));
-  
-  /* Write to TIMx SMCR */
-  TIMx->SMCR = tmpsmcr;
-  /* Write to TIMx CCMR1 */
-  TIMx->CCMR1 = tmpccmr1;
-  /* Write to TIMx CCER */
-  TIMx->CCER = tmpccer;
-}
-
-/**
-  * @brief  Forces the TIMx output 1 waveform to active or inactive level.
-  * @param  TIMx: where x can be  1 to 17 except 6 and 7 to select the TIM peripheral.
-  * @param  TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_ForcedAction_Active: Force active level on OC1REF
-  *     @arg TIM_ForcedAction_InActive: Force inactive level on OC1REF.
-  * @retval None
-  */
-void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
-{
-  uint16_t tmpccmr1 = 0;
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST8_PERIPH(TIMx));
-  assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
-  tmpccmr1 = TIMx->CCMR1;
-  /* Reset the OC1M Bits */
-  tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1M);
-  /* Configure The Forced output Mode */
-  tmpccmr1 |= TIM_ForcedAction;
-  /* Write to TIMx CCMR1 register */
-  TIMx->CCMR1 = tmpccmr1;
-}
-
-/**
-  * @brief  Forces the TIMx output 2 waveform to active or inactive level.
-  * @param  TIMx: where x can be  1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
-  * @param  TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_ForcedAction_Active: Force active level on OC2REF
-  *     @arg TIM_ForcedAction_InActive: Force inactive level on OC2REF.
-  * @retval None
-  */
-void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
-{
-  uint16_t tmpccmr1 = 0;
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST6_PERIPH(TIMx));
-  assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
-  tmpccmr1 = TIMx->CCMR1;
-  /* Reset the OC2M Bits */
-  tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2M);
-  /* Configure The Forced output Mode */
-  tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8);
-  /* Write to TIMx CCMR1 register */
-  TIMx->CCMR1 = tmpccmr1;
-}
-
-/**
-  * @brief  Forces the TIMx output 3 waveform to active or inactive level.
-  * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
-  * @param  TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_ForcedAction_Active: Force active level on OC3REF
-  *     @arg TIM_ForcedAction_InActive: Force inactive level on OC3REF.
-  * @retval None
-  */
-void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
-{
-  uint16_t tmpccmr2 = 0;
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
-  assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
-  tmpccmr2 = TIMx->CCMR2;
-  /* Reset the OC1M Bits */
-  tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3M);
-  /* Configure The Forced output Mode */
-  tmpccmr2 |= TIM_ForcedAction;
-  /* Write to TIMx CCMR2 register */
-  TIMx->CCMR2 = tmpccmr2;
-}
-
-/**
-  * @brief  Forces the TIMx output 4 waveform to active or inactive level.
-  * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
-  * @param  TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_ForcedAction_Active: Force active level on OC4REF
-  *     @arg TIM_ForcedAction_InActive: Force inactive level on OC4REF.
-  * @retval None
-  */
-void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
-{
-  uint16_t tmpccmr2 = 0;
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
-  assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
-  tmpccmr2 = TIMx->CCMR2;
-  /* Reset the OC2M Bits */
-  tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4M);
-  /* Configure The Forced output Mode */
-  tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8);
-  /* Write to TIMx CCMR2 register */
-  TIMx->CCMR2 = tmpccmr2;
-}
-
-/**
-  * @brief  Enables or disables TIMx peripheral Preload register on ARR.
-  * @param  TIMx: where x can be  1 to 17 to select the TIM peripheral.
-  * @param  NewState: new state of the TIMx peripheral Preload register
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_ALL_PERIPH(TIMx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  if (NewState != DISABLE)
-  {
-    /* Set the ARR Preload Bit */
-    TIMx->CR1 |= TIM_CR1_ARPE;
-  }
-  else
-  {
-    /* Reset the ARR Preload Bit */
-    TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_ARPE);
-  }
-}
-
-/**
-  * @brief  Selects the TIM peripheral Commutation event.
-  * @param  TIMx: where x can be  1, 8, 15, 16 or 17 to select the TIMx peripheral
-  * @param  NewState: new state of the Commutation event.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST2_PERIPH(TIMx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  if (NewState != DISABLE)
-  {
-    /* Set the COM Bit */
-    TIMx->CR2 |= TIM_CR2_CCUS;
-  }
-  else
-  {
-    /* Reset the COM Bit */
-    TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCUS);
-  }
-}
-
-/**
-  * @brief  Selects the TIMx peripheral Capture Compare DMA source.
-  * @param  TIMx: where x can be  1, 2, 3, 4, 5, 8, 15, 16 or 17 to select 
-  *         the TIM peripheral.
-  * @param  NewState: new state of the Capture Compare DMA source
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST4_PERIPH(TIMx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  if (NewState != DISABLE)
-  {
-    /* Set the CCDS Bit */
-    TIMx->CR2 |= TIM_CR2_CCDS;
-  }
-  else
-  {
-    /* Reset the CCDS Bit */
-    TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCDS);
-  }
-}
-
-/**
-  * @brief  Sets or Resets the TIM peripheral Capture Compare Preload Control bit.
-  * @param  TIMx: where x can be   1, 2, 3, 4, 5, 8 or 15 
-  *         to select the TIMx peripheral
-  * @param  NewState: new state of the Capture Compare Preload Control bit
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState)
-{ 
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST5_PERIPH(TIMx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  if (NewState != DISABLE)
-  {
-    /* Set the CCPC Bit */
-    TIMx->CR2 |= TIM_CR2_CCPC;
-  }
-  else
-  {
-    /* Reset the CCPC Bit */
-    TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCPC);
-  }
-}
-
-/**
-  * @brief  Enables or disables the TIMx peripheral Preload register on CCR1.
-  * @param  TIMx: where x can be  1 to 17 except 6 and 7 to select the TIM peripheral.
-  * @param  TIM_OCPreload: new state of the TIMx peripheral Preload register
-  *   This parameter can be one of the following values:
-  *     @arg TIM_OCPreload_Enable
-  *     @arg TIM_OCPreload_Disable
-  * @retval None
-  */
-void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
-{
-  uint16_t tmpccmr1 = 0;
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST8_PERIPH(TIMx));
-  assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
-  tmpccmr1 = TIMx->CCMR1;
-  /* Reset the OC1PE Bit */
-  tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1PE);
-  /* Enable or Disable the Output Compare Preload feature */
-  tmpccmr1 |= TIM_OCPreload;
-  /* Write to TIMx CCMR1 register */
-  TIMx->CCMR1 = tmpccmr1;
-}
-
-/**
-  * @brief  Enables or disables the TIMx peripheral Preload register on CCR2.
-  * @param  TIMx: where x can be  1, 2, 3, 4, 5, 8, 9, 12 or 15 to select 
-  *         the TIM peripheral.
-  * @param  TIM_OCPreload: new state of the TIMx peripheral Preload register
-  *   This parameter can be one of the following values:
-  *     @arg TIM_OCPreload_Enable
-  *     @arg TIM_OCPreload_Disable
-  * @retval None
-  */
-void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
-{
-  uint16_t tmpccmr1 = 0;
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST6_PERIPH(TIMx));
-  assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
-  tmpccmr1 = TIMx->CCMR1;
-  /* Reset the OC2PE Bit */
-  tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2PE);
-  /* Enable or Disable the Output Compare Preload feature */
-  tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8);
-  /* Write to TIMx CCMR1 register */
-  TIMx->CCMR1 = tmpccmr1;
-}
-
-/**
-  * @brief  Enables or disables the TIMx peripheral Preload register on CCR3.
-  * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
-  * @param  TIM_OCPreload: new state of the TIMx peripheral Preload register
-  *   This parameter can be one of the following values:
-  *     @arg TIM_OCPreload_Enable
-  *     @arg TIM_OCPreload_Disable
-  * @retval None
-  */
-void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
-{
-  uint16_t tmpccmr2 = 0;
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
-  assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
-  tmpccmr2 = TIMx->CCMR2;
-  /* Reset the OC3PE Bit */
-  tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3PE);
-  /* Enable or Disable the Output Compare Preload feature */
-  tmpccmr2 |= TIM_OCPreload;
-  /* Write to TIMx CCMR2 register */
-  TIMx->CCMR2 = tmpccmr2;
-}
-
-/**
-  * @brief  Enables or disables the TIMx peripheral Preload register on CCR4.
-  * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
-  * @param  TIM_OCPreload: new state of the TIMx peripheral Preload register
-  *   This parameter can be one of the following values:
-  *     @arg TIM_OCPreload_Enable
-  *     @arg TIM_OCPreload_Disable
-  * @retval None
-  */
-void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
-{
-  uint16_t tmpccmr2 = 0;
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
-  assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
-  tmpccmr2 = TIMx->CCMR2;
-  /* Reset the OC4PE Bit */
-  tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4PE);
-  /* Enable or Disable the Output Compare Preload feature */
-  tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8);
-  /* Write to TIMx CCMR2 register */
-  TIMx->CCMR2 = tmpccmr2;
-}
-
-/**
-  * @brief  Configures the TIMx Output Compare 1 Fast feature.
-  * @param  TIMx: where x can be  1 to 17 except 6 and 7 to select the TIM peripheral.
-  * @param  TIM_OCFast: new state of the Output Compare Fast Enable Bit.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_OCFast_Enable: TIM output compare fast enable
-  *     @arg TIM_OCFast_Disable: TIM output compare fast disable
-  * @retval None
-  */
-void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
-{
-  uint16_t tmpccmr1 = 0;
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST8_PERIPH(TIMx));
-  assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
-  /* Get the TIMx CCMR1 register value */
-  tmpccmr1 = TIMx->CCMR1;
-  /* Reset the OC1FE Bit */
-  tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1FE);
-  /* Enable or Disable the Output Compare Fast Bit */
-  tmpccmr1 |= TIM_OCFast;
-  /* Write to TIMx CCMR1 */
-  TIMx->CCMR1 = tmpccmr1;
-}
-
-/**
-  * @brief  Configures the TIMx Output Compare 2 Fast feature.
-  * @param  TIMx: where x can be  1, 2, 3, 4, 5, 8, 9, 12 or 15 to select 
-  *         the TIM peripheral.
-  * @param  TIM_OCFast: new state of the Output Compare Fast Enable Bit.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_OCFast_Enable: TIM output compare fast enable
-  *     @arg TIM_OCFast_Disable: TIM output compare fast disable
-  * @retval None
-  */
-void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
-{
-  uint16_t tmpccmr1 = 0;
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST6_PERIPH(TIMx));
-  assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
-  /* Get the TIMx CCMR1 register value */
-  tmpccmr1 = TIMx->CCMR1;
-  /* Reset the OC2FE Bit */
-  tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2FE);
-  /* Enable or Disable the Output Compare Fast Bit */
-  tmpccmr1 |= (uint16_t)(TIM_OCFast << 8);
-  /* Write to TIMx CCMR1 */
-  TIMx->CCMR1 = tmpccmr1;
-}
-
-/**
-  * @brief  Configures the TIMx Output Compare 3 Fast feature.
-  * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
-  * @param  TIM_OCFast: new state of the Output Compare Fast Enable Bit.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_OCFast_Enable: TIM output compare fast enable
-  *     @arg TIM_OCFast_Disable: TIM output compare fast disable
-  * @retval None
-  */
-void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
-{
-  uint16_t tmpccmr2 = 0;
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
-  assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
-  /* Get the TIMx CCMR2 register value */
-  tmpccmr2 = TIMx->CCMR2;
-  /* Reset the OC3FE Bit */
-  tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3FE);
-  /* Enable or Disable the Output Compare Fast Bit */
-  tmpccmr2 |= TIM_OCFast;
-  /* Write to TIMx CCMR2 */
-  TIMx->CCMR2 = tmpccmr2;
-}
-
-/**
-  * @brief  Configures the TIMx Output Compare 4 Fast feature.
-  * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
-  * @param  TIM_OCFast: new state of the Output Compare Fast Enable Bit.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_OCFast_Enable: TIM output compare fast enable
-  *     @arg TIM_OCFast_Disable: TIM output compare fast disable
-  * @retval None
-  */
-void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
-{
-  uint16_t tmpccmr2 = 0;
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
-  assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
-  /* Get the TIMx CCMR2 register value */
-  tmpccmr2 = TIMx->CCMR2;
-  /* Reset the OC4FE Bit */
-  tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4FE);
-  /* Enable or Disable the Output Compare Fast Bit */
-  tmpccmr2 |= (uint16_t)(TIM_OCFast << 8);
-  /* Write to TIMx CCMR2 */
-  TIMx->CCMR2 = tmpccmr2;
-}
-
-/**
-  * @brief  Clears or safeguards the OCREF1 signal on an external event
-  * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
-  * @param  TIM_OCClear: new state of the Output Compare Clear Enable Bit.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_OCClear_Enable: TIM Output clear enable
-  *     @arg TIM_OCClear_Disable: TIM Output clear disable
-  * @retval None
-  */
-void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
-{
-  uint16_t tmpccmr1 = 0;
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
-  assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
-
-  tmpccmr1 = TIMx->CCMR1;
-
-  /* Reset the OC1CE Bit */
-  tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1CE);
-  /* Enable or Disable the Output Compare Clear Bit */
-  tmpccmr1 |= TIM_OCClear;
-  /* Write to TIMx CCMR1 register */
-  TIMx->CCMR1 = tmpccmr1;
-}
-
-/**
-  * @brief  Clears or safeguards the OCREF2 signal on an external event
-  * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
-  * @param  TIM_OCClear: new state of the Output Compare Clear Enable Bit.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_OCClear_Enable: TIM Output clear enable
-  *     @arg TIM_OCClear_Disable: TIM Output clear disable
-  * @retval None
-  */
-void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
-{
-  uint16_t tmpccmr1 = 0;
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
-  assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
-  tmpccmr1 = TIMx->CCMR1;
-  /* Reset the OC2CE Bit */
-  tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2CE);
-  /* Enable or Disable the Output Compare Clear Bit */
-  tmpccmr1 |= (uint16_t)(TIM_OCClear << 8);
-  /* Write to TIMx CCMR1 register */
-  TIMx->CCMR1 = tmpccmr1;
-}
-
-/**
-  * @brief  Clears or safeguards the OCREF3 signal on an external event
-  * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
-  * @param  TIM_OCClear: new state of the Output Compare Clear Enable Bit.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_OCClear_Enable: TIM Output clear enable
-  *     @arg TIM_OCClear_Disable: TIM Output clear disable
-  * @retval None
-  */
-void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
-{
-  uint16_t tmpccmr2 = 0;
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
-  assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
-  tmpccmr2 = TIMx->CCMR2;
-  /* Reset the OC3CE Bit */
-  tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3CE);
-  /* Enable or Disable the Output Compare Clear Bit */
-  tmpccmr2 |= TIM_OCClear;
-  /* Write to TIMx CCMR2 register */
-  TIMx->CCMR2 = tmpccmr2;
-}
-
-/**
-  * @brief  Clears or safeguards the OCREF4 signal on an external event
-  * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
-  * @param  TIM_OCClear: new state of the Output Compare Clear Enable Bit.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_OCClear_Enable: TIM Output clear enable
-  *     @arg TIM_OCClear_Disable: TIM Output clear disable
-  * @retval None
-  */
-void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
-{
-  uint16_t tmpccmr2 = 0;
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
-  assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
-  tmpccmr2 = TIMx->CCMR2;
-  /* Reset the OC4CE Bit */
-  tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4CE);
-  /* Enable or Disable the Output Compare Clear Bit */
-  tmpccmr2 |= (uint16_t)(TIM_OCClear << 8);
-  /* Write to TIMx CCMR2 register */
-  TIMx->CCMR2 = tmpccmr2;
-}
-
-/**
-  * @brief  Configures the TIMx channel 1 polarity.
-  * @param  TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
-  * @param  TIM_OCPolarity: specifies the OC1 Polarity
-  *   This parameter can be one of the following values:
-  *     @arg TIM_OCPolarity_High: Output Compare active high
-  *     @arg TIM_OCPolarity_Low: Output Compare active low
-  * @retval None
-  */
-void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
-{
-  uint16_t tmpccer = 0;
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST8_PERIPH(TIMx));
-  assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
-  tmpccer = TIMx->CCER;
-  /* Set or Reset the CC1P Bit */
-  tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC1P);
-  tmpccer |= TIM_OCPolarity;
-  /* Write to TIMx CCER register */
-  TIMx->CCER = tmpccer;
-}
-
-/**
-  * @brief  Configures the TIMx Channel 1N polarity.
-  * @param  TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIM peripheral.
-  * @param  TIM_OCNPolarity: specifies the OC1N Polarity
-  *   This parameter can be one of the following values:
-  *     @arg TIM_OCNPolarity_High: Output Compare active high
-  *     @arg TIM_OCNPolarity_Low: Output Compare active low
-  * @retval None
-  */
-void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
-{
-  uint16_t tmpccer = 0;
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST2_PERIPH(TIMx));
-  assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
-   
-  tmpccer = TIMx->CCER;
-  /* Set or Reset the CC1NP Bit */
-  tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC1NP);
-  tmpccer |= TIM_OCNPolarity;
-  /* Write to TIMx CCER register */
-  TIMx->CCER = tmpccer;
-}
-
-/**
-  * @brief  Configures the TIMx channel 2 polarity.
-  * @param  TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
-  * @param  TIM_OCPolarity: specifies the OC2 Polarity
-  *   This parameter can be one of the following values:
-  *     @arg TIM_OCPolarity_High: Output Compare active high
-  *     @arg TIM_OCPolarity_Low: Output Compare active low
-  * @retval None
-  */
-void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
-{
-  uint16_t tmpccer = 0;
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST6_PERIPH(TIMx));
-  assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
-  tmpccer = TIMx->CCER;
-  /* Set or Reset the CC2P Bit */
-  tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC2P);
-  tmpccer |= (uint16_t)(TIM_OCPolarity << 4);
-  /* Write to TIMx CCER register */
-  TIMx->CCER = tmpccer;
-}
-
-/**
-  * @brief  Configures the TIMx Channel 2N polarity.
-  * @param  TIMx: where x can be 1 or 8 to select the TIM peripheral.
-  * @param  TIM_OCNPolarity: specifies the OC2N Polarity
-  *   This parameter can be one of the following values:
-  *     @arg TIM_OCNPolarity_High: Output Compare active high
-  *     @arg TIM_OCNPolarity_Low: Output Compare active low
-  * @retval None
-  */
-void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
-{
-  uint16_t tmpccer = 0;
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST1_PERIPH(TIMx));
-  assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
-  
-  tmpccer = TIMx->CCER;
-  /* Set or Reset the CC2NP Bit */
-  tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC2NP);
-  tmpccer |= (uint16_t)(TIM_OCNPolarity << 4);
-  /* Write to TIMx CCER register */
-  TIMx->CCER = tmpccer;
-}
-
-/**
-  * @brief  Configures the TIMx channel 3 polarity.
-  * @param  TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
-  * @param  TIM_OCPolarity: specifies the OC3 Polarity
-  *   This parameter can be one of the following values:
-  *     @arg TIM_OCPolarity_High: Output Compare active high
-  *     @arg TIM_OCPolarity_Low: Output Compare active low
-  * @retval None
-  */
-void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
-{
-  uint16_t tmpccer = 0;
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
-  assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
-  tmpccer = TIMx->CCER;
-  /* Set or Reset the CC3P Bit */
-  tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC3P);
-  tmpccer |= (uint16_t)(TIM_OCPolarity << 8);
-  /* Write to TIMx CCER register */
-  TIMx->CCER = tmpccer;
-}
-
-/**
-  * @brief  Configures the TIMx Channel 3N polarity.
-  * @param  TIMx: where x can be 1 or 8 to select the TIM peripheral.
-  * @param  TIM_OCNPolarity: specifies the OC3N Polarity
-  *   This parameter can be one of the following values:
-  *     @arg TIM_OCNPolarity_High: Output Compare active high
-  *     @arg TIM_OCNPolarity_Low: Output Compare active low
-  * @retval None
-  */
-void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
-{
-  uint16_t tmpccer = 0;
- 
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST1_PERIPH(TIMx));
-  assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
-    
-  tmpccer = TIMx->CCER;
-  /* Set or Reset the CC3NP Bit */
-  tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC3NP);
-  tmpccer |= (uint16_t)(TIM_OCNPolarity << 8);
-  /* Write to TIMx CCER register */
-  TIMx->CCER = tmpccer;
-}
-
-/**
-  * @brief  Configures the TIMx channel 4 polarity.
-  * @param  TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
-  * @param  TIM_OCPolarity: specifies the OC4 Polarity
-  *   This parameter can be one of the following values:
-  *     @arg TIM_OCPolarity_High: Output Compare active high
-  *     @arg TIM_OCPolarity_Low: Output Compare active low
-  * @retval None
-  */
-void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
-{
-  uint16_t tmpccer = 0;
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
-  assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
-  tmpccer = TIMx->CCER;
-  /* Set or Reset the CC4P Bit */
-  tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC4P);
-  tmpccer |= (uint16_t)(TIM_OCPolarity << 12);
-  /* Write to TIMx CCER register */
-  TIMx->CCER = tmpccer;
-}
-
-/**
-  * @brief  Enables or disables the TIM Capture Compare Channel x.
-  * @param  TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
-  * @param  TIM_Channel: specifies the TIM Channel
-  *   This parameter can be one of the following values:
-  *     @arg TIM_Channel_1: TIM Channel 1
-  *     @arg TIM_Channel_2: TIM Channel 2
-  *     @arg TIM_Channel_3: TIM Channel 3
-  *     @arg TIM_Channel_4: TIM Channel 4
-  * @param  TIM_CCx: specifies the TIM Channel CCxE bit new state.
-  *   This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable. 
-  * @retval None
-  */
-void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx)
-{
-  uint16_t tmp = 0;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST8_PERIPH(TIMx));
-  assert_param(IS_TIM_CHANNEL(TIM_Channel));
-  assert_param(IS_TIM_CCX(TIM_CCx));
-
-  tmp = CCER_CCE_Set << TIM_Channel;
-
-  /* Reset the CCxE Bit */
-  TIMx->CCER &= (uint16_t)~ tmp;
-
-  /* Set or reset the CCxE Bit */ 
-  TIMx->CCER |=  (uint16_t)(TIM_CCx << TIM_Channel);
-}
-
-/**
-  * @brief  Enables or disables the TIM Capture Compare Channel xN.
-  * @param  TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIM peripheral.
-  * @param  TIM_Channel: specifies the TIM Channel
-  *   This parameter can be one of the following values:
-  *     @arg TIM_Channel_1: TIM Channel 1
-  *     @arg TIM_Channel_2: TIM Channel 2
-  *     @arg TIM_Channel_3: TIM Channel 3
-  * @param  TIM_CCxN: specifies the TIM Channel CCxNE bit new state.
-  *   This parameter can be: TIM_CCxN_Enable or TIM_CCxN_Disable. 
-  * @retval None
-  */
-void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN)
-{
-  uint16_t tmp = 0;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST2_PERIPH(TIMx));
-  assert_param(IS_TIM_COMPLEMENTARY_CHANNEL(TIM_Channel));
-  assert_param(IS_TIM_CCXN(TIM_CCxN));
-
-  tmp = CCER_CCNE_Set << TIM_Channel;
-
-  /* Reset the CCxNE Bit */
-  TIMx->CCER &= (uint16_t) ~tmp;
-
-  /* Set or reset the CCxNE Bit */ 
-  TIMx->CCER |=  (uint16_t)(TIM_CCxN << TIM_Channel);
-}
-
-/**
-  * @brief  Selects the TIM Output Compare Mode.
-  * @note   This function disables the selected channel before changing the Output
-  *         Compare Mode.
-  *         User has to enable this channel using TIM_CCxCmd and TIM_CCxNCmd functions.
-  * @param  TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
-  * @param  TIM_Channel: specifies the TIM Channel
-  *   This parameter can be one of the following values:
-  *     @arg TIM_Channel_1: TIM Channel 1
-  *     @arg TIM_Channel_2: TIM Channel 2
-  *     @arg TIM_Channel_3: TIM Channel 3
-  *     @arg TIM_Channel_4: TIM Channel 4
-  * @param  TIM_OCMode: specifies the TIM Output Compare Mode.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_OCMode_Timing
-  *     @arg TIM_OCMode_Active
-  *     @arg TIM_OCMode_Toggle
-  *     @arg TIM_OCMode_PWM1
-  *     @arg TIM_OCMode_PWM2
-  *     @arg TIM_ForcedAction_Active
-  *     @arg TIM_ForcedAction_InActive
-  * @retval None
-  */
-void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode)
-{
-  uint32_t tmp = 0;
-  uint16_t tmp1 = 0;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST8_PERIPH(TIMx));
-  assert_param(IS_TIM_CHANNEL(TIM_Channel));
-  assert_param(IS_TIM_OCM(TIM_OCMode));
-
-  tmp = (uint32_t) TIMx;
-  tmp += CCMR_Offset;
-
-  tmp1 = CCER_CCE_Set << (uint16_t)TIM_Channel;
-
-  /* Disable the Channel: Reset the CCxE Bit */
-  TIMx->CCER &= (uint16_t) ~tmp1;
-
-  if((TIM_Channel == TIM_Channel_1) ||(TIM_Channel == TIM_Channel_3))
-  {
-    tmp += (TIM_Channel>>1);
-
-    /* Reset the OCxM bits in the CCMRx register */
-    *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC1M);
-   
-    /* Configure the OCxM bits in the CCMRx register */
-    *(__IO uint32_t *) tmp |= TIM_OCMode;
-  }
-  else
-  {
-    tmp += (uint16_t)(TIM_Channel - (uint16_t)4)>> (uint16_t)1;
-
-    /* Reset the OCxM bits in the CCMRx register */
-    *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC2M);
-    
-    /* Configure the OCxM bits in the CCMRx register */
-    *(__IO uint32_t *) tmp |= (uint16_t)(TIM_OCMode << 8);
-  }
-}
-
-/**
-  * @brief  Enables or Disables the TIMx Update event.
-  * @param  TIMx: where x can be 1 to 17 to select the TIM peripheral.
-  * @param  NewState: new state of the TIMx UDIS bit
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_ALL_PERIPH(TIMx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  if (NewState != DISABLE)
-  {
-    /* Set the Update Disable Bit */
-    TIMx->CR1 |= TIM_CR1_UDIS;
-  }
-  else
-  {
-    /* Reset the Update Disable Bit */
-    TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_UDIS);
-  }
-}
-
-/**
-  * @brief  Configures the TIMx Update Request Interrupt source.
-  * @param  TIMx: where x can be 1 to 17 to select the TIM peripheral.
-  * @param  TIM_UpdateSource: specifies the Update source.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_UpdateSource_Regular: Source of update is the counter overflow/underflow
-                                       or the setting of UG bit, or an update generation
-                                       through the slave mode controller.
-  *     @arg TIM_UpdateSource_Global: Source of update is counter overflow/underflow.
-  * @retval None
-  */
-void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_ALL_PERIPH(TIMx));
-  assert_param(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource));
-  if (TIM_UpdateSource != TIM_UpdateSource_Global)
-  {
-    /* Set the URS Bit */
-    TIMx->CR1 |= TIM_CR1_URS;
-  }
-  else
-  {
-    /* Reset the URS Bit */
-    TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_URS);
-  }
-}
-
-/**
-  * @brief  Enables or disables the TIMx's Hall sensor interface.
-  * @param  TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
-  * @param  NewState: new state of the TIMx Hall sensor interface.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST6_PERIPH(TIMx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  if (NewState != DISABLE)
-  {
-    /* Set the TI1S Bit */
-    TIMx->CR2 |= TIM_CR2_TI1S;
-  }
-  else
-  {
-    /* Reset the TI1S Bit */
-    TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_TI1S);
-  }
-}
-
-/**
-  * @brief  Selects the TIMx's One Pulse Mode.
-  * @param  TIMx: where x can be 1 to 17 to select the TIM peripheral.
-  * @param  TIM_OPMode: specifies the OPM Mode to be used.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_OPMode_Single
-  *     @arg TIM_OPMode_Repetitive
-  * @retval None
-  */
-void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_ALL_PERIPH(TIMx));
-  assert_param(IS_TIM_OPM_MODE(TIM_OPMode));
-  /* Reset the OPM Bit */
-  TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_OPM);
-  /* Configure the OPM Mode */
-  TIMx->CR1 |= TIM_OPMode;
-}
-
-/**
-  * @brief  Selects the TIMx Trigger Output Mode.
-  * @param  TIMx: where x can be 1, 2, 3, 4, 5, 6, 7, 8, 9, 12 or 15 to select the TIM peripheral.
-  * @param  TIM_TRGOSource: specifies the Trigger Output source.
-  *   This paramter can be one of the following values:
-  *
-  *  - For all TIMx
-  *     @arg TIM_TRGOSource_Reset:  The UG bit in the TIM_EGR register is used as the trigger output (TRGO).
-  *     @arg TIM_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output (TRGO).
-  *     @arg TIM_TRGOSource_Update: The update event is selected as the trigger output (TRGO).
-  *
-  *  - For all TIMx except TIM6 and TIM7
-  *     @arg TIM_TRGOSource_OC1: The trigger output sends a positive pulse when the CC1IF flag
-  *                              is to be set, as soon as a capture or compare match occurs (TRGO).
-  *     @arg TIM_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output (TRGO).
-  *     @arg TIM_TRGOSource_OC2Ref: OC2REF signal is used as the trigger output (TRGO).
-  *     @arg TIM_TRGOSource_OC3Ref: OC3REF signal is used as the trigger output (TRGO).
-  *     @arg TIM_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output (TRGO).
-  *
-  * @retval None
-  */
-void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST7_PERIPH(TIMx));
-  assert_param(IS_TIM_TRGO_SOURCE(TIM_TRGOSource));
-  /* Reset the MMS Bits */
-  TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_MMS);
-  /* Select the TRGO source */
-  TIMx->CR2 |=  TIM_TRGOSource;
-}
-
-/**
-  * @brief  Selects the TIMx Slave Mode.
-  * @param  TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
-  * @param  TIM_SlaveMode: specifies the Timer Slave Mode.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_SlaveMode_Reset: Rising edge of the selected trigger signal (TRGI) re-initializes
-  *                               the counter and triggers an update of the registers.
-  *     @arg TIM_SlaveMode_Gated:     The counter clock is enabled when the trigger signal (TRGI) is high.
-  *     @arg TIM_SlaveMode_Trigger:   The counter starts at a rising edge of the trigger TRGI.
-  *     @arg TIM_SlaveMode_External1: Rising edges of the selected trigger (TRGI) clock the counter.
-  * @retval None
-  */
-void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST6_PERIPH(TIMx));
-  assert_param(IS_TIM_SLAVE_MODE(TIM_SlaveMode));
- /* Reset the SMS Bits */
-  TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_SMS);
-  /* Select the Slave Mode */
-  TIMx->SMCR |= TIM_SlaveMode;
-}
-
-/**
-  * @brief  Sets or Resets the TIMx Master/Slave Mode.
-  * @param  TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
-  * @param  TIM_MasterSlaveMode: specifies the Timer Master Slave Mode.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_MasterSlaveMode_Enable: synchronization between the current timer
-  *                                      and its slaves (through TRGO).
-  *     @arg TIM_MasterSlaveMode_Disable: No action
-  * @retval None
-  */
-void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST6_PERIPH(TIMx));
-  assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode));
-  /* Reset the MSM Bit */
-  TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_MSM);
-  
-  /* Set or Reset the MSM Bit */
-  TIMx->SMCR |= TIM_MasterSlaveMode;
-}
-
-/**
-  * @brief  Sets the TIMx Counter Register value
-  * @param  TIMx: where x can be 1 to 17 to select the TIM peripheral.
-  * @param  Counter: specifies the Counter register new value.
-  * @retval None
-  */
-void TIM_SetCounter(TIM_TypeDef* TIMx, uint16_t Counter)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_ALL_PERIPH(TIMx));
-  /* Set the Counter Register value */
-  TIMx->CNT = Counter;
-}
-
-/**
-  * @brief  Sets the TIMx Autoreload Register value
-  * @param  TIMx: where x can be 1 to 17 to select the TIM peripheral.
-  * @param  Autoreload: specifies the Autoreload register new value.
-  * @retval None
-  */
-void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint16_t Autoreload)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_ALL_PERIPH(TIMx));
-  /* Set the Autoreload Register value */
-  TIMx->ARR = Autoreload;
-}
-
-/**
-  * @brief  Sets the TIMx Capture Compare1 Register value
-  * @param  TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
-  * @param  Compare1: specifies the Capture Compare1 register new value.
-  * @retval None
-  */
-void TIM_SetCompare1(TIM_TypeDef* TIMx, uint16_t Compare1)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST8_PERIPH(TIMx));
-  /* Set the Capture Compare1 Register value */
-  TIMx->CCR1 = Compare1;
-}
-
-/**
-  * @brief  Sets the TIMx Capture Compare2 Register value
-  * @param  TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
-  * @param  Compare2: specifies the Capture Compare2 register new value.
-  * @retval None
-  */
-void TIM_SetCompare2(TIM_TypeDef* TIMx, uint16_t Compare2)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST6_PERIPH(TIMx));
-  /* Set the Capture Compare2 Register value */
-  TIMx->CCR2 = Compare2;
-}
-
-/**
-  * @brief  Sets the TIMx Capture Compare3 Register value
-  * @param  TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
-  * @param  Compare3: specifies the Capture Compare3 register new value.
-  * @retval None
-  */
-void TIM_SetCompare3(TIM_TypeDef* TIMx, uint16_t Compare3)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
-  /* Set the Capture Compare3 Register value */
-  TIMx->CCR3 = Compare3;
-}
-
-/**
-  * @brief  Sets the TIMx Capture Compare4 Register value
-  * @param  TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
-  * @param  Compare4: specifies the Capture Compare4 register new value.
-  * @retval None
-  */
-void TIM_SetCompare4(TIM_TypeDef* TIMx, uint16_t Compare4)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
-  /* Set the Capture Compare4 Register value */
-  TIMx->CCR4 = Compare4;
-}
-
-/**
-  * @brief  Sets the TIMx Input Capture 1 prescaler.
-  * @param  TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
-  * @param  TIM_ICPSC: specifies the Input Capture1 prescaler new value.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_ICPSC_DIV1: no prescaler
-  *     @arg TIM_ICPSC_DIV2: capture is done once every 2 events
-  *     @arg TIM_ICPSC_DIV4: capture is done once every 4 events
-  *     @arg TIM_ICPSC_DIV8: capture is done once every 8 events
-  * @retval None
-  */
-void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST8_PERIPH(TIMx));
-  assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
-  /* Reset the IC1PSC Bits */
-  TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC1PSC);
-  /* Set the IC1PSC value */
-  TIMx->CCMR1 |= TIM_ICPSC;
-}
-
-/**
-  * @brief  Sets the TIMx Input Capture 2 prescaler.
-  * @param  TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
-  * @param  TIM_ICPSC: specifies the Input Capture2 prescaler new value.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_ICPSC_DIV1: no prescaler
-  *     @arg TIM_ICPSC_DIV2: capture is done once every 2 events
-  *     @arg TIM_ICPSC_DIV4: capture is done once every 4 events
-  *     @arg TIM_ICPSC_DIV8: capture is done once every 8 events
-  * @retval None
-  */
-void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST6_PERIPH(TIMx));
-  assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
-  /* Reset the IC2PSC Bits */
-  TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC2PSC);
-  /* Set the IC2PSC value */
-  TIMx->CCMR1 |= (uint16_t)(TIM_ICPSC << 8);
-}
-
-/**
-  * @brief  Sets the TIMx Input Capture 3 prescaler.
-  * @param  TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
-  * @param  TIM_ICPSC: specifies the Input Capture3 prescaler new value.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_ICPSC_DIV1: no prescaler
-  *     @arg TIM_ICPSC_DIV2: capture is done once every 2 events
-  *     @arg TIM_ICPSC_DIV4: capture is done once every 4 events
-  *     @arg TIM_ICPSC_DIV8: capture is done once every 8 events
-  * @retval None
-  */
-void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
-  assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
-  /* Reset the IC3PSC Bits */
-  TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC3PSC);
-  /* Set the IC3PSC value */
-  TIMx->CCMR2 |= TIM_ICPSC;
-}
-
-/**
-  * @brief  Sets the TIMx Input Capture 4 prescaler.
-  * @param  TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
-  * @param  TIM_ICPSC: specifies the Input Capture4 prescaler new value.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_ICPSC_DIV1: no prescaler
-  *     @arg TIM_ICPSC_DIV2: capture is done once every 2 events
-  *     @arg TIM_ICPSC_DIV4: capture is done once every 4 events
-  *     @arg TIM_ICPSC_DIV8: capture is done once every 8 events
-  * @retval None
-  */
-void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
-{  
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
-  assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
-  /* Reset the IC4PSC Bits */
-  TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC4PSC);
-  /* Set the IC4PSC value */
-  TIMx->CCMR2 |= (uint16_t)(TIM_ICPSC << 8);
-}
-
-/**
-  * @brief  Sets the TIMx Clock Division value.
-  * @param  TIMx: where x can be  1 to 17 except 6 and 7 to select 
-  *   the TIM peripheral.
-  * @param  TIM_CKD: specifies the clock division value.
-  *   This parameter can be one of the following value:
-  *     @arg TIM_CKD_DIV1: TDTS = Tck_tim
-  *     @arg TIM_CKD_DIV2: TDTS = 2*Tck_tim
-  *     @arg TIM_CKD_DIV4: TDTS = 4*Tck_tim
-  * @retval None
-  */
-void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST8_PERIPH(TIMx));
-  assert_param(IS_TIM_CKD_DIV(TIM_CKD));
-  /* Reset the CKD Bits */
-  TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_CKD);
-  /* Set the CKD value */
-  TIMx->CR1 |= TIM_CKD;
-}
-
-/**
-  * @brief  Gets the TIMx Input Capture 1 value.
-  * @param  TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
-  * @retval Capture Compare 1 Register value.
-  */
-uint16_t TIM_GetCapture1(TIM_TypeDef* TIMx)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST8_PERIPH(TIMx));
-  /* Get the Capture 1 Register value */
-  return TIMx->CCR1;
-}
-
-/**
-  * @brief  Gets the TIMx Input Capture 2 value.
-  * @param  TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
-  * @retval Capture Compare 2 Register value.
-  */
-uint16_t TIM_GetCapture2(TIM_TypeDef* TIMx)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST6_PERIPH(TIMx));
-  /* Get the Capture 2 Register value */
-  return TIMx->CCR2;
-}
-
-/**
-  * @brief  Gets the TIMx Input Capture 3 value.
-  * @param  TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
-  * @retval Capture Compare 3 Register value.
-  */
-uint16_t TIM_GetCapture3(TIM_TypeDef* TIMx)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST3_PERIPH(TIMx)); 
-  /* Get the Capture 3 Register value */
-  return TIMx->CCR3;
-}
-
-/**
-  * @brief  Gets the TIMx Input Capture 4 value.
-  * @param  TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
-  * @retval Capture Compare 4 Register value.
-  */
-uint16_t TIM_GetCapture4(TIM_TypeDef* TIMx)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
-  /* Get the Capture 4 Register value */
-  return TIMx->CCR4;
-}
-
-/**
-  * @brief  Gets the TIMx Counter value.
-  * @param  TIMx: where x can be 1 to 17 to select the TIM peripheral.
-  * @retval Counter Register value.
-  */
-uint16_t TIM_GetCounter(TIM_TypeDef* TIMx)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_ALL_PERIPH(TIMx));
-  /* Get the Counter Register value */
-  return TIMx->CNT;
-}
-
-/**
-  * @brief  Gets the TIMx Prescaler value.
-  * @param  TIMx: where x can be 1 to 17 to select the TIM peripheral.
-  * @retval Prescaler Register value.
-  */
-uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_ALL_PERIPH(TIMx));
-  /* Get the Prescaler Register value */
-  return TIMx->PSC;
-}
-
-/**
-  * @brief  Checks whether the specified TIM flag is set or not.
-  * @param  TIMx: where x can be 1 to 17 to select the TIM peripheral.
-  * @param  TIM_FLAG: specifies the flag to check.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_FLAG_Update: TIM update Flag
-  *     @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag
-  *     @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag
-  *     @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag
-  *     @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag
-  *     @arg TIM_FLAG_COM: TIM Commutation Flag
-  *     @arg TIM_FLAG_Trigger: TIM Trigger Flag
-  *     @arg TIM_FLAG_Break: TIM Break Flag
-  *     @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag
-  *     @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag
-  *     @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag
-  *     @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag
-  * @note
-  *   - TIM6 and TIM7 can have only one update flag. 
-  *   - TIM9, TIM12 and TIM15 can have only TIM_FLAG_Update, TIM_FLAG_CC1,
-  *      TIM_FLAG_CC2 or TIM_FLAG_Trigger. 
-  *   - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_FLAG_Update or TIM_FLAG_CC1.   
-  *   - TIM_FLAG_Break is used only with TIM1, TIM8 and TIM15. 
-  *   - TIM_FLAG_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17.    
-  * @retval The new state of TIM_FLAG (SET or RESET).
-  */
-FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)
-{ 
-  ITStatus bitstatus = RESET;  
-  /* Check the parameters */
-  assert_param(IS_TIM_ALL_PERIPH(TIMx));
-  assert_param(IS_TIM_GET_FLAG(TIM_FLAG));
-  
-  if ((TIMx->SR & TIM_FLAG) != (uint16_t)RESET)
-  {
-    bitstatus = SET;
-  }
-  else
-  {
-    bitstatus = RESET;
-  }
-  return bitstatus;
-}
-
-/**
-  * @brief  Clears the TIMx's pending flags.
-  * @param  TIMx: where x can be 1 to 17 to select the TIM peripheral.
-  * @param  TIM_FLAG: specifies the flag bit to clear.
-  *   This parameter can be any combination of the following values:
-  *     @arg TIM_FLAG_Update: TIM update Flag
-  *     @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag
-  *     @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag
-  *     @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag
-  *     @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag
-  *     @arg TIM_FLAG_COM: TIM Commutation Flag
-  *     @arg TIM_FLAG_Trigger: TIM Trigger Flag
-  *     @arg TIM_FLAG_Break: TIM Break Flag
-  *     @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag
-  *     @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag
-  *     @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag
-  *     @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag
-  * @note
-  *   - TIM6 and TIM7 can have only one update flag. 
-  *   - TIM9, TIM12 and TIM15 can have only TIM_FLAG_Update, TIM_FLAG_CC1,
-  *      TIM_FLAG_CC2 or TIM_FLAG_Trigger. 
-  *   - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_FLAG_Update or TIM_FLAG_CC1.   
-  *   - TIM_FLAG_Break is used only with TIM1, TIM8 and TIM15. 
-  *   - TIM_FLAG_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17.   
-  * @retval None
-  */
-void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)
-{  
-  /* Check the parameters */
-  assert_param(IS_TIM_ALL_PERIPH(TIMx));
-  assert_param(IS_TIM_CLEAR_FLAG(TIM_FLAG));
-   
-  /* Clear the flags */
-  TIMx->SR = (uint16_t)~TIM_FLAG;
-}
-
-/**
-  * @brief  Checks whether the TIM interrupt has occurred or not.
-  * @param  TIMx: where x can be 1 to 17 to select the TIM peripheral.
-  * @param  TIM_IT: specifies the TIM interrupt source to check.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_IT_Update: TIM update Interrupt source
-  *     @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
-  *     @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
-  *     @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
-  *     @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
-  *     @arg TIM_IT_COM: TIM Commutation Interrupt source
-  *     @arg TIM_IT_Trigger: TIM Trigger Interrupt source
-  *     @arg TIM_IT_Break: TIM Break Interrupt source
-  * @note
-  *   - TIM6 and TIM7 can generate only an update interrupt.
-  *   - TIM9, TIM12 and TIM15 can have only TIM_IT_Update, TIM_IT_CC1,
-  *      TIM_IT_CC2 or TIM_IT_Trigger. 
-  *   - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1.   
-  *   - TIM_IT_Break is used only with TIM1, TIM8 and TIM15. 
-  *   - TIM_IT_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17.  
-  * @retval The new state of the TIM_IT(SET or RESET).
-  */
-ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT)
-{
-  ITStatus bitstatus = RESET;  
-  uint16_t itstatus = 0x0, itenable = 0x0;
-  /* Check the parameters */
-  assert_param(IS_TIM_ALL_PERIPH(TIMx));
-  assert_param(IS_TIM_GET_IT(TIM_IT));
-   
-  itstatus = TIMx->SR & TIM_IT;
-  
-  itenable = TIMx->DIER & TIM_IT;
-  if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET))
-  {
-    bitstatus = SET;
-  }
-  else
-  {
-    bitstatus = RESET;
-  }
-  return bitstatus;
-}
-
-/**
-  * @brief  Clears the TIMx's interrupt pending bits.
-  * @param  TIMx: where x can be 1 to 17 to select the TIM peripheral.
-  * @param  TIM_IT: specifies the pending bit to clear.
-  *   This parameter can be any combination of the following values:
-  *     @arg TIM_IT_Update: TIM1 update Interrupt source
-  *     @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
-  *     @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
-  *     @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
-  *     @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
-  *     @arg TIM_IT_COM: TIM Commutation Interrupt source
-  *     @arg TIM_IT_Trigger: TIM Trigger Interrupt source
-  *     @arg TIM_IT_Break: TIM Break Interrupt source
-  * @note
-  *   - TIM6 and TIM7 can generate only an update interrupt.
-  *   - TIM9, TIM12 and TIM15 can have only TIM_IT_Update, TIM_IT_CC1,
-  *      TIM_IT_CC2 or TIM_IT_Trigger. 
-  *   - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1.   
-  *   - TIM_IT_Break is used only with TIM1, TIM8 and TIM15. 
-  *   - TIM_IT_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17.    
-  * @retval None
-  */
-void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_ALL_PERIPH(TIMx));
-  assert_param(IS_TIM_IT(TIM_IT));
-  /* Clear the IT pending Bit */
-  TIMx->SR = (uint16_t)~TIM_IT;
-}
-
-/**
-  * @brief  Configure the TI1 as Input.
-  * @param  TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
-  * @param  TIM_ICPolarity : The Input Polarity.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_ICPolarity_Rising
-  *     @arg TIM_ICPolarity_Falling
-  * @param  TIM_ICSelection: specifies the input to be used.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
-  *     @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
-  *     @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
-  * @param  TIM_ICFilter: Specifies the Input Capture Filter.
-  *   This parameter must be a value between 0x00 and 0x0F.
-  * @retval None
-  */
-static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
-                       uint16_t TIM_ICFilter)
-{
-  uint16_t tmpccmr1 = 0, tmpccer = 0;
-  /* Disable the Channel 1: Reset the CC1E Bit */
-  TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC1E);
-  tmpccmr1 = TIMx->CCMR1;
-  tmpccer = TIMx->CCER;
-  /* Select the Input and set the filter */
-  tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC1F)));
-  tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));
-  
-  if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) ||
-     (TIMx == TIM4) ||(TIMx == TIM5))
-  {
-    /* Select the Polarity and set the CC1E Bit */
-    tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC1P));
-    tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E);
-  }
-  else
-  {
-    /* Select the Polarity and set the CC1E Bit */
-    tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC1P | TIM_CCER_CC1NP));
-    tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E);
-  }
-
-  /* Write to TIMx CCMR1 and CCER registers */
-  TIMx->CCMR1 = tmpccmr1;
-  TIMx->CCER = tmpccer;
-}
-
-/**
-  * @brief  Configure the TI2 as Input.
-  * @param  TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
-  * @param  TIM_ICPolarity : The Input Polarity.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_ICPolarity_Rising
-  *     @arg TIM_ICPolarity_Falling
-  * @param  TIM_ICSelection: specifies the input to be used.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.
-  *     @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.
-  *     @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.
-  * @param  TIM_ICFilter: Specifies the Input Capture Filter.
-  *   This parameter must be a value between 0x00 and 0x0F.
-  * @retval None
-  */
-static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
-                       uint16_t TIM_ICFilter)
-{
-  uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0;
-  /* Disable the Channel 2: Reset the CC2E Bit */
-  TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC2E);
-  tmpccmr1 = TIMx->CCMR1;
-  tmpccer = TIMx->CCER;
-  tmp = (uint16_t)(TIM_ICPolarity << 4);
-  /* Select the Input and set the filter */
-  tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC2S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC2F)));
-  tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12);
-  tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8);
-  
-  if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) ||
-     (TIMx == TIM4) ||(TIMx == TIM5))
-  {
-    /* Select the Polarity and set the CC2E Bit */
-    tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC2P));
-    tmpccer |=  (uint16_t)(tmp | (uint16_t)TIM_CCER_CC2E);
-  }
-  else
-  {
-    /* Select the Polarity and set the CC2E Bit */
-    tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC2P | TIM_CCER_CC2NP));
-    tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC2E);
-  }
-  
-  /* Write to TIMx CCMR1 and CCER registers */
-  TIMx->CCMR1 = tmpccmr1 ;
-  TIMx->CCER = tmpccer;
-}
-
-/**
-  * @brief  Configure the TI3 as Input.
-  * @param  TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
-  * @param  TIM_ICPolarity : The Input Polarity.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_ICPolarity_Rising
-  *     @arg TIM_ICPolarity_Falling
-  * @param  TIM_ICSelection: specifies the input to be used.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.
-  *     @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.
-  *     @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.
-  * @param  TIM_ICFilter: Specifies the Input Capture Filter.
-  *   This parameter must be a value between 0x00 and 0x0F.
-  * @retval None
-  */
-static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
-                       uint16_t TIM_ICFilter)
-{
-  uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
-  /* Disable the Channel 3: Reset the CC3E Bit */
-  TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC3E);
-  tmpccmr2 = TIMx->CCMR2;
-  tmpccer = TIMx->CCER;
-  tmp = (uint16_t)(TIM_ICPolarity << 8);
-  /* Select the Input and set the filter */
-  tmpccmr2 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR2_CC3S)) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC3F)));
-  tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));
-    
-  if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) ||
-     (TIMx == TIM4) ||(TIMx == TIM5))
-  {
-    /* Select the Polarity and set the CC3E Bit */
-    tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P));
-    tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC3E);
-  }
-  else
-  {
-    /* Select the Polarity and set the CC3E Bit */
-    tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P | TIM_CCER_CC3NP));
-    tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC3E);
-  }
-  
-  /* Write to TIMx CCMR2 and CCER registers */
-  TIMx->CCMR2 = tmpccmr2;
-  TIMx->CCER = tmpccer;
-}
-
-/**
-  * @brief  Configure the TI4 as Input.
-  * @param  TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
-  * @param  TIM_ICPolarity : The Input Polarity.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_ICPolarity_Rising
-  *     @arg TIM_ICPolarity_Falling
-  * @param  TIM_ICSelection: specifies the input to be used.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.
-  *     @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.
-  *     @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.
-  * @param  TIM_ICFilter: Specifies the Input Capture Filter.
-  *   This parameter must be a value between 0x00 and 0x0F.
-  * @retval None
-  */
-static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
-                       uint16_t TIM_ICFilter)
-{
-  uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
-
-   /* Disable the Channel 4: Reset the CC4E Bit */
-  TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC4E);
-  tmpccmr2 = TIMx->CCMR2;
-  tmpccer = TIMx->CCER;
-  tmp = (uint16_t)(TIM_ICPolarity << 12);
-  /* Select the Input and set the filter */
-  tmpccmr2 &= (uint16_t)((uint16_t)(~(uint16_t)TIM_CCMR2_CC4S) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC4F)));
-  tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8);
-  tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12);
-  
-  if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) ||
-     (TIMx == TIM4) ||(TIMx == TIM5))
-  {
-    /* Select the Polarity and set the CC4E Bit */
-    tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC4P));
-    tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC4E);
-  }
-  else
-  {
-    /* Select the Polarity and set the CC4E Bit */
-    tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P | TIM_CCER_CC4NP));
-    tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC4E);
-  }
-  /* Write to TIMx CCMR2 and CCER registers */
-  TIMx->CCMR2 = tmpccmr2;
-  TIMx->CCER = tmpccer;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c
deleted file mode 100644
index e794eae..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c
+++ /dev/null
@@ -1,1058 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f10x_usart.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    11-March-2011
-  * @brief   This file provides all the USART firmware functions.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_usart.h"
-#include "stm32f10x_rcc.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Driver
-  * @{
-  */
-
-/** @defgroup USART 
-  * @brief USART driver modules
-  * @{
-  */
-
-/** @defgroup USART_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup USART_Private_Defines
-  * @{
-  */
-
-#define CR1_UE_Set                ((uint16_t)0x2000)  /*!< USART Enable Mask */
-#define CR1_UE_Reset              ((uint16_t)0xDFFF)  /*!< USART Disable Mask */
-
-#define CR1_WAKE_Mask             ((uint16_t)0xF7FF)  /*!< USART WakeUp Method Mask */
-
-#define CR1_RWU_Set               ((uint16_t)0x0002)  /*!< USART mute mode Enable Mask */
-#define CR1_RWU_Reset             ((uint16_t)0xFFFD)  /*!< USART mute mode Enable Mask */
-#define CR1_SBK_Set               ((uint16_t)0x0001)  /*!< USART Break Character send Mask */
-#define CR1_CLEAR_Mask            ((uint16_t)0xE9F3)  /*!< USART CR1 Mask */
-#define CR2_Address_Mask          ((uint16_t)0xFFF0)  /*!< USART address Mask */
-
-#define CR2_LINEN_Set              ((uint16_t)0x4000)  /*!< USART LIN Enable Mask */
-#define CR2_LINEN_Reset            ((uint16_t)0xBFFF)  /*!< USART LIN Disable Mask */
-
-#define CR2_LBDL_Mask             ((uint16_t)0xFFDF)  /*!< USART LIN Break detection Mask */
-#define CR2_STOP_CLEAR_Mask       ((uint16_t)0xCFFF)  /*!< USART CR2 STOP Bits Mask */
-#define CR2_CLOCK_CLEAR_Mask      ((uint16_t)0xF0FF)  /*!< USART CR2 Clock Mask */
-
-#define CR3_SCEN_Set              ((uint16_t)0x0020)  /*!< USART SC Enable Mask */
-#define CR3_SCEN_Reset            ((uint16_t)0xFFDF)  /*!< USART SC Disable Mask */
-
-#define CR3_NACK_Set              ((uint16_t)0x0010)  /*!< USART SC NACK Enable Mask */
-#define CR3_NACK_Reset            ((uint16_t)0xFFEF)  /*!< USART SC NACK Disable Mask */
-
-#define CR3_HDSEL_Set             ((uint16_t)0x0008)  /*!< USART Half-Duplex Enable Mask */
-#define CR3_HDSEL_Reset           ((uint16_t)0xFFF7)  /*!< USART Half-Duplex Disable Mask */
-
-#define CR3_IRLP_Mask             ((uint16_t)0xFFFB)  /*!< USART IrDA LowPower mode Mask */
-#define CR3_CLEAR_Mask            ((uint16_t)0xFCFF)  /*!< USART CR3 Mask */
-
-#define CR3_IREN_Set              ((uint16_t)0x0002)  /*!< USART IrDA Enable Mask */
-#define CR3_IREN_Reset            ((uint16_t)0xFFFD)  /*!< USART IrDA Disable Mask */
-#define GTPR_LSB_Mask             ((uint16_t)0x00FF)  /*!< Guard Time Register LSB Mask */
-#define GTPR_MSB_Mask             ((uint16_t)0xFF00)  /*!< Guard Time Register MSB Mask */
-#define IT_Mask                   ((uint16_t)0x001F)  /*!< USART Interrupt Mask */
-
-/* USART OverSampling-8 Mask */
-#define CR1_OVER8_Set             ((u16)0x8000)  /* USART OVER8 mode Enable Mask */
-#define CR1_OVER8_Reset           ((u16)0x7FFF)  /* USART OVER8 mode Disable Mask */
-
-/* USART One Bit Sampling Mask */
-#define CR3_ONEBITE_Set           ((u16)0x0800)  /* USART ONEBITE mode Enable Mask */
-#define CR3_ONEBITE_Reset         ((u16)0xF7FF)  /* USART ONEBITE mode Disable Mask */
-
-/**
-  * @}
-  */
-
-/** @defgroup USART_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup USART_Private_Variables
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup USART_Private_FunctionPrototypes
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup USART_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Deinitializes the USARTx peripheral registers to their default reset values.
-  * @param  USARTx: Select the USART or the UART peripheral. 
-  *   This parameter can be one of the following values: 
-  *      USART1, USART2, USART3, UART4 or UART5.
-  * @retval None
-  */
-void USART_DeInit(USART_TypeDef* USARTx)
-{
-  /* Check the parameters */
-  assert_param(IS_USART_ALL_PERIPH(USARTx));
-
-  if (USARTx == USART1)
-  {
-    RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE);
-    RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE);
-  }
-  else if (USARTx == USART2)
-  {
-    RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE);
-    RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE);
-  }
-  else if (USARTx == USART3)
-  {
-    RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE);
-    RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE);
-  }    
-  else if (USARTx == UART4)
-  {
-    RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, ENABLE);
-    RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, DISABLE);
-  }    
-  else
-  {
-    if (USARTx == UART5)
-    { 
-      RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, ENABLE);
-      RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, DISABLE);
-    }
-  }
-}
-
-/**
-  * @brief  Initializes the USARTx peripheral according to the specified
-  *         parameters in the USART_InitStruct .
-  * @param  USARTx: Select the USART or the UART peripheral. 
-  *   This parameter can be one of the following values:
-  *   USART1, USART2, USART3, UART4 or UART5.
-  * @param  USART_InitStruct: pointer to a USART_InitTypeDef structure
-  *         that contains the configuration information for the specified USART 
-  *         peripheral.
-  * @retval None
-  */
-void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct)
-{
-  uint32_t tmpreg = 0x00, apbclock = 0x00;
-  uint32_t integerdivider = 0x00;
-  uint32_t fractionaldivider = 0x00;
-  uint32_t usartxbase = 0;
-  RCC_ClocksTypeDef RCC_ClocksStatus;
-  /* Check the parameters */
-  assert_param(IS_USART_ALL_PERIPH(USARTx));
-  assert_param(IS_USART_BAUDRATE(USART_InitStruct->USART_BaudRate));  
-  assert_param(IS_USART_WORD_LENGTH(USART_InitStruct->USART_WordLength));
-  assert_param(IS_USART_STOPBITS(USART_InitStruct->USART_StopBits));
-  assert_param(IS_USART_PARITY(USART_InitStruct->USART_Parity));
-  assert_param(IS_USART_MODE(USART_InitStruct->USART_Mode));
-  assert_param(IS_USART_HARDWARE_FLOW_CONTROL(USART_InitStruct->USART_HardwareFlowControl));
-  /* The hardware flow control is available only for USART1, USART2 and USART3 */
-  if (USART_InitStruct->USART_HardwareFlowControl != USART_HardwareFlowControl_None)
-  {
-    assert_param(IS_USART_123_PERIPH(USARTx));
-  }
-
-  usartxbase = (uint32_t)USARTx;
-
-/*---------------------------- USART CR2 Configuration -----------------------*/
-  tmpreg = USARTx->CR2;
-  /* Clear STOP[13:12] bits */
-  tmpreg &= CR2_STOP_CLEAR_Mask;
-  /* Configure the USART Stop Bits, Clock, CPOL, CPHA and LastBit ------------*/
-  /* Set STOP[13:12] bits according to USART_StopBits value */
-  tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits;
-  
-  /* Write to USART CR2 */
-  USARTx->CR2 = (uint16_t)tmpreg;
-
-/*---------------------------- USART CR1 Configuration -----------------------*/
-  tmpreg = USARTx->CR1;
-  /* Clear M, PCE, PS, TE and RE bits */
-  tmpreg &= CR1_CLEAR_Mask;
-  /* Configure the USART Word Length, Parity and mode ----------------------- */
-  /* Set the M bits according to USART_WordLength value */
-  /* Set PCE and PS bits according to USART_Parity value */
-  /* Set TE and RE bits according to USART_Mode value */
-  tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity |
-            USART_InitStruct->USART_Mode;
-  /* Write to USART CR1 */
-  USARTx->CR1 = (uint16_t)tmpreg;
-
-/*---------------------------- USART CR3 Configuration -----------------------*/  
-  tmpreg = USARTx->CR3;
-  /* Clear CTSE and RTSE bits */
-  tmpreg &= CR3_CLEAR_Mask;
-  /* Configure the USART HFC -------------------------------------------------*/
-  /* Set CTSE and RTSE bits according to USART_HardwareFlowControl value */
-  tmpreg |= USART_InitStruct->USART_HardwareFlowControl;
-  /* Write to USART CR3 */
-  USARTx->CR3 = (uint16_t)tmpreg;
-
-/*---------------------------- USART BRR Configuration -----------------------*/
-  /* Configure the USART Baud Rate -------------------------------------------*/
-  RCC_GetClocksFreq(&RCC_ClocksStatus);
-  if (usartxbase == USART1_BASE)
-  {
-    apbclock = RCC_ClocksStatus.PCLK2_Frequency;
-  }
-  else
-  {
-    apbclock = RCC_ClocksStatus.PCLK1_Frequency;
-  }
-  
-  /* Determine the integer part */
-  if ((USARTx->CR1 & CR1_OVER8_Set) != 0)
-  {
-    /* Integer part computing in case Oversampling mode is 8 Samples */
-    integerdivider = ((25 * apbclock) / (2 * (USART_InitStruct->USART_BaudRate)));    
-  }
-  else /* if ((USARTx->CR1 & CR1_OVER8_Set) == 0) */
-  {
-    /* Integer part computing in case Oversampling mode is 16 Samples */
-    integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->USART_BaudRate)));    
-  }
-  tmpreg = (integerdivider / 100) << 4;
-
-  /* Determine the fractional part */
-  fractionaldivider = integerdivider - (100 * (tmpreg >> 4));
-
-  /* Implement the fractional part in the register */
-  if ((USARTx->CR1 & CR1_OVER8_Set) != 0)
-  {
-    tmpreg |= ((((fractionaldivider * 8) + 50) / 100)) & ((uint8_t)0x07);
-  }
-  else /* if ((USARTx->CR1 & CR1_OVER8_Set) == 0) */
-  {
-    tmpreg |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F);
-  }
-  
-  /* Write to USART BRR */
-  USARTx->BRR = (uint16_t)tmpreg;
-}
-
-/**
-  * @brief  Fills each USART_InitStruct member with its default value.
-  * @param  USART_InitStruct: pointer to a USART_InitTypeDef structure
-  *         which will be initialized.
-  * @retval None
-  */
-void USART_StructInit(USART_InitTypeDef* USART_InitStruct)
-{
-  /* USART_InitStruct members default value */
-  USART_InitStruct->USART_BaudRate = 9600;
-  USART_InitStruct->USART_WordLength = USART_WordLength_8b;
-  USART_InitStruct->USART_StopBits = USART_StopBits_1;
-  USART_InitStruct->USART_Parity = USART_Parity_No ;
-  USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
-  USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None;  
-}
-
-/**
-  * @brief  Initializes the USARTx peripheral Clock according to the 
-  *          specified parameters in the USART_ClockInitStruct .
-  * @param  USARTx: where x can be 1, 2, 3 to select the USART peripheral.
-  * @param  USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef
-  *         structure that contains the configuration information for the specified 
-  *         USART peripheral.  
-  * @note The Smart Card and Synchronous modes are not available for UART4 and UART5.
-  * @retval None
-  */
-void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct)
-{
-  uint32_t tmpreg = 0x00;
-  /* Check the parameters */
-  assert_param(IS_USART_123_PERIPH(USARTx));
-  assert_param(IS_USART_CLOCK(USART_ClockInitStruct->USART_Clock));
-  assert_param(IS_USART_CPOL(USART_ClockInitStruct->USART_CPOL));
-  assert_param(IS_USART_CPHA(USART_ClockInitStruct->USART_CPHA));
-  assert_param(IS_USART_LASTBIT(USART_ClockInitStruct->USART_LastBit));
-  
-/*---------------------------- USART CR2 Configuration -----------------------*/
-  tmpreg = USARTx->CR2;
-  /* Clear CLKEN, CPOL, CPHA and LBCL bits */
-  tmpreg &= CR2_CLOCK_CLEAR_Mask;
-  /* Configure the USART Clock, CPOL, CPHA and LastBit ------------*/
-  /* Set CLKEN bit according to USART_Clock value */
-  /* Set CPOL bit according to USART_CPOL value */
-  /* Set CPHA bit according to USART_CPHA value */
-  /* Set LBCL bit according to USART_LastBit value */
-  tmpreg |= (uint32_t)USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL | 
-                 USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit;
-  /* Write to USART CR2 */
-  USARTx->CR2 = (uint16_t)tmpreg;
-}
-
-/**
-  * @brief  Fills each USART_ClockInitStruct member with its default value.
-  * @param  USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef
-  *         structure which will be initialized.
-  * @retval None
-  */
-void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct)
-{
-  /* USART_ClockInitStruct members default value */
-  USART_ClockInitStruct->USART_Clock = USART_Clock_Disable;
-  USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low;
-  USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge;
-  USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable;
-}
-
-/**
-  * @brief  Enables or disables the specified USART peripheral.
-  * @param  USARTx: Select the USART or the UART peripheral. 
-  *         This parameter can be one of the following values:
-  *           USART1, USART2, USART3, UART4 or UART5.
-  * @param  NewState: new state of the USARTx peripheral.
-  *         This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_USART_ALL_PERIPH(USARTx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  
-  if (NewState != DISABLE)
-  {
-    /* Enable the selected USART by setting the UE bit in the CR1 register */
-    USARTx->CR1 |= CR1_UE_Set;
-  }
-  else
-  {
-    /* Disable the selected USART by clearing the UE bit in the CR1 register */
-    USARTx->CR1 &= CR1_UE_Reset;
-  }
-}
-
-/**
-  * @brief  Enables or disables the specified USART interrupts.
-  * @param  USARTx: Select the USART or the UART peripheral. 
-  *   This parameter can be one of the following values:
-  *   USART1, USART2, USART3, UART4 or UART5.
-  * @param  USART_IT: specifies the USART interrupt sources to be enabled or disabled.
-  *   This parameter can be one of the following values:
-  *     @arg USART_IT_CTS:  CTS change interrupt (not available for UART4 and UART5)
-  *     @arg USART_IT_LBD:  LIN Break detection interrupt
-  *     @arg USART_IT_TXE:  Transmit Data Register empty interrupt
-  *     @arg USART_IT_TC:   Transmission complete interrupt
-  *     @arg USART_IT_RXNE: Receive Data register not empty interrupt
-  *     @arg USART_IT_IDLE: Idle line detection interrupt
-  *     @arg USART_IT_PE:   Parity Error interrupt
-  *     @arg USART_IT_ERR:  Error interrupt(Frame error, noise error, overrun error)
-  * @param  NewState: new state of the specified USARTx interrupts.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState)
-{
-  uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00;
-  uint32_t usartxbase = 0x00;
-  /* Check the parameters */
-  assert_param(IS_USART_ALL_PERIPH(USARTx));
-  assert_param(IS_USART_CONFIG_IT(USART_IT));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  /* The CTS interrupt is not available for UART4 and UART5 */
-  if (USART_IT == USART_IT_CTS)
-  {
-    assert_param(IS_USART_123_PERIPH(USARTx));
-  }   
-  
-  usartxbase = (uint32_t)USARTx;
-
-  /* Get the USART register index */
-  usartreg = (((uint8_t)USART_IT) >> 0x05);
-
-  /* Get the interrupt position */
-  itpos = USART_IT & IT_Mask;
-  itmask = (((uint32_t)0x01) << itpos);
-    
-  if (usartreg == 0x01) /* The IT is in CR1 register */
-  {
-    usartxbase += 0x0C;
-  }
-  else if (usartreg == 0x02) /* The IT is in CR2 register */
-  {
-    usartxbase += 0x10;
-  }
-  else /* The IT is in CR3 register */
-  {
-    usartxbase += 0x14; 
-  }
-  if (NewState != DISABLE)
-  {
-    *(__IO uint32_t*)usartxbase  |= itmask;
-  }
-  else
-  {
-    *(__IO uint32_t*)usartxbase &= ~itmask;
-  }
-}
-
-/**
-  * @brief  Enables or disables the USART’s DMA interface.
-  * @param  USARTx: Select the USART or the UART peripheral. 
-  *   This parameter can be one of the following values:
-  *   USART1, USART2, USART3, UART4 or UART5.
-  * @param  USART_DMAReq: specifies the DMA request.
-  *   This parameter can be any combination of the following values:
-  *     @arg USART_DMAReq_Tx: USART DMA transmit request
-  *     @arg USART_DMAReq_Rx: USART DMA receive request
-  * @param  NewState: new state of the DMA Request sources.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @note The DMA mode is not available for UART5 except in the STM32
-  *       High density value line devices(STM32F10X_HD_VL).  
-  * @retval None
-  */
-void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_USART_ALL_PERIPH(USARTx));
-  assert_param(IS_USART_DMAREQ(USART_DMAReq));  
-  assert_param(IS_FUNCTIONAL_STATE(NewState)); 
-  if (NewState != DISABLE)
-  {
-    /* Enable the DMA transfer for selected requests by setting the DMAT and/or
-       DMAR bits in the USART CR3 register */
-    USARTx->CR3 |= USART_DMAReq;
-  }
-  else
-  {
-    /* Disable the DMA transfer for selected requests by clearing the DMAT and/or
-       DMAR bits in the USART CR3 register */
-    USARTx->CR3 &= (uint16_t)~USART_DMAReq;
-  }
-}
-
-/**
-  * @brief  Sets the address of the USART node.
-  * @param  USARTx: Select the USART or the UART peripheral. 
-  *   This parameter can be one of the following values:
-  *   USART1, USART2, USART3, UART4 or UART5.
-  * @param  USART_Address: Indicates the address of the USART node.
-  * @retval None
-  */
-void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address)
-{
-  /* Check the parameters */
-  assert_param(IS_USART_ALL_PERIPH(USARTx));
-  assert_param(IS_USART_ADDRESS(USART_Address)); 
-    
-  /* Clear the USART address */
-  USARTx->CR2 &= CR2_Address_Mask;
-  /* Set the USART address node */
-  USARTx->CR2 |= USART_Address;
-}
-
-/**
-  * @brief  Selects the USART WakeUp method.
-  * @param  USARTx: Select the USART or the UART peripheral. 
-  *   This parameter can be one of the following values:
-  *   USART1, USART2, USART3, UART4 or UART5.
-  * @param  USART_WakeUp: specifies the USART wakeup method.
-  *   This parameter can be one of the following values:
-  *     @arg USART_WakeUp_IdleLine: WakeUp by an idle line detection
-  *     @arg USART_WakeUp_AddressMark: WakeUp by an address mark
-  * @retval None
-  */
-void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp)
-{
-  /* Check the parameters */
-  assert_param(IS_USART_ALL_PERIPH(USARTx));
-  assert_param(IS_USART_WAKEUP(USART_WakeUp));
-  
-  USARTx->CR1 &= CR1_WAKE_Mask;
-  USARTx->CR1 |= USART_WakeUp;
-}
-
-/**
-  * @brief  Determines if the USART is in mute mode or not.
-  * @param  USARTx: Select the USART or the UART peripheral. 
-  *   This parameter can be one of the following values:
-  *   USART1, USART2, USART3, UART4 or UART5.
-  * @param  NewState: new state of the USART mute mode.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_USART_ALL_PERIPH(USARTx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState)); 
-  
-  if (NewState != DISABLE)
-  {
-    /* Enable the USART mute mode  by setting the RWU bit in the CR1 register */
-    USARTx->CR1 |= CR1_RWU_Set;
-  }
-  else
-  {
-    /* Disable the USART mute mode by clearing the RWU bit in the CR1 register */
-    USARTx->CR1 &= CR1_RWU_Reset;
-  }
-}
-
-/**
-  * @brief  Sets the USART LIN Break detection length.
-  * @param  USARTx: Select the USART or the UART peripheral. 
-  *   This parameter can be one of the following values:
-  *   USART1, USART2, USART3, UART4 or UART5.
-  * @param  USART_LINBreakDetectLength: specifies the LIN break detection length.
-  *   This parameter can be one of the following values:
-  *     @arg USART_LINBreakDetectLength_10b: 10-bit break detection
-  *     @arg USART_LINBreakDetectLength_11b: 11-bit break detection
-  * @retval None
-  */
-void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength)
-{
-  /* Check the parameters */
-  assert_param(IS_USART_ALL_PERIPH(USARTx));
-  assert_param(IS_USART_LIN_BREAK_DETECT_LENGTH(USART_LINBreakDetectLength));
-  
-  USARTx->CR2 &= CR2_LBDL_Mask;
-  USARTx->CR2 |= USART_LINBreakDetectLength;  
-}
-
-/**
-  * @brief  Enables or disables the USART’s LIN mode.
-  * @param  USARTx: Select the USART or the UART peripheral. 
-  *   This parameter can be one of the following values:
-  *   USART1, USART2, USART3, UART4 or UART5.
-  * @param  NewState: new state of the USART LIN mode.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_USART_ALL_PERIPH(USARTx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  
-  if (NewState != DISABLE)
-  {
-    /* Enable the LIN mode by setting the LINEN bit in the CR2 register */
-    USARTx->CR2 |= CR2_LINEN_Set;
-  }
-  else
-  {
-    /* Disable the LIN mode by clearing the LINEN bit in the CR2 register */
-    USARTx->CR2 &= CR2_LINEN_Reset;
-  }
-}
-
-/**
-  * @brief  Transmits single data through the USARTx peripheral.
-  * @param  USARTx: Select the USART or the UART peripheral. 
-  *   This parameter can be one of the following values:
-  *   USART1, USART2, USART3, UART4 or UART5.
-  * @param  Data: the data to transmit.
-  * @retval None
-  */
-void USART_SendData(USART_TypeDef* USARTx, uint16_t Data)
-{
-  /* Check the parameters */
-  assert_param(IS_USART_ALL_PERIPH(USARTx));
-  assert_param(IS_USART_DATA(Data)); 
-    
-  /* Transmit Data */
-  USARTx->DR = (Data & (uint16_t)0x01FF);
-}
-
-/**
-  * @brief  Returns the most recent received data by the USARTx peripheral.
-  * @param  USARTx: Select the USART or the UART peripheral. 
-  *   This parameter can be one of the following values:
-  *   USART1, USART2, USART3, UART4 or UART5.
-  * @retval The received data.
-  */
-uint16_t USART_ReceiveData(USART_TypeDef* USARTx)
-{
-  /* Check the parameters */
-  assert_param(IS_USART_ALL_PERIPH(USARTx));
-  
-  /* Receive Data */
-  return (uint16_t)(USARTx->DR & (uint16_t)0x01FF);
-}
-
-/**
-  * @brief  Transmits break characters.
-  * @param  USARTx: Select the USART or the UART peripheral. 
-  *   This parameter can be one of the following values:
-  *   USART1, USART2, USART3, UART4 or UART5.
-  * @retval None
-  */
-void USART_SendBreak(USART_TypeDef* USARTx)
-{
-  /* Check the parameters */
-  assert_param(IS_USART_ALL_PERIPH(USARTx));
-  
-  /* Send break characters */
-  USARTx->CR1 |= CR1_SBK_Set;
-}
-
-/**
-  * @brief  Sets the specified USART guard time.
-  * @param  USARTx: where x can be 1, 2 or 3 to select the USART peripheral.
-  * @param  USART_GuardTime: specifies the guard time.
-  * @note The guard time bits are not available for UART4 and UART5.   
-  * @retval None
-  */
-void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime)
-{    
-  /* Check the parameters */
-  assert_param(IS_USART_123_PERIPH(USARTx));
-  
-  /* Clear the USART Guard time */
-  USARTx->GTPR &= GTPR_LSB_Mask;
-  /* Set the USART guard time */
-  USARTx->GTPR |= (uint16_t)((uint16_t)USART_GuardTime << 0x08);
-}
-
-/**
-  * @brief  Sets the system clock prescaler.
-  * @param  USARTx: Select the USART or the UART peripheral. 
-  *   This parameter can be one of the following values:
-  *   USART1, USART2, USART3, UART4 or UART5.
-  * @param  USART_Prescaler: specifies the prescaler clock.  
-  * @note   The function is used for IrDA mode with UART4 and UART5.
-  * @retval None
-  */
-void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler)
-{ 
-  /* Check the parameters */
-  assert_param(IS_USART_ALL_PERIPH(USARTx));
-  
-  /* Clear the USART prescaler */
-  USARTx->GTPR &= GTPR_MSB_Mask;
-  /* Set the USART prescaler */
-  USARTx->GTPR |= USART_Prescaler;
-}
-
-/**
-  * @brief  Enables or disables the USART’s Smart Card mode.
-  * @param  USARTx: where x can be 1, 2 or 3 to select the USART peripheral.
-  * @param  NewState: new state of the Smart Card mode.
-  *   This parameter can be: ENABLE or DISABLE.     
-  * @note The Smart Card mode is not available for UART4 and UART5. 
-  * @retval None
-  */
-void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_USART_123_PERIPH(USARTx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  if (NewState != DISABLE)
-  {
-    /* Enable the SC mode by setting the SCEN bit in the CR3 register */
-    USARTx->CR3 |= CR3_SCEN_Set;
-  }
-  else
-  {
-    /* Disable the SC mode by clearing the SCEN bit in the CR3 register */
-    USARTx->CR3 &= CR3_SCEN_Reset;
-  }
-}
-
-/**
-  * @brief  Enables or disables NACK transmission.
-  * @param  USARTx: where x can be 1, 2 or 3 to select the USART peripheral. 
-  * @param  NewState: new state of the NACK transmission.
-  *   This parameter can be: ENABLE or DISABLE.  
-  * @note The Smart Card mode is not available for UART4 and UART5.
-  * @retval None
-  */
-void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_USART_123_PERIPH(USARTx));  
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  if (NewState != DISABLE)
-  {
-    /* Enable the NACK transmission by setting the NACK bit in the CR3 register */
-    USARTx->CR3 |= CR3_NACK_Set;
-  }
-  else
-  {
-    /* Disable the NACK transmission by clearing the NACK bit in the CR3 register */
-    USARTx->CR3 &= CR3_NACK_Reset;
-  }
-}
-
-/**
-  * @brief  Enables or disables the USART’s Half Duplex communication.
-  * @param  USARTx: Select the USART or the UART peripheral. 
-  *   This parameter can be one of the following values:
-  *   USART1, USART2, USART3, UART4 or UART5.
-  * @param  NewState: new state of the USART Communication.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_USART_ALL_PERIPH(USARTx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  
-  if (NewState != DISABLE)
-  {
-    /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */
-    USARTx->CR3 |= CR3_HDSEL_Set;
-  }
-  else
-  {
-    /* Disable the Half-Duplex mode by clearing the HDSEL bit in the CR3 register */
-    USARTx->CR3 &= CR3_HDSEL_Reset;
-  }
-}
-
-
-/**
-  * @brief  Enables or disables the USART's 8x oversampling mode.
-  * @param  USARTx: Select the USART or the UART peripheral.
-  *   This parameter can be one of the following values:
-  *   USART1, USART2, USART3, UART4 or UART5.
-  * @param  NewState: new state of the USART one bit sampling method.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @note
-  *     This function has to be called before calling USART_Init()
-  *     function in order to have correct baudrate Divider value.   
-  * @retval None
-  */
-void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_USART_ALL_PERIPH(USARTx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  
-  if (NewState != DISABLE)
-  {
-    /* Enable the 8x Oversampling mode by setting the OVER8 bit in the CR1 register */
-    USARTx->CR1 |= CR1_OVER8_Set;
-  }
-  else
-  {
-    /* Disable the 8x Oversampling mode by clearing the OVER8 bit in the CR1 register */
-    USARTx->CR1 &= CR1_OVER8_Reset;
-  }
-}
-
-/**
-  * @brief  Enables or disables the USART's one bit sampling method.
-  * @param  USARTx: Select the USART or the UART peripheral.
-  *   This parameter can be one of the following values:
-  *   USART1, USART2, USART3, UART4 or UART5.
-  * @param  NewState: new state of the USART one bit sampling method.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_USART_ALL_PERIPH(USARTx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  
-  if (NewState != DISABLE)
-  {
-    /* Enable the one bit method by setting the ONEBITE bit in the CR3 register */
-    USARTx->CR3 |= CR3_ONEBITE_Set;
-  }
-  else
-  {
-    /* Disable tthe one bit method by clearing the ONEBITE bit in the CR3 register */
-    USARTx->CR3 &= CR3_ONEBITE_Reset;
-  }
-}
-
-/**
-  * @brief  Configures the USART's IrDA interface.
-  * @param  USARTx: Select the USART or the UART peripheral. 
-  *   This parameter can be one of the following values:
-  *   USART1, USART2, USART3, UART4 or UART5.
-  * @param  USART_IrDAMode: specifies the IrDA mode.
-  *   This parameter can be one of the following values:
-  *     @arg USART_IrDAMode_LowPower
-  *     @arg USART_IrDAMode_Normal
-  * @retval None
-  */
-void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode)
-{
-  /* Check the parameters */
-  assert_param(IS_USART_ALL_PERIPH(USARTx));
-  assert_param(IS_USART_IRDA_MODE(USART_IrDAMode));
-    
-  USARTx->CR3 &= CR3_IRLP_Mask;
-  USARTx->CR3 |= USART_IrDAMode;
-}
-
-/**
-  * @brief  Enables or disables the USART's IrDA interface.
-  * @param  USARTx: Select the USART or the UART peripheral. 
-  *   This parameter can be one of the following values:
-  *   USART1, USART2, USART3, UART4 or UART5.
-  * @param  NewState: new state of the IrDA mode.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_USART_ALL_PERIPH(USARTx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-    
-  if (NewState != DISABLE)
-  {
-    /* Enable the IrDA mode by setting the IREN bit in the CR3 register */
-    USARTx->CR3 |= CR3_IREN_Set;
-  }
-  else
-  {
-    /* Disable the IrDA mode by clearing the IREN bit in the CR3 register */
-    USARTx->CR3 &= CR3_IREN_Reset;
-  }
-}
-
-/**
-  * @brief  Checks whether the specified USART flag is set or not.
-  * @param  USARTx: Select the USART or the UART peripheral. 
-  *   This parameter can be one of the following values:
-  *   USART1, USART2, USART3, UART4 or UART5.
-  * @param  USART_FLAG: specifies the flag to check.
-  *   This parameter can be one of the following values:
-  *     @arg USART_FLAG_CTS:  CTS Change flag (not available for UART4 and UART5)
-  *     @arg USART_FLAG_LBD:  LIN Break detection flag
-  *     @arg USART_FLAG_TXE:  Transmit data register empty flag
-  *     @arg USART_FLAG_TC:   Transmission Complete flag
-  *     @arg USART_FLAG_RXNE: Receive data register not empty flag
-  *     @arg USART_FLAG_IDLE: Idle Line detection flag
-  *     @arg USART_FLAG_ORE:  OverRun Error flag
-  *     @arg USART_FLAG_NE:   Noise Error flag
-  *     @arg USART_FLAG_FE:   Framing Error flag
-  *     @arg USART_FLAG_PE:   Parity Error flag
-  * @retval The new state of USART_FLAG (SET or RESET).
-  */
-FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG)
-{
-  FlagStatus bitstatus = RESET;
-  /* Check the parameters */
-  assert_param(IS_USART_ALL_PERIPH(USARTx));
-  assert_param(IS_USART_FLAG(USART_FLAG));
-  /* The CTS flag is not available for UART4 and UART5 */
-  if (USART_FLAG == USART_FLAG_CTS)
-  {
-    assert_param(IS_USART_123_PERIPH(USARTx));
-  }  
-  
-  if ((USARTx->SR & USART_FLAG) != (uint16_t)RESET)
-  {
-    bitstatus = SET;
-  }
-  else
-  {
-    bitstatus = RESET;
-  }
-  return bitstatus;
-}
-
-/**
-  * @brief  Clears the USARTx's pending flags.
-  * @param  USARTx: Select the USART or the UART peripheral. 
-  *   This parameter can be one of the following values:
-  *   USART1, USART2, USART3, UART4 or UART5.
-  * @param  USART_FLAG: specifies the flag to clear.
-  *   This parameter can be any combination of the following values:
-  *     @arg USART_FLAG_CTS:  CTS Change flag (not available for UART4 and UART5).
-  *     @arg USART_FLAG_LBD:  LIN Break detection flag.
-  *     @arg USART_FLAG_TC:   Transmission Complete flag.
-  *     @arg USART_FLAG_RXNE: Receive data register not empty flag.
-  *   
-  * @note
-  *   - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun 
-  *     error) and IDLE (Idle line detected) flags are cleared by software 
-  *     sequence: a read operation to USART_SR register (USART_GetFlagStatus()) 
-  *     followed by a read operation to USART_DR register (USART_ReceiveData()).
-  *   - RXNE flag can be also cleared by a read to the USART_DR register 
-  *     (USART_ReceiveData()).
-  *   - TC flag can be also cleared by software sequence: a read operation to 
-  *     USART_SR register (USART_GetFlagStatus()) followed by a write operation
-  *     to USART_DR register (USART_SendData()).
-  *   - TXE flag is cleared only by a write to the USART_DR register 
-  *     (USART_SendData()).
-  * @retval None
-  */
-void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG)
-{
-  /* Check the parameters */
-  assert_param(IS_USART_ALL_PERIPH(USARTx));
-  assert_param(IS_USART_CLEAR_FLAG(USART_FLAG));
-  /* The CTS flag is not available for UART4 and UART5 */
-  if ((USART_FLAG & USART_FLAG_CTS) == USART_FLAG_CTS)
-  {
-    assert_param(IS_USART_123_PERIPH(USARTx));
-  } 
-   
-  USARTx->SR = (uint16_t)~USART_FLAG;
-}
-
-/**
-  * @brief  Checks whether the specified USART interrupt has occurred or not.
-  * @param  USARTx: Select the USART or the UART peripheral. 
-  *   This parameter can be one of the following values:
-  *   USART1, USART2, USART3, UART4 or UART5.
-  * @param  USART_IT: specifies the USART interrupt source to check.
-  *   This parameter can be one of the following values:
-  *     @arg USART_IT_CTS:  CTS change interrupt (not available for UART4 and UART5)
-  *     @arg USART_IT_LBD:  LIN Break detection interrupt
-  *     @arg USART_IT_TXE:  Tansmit Data Register empty interrupt
-  *     @arg USART_IT_TC:   Transmission complete interrupt
-  *     @arg USART_IT_RXNE: Receive Data register not empty interrupt
-  *     @arg USART_IT_IDLE: Idle line detection interrupt
-  *     @arg USART_IT_ORE:  OverRun Error interrupt
-  *     @arg USART_IT_NE:   Noise Error interrupt
-  *     @arg USART_IT_FE:   Framing Error interrupt
-  *     @arg USART_IT_PE:   Parity Error interrupt
-  * @retval The new state of USART_IT (SET or RESET).
-  */
-ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT)
-{
-  uint32_t bitpos = 0x00, itmask = 0x00, usartreg = 0x00;
-  ITStatus bitstatus = RESET;
-  /* Check the parameters */
-  assert_param(IS_USART_ALL_PERIPH(USARTx));
-  assert_param(IS_USART_GET_IT(USART_IT));
-  /* The CTS interrupt is not available for UART4 and UART5 */ 
-  if (USART_IT == USART_IT_CTS)
-  {
-    assert_param(IS_USART_123_PERIPH(USARTx));
-  }   
-  
-  /* Get the USART register index */
-  usartreg = (((uint8_t)USART_IT) >> 0x05);
-  /* Get the interrupt position */
-  itmask = USART_IT & IT_Mask;
-  itmask = (uint32_t)0x01 << itmask;
-  
-  if (usartreg == 0x01) /* The IT  is in CR1 register */
-  {
-    itmask &= USARTx->CR1;
-  }
-  else if (usartreg == 0x02) /* The IT  is in CR2 register */
-  {
-    itmask &= USARTx->CR2;
-  }
-  else /* The IT  is in CR3 register */
-  {
-    itmask &= USARTx->CR3;
-  }
-  
-  bitpos = USART_IT >> 0x08;
-  bitpos = (uint32_t)0x01 << bitpos;
-  bitpos &= USARTx->SR;
-  if ((itmask != (uint16_t)RESET)&&(bitpos != (uint16_t)RESET))
-  {
-    bitstatus = SET;
-  }
-  else
-  {
-    bitstatus = RESET;
-  }
-  
-  return bitstatus;  
-}
-
-/**
-  * @brief  Clears the USARTx's interrupt pending bits.
-  * @param  USARTx: Select the USART or the UART peripheral. 
-  *   This parameter can be one of the following values:
-  *   USART1, USART2, USART3, UART4 or UART5.
-  * @param  USART_IT: specifies the interrupt pending bit to clear.
-  *   This parameter can be one of the following values:
-  *     @arg USART_IT_CTS:  CTS change interrupt (not available for UART4 and UART5)
-  *     @arg USART_IT_LBD:  LIN Break detection interrupt
-  *     @arg USART_IT_TC:   Transmission complete interrupt. 
-  *     @arg USART_IT_RXNE: Receive Data register not empty interrupt.
-  *   
-  * @note
-  *   - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun 
-  *     error) and IDLE (Idle line detected) pending bits are cleared by 
-  *     software sequence: a read operation to USART_SR register 
-  *     (USART_GetITStatus()) followed by a read operation to USART_DR register 
-  *     (USART_ReceiveData()).
-  *   - RXNE pending bit can be also cleared by a read to the USART_DR register 
-  *     (USART_ReceiveData()).
-  *   - TC pending bit can be also cleared by software sequence: a read 
-  *     operation to USART_SR register (USART_GetITStatus()) followed by a write 
-  *     operation to USART_DR register (USART_SendData()).
-  *   - TXE pending bit is cleared only by a write to the USART_DR register 
-  *     (USART_SendData()).
-  * @retval None
-  */
-void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT)
-{
-  uint16_t bitpos = 0x00, itmask = 0x00;
-  /* Check the parameters */
-  assert_param(IS_USART_ALL_PERIPH(USARTx));
-  assert_param(IS_USART_CLEAR_IT(USART_IT));
-  /* The CTS interrupt is not available for UART4 and UART5 */
-  if (USART_IT == USART_IT_CTS)
-  {
-    assert_param(IS_USART_123_PERIPH(USARTx));
-  }   
-  
-  bitpos = USART_IT >> 0x08;
-  itmask = ((uint16_t)0x01 << (uint16_t)bitpos);
-  USARTx->SR = (uint16_t)~itmask;
-}
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_wwdg.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_wwdg.c
deleted file mode 100644
index 4a901e4..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_wwdg.c
+++ /dev/null
@@ -1,224 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f10x_wwdg.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    11-March-2011
-  * @brief   This file provides all the WWDG firmware functions.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_wwdg.h"
-#include "stm32f10x_rcc.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Driver
-  * @{
-  */
-
-/** @defgroup WWDG 
-  * @brief WWDG driver modules
-  * @{
-  */
-
-/** @defgroup WWDG_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup WWDG_Private_Defines
-  * @{
-  */
-
-/* ----------- WWDG registers bit address in the alias region ----------- */
-#define WWDG_OFFSET       (WWDG_BASE - PERIPH_BASE)
-
-/* Alias word address of EWI bit */
-#define CFR_OFFSET        (WWDG_OFFSET + 0x04)
-#define EWI_BitNumber     0x09
-#define CFR_EWI_BB        (PERIPH_BB_BASE + (CFR_OFFSET * 32) + (EWI_BitNumber * 4))
-
-/* --------------------- WWDG registers bit mask ------------------------ */
-
-/* CR register bit mask */
-#define CR_WDGA_Set       ((uint32_t)0x00000080)
-
-/* CFR register bit mask */
-#define CFR_WDGTB_Mask    ((uint32_t)0xFFFFFE7F)
-#define CFR_W_Mask        ((uint32_t)0xFFFFFF80)
-#define BIT_Mask          ((uint8_t)0x7F)
-
-/**
-  * @}
-  */
-
-/** @defgroup WWDG_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup WWDG_Private_Variables
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup WWDG_Private_FunctionPrototypes
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup WWDG_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Deinitializes the WWDG peripheral registers to their default reset values.
-  * @param  None
-  * @retval None
-  */
-void WWDG_DeInit(void)
-{
-  RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE);
-  RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE);
-}
-
-/**
-  * @brief  Sets the WWDG Prescaler.
-  * @param  WWDG_Prescaler: specifies the WWDG Prescaler.
-  *   This parameter can be one of the following values:
-  *     @arg WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1
-  *     @arg WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2
-  *     @arg WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4
-  *     @arg WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8
-  * @retval None
-  */
-void WWDG_SetPrescaler(uint32_t WWDG_Prescaler)
-{
-  uint32_t tmpreg = 0;
-  /* Check the parameters */
-  assert_param(IS_WWDG_PRESCALER(WWDG_Prescaler));
-  /* Clear WDGTB[1:0] bits */
-  tmpreg = WWDG->CFR & CFR_WDGTB_Mask;
-  /* Set WDGTB[1:0] bits according to WWDG_Prescaler value */
-  tmpreg |= WWDG_Prescaler;
-  /* Store the new value */
-  WWDG->CFR = tmpreg;
-}
-
-/**
-  * @brief  Sets the WWDG window value.
-  * @param  WindowValue: specifies the window value to be compared to the downcounter.
-  *   This parameter value must be lower than 0x80.
-  * @retval None
-  */
-void WWDG_SetWindowValue(uint8_t WindowValue)
-{
-  __IO uint32_t tmpreg = 0;
-
-  /* Check the parameters */
-  assert_param(IS_WWDG_WINDOW_VALUE(WindowValue));
-  /* Clear W[6:0] bits */
-
-  tmpreg = WWDG->CFR & CFR_W_Mask;
-
-  /* Set W[6:0] bits according to WindowValue value */
-  tmpreg |= WindowValue & (uint32_t) BIT_Mask;
-
-  /* Store the new value */
-  WWDG->CFR = tmpreg;
-}
-
-/**
-  * @brief  Enables the WWDG Early Wakeup interrupt(EWI).
-  * @param  None
-  * @retval None
-  */
-void WWDG_EnableIT(void)
-{
-  *(__IO uint32_t *) CFR_EWI_BB = (uint32_t)ENABLE;
-}
-
-/**
-  * @brief  Sets the WWDG counter value.
-  * @param  Counter: specifies the watchdog counter value.
-  *   This parameter must be a number between 0x40 and 0x7F.
-  * @retval None
-  */
-void WWDG_SetCounter(uint8_t Counter)
-{
-  /* Check the parameters */
-  assert_param(IS_WWDG_COUNTER(Counter));
-  /* Write to T[6:0] bits to configure the counter value, no need to do
-     a read-modify-write; writing a 0 to WDGA bit does nothing */
-  WWDG->CR = Counter & BIT_Mask;
-}
-
-/**
-  * @brief  Enables WWDG and load the counter value.                  
-  * @param  Counter: specifies the watchdog counter value.
-  *   This parameter must be a number between 0x40 and 0x7F.
-  * @retval None
-  */
-void WWDG_Enable(uint8_t Counter)
-{
-  /* Check the parameters */
-  assert_param(IS_WWDG_COUNTER(Counter));
-  WWDG->CR = CR_WDGA_Set | Counter;
-}
-
-/**
-  * @brief  Checks whether the Early Wakeup interrupt flag is set or not.
-  * @param  None
-  * @retval The new state of the Early Wakeup interrupt flag (SET or RESET)
-  */
-FlagStatus WWDG_GetFlagStatus(void)
-{
-  return (FlagStatus)(WWDG->SR);
-}
-
-/**
-  * @brief  Clears Early Wakeup interrupt flag.
-  * @param  None
-  * @retval None
-  */
-void WWDG_ClearFlag(void)
-{
-  WWDG->SR = (uint32_t)RESET;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/