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-rw-r--r--src/target/Makefile.am9
-rw-r--r--src/target/board/arm_evaluator7t.cfg10
-rw-r--r--src/target/board/at91rm9200-dk.cfg78
-rw-r--r--src/target/board/crossbow_tech_imote2.cfg46
-rw-r--r--src/target/board/digi_connectcore_wi-9c.cfg127
-rw-r--r--src/target/board/dm355evm.cfg119
-rw-r--r--src/target/board/eir.cfg94
-rw-r--r--src/target/board/hammer.cfg36
-rw-r--r--src/target/board/hitex_stm32-performancestick.cfg50
-rw-r--r--src/target/board/hitex_str9-comstick.cfg72
-rw-r--r--src/target/board/iar_str912_sk.cfg3
-rw-r--r--src/target/board/imx27ads.cfg75
-rw-r--r--src/target/board/imx27lnst.cfg59
-rw-r--r--src/target/board/imx31pdk.cfg101
-rw-r--r--src/target/board/keil_mcb2140.cfg8
-rw-r--r--src/target/board/linksys_nslu2.cfg8
-rw-r--r--src/target/board/logicpd_imx27.cfg12
-rw-r--r--src/target/board/olimex_LPC2378STK.cfg11
-rw-r--r--src/target/board/olimex_lpc_h2148.cfg8
-rw-r--r--src/target/board/olimex_sam7_ex256.cfg4
-rw-r--r--src/target/board/olimex_sam9_l9260.cfg10
-rw-r--r--src/target/board/olimex_stm32_h103.cfg8
-rw-r--r--src/target/board/pic-p32mx.cfg8
-rw-r--r--src/target/board/pxa255_sst.cfg15
-rw-r--r--src/target/board/sheevaplug.cfg122
-rw-r--r--src/target/board/stm3210e_eval.cfg3
-rw-r--r--src/target/board/stm32f10x_128k_eval.cfg4
-rw-r--r--src/target/board/str910-eval.cfg61
-rw-r--r--src/target/board/ti_beagleboard.cfg14
-rw-r--r--src/target/board/unknown-board-atmel-at91sam9260.cfg82
-rw-r--r--src/target/board/x300t.cfg30
-rw-r--r--src/target/board/zy1000.cfg110
-rw-r--r--src/target/interface/arm-jtag-ew.cfg8
-rw-r--r--src/target/interface/arm-usb-ocd.cfg11
-rw-r--r--src/target/interface/at91rm9200.cfg9
-rw-r--r--src/target/interface/axm0432.cfg11
-rw-r--r--src/target/interface/calao-usb-a9260-c01.cfg13
-rw-r--r--src/target/interface/calao-usb-a9260-c02.cfg13
-rw-r--r--src/target/interface/calao-usb-a9260.cfg16
-rw-r--r--src/target/interface/chameleon.cfg9
-rw-r--r--src/target/interface/dummy.cfg6
-rw-r--r--src/target/interface/flyswatter.cfg12
-rw-r--r--src/target/interface/hitex_str9-comstick.cfg11
-rw-r--r--src/target/interface/icebear.cfg11
-rw-r--r--src/target/interface/jlink.cfg8
-rw-r--r--src/target/interface/jtagkey-tiny.cfg9
-rw-r--r--src/target/interface/jtagkey.cfg11
-rw-r--r--src/target/interface/luminary-lm3s811.cfg10
-rw-r--r--src/target/interface/luminary.cfg11
-rw-r--r--src/target/interface/olimex-arm-usb-ocd.cfg11
-rw-r--r--src/target/interface/olimex-jtag-tiny.cfg11
-rw-r--r--src/target/interface/oocdlink.cfg12
-rw-r--r--src/target/interface/openocd-usb.cfg14
-rw-r--r--src/target/interface/parport.cfg9
-rw-r--r--src/target/interface/parport_dlc5.cfg11
-rw-r--r--src/target/interface/rlink.cfg8
-rw-r--r--src/target/interface/sheevaplug.cfg12
-rw-r--r--src/target/interface/signalyzer.cfg11
-rw-r--r--src/target/interface/stm32-stick.cfg11
-rw-r--r--src/target/interface/turtelizer2.cfg11
-rw-r--r--src/target/interface/usbprog.cfg8
-rw-r--r--src/target/interface/vsllink.cfg25
-rw-r--r--src/target/target/aduc702x.cfg61
-rw-r--r--src/target/target/at91eb40a.cfg61
-rw-r--r--src/target/target/at91r40008.cfg50
-rw-r--r--src/target/target/at91rm9200.cfg51
-rw-r--r--src/target/target/at91sam9260.cfg42
-rw-r--r--src/target/target/at91sam9260_ext_RAM_ext_flash.cfg127
-rw-r--r--src/target/target/davinci.cfg170
-rw-r--r--src/target/target/epc9301.cfg31
-rw-r--r--src/target/target/feroceon.cfg30
-rw-r--r--src/target/target/imx21.cfg32
-rw-r--r--src/target/target/imx27.cfg42
-rw-r--r--src/target/target/imx31.cfg62
-rw-r--r--src/target/target/imx35.cfg50
-rw-r--r--src/target/target/is5114.cfg49
-rw-r--r--src/target/target/ixp42x.cfg32
-rw-r--r--src/target/target/lm3s3748.cfg49
-rw-r--r--src/target/target/lm3s6965.cfg46
-rw-r--r--src/target/target/lm3s811.cfg45
-rw-r--r--src/target/target/lpc2103.cfg39
-rw-r--r--src/target/target/lpc2124.cfg42
-rw-r--r--src/target/target/lpc2129.cfg41
-rw-r--r--src/target/target/lpc2148.cfg56
-rw-r--r--src/target/target/lpc2294.cfg38
-rw-r--r--src/target/target/lpc2378.cfg49
-rw-r--r--src/target/target/lpc2478.cfg35
-rw-r--r--src/target/target/mega128.cfg42
-rw-r--r--src/target/target/netx500.cfg34
-rw-r--r--src/target/target/omap3530.cfg57
-rw-r--r--src/target/target/omap5912.cfg63
-rw-r--r--src/target/target/pic32mx.cfg40
-rw-r--r--src/target/target/pxa255.cfg104
-rw-r--r--src/target/target/pxa270.cfg39
-rw-r--r--src/target/target/readme.txt41
-rw-r--r--src/target/target/sam7se512.cfg39
-rw-r--r--src/target/target/sam7x256.cfg52
-rw-r--r--src/target/target/samsung_s3c2410.cfg35
-rw-r--r--src/target/target/samsung_s3c2440.cfg35
-rw-r--r--src/target/target/samsung_s3c4510.cfg25
-rw-r--r--src/target/target/samsung_s3c6410.cfg49
-rw-r--r--src/target/target/sharp_lh79532.cfg26
-rw-r--r--src/target/target/smdk6410.cfg8
-rw-r--r--src/target/target/smp8634.cfg32
-rw-r--r--src/target/target/stm32.cfg58
-rw-r--r--src/target/target/str710.cfg45
-rw-r--r--src/target/target/str730.cfg46
-rw-r--r--src/target/target/str750.cfg51
-rw-r--r--src/target/target/str912.cfg70
-rw-r--r--src/target/target/test_reset_syntax_error.cfg17
-rw-r--r--src/target/target/test_syntax_error.cfg4
-rw-r--r--src/target/target/ti_dm355.cfg92
-rw-r--r--src/target/target/ti_dm6446.cfg66
-rw-r--r--src/target/target/xba_revA3.cfg86
-rw-r--r--src/target/test/selftest.cfg17
-rw-r--r--src/target/test/syntax1.cfg29
116 files changed, 0 insertions, 4362 deletions
diff --git a/src/target/Makefile.am b/src/target/Makefile.am
index 90796180..28a2981a 100644
--- a/src/target/Makefile.am
+++ b/src/target/Makefile.am
@@ -26,14 +26,5 @@ noinst_HEADERS = target.h trace.h register.h armv4_5.h embeddedice.h etm.h arm7t
nobase_dist_pkglib_DATA =
nobase_dist_pkglib_DATA += xscale/debug_handler.bin
nobase_dist_pkglib_DATA += ecos/at91eb40a.elf
-# Various chip targets
-nobase_dist_pkglib_DATA += $(wildcard $(srcdir)/target/*.cfg)
-# Various jtag interfaces
-nobase_dist_pkglib_DATA += $(wildcard $(srcdir)/interface/*.cfg)
-# Various preconfigured boards
-nobase_dist_pkglib_DATA += $(wildcard $(srcdir)/board/*.cfg)
-
-# test files
-nobase_dist_pkglib_DATA += $(wildcard $(srcdir)/test/*.cfg)
MAINTAINERCLEANFILES = Makefile.in
diff --git a/src/target/board/arm_evaluator7t.cfg b/src/target/board/arm_evaluator7t.cfg
deleted file mode 100644
index 9cca2391..00000000
--- a/src/target/board/arm_evaluator7t.cfg
+++ /dev/null
@@ -1,10 +0,0 @@
-# This board is from ARM and has an samsung s3c45101x01 chip
-
-source [find target/samsung_s3c4510.cfg]
-
-#
-# FIXME:
-# Add (A) sdram configuration
-# Add (B) flash cfi programing configuration
-#
-
diff --git a/src/target/board/at91rm9200-dk.cfg b/src/target/board/at91rm9200-dk.cfg
deleted file mode 100644
index 900ee351..00000000
--- a/src/target/board/at91rm9200-dk.cfg
+++ /dev/null
@@ -1,78 +0,0 @@
-#
-# This is for the "at91rm9200-DK" (not the EK) eval board.
-#
-# The two are probably very simular.... I have DK...
-#
-# It has atmel at91rm9200 chip.
-source [find target/at91rm9200.cfg]
-$_TARGETNAME configure -event gdb-attach { reset init }
-$_TARGETNAME configure -event reset-init { at91rm9200_dk_init }
-
-#flash bank <driver> <base> <size> <chip_width> <bus_width>
-flash_bank cfi 0x10000000 0x00200000 2 2 0
-
-
-proc at91rm9200_dk_init { } {
- # Try to run at 1khz... Yea, that slow!
- # Chip is really running @ 32khz
- jtag_khz 8
-
- mww 0xfffffc64 0xffffffff
- ## disable all clocks but system clock
- mww 0xfffffc04 0xfffffffe
- ## disable all clocks to pioa and piob
- mww 0xfffffc14 0xffffffc3
- ## master clock = slow cpu = slow
- ## (means the CPU is running at 32khz!)
- mww 0xfffffc30 0
- ## main osc enable
- mww 0xfffffc20 0x0000ff01
- ## program pllA
- mww 0xfffffc28 0x20263e04
- ## program pllB
- mww 0xfffffc2c 0x10483e0e
- ## let pll settle... sleep 100msec
- sleep 100
- ## switch to fast clock
- mww 0xfffffc30 0x202
- ## Sleep some - (go read)
- sleep 100
-
- #========================================
- # CPU now runs at 180mhz
- # SYS runs at 60mhz.
- jtag_khz 40000
- #========================================
-
-
- ## set memc for all memories
- mww 0xffffff60 0x02
- ## program smc controller
- mww 0xffffff70 0x3284
- ## init sdram
- mww 0xffffff98 0x7fffffd0
- ## all banks precharge
- mww 0xffffff80 0x02
- ## touch sdram chip to make it work
- mww 0x20000000 0
- ## sdram controller mode register
- mww 0xffffff90 0x04
- mww 0x20000000 0
- mww 0x20000000 0
- mww 0x20000000 0
- mww 0x20000000 0
- mww 0x20000000 0
- mww 0x20000000 0
- mww 0x20000000 0
- mww 0x20000000 0
- ## sdram controller mode register
- ## Refresh, etc....
- mww 0xffffff90 0x03
- mww 0x20000080 0
- mww 0xffffff94 0x1f4
- mww 0x20000080 0
- mww 0xffffff90 0x10
- mww 0x20000000 0
- mww 0xffffff00 0x01
-
-}
diff --git a/src/target/board/crossbow_tech_imote2.cfg b/src/target/board/crossbow_tech_imote2.cfg
deleted file mode 100644
index 7527bef8..00000000
--- a/src/target/board/crossbow_tech_imote2.cfg
+++ /dev/null
@@ -1,46 +0,0 @@
-# Crossbow Technology iMote2
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME imote2
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-if { [info exists CPUTAPID ] } {
- set _CPUTAPID $CPUTAPID
-} else {
- # force an error till we get a good number
- set _CPUTAPID 0xffffffff
-}
-
-# PXA271 and an Intel Strataflash of 32 Megabytes (p30)
-#
-# Marvell/Intel PXA270 Script
-# set jtag_nsrst_delay to the delay introduced by your reset circuit
-# the rest of the needed delays are built into the openocd program
-jtag_nsrst_delay 800
-# set the jtag_ntrst_delay to the delay introduced by a reset circuit
-# the rest of the needed delays are built into the openocd program
-jtag_ntrst_delay 0
-#use combined on interfaces or targets that can't set TRST/SRST separately
-reset_config trst_and_srst separate
-#jtag scan chain
-
-jtag newtap $_CHIPNAME cpu -irlen 7 -ircapture 0x1 -irmask 0x7f -expected-id $_CPUTAPID
-
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
-target create $_TARGETNAME xscale -endian $_ENDIAN -chain-position $_TARGETNAME -variant pxa27x
-$_TARGETNAME configure -work-area-virt 0x0x5c000000 -work-area-phys 0x0x5c000000 -work-area-size 0x10000 -work-area-backup 1
-# maps to PXA internal RAM. If you are using a PXA255
-# you must initialize SDRAM or leave this option off
-
-
-#flash bank <driver> <base> <size> <chip_width> <bus_width>
-# works for P30 flash
-flash bank cfi 0x00000000 0x2000000 2 2 0
diff --git a/src/target/board/digi_connectcore_wi-9c.cfg b/src/target/board/digi_connectcore_wi-9c.cfg
deleted file mode 100644
index 93317327..00000000
--- a/src/target/board/digi_connectcore_wi-9c.cfg
+++ /dev/null
@@ -1,127 +0,0 @@
-######################################
-# Target: DIGI ConnectCore Wi-9C
-######################################
-
-reset_config trst_and_srst
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME ns9360
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- # This config file was defaulting to big endian..
- set _ENDIAN big
-}
-
-
-# What's a good fallback frequency for this board if RCLK is
-# not available??
-jtag_rclk 1000
-
-
-if { [info exists CPUTAPID ] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0xFFFFFFFF
-}
-
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-jtag_nsrst_delay 200
-jtag_ntrst_delay 0
-
-
-######################
-# Target configuration
-######################
-
-target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm926ejs
-$_TARGETNAME configure -event reset-init {
- mww 0x90600104 0x33313333
- mww 0xA0700000 0x00000001 # Enable the memory controller.
- mww 0xA0700024 0x00000006 # Set the refresh counter 6
- mww 0xA0700028 0x00000001 #
- mww 0xA0700030 0x00000001 # Set the precharge period
- mww 0xA0700034 0x00000004 # Active to precharge command period is 16 clock cycles
- mww 0xA070003C 0x00000001 # tAPR
- mww 0xA0700040 0x00000005 # tDAL
- mww 0xA0700044 0x00000001 # tWR
- mww 0xA0700048 0x00000006 # tRC 32 clock cycles
- mww 0xA070004C 0x00000006 # tRFC 32 clock cycles
- mww 0xA0700054 0x00000001 # tRRD
- mww 0xA0700058 0x00000001 # tMRD
- mww 0xA0700100 0x00004280 # Dynamic Config 0 (cs4)
- mww 0xA0700120 0x00004280 # Dynamic Config 1 (cs5)
- mww 0xA0700140 0x00004280 # Dynamic Config 2 (cs6)
- mww 0xA0700160 0x00004280 # Dynamic Config 3 (cs7)
- #
- mww 0xA0700104 0x00000203 # CAS latency is 2 at 100 MHz
- mww 0xA0700124 0x00000203 # CAS latency is 2 at 100 MHz
- mww 0xA0700144 0x00000203 # CAS latency is 2 at 100 MHz
- mww 0xA0700164 0x00000203 # CAS latency is 2 at 100 MHz
- #
- mww 0xA0700020 0x00000103 # issue SDRAM PALL command
- #
- mww 0xA0700024 0x00000001 # Set the refresh counter to be as small as possible
- #
- # Add some dummy writes to give the SDRAM time to settle, it needs two
- # AHB clock cycles, here we poke in the debugger flag, this lets
- # the software know that we are in the debugger
- mww 0xA0900000 0x00000002
- mww 0xA0900000 0x00000002
- mww 0xA0900000 0x00000002
- mww 0xA0900000 0x00000002
- mww 0xA0900000 0x00000002
- #
- mdw 0xA0900000
- mdw 0xA0900000
- mdw 0xA0900000
- mdw 0xA0900000
- mdw 0xA0900000
- #
- mww 0xA0700024 0x00000030 # Set the refresh counter to 30
- mww 0xA0700020 0x00000083 # Issue SDRAM MODE command
- #
- # Next we perform a read of RAM.
- # mw = move word.
- mdw 0x00022000
- # mw 0x00022000:P, r3 # 22000 for cas2 latency, 32000 for cas 3
- #
- mww 0xA0700020 0x00000003 # issue SDRAM NORMAL command
- mww 0xA0700100 0x00084280 # Enable buffer access
- mww 0xA0700120 0x00084280 # Enable buffer access
- mww 0xA0700140 0x00084280 # Enable buffer access
- mww 0xA0700160 0x00084280 # Enable buffer access
-
- #Set byte lane state (static mem 1)"
- mww 0xA0700220, 0x00000082
- #Flash Start
- mww 0xA09001F8, 0x50000000
- #Flash Mask Reg
- mww 0xA09001FC, 0xFF000001
- mww 0xA0700028, 0x00000001
-
- # RAMAddr = 0x00020000
- # RAMSize = 0x00004000
-
- # Set the processor mode
- reg cpsr 0xd3
-}
-
-$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x00000000 -work-area-size 0x1000 -work-area-backup 1
-
-#####################
-# Flash configuration
-#####################
-
-#M29DW323DB - not working
-#flash bank cfi <base> <size> <chip width> <bus width> <target#>
-flash bank cfi 0x50000000 0x0400000 2 2 0
-
-
-
diff --git a/src/target/board/dm355evm.cfg b/src/target/board/dm355evm.cfg
deleted file mode 100644
index 9e6dc73b..00000000
--- a/src/target/board/dm355evm.cfg
+++ /dev/null
@@ -1,119 +0,0 @@
-#
-# DM355 EVM board
-# http://focus.ti.com/docs/toolsw/folders/print/tmdsevm355.html
-# http://c6000.spectrumdigital.com/evmdm355/
-
-source [find target/ti_dm355.cfg]
-
-reset_config trst_and_srst separate
-
-# NOTE: disable or replace this call to dm355evm_init if you're
-# debugging new UBL code from SRAM.
-$_TARGETNAME configure -event reset-init { dm355evm_init }
-
-#
-# This post-reset init is called when the MMU isn't active, all IRQs
-# are disabled, etc. It should do most of what a UBL does, except for
-# loading code (like U-Boot) into DRAM and running it.
-#
-proc dm355evm_init {} {
- global dm355
-
- puts "Initialize DM355 EVM board"
-
- # CLKIN = 24 MHz ... can't talk quickly to ARM yet
- jtag_khz 1500
-
- ########################
- # PLL1 = 432 MHz (/8, x144)
- # ...SYSCLK1 = 216 MHz (/2) ... ARM, MJCP
- # ...SYSCLK2 = 108 MHz (/4) ... Peripherals
- # ...SYSCLK3 = 27 MHz (/16) ... VPBE, DAC
- # ...SYSCLK4 = 108 MHz (/4) ... VPSS
- # pll1.{prediv,div1,div2} are fixed
- # pll1.postdiv set in MISC (for *this* speed grade)
-
- set addr [dict get $dm355 pllc1]
- set pll_divs [dict create]
- dict set pll_divs div3 16
- dict set pll_divs div4 8
- pll_setup $addr 144 $pll_divs
-
- # ARM is now running at 216 MHz, so JTAG can go faster
- jtag_khz 20000
-
- ########################
- # PLL2 = 342 MHz (/8, x114)
- # ....SYSCLK1 = 342 MHz (/1) ... DDR PHY at 171 MHz, 2x clock
- # pll2.{postdiv,div1} are fixed
-
- set addr [dict get $dm355 pllc2]
- set pll_divs [dict create]
- dict set pll_divs prediv 8
- pll_setup $addr 114 $pll_divs
-
- ########################
- # PINMUX
-
- # All Video Inputs
- davinci_pinmux $dm355 0 0x00007f55
- # All Video Outputs
- davinci_pinmux $dm355 1 0x00145555
- # EMIFA (NOTE: more could be set up for use as GPIOs)
- davinci_pinmux $dm355 2 0x00000c08
- # SPI0, SPI1, UART1, I2C, SD0, SD1, McBSP0, CLKOUTs
- davinci_pinmux $dm355 3 0x1bff55ff
- # MMC/SD0 instead of MS; SPI0
- davinci_pinmux $dm355 4 0x00000000
-
- ########################
- # PSC setup (minimal)
-
- # DDR EMIF/13, AEMIF/14, UART0/19
- psc_enable 13
- psc_enable 14
- psc_enable 19
- psc_go
-
- ########################
- # DDR2 EMIF
-
- # FIXME setup
-
- ########################
- # ASYNC EMIF
-
- set addr [dict get $dm355 a_emif]
-
- # slow/pessimistic timings
- set nand_timings 0x40400204
- # fast (25% faster page reads)
- #set nand_timings 0x0400008c
-
- # AWCCR
- mww [expr $addr + 0x04] 0xff
- # CS0 == socketed NAND (default MT29F16G08FAA, 2GByte)
- mww [expr $addr + 0x10] $nand_timings
- # CS1 == dm9000 Ethernet
- mww [expr $addr + 0x14] 0x00a00505
- # NANDFCR -- only CS0 has NAND
- mww [expr $addr + 0x60] 0x01
-
- ########################
- # UART0
-
- # FIXME setup
-}
-
-# NAND -- socket has two chipselects, MT29F16G08FAA puts 1GByte on each one.
-#
-# NOTE: "hwecc4" here presumes that if you're using the standard 2GB NAND
-# you either (a) have 'new' DM355 chips, with boot ROMs that don't need to
-# use "hwecc4_infix" for the UBL; or else (b) aren't updating anything that
-# needs infix layout ... like an old UBL, old U-Boot, old MVL kernel, etc.
-nand device davinci 0 0x02000000 hwecc4 0x01e10000
-nand device davinci 0 0x02004000 hwecc4 0x01e10000
-
-# FIXME
-# - support writing UBL with its header (new layout only with new ROMs)
-# - support writing ABL/U-Boot with its header (new layout)
diff --git a/src/target/board/eir.cfg b/src/target/board/eir.cfg
deleted file mode 100644
index 08765658..00000000
--- a/src/target/board/eir.cfg
+++ /dev/null
@@ -1,94 +0,0 @@
-# Elector Internet Radio board
-# http://www.ethernut.de/en/hardware/eir/index.html
-
-source [find target/sam7se512.cfg]
-
-$_TARGETNAME configure -event reset-init {
- # WDT_MR, disable watchdog
- mww 0xFFFFFD44 0x00008000
-
- # RSTC_MR, enable user reset
- mww 0xfffffd08 0xa5000001
-
- # CKGR_MOR
- mww 0xFFFFFC20 0x00000601
- sleep 10
-
- # CKGR_PLLR
- mww 0xFFFFFC2C 0x00481c0e
- sleep 10
-
- # PMC_MCKR
- mww 0xFFFFFC30 0x00000007
- sleep 10
-
- # PMC_IER
- mww 0xFFFFFF60 0x00480100
-
- #
- # Enable SDRAM interface.
- #
-
- # Enable SDRAM control at PIO A.
- mww 0xfffff474 0x3f800000 # PIO_BSR_OFF
- mww 0xfffff404 0x3f800000 # PIO_PDR_OFF
-
- # Enable address bus (A0, A2-A11, A13-A17) at PIO B
- mww 0xfffff674 0x0003effd # PIO_BSR_OFF
- mww 0xfffff604 0x0003effd # PIO_PDR_OFF
-
- # Enable 16 bit data bus at PIO C
- mww 0xfffff870 0x0000ffff # PIO_ASR_OFF
- mww 0xfffff804 0x0000ffff # PIO_PDR_OFF
-
- # Enable SDRAM chip select
- mww 0xffffff80 0x00000002 # EBI_CSA_OFF
-
- # Set SDRAM characteristics in configuration register.
- # Hard coded values for MT48LC32M16A2 with 48MHz CPU.
- mww 0xffffffb8 0x2192215a # SDRAMC_CR_OFF
- sleep 10
-
- # Issue 16 bit SDRAM command: NOP
- mww 0xffffffb0 0x00000011 # SDRAMC_MR_OFF
- mww 0x20000000 0x00000000
-
- # Issue 16 bit SDRAM command: Precharge all
- mww 0xffffffb0 0x00000012 # SDRAMC_MR_OFF
- mww 0x20000000 0x00000000
-
- # Issue 8 auto-refresh cycles
- mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
- mww 0x20000000 0x00000000
- mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
- mww 0x20000000 0x00000000
- mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
- mww 0x20000000 0x00000000
- mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
- mww 0x20000000 0x00000000
- mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
- mww 0x20000000 0x00000000
- mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
- mww 0x20000000 0x00000000
- mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
- mww 0x20000000 0x00000000
- mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
- mww 0x20000000 0x00000000
-
- # Issue 16 bit SDRAM command: Set mode register
- mww 0xffffffb0 0x00000013 # SDRAMC_MR_OFF
- mww 0x20000014 0xcafedede
-
- # Set refresh rate count ???
- mww 0xffffffb4 0x00000013 # SDRAMC_TR_OFF
-
- # Issue 16 bit SDRAM command: Normal mode
- mww 0xffffffb0 0x00000010 # SDRAMC_MR_OFF
- mww 0x20000000 0x00000180
-
- #
- # Enable external reset key.
- #
- mww 0xfffffd08 0xa5000001
-}
-
diff --git a/src/target/board/hammer.cfg b/src/target/board/hammer.cfg
deleted file mode 100644
index ed83803f..00000000
--- a/src/target/board/hammer.cfg
+++ /dev/null
@@ -1,36 +0,0 @@
-# Target Configuration for the TinCanTools S3C2410 Based Hammer Module
-# http://www.tincantools.com
-
-source [find target/samsung_s3c2410.cfg]
-
-$_TARGETNAME configure -event reset-init {
- # Reset Script for the TinCanTools S3C2410 Based Hammer Module
- # http://www.tincantools.com
- #
- # Setup primary clocks and initialize the SDRAM
- mww 0x53000000 0x00000000
- mww 0x4a000008 0xffffffff
- mww 0x4a00000c 0x000007ff
- mww 0x4c000000 0x00ffffff
- mww 0x4c000014 0x00000003
- mww 0x4c000004 0x000a1031
- mww 0x48000000 0x11111122
- mww 0x48000004 0x00000700
- mww 0x48000008 0x00000700
- mww 0x4800000c 0x00000700
- mww 0x48000010 0x00000700
- mww 0x48000014 0x00000700
- mww 0x48000018 0x00000700
- mww 0x4800001c 0x00018005
- mww 0x48000020 0x00018005
- mww 0x48000024 0x009c0459
- mww 0x48000028 0x000000b2
- mww 0x4800002c 0x00000030
- mww 0x48000030 0x00000030
- flash probe 0
-}
-
-
-#flash configuration
-#flash bank <driver> <base> <size> <chip_width> <bus_width> [driver_options ...]
-flash bank cfi 0x00000000 0x1000000 2 2 0
diff --git a/src/target/board/hitex_stm32-performancestick.cfg b/src/target/board/hitex_stm32-performancestick.cfg
deleted file mode 100644
index 5effbd96..00000000
--- a/src/target/board/hitex_stm32-performancestick.cfg
+++ /dev/null
@@ -1,50 +0,0 @@
-# Hitex stm32 performance stick
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME stm32_hitex
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-# set jtag speed
-jtag_khz 500
-
-jtag_nsrst_delay 100
-jtag_ntrst_delay 100
-
-#use combined on interfaces or targets that can't set TRST/SRST separately
-reset_config trst_and_srst
-
-#jtag scan chain
-# The CPU
-if { [info exists CPUTAPID ] } {
- set _CPUTAPID $CPUTAPID
-} else {
- # See STM Document RM0008
- # Section 26.6.3
- set _CPUTAPID 0x3ba00477
-}
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-# The boundery scan register, leave the "expected-id" undefined.
-jtag newtap $_CHIPNAME bs -irlen 5 -ircapture 0x1 -irmask 0x1
-
-# configure str750 connected to jtag chain
-jtag newtap $_CHIPNAME unknown -irlen 4 -ircapture 0x1 -irmask 0x0f
-
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
-target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
-
-$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x20000000 -work-area-size 16384 -work-area-backup 0
-
-#
-flash bank stm32x 0 0 0 0 0
-
-# For more information about the configuration files, take a look at:
-# openocd.texi
diff --git a/src/target/board/hitex_str9-comstick.cfg b/src/target/board/hitex_str9-comstick.cfg
deleted file mode 100644
index de4d56dd..00000000
--- a/src/target/board/hitex_str9-comstick.cfg
+++ /dev/null
@@ -1,72 +0,0 @@
-# Hitex STR9-comStick
-# http://www.hitex.com/index.php?id=383
-# This works for the STR9-comStick revisions STR912CS-A1 and STR912CS-A2.
-
-source [find interface/hitex_str9-comstick.cfg]
-
-# set jtag speed
-jtag_khz 3000
-
-jtag_nsrst_delay 100
-jtag_ntrst_delay 100
-#use combined on interfaces or targets that can't set TRST/SRST separately
-reset_config trst_and_srst
-#jtag scan chain
-#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME str912
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-if { [info exists FLASHTAPID ] } {
- set _FLASHTAPID $FLASHTAPID
-} else {
- set _FLASHTAPID 0x04570041
-}
-jtag newtap $_CHIPNAME flash -irlen 8 -ircapture 0x1 -irmask 0x1 -expected-id $_FLASHTAPID
-
-if { [info exists CPUTAPID ] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x25966041
-}
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-if { [info exists BSTAPID ] } {
- set _BSTAPID $BSTAPID
-} else {
- # Found on STR9-comStick, revision STR912CS-A1
- set _BSTAPID1 0x1457f041
- # Found on STR9-comStick, revision STR912CS-A2
- set _BSTAPID2 0x2457f041
-}
-jtag newtap $_CHIPNAME bs -irlen 5 -ircapture 0x1 -irmask 0x1 -expected-id $_BSTAPID1 -expected-id $_BSTAPID2
-
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
-target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm966e
-
-$_TARGETNAME configure -event reset-init {
- # We can increase speed now that we know the target is halted.
- #jtag_rclk 3000
-
- # -- Enable 96K RAM
- # PFQBC enabled / DTCM & AHB wait-states disabled
- mww 0x5C002034 0x0191
-
- str9x flash_config 0 4 2 0 0x80000
- flash protect 0 0 7 off
-}
-
-$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x50000000 -work-area-size 16384 -work-area-backup 0
-
-#flash bank <driver> <base> <size> <chip_width> <bus_width>
-flash bank str9x 0x00000000 0x00080000 0 0 0
-flash bank str9x 0x00080000 0x00008000 0 0 0
diff --git a/src/target/board/iar_str912_sk.cfg b/src/target/board/iar_str912_sk.cfg
deleted file mode 100644
index ba060a04..00000000
--- a/src/target/board/iar_str912_sk.cfg
+++ /dev/null
@@ -1,3 +0,0 @@
-# The IAR str912-sk evaluation kick start board has an str912
-
-source [find target/str912.cfg] \ No newline at end of file
diff --git a/src/target/board/imx27ads.cfg b/src/target/board/imx27ads.cfg
deleted file mode 100644
index dc0de4a6..00000000
--- a/src/target/board/imx27ads.cfg
+++ /dev/null
@@ -1,75 +0,0 @@
-# The IMX27 ADS eval board has a single IMX27 chip
-# Note: tested on IMX27ADS Board REV-2.6 and REV-2.8
-source [find target/imx27.cfg]
-$_TARGETNAME configure -event gdb-attach { reset init }
-$_TARGETNAME configure -event reset-init { imx27ads_init }
-
-# The IMX27 ADS board has a NOR flash on CS0
-flash_bank cfi 0xc0000000 0x00200000 2 2 0
-
-proc imx27ads_init { } {
- # This setup puts RAM at 0xA0000000
-
- # reset the board correctly
- reset run
- reset halt
-
- mww 0x10000000 0x20040304
- mww 0x10020000 0x00000000
- mww 0x10000004 0xDFFBFCFB
- mww 0x10020004 0xFFFFFFFF
-
- sleep 100
-
- # ========================================
- # Configure DDR on CSD0 -- initial reset
- # ========================================
- mww 0xD8001010 0x00000008
-
- # ========================================
- # Configure PSRAM on CS5
- # ========================================
- mww 0xd8002050 0x0000dcf6
- mww 0xd8002054 0x444a4541
- mww 0xd8002058 0x44443302
-
- # ========================================
- # Configure16 bit NorFlash on CS0
- # ========================================
- mww 0xd8002000 0x0000CC03
- mww 0xd8002004 0xa0330D01
- mww 0xd8002008 0x00220800
-
- # ========================================
- # Configure CPLD on CS4
- # ========================================
- mww 0xd8002040 0x0000DCF6
- mww 0xd8002044 0x444A4541
- mww 0xd8002048 0x44443302
-
- # ========================================
- # Configure DDR on CSD0 -- wait 5000 cycle
- # ========================================
- mww 0x10027828 0x55555555
- mww 0x10027830 0x55555555
- mww 0x10027834 0x55555555
- mww 0x10027838 0x00005005
- mww 0x1002783C 0x15555555
-
- mww 0xD8001010 0x00000004
-
- mww 0xD8001004 0x00795729
-
- mww 0xD8001000 0x92200000
- mww 0xA0000F00 0x0
-
- mww 0xD8001000 0xA2200000
- mww 0xA0000F00 0x0
- mww 0xA0000F00 0x0
-
- mww 0xD8001000 0xB2200000
- mwb 0xA0000033 0xFF
- mwb 0xA1000000 0xAA
-
- mww 0xD8001000 0x82228085
-}
diff --git a/src/target/board/imx27lnst.cfg b/src/target/board/imx27lnst.cfg
deleted file mode 100644
index 2ee7f094..00000000
--- a/src/target/board/imx27lnst.cfg
+++ /dev/null
@@ -1,59 +0,0 @@
-# The Linuxstamp-mx27 is board has a single IMX27 chip
-# For further info see http://opencircuits.com/Linuxstamp_mx27#OpenOCD
-source [find target/imx27.cfg]
-$_TARGETNAME configure -event gdb-attach { reset init }
-$_TARGETNAME configure -event reset-init { imx27lnst_init }
-
-proc imx27lnst_init { } {
- # This setup puts RAM at 0xA0000000
-
- # reset the board correctly
- jtag_khz 500
- reset run
- reset halt
-
- mww 0x10000000 0x20040304
- mww 0x10020000 0x00000000
- mww 0x10000004 0xDFFBFCFB
- mww 0x10020004 0xFFFFFFFF
-
- sleep 100
-
- # ========================================
- # Configure DDR on CSD0 -- initial reset
- # ========================================
- mww 0xD8001010 0x00000008
-
- sleep 100
-
- # ========================================
- # Configure DDR on CSD0 -- wait 5000 cycle
- # ========================================
- mww 0x10027828 0x55555555
- mww 0x10027830 0x55555555
- mww 0x10027834 0x55555555
- mww 0x10027838 0x00005005
- mww 0x1002783C 0x15555555
-
- mww 0xD8001010 0x00000004
-
- mww 0xD8001004 0x00795729
-
- #mww 0xD8001000 0x92200000
- mww 0xD8001000 0x91120000
- mww 0xA0000F00 0x0
-
- #mww 0xD8001000 0xA2200000
- mww 0xD8001000 0xA1120000
- mww 0xA0000F00 0x0
- mww 0xA0000F00 0x0
-
- #mww 0xD8001000 0xB2200000
- mww 0xD8001000 0xB1120000
- mwb 0xA0000033 0xFF
- mwb 0xA1000000 0xAA
-
- #mww 0xD8001000 0x82228085
- mww 0xD8001000 0x81128080
-
-}
diff --git a/src/target/board/imx31pdk.cfg b/src/target/board/imx31pdk.cfg
deleted file mode 100644
index 67233567..00000000
--- a/src/target/board/imx31pdk.cfg
+++ /dev/null
@@ -1,101 +0,0 @@
-# The IMX31PDK eval board has a single IMX31 chip
-source [find target/imx31.cfg]
-$_TARGETNAME configure -event gdb-attach { reset init }
-$_TARGETNAME configure -event reset-init { imx31pdk_init }
-
-proc imx31pdk_init { } {
- # This setup puts RAM at 0x80000000
-
- # reset the board correctly
- reset run
- reset halt
-
- # ========================================
- # Init CCM
- # ========================================
- mww 0x53FC0000 0x040
- mww 0x53F80000 0x074B0B7D
-
- sleep 100
-
- # ========================================
- # 399MHz - 26MHz input, PD=1,MFI=7, MFN=27, MFD=40
- # ========================================
- mww 0x53F80004 0xFF871D50
- mww 0x53F80010 0x00271C1B
-
- # ========================================
- # Configure CPLD on CS5
- # ========================================
- mww 0xb8002050 0x0000DCF6
- mww 0xb8002054 0x444A4541
- mww 0xb8002058 0x44443302
-
- # ========================================
- # SDCLK
- # ========================================
- mww 0x43FAC26C 0
-
- # ========================================
- # CAS
- # ========================================
- mww 0x43FAC270 0
-
- # ========================================
- # RAS
- # ========================================
- mww 0x43FAC274 0
-
- # ========================================
- # CS2 (CSD0)
- # ========================================
- mww 0x43FAC27C 0x1000
-
- # ========================================
- # DQM3
- # ========================================
- mww 0x43FAC284 0
-
- # ========================================
- # DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC)
- # ========================================
- mww 0x43FAC288 0
- mww 0x43FAC28C 0
- mww 0x43FAC290 0
- mww 0x43FAC294 0
- mww 0x43FAC298 0
- mww 0x43FAC29C 0
- mww 0x43FAC2A0 0
- mww 0x43FAC2A4 0
- mww 0x43FAC2A8 0
- mww 0x43FAC2AC 0
- mww 0x43FAC2B0 0
- mww 0x43FAC2B4 0
- mww 0x43FAC2B8 0
- mww 0x43FAC2BC 0
- mww 0x43FAC2C0 0
- mww 0x43FAC2C4 0
- mww 0x43FAC2C8 0
- mww 0x43FAC2CC 0
- mww 0x43FAC2D0 0
- mww 0x43FAC2D4 0
- mww 0x43FAC2D8 0
- mww 0x43FAC2DC 0
-
- # ========================================
- # Initialization script for 32 bit DDR on MX31 PDK
- # ========================================
- mww 0xB8001010 0x00000004
- mww 0xB8001004 0x006ac73a
- mww 0xB8001000 0x92100000
- mww 0x80000f00 0x12344321
- mww 0xB8001000 0xa2100000
- mww 0x80000000 0x12344321
- mww 0x80000000 0x12344321
- mww 0xB8001000 0xb2100000
- mwb 0x80000033 0xda
- mwb 0x81000000 0xff
- mww 0xB8001000 0x82226080
- mww 0x80000000 0xDEADBEEF
- mww 0xB8001010 0x0000000c
-}
diff --git a/src/target/board/keil_mcb2140.cfg b/src/target/board/keil_mcb2140.cfg
deleted file mode 100644
index db81efad..00000000
--- a/src/target/board/keil_mcb2140.cfg
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# Keil MCB2140 eval board
-#
-# http://www.keil.com/mcb2140/picture.asp
-#
-
-source [find target/lpc2148.cfg]
-
diff --git a/src/target/board/linksys_nslu2.cfg b/src/target/board/linksys_nslu2.cfg
deleted file mode 100644
index 52984107..00000000
--- a/src/target/board/linksys_nslu2.cfg
+++ /dev/null
@@ -1,8 +0,0 @@
-# This is for the LinkSys (CISCO) NSLU2 board
-# It is an Intel XSCALE IXP420 CPU.
-
-source [find target/ixp42x.cfg]
-# The _TARGETNAME is set by the above.
-
-$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x00020000 -work-area-size 0x10000 -work-area-backup 0
-
diff --git a/src/target/board/logicpd_imx27.cfg b/src/target/board/logicpd_imx27.cfg
deleted file mode 100644
index b068f1a1..00000000
--- a/src/target/board/logicpd_imx27.cfg
+++ /dev/null
@@ -1,12 +0,0 @@
-# The LogicPD Eval IMX27 eval board has a single IMX27 chip
-source [find target/imx27.cfg]
-
-# The Logic PD board has a NOR flash on CS0
-flash_bank cfi 0xc0000000 0x00200000 2 2 0
-
-#
-# FIX ME, Add support to
-#
-# (A) hard reset the board.
-# (B) Initialize the SDRAM on the board
-#
diff --git a/src/target/board/olimex_LPC2378STK.cfg b/src/target/board/olimex_LPC2378STK.cfg
deleted file mode 100644
index a4b422dc..00000000
--- a/src/target/board/olimex_LPC2378STK.cfg
+++ /dev/null
@@ -1,11 +0,0 @@
-#####################################################
-# Olimex LPC2378STK eval board
-#
-# http://olimex.com/dev/lpc-2378stk.html
-#
-# Author: Sten, debian@sansys-electronic.com
-#####################################################
-#
-
-source [find target/lpc2378.cfg]
-
diff --git a/src/target/board/olimex_lpc_h2148.cfg b/src/target/board/olimex_lpc_h2148.cfg
deleted file mode 100644
index 7833fdec..00000000
--- a/src/target/board/olimex_lpc_h2148.cfg
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# Olimex LPC-H2148 eval board
-#
-# http://www.olimex.com/dev/lpc-h2148.html
-#
-
-source [find target/lpc2148.cfg]
-
diff --git a/src/target/board/olimex_sam7_ex256.cfg b/src/target/board/olimex_sam7_ex256.cfg
deleted file mode 100644
index 5f83629d..00000000
--- a/src/target/board/olimex_sam7_ex256.cfg
+++ /dev/null
@@ -1,4 +0,0 @@
-# Olimex SAM7-EX256 has a single Atmel at91sam7ex256 on it.
-
-source [find target/sam7x256.cfg]
-
diff --git a/src/target/board/olimex_sam9_l9260.cfg b/src/target/board/olimex_sam9_l9260.cfg
deleted file mode 100644
index fbd8f5c0..00000000
--- a/src/target/board/olimex_sam9_l9260.cfg
+++ /dev/null
@@ -1,10 +0,0 @@
-##
-# Olimex SAM9-L9260 board configuration file
-#
-# Date Author Change
-# ---- ----- -----
-# 17/Jan/2009 Dean Glazeski Initial Creation
-#
-##
-
-source [find target/at91sam9260.cfg]
diff --git a/src/target/board/olimex_stm32_h103.cfg b/src/target/board/olimex_stm32_h103.cfg
deleted file mode 100644
index fadf1755..00000000
--- a/src/target/board/olimex_stm32_h103.cfg
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# Olimex STM32-H103 eval board
-#
-# http://olimex.com/dev/stm32-h103.html
-#
-
-source [find target/stm32.cfg]
-
diff --git a/src/target/board/pic-p32mx.cfg b/src/target/board/pic-p32mx.cfg
deleted file mode 100644
index 412a5067..00000000
--- a/src/target/board/pic-p32mx.cfg
+++ /dev/null
@@ -1,8 +0,0 @@
-# The Olimex PIC-P32MX has a PIC32MX
-
-set CPUTAPID 0x40916053
-source [find target/pic32mx.cfg]
-
-init
-flash probe 0
-flash probe 1
diff --git a/src/target/board/pxa255_sst.cfg b/src/target/board/pxa255_sst.cfg
deleted file mode 100644
index 37ff1a8b..00000000
--- a/src/target/board/pxa255_sst.cfg
+++ /dev/null
@@ -1,15 +0,0 @@
-# A PXA255 test board with SST 39LF400A flash
-#
-# At reset the memory map is as follows. Note that
-# the memory map changes later on as the application
-# starts...
-#
-# RAM at 0x4000000
-# Flash at 0x00000000
-#
-source [find target/pxa255.cfg]
-# Target name is set by above
-$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x4000000 -work-area-size 0x4000 -work-area-backup 0
-# flash bank <driver> <base> <size> <chip_width> <bus_width> <targetNum> [options]
-flash bank cfi 0x00000000 0x80000 2 2 0 jedec_probe
-
diff --git a/src/target/board/sheevaplug.cfg b/src/target/board/sheevaplug.cfg
deleted file mode 100644
index 6fe3ce3e..00000000
--- a/src/target/board/sheevaplug.cfg
+++ /dev/null
@@ -1,122 +0,0 @@
-# Marvell SheevaPlug
-
-source [find interface/sheevaplug.cfg]
-source [find target/feroceon.cfg]
-
-$_TARGETNAME configure \
- -work-area-phys 0x10000000 \
- -work-area-size 65536 \
- -work-area-backup 0
-
-arm7_9 dcc_downloads enable
-
-# this assumes the hardware default peripherals location before u-Boot moves it
-nand device orion 0 0xd8000000
-
-proc sheevaplug_init { } {
-
- # We need to assert DBGRQ while holding nSRST down.
- # However DBGACK will be set only when nSRST is released.
- # Furthermore, the JTAG interface doesn't respond at all when
- # the CPU is in the WFI (wait for interrupts) state, so it is
- # possible that initial tap examination failed. So let's
- # re-examine the target again here when nSRST is asserted which
- # should then succeed.
- jtag_reset 0 1
- feroceon.cpu arp_examine
- halt 0
- jtag_reset 0 0
- wait_halt
-
- arm926ejs cp15 0 0 1 0 0x00052078
-
- mww 0xD0001400 0x43000C30 # DDR SDRAM Configuration Register
- mww 0xD0001404 0x39543000 # Dunit Control Low Register
- mww 0xD0001408 0x22125451 # DDR SDRAM Timing (Low) Register
- mww 0xD000140C 0x00000833 # DDR SDRAM Timing (High) Register
- mww 0xD0001410 0x000000CC # DDR SDRAM Address Control Register
- mww 0xD0001414 0x00000000 # DDR SDRAM Open Pages Control Register
- mww 0xD0001418 0x00000000 # DDR SDRAM Operation Register
- mww 0xD000141C 0x00000C52 # DDR SDRAM Mode Register
- mww 0xD0001420 0x00000042 # DDR SDRAM Extended Mode Register
- mww 0xD0001424 0x0000F17F # Dunit Control High Register
- mww 0xD0001428 0x00085520 # Dunit Control High Register
- mww 0xD000147c 0x00008552 # Dunit Control High Register
- mww 0xD0001504 0x0FFFFFF1 # CS0n Size Register
- mww 0xD0001508 0x10000000 # CS1n Base Register
- mww 0xD000150C 0x0FFFFFF5 # CS1n Size Register
- mww 0xD0001514 0x00000000 # CS2n Size Register
- mww 0xD000151C 0x00000000 # CS3n Size Register
- mww 0xD0001494 0x003C0000 # DDR2 SDRAM ODT Control (Low) Register
- mww 0xD0001498 0x00000000 # DDR2 SDRAM ODT Control (High) REgister
- mww 0xD000149C 0x0000F80F # DDR2 Dunit ODT Control Register
- mww 0xD0001480 0x00000001 # DDR SDRAM Initialization Control Register
- mww 0xD0020204 0x00000000 # Main IRQ Interrupt Mask Register
- mww 0xD0020204 0x00000000 # "
- mww 0xD0020204 0x00000000 # "
- mww 0xD0020204 0x00000000 # "
- mww 0xD0020204 0x00000000 # "
- mww 0xD0020204 0x00000000 # "
- mww 0xD0020204 0x00000000 # "
- mww 0xD0020204 0x00000000 # "
- mww 0xD0020204 0x00000000 # "
- mww 0xD0020204 0x00000000 # "
- mww 0xD0020204 0x00000000 # "
- mww 0xD0020204 0x00000000 # "
- mww 0xD0020204 0x00000000 # "
- mww 0xD0020204 0x00000000 # "
- mww 0xD0020204 0x00000000 # "
- mww 0xD0020204 0x00000000 # "
- mww 0xD0020204 0x00000000 # "
- mww 0xD0020204 0x00000000 # "
- mww 0xD0020204 0x00000000 # "
- mww 0xD0020204 0x00000000 # "
- mww 0xD0020204 0x00000000 # "
- mww 0xD0020204 0x00000000 # "
- mww 0xD0020204 0x00000000 # "
- mww 0xD0020204 0x00000000 # "
- mww 0xD0020204 0x00000000 # "
- mww 0xD0020204 0x00000000 # "
- mww 0xD0020204 0x00000000 # "
- mww 0xD0020204 0x00000000 # "
- mww 0xD0020204 0x00000000 # "
- mww 0xD0020204 0x00000000 # "
- mww 0xD0020204 0x00000000 # "
- mww 0xD0020204 0x00000000 # "
- mww 0xD0020204 0x00000000 # "
- mww 0xD0020204 0x00000000 # "
- mww 0xD0020204 0x00000000 # "
- mww 0xD0020204 0x00000000 # "
- mww 0xD0020204 0x00000000 # "
-
- mww 0xD0010000 0x01111111 # MPP 0 to 7
- mww 0xD0010004 0x11113322 # MPP 8 to 15
- mww 0xD0010008 0x00001111 # MPP 16 to 23
-
- mww 0xD0010418 0x003E07CF # NAND Read Parameters REgister
- mww 0xD001041C 0x000F0F0F # NAND Write Parameters Register
- mww 0xD0010470 0x01C7D943 # NAND Flash Control Register
-
-}
-
-proc sheevaplug_reflash_uboot { } {
-
- # reflash the u-Boot binary and reboot into it
- sheevaplug_init
- nand probe 0
- nand erase 0 0x0 0xa0000
- nand write 0 uboot.bin 0 oob_softecc_kw
- resume
-
-}
-
-proc sheevaplug_load_uboot { } {
-
- # load u-Boot into RAM and execute it
- sheevaplug_init
- load_image uboot.elf
- verify_image uboot.elf
- resume 0x00600000
-
-}
-
diff --git a/src/target/board/stm3210e_eval.cfg b/src/target/board/stm3210e_eval.cfg
deleted file mode 100644
index ab2f64f0..00000000
--- a/src/target/board/stm3210e_eval.cfg
+++ /dev/null
@@ -1,3 +0,0 @@
-# This is an STM32 eval board with a single STM32F103ZET6 chip on it.
-
-source [find target/stm32.cfg]
diff --git a/src/target/board/stm32f10x_128k_eval.cfg b/src/target/board/stm32f10x_128k_eval.cfg
deleted file mode 100644
index ce073708..00000000
--- a/src/target/board/stm32f10x_128k_eval.cfg
+++ /dev/null
@@ -1,4 +0,0 @@
-# This is an STM32 eval board with a single STM32F103VBT6 chip on it.
-
-source [find target/stm32.cfg]
-
diff --git a/src/target/board/str910-eval.cfg b/src/target/board/str910-eval.cfg
deleted file mode 100644
index 10a2100b..00000000
--- a/src/target/board/str910-eval.cfg
+++ /dev/null
@@ -1,61 +0,0 @@
-# str910-eval eval board
-#
-# Need reset scripts
-reset_config trst_and_srst
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME str912
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-if { [info exists FLASHTAPID ] } {
- set _FLASHTAPID $FLASHTAPID
-} else {
- set _FLASHTAPID 0x04570041
-}
-jtag newtap $_CHIPNAME flash -irlen 8 -ircapture 0x1 -irmask 0x1 -expected-id $_FLASHTAPID
-
-
-if { [info exists CPUTAPID ] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x25966041
-}
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-if { [info exists BSTAPID ] } {
- set _BSTAPID $BSTAPID
-} else {
- set _BSTAPID 0x1457f041
-}
-jtag newtap $_CHIPNAME bs -irlen 5 -ircapture 0x1 -irmask 0x1 -expected-id $_BSTAPID
-
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
-target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm966e
-$_TARGETNAME configure -work-area-phys 0x50000000 -work-area-virt 0x50000000 -work-area-size 16384 -work-area-backup 1
-
-$_TARGETNAME configure -event reset-init {
- # We can increase speed now that we know the target is halted.
- #jtag_rclk 3000
-
- # -- Enable 96K RAM
- # PFQBC enabled / DTCM & AHB wait-states disabled
- mww 0x5C002034 0x0191
-
- str9x flash_config 0 4 2 0 0x80000
- flash protect 0 0 7 off
-}
-
-#flash bank str9x <base> <size> 0 0 <target#> <variant>
-flash bank str9x 0x00000000 0x00080000 0 0 0
-flash bank str9x 0x00080000 0x00008000 0 0 0
-
-# For more information about the configuration files, take a look at:
-# openocd.texi
diff --git a/src/target/board/ti_beagleboard.cfg b/src/target/board/ti_beagleboard.cfg
deleted file mode 100644
index 170df460..00000000
--- a/src/target/board/ti_beagleboard.cfg
+++ /dev/null
@@ -1,14 +0,0 @@
-
-source [find target/omap3530.cfg]
-
-reset_config trst_and_srst
-jtag_reset 1 1
-sleep 10
-runtest 10
-jtag_reset 0 0
-
-endstate RUN/IDLE
-
-init
-
-omap3_dbginit
diff --git a/src/target/board/unknown-board-atmel-at91sam9260.cfg b/src/target/board/unknown-board-atmel-at91sam9260.cfg
deleted file mode 100644
index 4d69f0fd..00000000
--- a/src/target/board/unknown-board-atmel-at91sam9260.cfg
+++ /dev/null
@@ -1,82 +0,0 @@
-# Thanks to Pieter Conradie for this script!
-# Target: Atmel AT91SAM9260
-######################################
-
-# We add to the minimal configuration.
-source [find target/at91sam9260.cfg]
-
-######################
-# Target configuration
-######################
-
-$_TARGETNAME configure -event reset-init {
- # at reset chip runs at 32khz
- jtag_khz 8
- mww 0xfffffd08 0xa5000501 # RSTC_MR : enable user reset
- mww 0xfffffd44 0x00008000 # WDT_MR : disable watchdog
-
- mww 0xfffffc20 0x00004001 # CKGR_MOR : enable the main oscillator
- sleep 20 # wait 20 ms
- mww 0xfffffc30 0x00000001 # PMC_MCKR : switch to main oscillator
- sleep 10 # wait 10 ms
- mww 0xfffffc28 0x2060bf09 # CKGR_PLLAR: Set PLLA Register for 198,656MHz
- sleep 20 # wait 20 ms
- mww 0xfffffc30 0x00000101 # PMC_MCKR : Select prescaler
- sleep 10 # wait 10 ms
- mww 0xfffffc30 0x00000102 # PMC_MCKR : Clock from PLLA is selected
- sleep 10 # wait 10 ms
-
- # Now run at anything fast... ie: 10mhz!
- jtag_khz 10000 # Increase JTAG Speed to 6 MHz
- arm7_9 dcc_downloads enable # Enable faster DCC downloads
-
- mww 0xffffec00 0x01020102 # SMC_SETUP0 : Setup SMC for Intel NOR Flash JS28F128P30T85 128MBit
- mww 0xffffec04 0x09070806 # SMC_PULSE0
- mww 0xffffec08 0x000d000b # SMC_CYCLE0
- mww 0xffffec0c 0x00001003 # SMC_MODE0
-
- flash probe 0 # Identify flash bank 0
-
- mww 0xfffff870 0xffff0000 # PIO_ASR : Select peripheral function for D15..D31
- mww 0xfffff804 0xffff0000 # PIO_PDR : Disable PIO function for D15..D31
-
- mww 0xffffef1c 0x2 # EBI_CSA : Assign EBI Chip Select 1 to SDRAM
-
- #mww 0xffffea08 0x85227259 # SDRAMC_CR : Configure SDRAM (2 x Samsung K4S561632H-UC75 : 4M x 16Bit x 4 Banks)
- mww 0xffffea08 0x85227254 # SDRAMC_CR : Configure SDRAM (2 x Samsung K4S641632H-UC75 : 1M x 16Bit x 4 Banks)
-
- mww 0xffffea00 0x1 # SDRAMC_MR : issue a NOP command
- mww 0x20000000 0
- mww 0xffffea00 0x2 # SDRAMC_MR : issue an 'All Banks Precharge' command
- mww 0x20000000 0
- mww 0xffffea00 0x4 # SDRAMC_MR : issue 8 x 'Auto-Refresh' Command
- mww 0x20000000 0
- mww 0xffffea00 0x4
- mww 0x20000000 0
- mww 0xffffea00 0x4
- mww 0x20000000 0
- mww 0xffffea00 0x4
- mww 0x20000000 0
- mww 0xffffea00 0x4
- mww 0x20000000 0
- mww 0xffffea00 0x4
- mww 0x20000000 0
- mww 0xffffea00 0x4
- mww 0x20000000 0
- mww 0xffffea00 0x4
- mww 0x20000000 0
- mww 0xffffea00 0x3 # SDRAMC_MR : issue a 'Load Mode Register' command
- mww 0x20000000 0
- mww 0xffffea00 0x0 # SDRAMC_MR : normal mode
- mww 0x20000000 0
- mww 0xffffea04 0x5d2 # SDRAMC_TR : Set refresh timer count to 15us
-}
-
-
-#####################
-# Flash configuration
-#####################
-
-#flash bank cfi <base> <size> <chip width> <bus width> <target#>
-flash bank cfi 0x10000000 0x01000000 2 2 0
-
diff --git a/src/target/board/x300t.cfg b/src/target/board/x300t.cfg
deleted file mode 100644
index 985f44ed..00000000
--- a/src/target/board/x300t.cfg
+++ /dev/null
@@ -1,30 +0,0 @@
-# This is for the T-Home X300T / X301T IPTV box,
-# which are based on IPTV reference designs from Kiss/Cisco KMM-3***
-#
-# It has Sigma Designs SMP8634 chip.
-source [find target/smp8634.cfg]
-
-$_TARGETNAME configure -event reset-init { x300t_init }
-
-# 1MB CFI capable flash
-# flash bank <driver> <base> <size> <chip_width> <bus_width>
-flash bank cfi 0xac000000 0x100000 2 2 0
-
-proc x300t_init { } {
- # Setup SDRAM config and flash mapping
- # initialize ram
- mww 0xa003fffc 3
- mww 0xa003fffc 2
- mww 0xa0030000 0xE34111BA
- mww 0xa003fffc 0xa4444
- mww 0xa003fffc 0
-
- # remap boot vector in CPU local RAM
- mww 0xa006f000 0x60000
-
- # map flash to CPU address space REG_BASE_cpu_block+CPU_remap4
- mww 0x0006f010 0x48000000
-
- # map flash addr to REG_BASE_cpu_block + LR_XENV_LOCATION (normally done by XOS)
- mww 0x00061ff0 0x48000000
-}
diff --git a/src/target/board/zy1000.cfg b/src/target/board/zy1000.cfg
deleted file mode 100644
index d8bb4650..00000000
--- a/src/target/board/zy1000.cfg
+++ /dev/null
@@ -1,110 +0,0 @@
-#Script for ZY1000
-
-#Atmel ties SRST & TRST together, at which point it makes
-#no sense to use TRST, but use TMS instead.
-#
-#The annoying thing with tying SRST & TRST together is that
-#there is no way to halt the CPU *before and during* the
-#SRST reset, which means that the CPU will run a number
-#of cycles before it can be halted(as much as milliseconds).
-reset_config srst_only srst_pulls_trst
-
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME zy1000
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-
-#jtag scan chain
-if { [info exists CPUTAPID ] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x1f0f0f0f
-}
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
-target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi-s_r4
-
-# at CPU CLK <32kHz this must be disabled
-arm7_9 fast_memory_access enable
-arm7_9 dcc_downloads enable
-
-flash bank ecosflash 0x01000000 0x200000 2 2 0 ecos/at91eb40a.elf
-$_TARGETNAME configure -event reset-init {
- # Set up chip selects & timings
- mww 0xFFE00000 0x0100273D
- mww 0xFFE00004 0x08002125
- mww 0xFFEe0008 0x02002125
- mww 0xFFE0000c 0x03002125
- mww 0xFFE00010 0x40000000
- mww 0xFFE00014 0x50000000
- mww 0xFFE00018 0x60000000
- mww 0xFFE0001c 0x70000000
- mww 0xFFE00020 0x00000001
- mww 0xFFE00024 0x00000000
-
- # remap
- mww 0xFFFFF124 0xFFFFFFFF
- mww 0xffff0010 0x100
- mww 0xffff0034 0x100
-
- #disable 16x5x UART interrupts
- mww 0x08020004 0
-}
-
-# required for usable performance. Used for lots of
-# other things than flash programming.
-$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x00020000 -work-area-size 0x20000 -work-area-backup 0
-
-jtag_khz 16000
-
-
-proc production_info {} {
- return "Serial number is official MAC number. Format XXXXXXXXXXXX"
-}
-
-# There is no return value from this procedure. If it is
-# successful it does not throw an exception
-#
-# Progress messages are output via puts
-proc production {firmwarefile serialnumber} {
- if {[string length $serialnumber]!=12} {
- puts "Invalid serial number"
- return
- }
-
- puts "Power cycling target"
- power off
- sleep 3000
- power on
- sleep 1000
- reset init
- flash write_image erase $firmwarefile 0x1000000 bin
- verify_image $firmwarefile 0x1000000 bin
-
- # Big endian... weee!!!!
- puts "Setting MAC number to $serialnumber"
- flash fillw [expr 0x1030000-0x8] "0x[string range $serialnumber 2 3][string range $serialnumber 0 1]0000" 1
- flash fillw [expr 0x1030000-0x4] "0x[string range $serialnumber 10 11][string range $serialnumber 8 9][string range $serialnumber 6 7][string range $serialnumber 4 5]" 1
- puts "Production successful"
-}
-
-
-proc production_test {} {
- power on
- sleep 1000
- target_request debugmsgs enable
- reset run
- sleep 25000
- target_request debugmsgs disable
- return "See IP address above..."
-}
diff --git a/src/target/interface/arm-jtag-ew.cfg b/src/target/interface/arm-jtag-ew.cfg
deleted file mode 100644
index 2e8b57e4..00000000
--- a/src/target/interface/arm-jtag-ew.cfg
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# Olimex ARM-JTAG-EW
-#
-# http://www.olimex.com/dev/arm-jtag-ew.html
-#
-
-interface arm-jtag-ew
-
diff --git a/src/target/interface/arm-usb-ocd.cfg b/src/target/interface/arm-usb-ocd.cfg
deleted file mode 100644
index e1fcf6e5..00000000
--- a/src/target/interface/arm-usb-ocd.cfg
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# Olimex ARM-USB-OCD
-#
-# http://www.olimex.com/dev/arm-usb-ocd.html
-#
-
-interface ft2232
-ft2232_device_desc "Olimex OpenOCD JTAG A"
-ft2232_layout "olimex-jtag"
-ft2232_vid_pid 0x15BA 0x0003
-
diff --git a/src/target/interface/at91rm9200.cfg b/src/target/interface/at91rm9200.cfg
deleted file mode 100644
index 20826478..00000000
--- a/src/target/interface/at91rm9200.cfg
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# Various Atmel AT91RM9200 boards
-#
-# TODO: URL?
-#
-
-interface at91rm9200
-at91rm9200_device rea_ecr
-
diff --git a/src/target/interface/axm0432.cfg b/src/target/interface/axm0432.cfg
deleted file mode 100644
index 204c3878..00000000
--- a/src/target/interface/axm0432.cfg
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# Axiom axm0432
-#
-# http://www.axman.com
-#
-
-interface ft2232
-ft2232_device_desc "Symphony SoundBite A"
-ft2232_layout "axm0432_jtag"
-ft2232_vid_pid 0x0403 0x6010
-
diff --git a/src/target/interface/calao-usb-a9260-c01.cfg b/src/target/interface/calao-usb-a9260-c01.cfg
deleted file mode 100644
index 0fbce9cb..00000000
--- a/src/target/interface/calao-usb-a9260-c01.cfg
+++ /dev/null
@@ -1,13 +0,0 @@
-#
-# CALAO Systems USB-A9260-C01
-#
-# http://www.calao-systems.com/
-#
-
-interface ft2232
-ft2232_layout jtagkey
-ft2232_device_desc "USB-A9260 A"
-ft2232_vid_pid 0x0403 0x6010
-script interface/calao-usb-a9260.cfg
-script target/at91sam9260minimal.cfg
-
diff --git a/src/target/interface/calao-usb-a9260-c02.cfg b/src/target/interface/calao-usb-a9260-c02.cfg
deleted file mode 100644
index d4eff34d..00000000
--- a/src/target/interface/calao-usb-a9260-c02.cfg
+++ /dev/null
@@ -1,13 +0,0 @@
-#
-# CALAO Systems USB-A9260-C02
-#
-# http://www.calao-systems.com/
-#
-
-interface ft2232
-ft2232_layout jtagkey
-ft2232_device_desc "USB-A9260 A"
-ft2232_vid_pid 0x0403 0x6001
-script interface/calao-usb-a9260.cfg
-script target/at91sam9260minimal.cfg
-
diff --git a/src/target/interface/calao-usb-a9260.cfg b/src/target/interface/calao-usb-a9260.cfg
deleted file mode 100644
index 57c68d61..00000000
--- a/src/target/interface/calao-usb-a9260.cfg
+++ /dev/null
@@ -1,16 +0,0 @@
-#
-# CALAO Systems USB-A9260 common -C01 -C02 setup
-#
-# http://www.calao-systems.com/
-#
-# See calao-usb-a9260-c01.cfg and calao-usb-a9260-c02.cfg.
-#
-# Note: You must have an OpenOCD version where jtag_speed sets two values.
-# trunk r606 contains the fix for this particular issue which can
-# be seen if jtag_speed does not set two separate values.
-#
-
-jtag_speed 1200 0
-jtag_nsrst_delay 200
-jtag_ntrst_delay 200
-
diff --git a/src/target/interface/chameleon.cfg b/src/target/interface/chameleon.cfg
deleted file mode 100644
index 2fb74681..00000000
--- a/src/target/interface/chameleon.cfg
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# Amontec Chameleon POD
-#
-# http://www.amontec.com/chameleon.shtml
-#
-
-interface parport
-parport_cable chameleon
-
diff --git a/src/target/interface/dummy.cfg b/src/target/interface/dummy.cfg
deleted file mode 100644
index 1c148c0c..00000000
--- a/src/target/interface/dummy.cfg
+++ /dev/null
@@ -1,6 +0,0 @@
-#
-# Dummy interface (for testing purposes)
-#
-
-interface dummy
-
diff --git a/src/target/interface/flyswatter.cfg b/src/target/interface/flyswatter.cfg
deleted file mode 100644
index 7b3c453f..00000000
--- a/src/target/interface/flyswatter.cfg
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# TinCanTools Flyswatter
-#
-# http://www.tincantools.com/product.php?productid=16134
-#
-
-interface ft2232
-ft2232_device_desc "Flyswatter A"
-ft2232_layout "flyswatter"
-ft2232_vid_pid 0x0403 0x6010
-jtag_speed 1
-
diff --git a/src/target/interface/hitex_str9-comstick.cfg b/src/target/interface/hitex_str9-comstick.cfg
deleted file mode 100644
index 32f19c68..00000000
--- a/src/target/interface/hitex_str9-comstick.cfg
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# Hitex STR9-comStick
-#
-# http://www.hitex.com/index.php?id=383
-#
-
-interface ft2232
-ft2232_device_desc "STR9-comStick A"
-ft2232_layout comstick
-ft2232_vid_pid 0x0640 0x002c
-
diff --git a/src/target/interface/icebear.cfg b/src/target/interface/icebear.cfg
deleted file mode 100644
index 3df42cb5..00000000
--- a/src/target/interface/icebear.cfg
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# Section5 ICEBear
-#
-# http://section5.ch/icebear
-#
-
-interface ft2232
-# ft2232_device_desc ""
-ft2232_layout icebear
-ft2232_vid_pid 0x0403 0xc140
-
diff --git a/src/target/interface/jlink.cfg b/src/target/interface/jlink.cfg
deleted file mode 100644
index f5ff7c7b..00000000
--- a/src/target/interface/jlink.cfg
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# Segger J-Link
-#
-# http://www.segger.com/jlink.html
-#
-
-interface jlink
-
diff --git a/src/target/interface/jtagkey-tiny.cfg b/src/target/interface/jtagkey-tiny.cfg
deleted file mode 100644
index 633fdda8..00000000
--- a/src/target/interface/jtagkey-tiny.cfg
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# Amontec JTAGkey-tiny
-#
-# http://www.amontec.com/jtagkey-tiny.shtml
-#
-
-# The JTAGkey-tiny uses exactly the same config as the JTAGkey.
-source [find interface/jtagkey.cfg]
-
diff --git a/src/target/interface/jtagkey.cfg b/src/target/interface/jtagkey.cfg
deleted file mode 100644
index beba7da1..00000000
--- a/src/target/interface/jtagkey.cfg
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# Amontec JTAGkey
-#
-# http://www.amontec.com/jtagkey.shtml
-#
-
-interface ft2232
-ft2232_device_desc "Amontec JTAGkey A"
-ft2232_layout jtagkey
-ft2232_vid_pid 0x0403 0xcff8
-
diff --git a/src/target/interface/luminary-lm3s811.cfg b/src/target/interface/luminary-lm3s811.cfg
deleted file mode 100644
index 8d90e858..00000000
--- a/src/target/interface/luminary-lm3s811.cfg
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# Luminary Micro Stellaris LM3S811 Evaluation Kit
-#
-# http://www.luminarymicro.com/products/stellaris_811_evaluation_kits.html
-#
-
-interface ft2232
-ft2232_device_desc "LM3S811 Evaluation Board A"
-ft2232_layout evb_lm3s811
-
diff --git a/src/target/interface/luminary.cfg b/src/target/interface/luminary.cfg
deleted file mode 100644
index bd324b18..00000000
--- a/src/target/interface/luminary.cfg
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# Luminary Micro Stellaris LM3S811 Evaluation Kit
-#
-# http://www.luminarymicro.com/products/stellaris_811_evaluation_kits.html
-#
-
-interface ft2232
-ft2232_device_desc "Stellaris Evaluation Board A"
-ft2232_layout evb_lm3s811
-ft2232_vid_pid 0x0403 0xbcd9
-
diff --git a/src/target/interface/olimex-arm-usb-ocd.cfg b/src/target/interface/olimex-arm-usb-ocd.cfg
deleted file mode 100644
index 76b6742c..00000000
--- a/src/target/interface/olimex-arm-usb-ocd.cfg
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# Olimex ARM-USB-OCD
-#
-# http://www.olimex.com/dev/arm-usb-ocd.html
-#
-
-interface ft2232
-ft2232_device_desc "Olimex OpenOCD JTAG A"
-ft2232_layout olimex-jtag
-ft2232_vid_pid 0x15ba 0x0003
-
diff --git a/src/target/interface/olimex-jtag-tiny.cfg b/src/target/interface/olimex-jtag-tiny.cfg
deleted file mode 100644
index 0ace5cb1..00000000
--- a/src/target/interface/olimex-jtag-tiny.cfg
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# Olimex ARM-USB-TINY
-#
-# http://www.olimex.com/dev/arm-usb-tiny.html
-#
-
-interface ft2232
-ft2232_device_desc "Olimex OpenOCD JTAG TINY A"
-ft2232_layout olimex-jtag
-ft2232_vid_pid 0x15ba 0x0004
-
diff --git a/src/target/interface/oocdlink.cfg b/src/target/interface/oocdlink.cfg
deleted file mode 100644
index 8ef8dbfa..00000000
--- a/src/target/interface/oocdlink.cfg
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# Joern Kaipf's OOCDLink
-#
-# http://www.joernonline.de/contrexx2/cms/index.php?page=126
-#
-
-interface ft2232
-ft2232_device_desc "OOCDLink A"
-ft2232_layout oocdlink
-ft2232_vid_pid 0x0403 0xbaf8
-jtag_khz 5
-
diff --git a/src/target/interface/openocd-usb.cfg b/src/target/interface/openocd-usb.cfg
deleted file mode 100644
index 0ef82ab2..00000000
--- a/src/target/interface/openocd-usb.cfg
+++ /dev/null
@@ -1,14 +0,0 @@
-#
-# Hubert Hoegl's USB to JTAG
-#
-# http://www.hs-augsburg.de/~hhoegl/proj/usbjtag/usbjtag.html
-#
-
-interface ft2232
-ft2232_vid_pid 0x0403 0x6010
-ft2232_device_desc "Dual RS232 A"
-ft2232_layout "oocdlink"
-ft2232_latency 2
-# 6/(1+n) Mhz TCLK
-jtag_speed 1
-
diff --git a/src/target/interface/parport.cfg b/src/target/interface/parport.cfg
deleted file mode 100644
index 6aaf80b7..00000000
--- a/src/target/interface/parport.cfg
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# Parallel port wiggler (many clones available) on port 0xc8b8
-#
-
-interface parport
-parport_port 0xc8b8
-parport_cable wiggler
-jtag_speed 0
-
diff --git a/src/target/interface/parport_dlc5.cfg b/src/target/interface/parport_dlc5.cfg
deleted file mode 100644
index defda3f3..00000000
--- a/src/target/interface/parport_dlc5.cfg
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# Xilinx Parallel Cable III 'DLC 5' (and various clones)
-#
-# http://www.xilinx.com/itp/xilinx4/data/docs/pac/appendixb.html
-#
-
-interface parport
-parport_port /dev/parport0
-parport_cable dlc5
-jtag_speed 0
-
diff --git a/src/target/interface/rlink.cfg b/src/target/interface/rlink.cfg
deleted file mode 100644
index 2f13cc48..00000000
--- a/src/target/interface/rlink.cfg
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# Raisonance RLink
-#
-# http://www.mcu-raisonance.com/~rlink-debugger-programmer__microcontrollers__tool~tool__T018:4cn9ziz4bnx6.html
-#
-
-interface rlink
-
diff --git a/src/target/interface/sheevaplug.cfg b/src/target/interface/sheevaplug.cfg
deleted file mode 100644
index 556f44d5..00000000
--- a/src/target/interface/sheevaplug.cfg
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# Marvel SheevaPlug Development Kit
-#
-# http://www.marvell.com/products/embedded_processors/developer/kirkwood/sheevaplug.jsp
-#
-
-interface ft2232
-ft2232_layout sheevaplug
-ft2232_vid_pid 0x9e88 0x9e8f
-ft2232_device_desc "SheevaPlug JTAGKey FT2232D B"
-jtag_khz 2000
-
diff --git a/src/target/interface/signalyzer.cfg b/src/target/interface/signalyzer.cfg
deleted file mode 100644
index 2c917d23..00000000
--- a/src/target/interface/signalyzer.cfg
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# Xverve Signalyzer Tool (DT-USB-ST)
-#
-# http://www.signalyzer.com/products/development-tools/signalyzer-tool-dt-usb-st.html
-#
-
-interface ft2232
-ft2232_device_desc "Signalyzer A"
-ft2232_layout signalyzer
-ft2232_vid_pid 0x0403 0xbca0
-
diff --git a/src/target/interface/stm32-stick.cfg b/src/target/interface/stm32-stick.cfg
deleted file mode 100644
index 89bcf674..00000000
--- a/src/target/interface/stm32-stick.cfg
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# Hitex STM32-PerformanceStick
-#
-# http://www.hitex.com/index.php?id=340
-#
-
-interface ft2232
-ft2232_device_desc "STM32-PerformanceStick A"
-ft2232_layout stm32stick
-ft2232_vid_pid 0x0640 0x002d
-
diff --git a/src/target/interface/turtelizer2.cfg b/src/target/interface/turtelizer2.cfg
deleted file mode 100644
index 31c34ff5..00000000
--- a/src/target/interface/turtelizer2.cfg
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# egnite Turtelizer 2
-#
-# http://www.ethernut.de/en/hardware/turtelizer/index.html
-#
-
-interface ft2232
-ft2232_device_desc "Turtelizer JTAG/RS232 Adapter A"
-ft2232_layout turtelizer2
-ft2232_vid_pid 0x0403 0xbdc8
-
diff --git a/src/target/interface/usbprog.cfg b/src/target/interface/usbprog.cfg
deleted file mode 100644
index 269ea944..00000000
--- a/src/target/interface/usbprog.cfg
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# Embedded Projects USBprog
-#
-# http://embedded-projects.net/index.php?page_id=135
-#
-
-interface usbprog
-
diff --git a/src/target/interface/vsllink.cfg b/src/target/interface/vsllink.cfg
deleted file mode 100644
index 7c9de7fe..00000000
--- a/src/target/interface/vsllink.cfg
+++ /dev/null
@@ -1,25 +0,0 @@
-#
-# Versaloon Link -- VSLLink
-#
-# http://www.simonqian.com/en/Versaloon
-#
-
-interface vsllink
-
-#vsllink_usb_vid 0x03EB
-#vsllink_usb_pid 0x2103
-#vsllink_usb_bulkin 0x02
-#vsllink_usb_bulkout 0x02
-#vsllink_usb_interface 0
-
-vsllink_usb_vid 0x0483
-vsllink_usb_pid 0x5740
-vsllink_usb_bulkin 0x02
-vsllink_usb_bulkout 0x03
-vsllink_usb_interface 1
-
-# vsllink mode, dma or normal
-# for low jtag_khz, use normal
-# for high jtag_khz, use dma
-#vsllink_mode dma
-vsllink_mode normal
diff --git a/src/target/target/aduc702x.cfg b/src/target/target/aduc702x.cfg
deleted file mode 100644
index ef1beb78..00000000
--- a/src/target/target/aduc702x.cfg
+++ /dev/null
@@ -1,61 +0,0 @@
-## -*- tcl -*-
-##
-
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME s3c2410
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- # This config file was defaulting to big endian..
- set _ENDIAN little
-}
-
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0xffffffff
-}
-
-
-jtag_nsrst_delay 200
-jtag_ntrst_delay 200
-
-# This is for the case that TRST/SRST is not wired on your JTAG adaptor.
-# Don't really need them anyways.
-reset_config none
-
-## JTAG scan chain
-#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-##
-## Target configuration
-##
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
-target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME
-
-# allocate the entire SRAM as working area
-$_TARGETNAME configure -work-area-phys 0x10000 -work-area-size 0x2000
-
-## flash configuration
-# only target number is needed
-flash bank aduc702x 0 0 0 0 0
-
-## If you use the watchdog, the following code makes sure that the board
-## doesn't reboot when halted via JTAG. Yes, on the older generation
-## AdUC702x, timer3 continues running even when the CPU is halted.
-
-proc watchdog_service {} {
- global watchdog_hdl
- mww 0xffff036c 0
-# puts "watchdog!!"
- set watchdog_hdl [after 500 watchdog_service]
-}
-
-$_TARGETNAME configure -event reset-halt-post { watchdog_service }
-$_TARGETNAME configure -event old-pre_resume { global watchdog_hdl; after cancel $watchdog_hdl }
diff --git a/src/target/target/at91eb40a.cfg b/src/target/target/at91eb40a.cfg
deleted file mode 100644
index 39fbe095..00000000
--- a/src/target/target/at91eb40a.cfg
+++ /dev/null
@@ -1,61 +0,0 @@
-#Script for AT91EB40a
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME at91eb40a
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-if { [info exists CPUTAPID ] } {
- set _CPUTAPID $CPUTAPID
-} else {
- # force an error till we get a good number
- set _CPUTAPID 0x1f0f0f0f
-}
-
-
-#Atmel ties SRST & TRST together, at which point it makes
-#no sense to use TRST, but use TMS instead.
-#
-#The annoying thing with tying SRST & TRST together is that
-#there is no way to halt the CPU *before and during* the
-#SRST reset, which means that the CPU will run a number
-#of cycles before it can be halted(as much as milliseconds).
-reset_config srst_only srst_pulls_trst
-
-#jtag scan chain
-#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-#target configuration
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
-target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi-s_r4
-
-# speed up memory downloads
-arm7_9 fast_memory_access enable
-arm7_9 dcc_downloads enable
-
-#flash driver
-flash bank ecosflash 0x01000000 0x200000 2 2 0 ecos/at91eb40a.elf
-
-# required for usable performance. Used for lots of
-# other things than flash programming.
-$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x00030000 -work-area-size 0x10000 -work-area-backup 0
-
-$_TARGETNAME configure -event reset-init {
- puts "Running reset init script for AT91EB40A"
- # Reset script for AT91EB40a
- reg cpsr 0x000000D3
- mww 0xFFE00020 0x1
- mww 0xFFE00024 0x00000000
- mww 0xFFE00000 0x01002539
- mww 0xFFFFF124 0xFFFFFFFF
- mww 0xffff0010 0x100
- mww 0xffff0034 0x100
-}
diff --git a/src/target/target/at91r40008.cfg b/src/target/target/at91r40008.cfg
deleted file mode 100644
index f8f5d410..00000000
--- a/src/target/target/at91r40008.cfg
+++ /dev/null
@@ -1,50 +0,0 @@
-
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME at9r40008
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-if { [info exists CPUTAPID ] } {
- set _CPUTAPID $CPUTAPID
-} else {
- # force an error till we get a good number
- set _CPUTAPID 0xffffffff
-}
-
-jtag_nsrst_delay 200
-jtag_ntrst_delay 200
-
-#use combined on interfaces or targets that can't set TRST/SRST separately
-reset_config srst_only srst_pulls_trst
-
-#jtag scan chain
-#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
-target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi
-
-
-$_TARGETNAME configure -event gdb-flash-erase-start {
- wait_halt
- sleep 10
- poll
- # Ethernut 3 remapping is required to access external flash memory.
- mww 0xffe00000 0x1000213d
- mww 0xffe00004 0x20003e3d
- mww 0xffe00020 0x00000001
-}
-
-$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x3C000 -work-area-size 0x4000 -work-area-backup 0
-
-flash bank cfi 0x10000000 0x400000 2 2 0
-
-# For more information about the configuration files, take a look at:
-# openocd.texi
diff --git a/src/target/target/at91rm9200.cfg b/src/target/target/at91rm9200.cfg
deleted file mode 100644
index 58c7318e..00000000
--- a/src/target/target/at91rm9200.cfg
+++ /dev/null
@@ -1,51 +0,0 @@
-
-reset_config trst_and_srst
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME at91rm9200
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-if { [info exists CPUTAPID ] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x05b0203f
-}
-
-# Never allow the following!
-if { $_CPUTAPID == 0x15b0203f } {
- puts "-------------------------------------------------------"
- puts "- ERROR: -"
- puts "- ERROR: TapID 0x15b0203f is wrong for at91rm9200 -"
- puts "- ERROR: The chip/board has a JTAG select pin/jumper -"
- puts "- ERROR: -"
- puts "- ERROR: In one position (0x05b0203f) it selects the -"
- puts "- ERROR: ARM CPU, in the other position (0x1b0203f) -"
- puts "- ERROR: it selects boundry-scan not the ARM -"
- puts "- ERROR: -"
- puts "-------------------------------------------------------"
-}
-
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-
-# Create the GDB Target.
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
-target create $_TARGETNAME arm920t -endian $_ENDIAN -chain-position $_TARGETNAME
-# AT91RM9200 has a 16K block of sram @ 0x0020.0000
-$_TARGETNAME configure -work-area-virt 0x00200000 -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 1
-
-# This chip has a DCC ... use it
-arm7_9 dcc_downloads enable
-
-
-
-
-
diff --git a/src/target/target/at91sam9260.cfg b/src/target/target/at91sam9260.cfg
deleted file mode 100644
index 4d51831d..00000000
--- a/src/target/target/at91sam9260.cfg
+++ /dev/null
@@ -1,42 +0,0 @@
-######################################
-# Target: Atmel AT91SAM9260
-######################################
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME at91sam9260
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-if { [info exists CPUTAPID ] } {
- set _CPUTAPID $CPUTAPID
-} else {
- # force an error till we get a good number
- set _CPUTAPID 0x0792603f
-}
-
-reset_config trst_and_srst
-
-#
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-jtag_nsrst_delay 200
-jtag_ntrst_delay 200
-
-######################
-# Target configuration
-######################
-
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
-target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm926ejs
-
-# Internal sram1 memory
-$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x00300000 -work-area-size 0x1000 -work-area-backup 1
-
-
diff --git a/src/target/target/at91sam9260_ext_RAM_ext_flash.cfg b/src/target/target/at91sam9260_ext_RAM_ext_flash.cfg
deleted file mode 100644
index f10a021c..00000000
--- a/src/target/target/at91sam9260_ext_RAM_ext_flash.cfg
+++ /dev/null
@@ -1,127 +0,0 @@
-
-
-
-jtag_khz 4
-
-
-######################################
-# Target: Atmel AT91SAM9260
-######################################
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME at91sam9260
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-if { [info exists CPUTAPID ] } {
- set _CPUTAPID $CPUTAPID
-} else {
- # force an error till we get a good number
- set _CPUTAPID 0x0792603f
-}
-
-reset_config trst_and_srst
-
-
-jtag_nsrst_delay 200
-jtag_ntrst_delay 200
-
-
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-
-######################
-# Target configuration
-######################
-
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
-target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm926ejs
-
-$_TARGETNAME invoke-event halted
-
-# Internal sram1 memory
-$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x00300000 -work-area-size 0x1000 -work-area-backup 1
-
-scan_chain
-$_TARGETNAME configure -event reset-deassert-post {at91sam_init}
-
-
-# Flash configuration
-#flash bank cfi <base> <size> <chip width> <bus width> <target#>
-flash bank cfi 0x10000000 0x01000000 2 2 $_TARGETNAME
-
-
-proc at91sam_init { } {
-
- # at reset chip runs at 32khz
- jtag_khz 8
- halt
- mww 0xfffffd08 0xa5000501 # RSTC_MR : enable user reset
- mww 0xfffffd44 0x00008000 # WDT_MR : disable watchdog
-
- mww 0xfffffc20 0x00004001 # CKGR_MOR : enable the main oscillator
- sleep 20 # wait 20 ms
- mww 0xfffffc30 0x00000001 # PMC_MCKR : switch to main oscillator
- sleep 10 # wait 10 ms
- mww 0xfffffc28 0x2060bf09 # CKGR_PLLAR: Set PLLA Register for 198,656MHz
- sleep 20 # wait 20 ms
- mww 0xfffffc30 0x00000101 # PMC_MCKR : Select prescaler
- sleep 10 # wait 10 ms
- mww 0xfffffc30 0x00000102 # PMC_MCKR : Clock from PLLA is selected
- sleep 10 # wait 10 ms
-
- # Now run at anything fast... ie: 10mhz!
- jtag_khz 10000 # Increase JTAG Speed to 6 MHz
- arm7_9 dcc_downloads enable # Enable faster DCC downloads
-
- mww 0xffffec00 0x0a0a0a0a # SMC_SETUP0 : Setup SMC for Intel NOR Flash JS28F128P30T85 128MBit
- mww 0xffffec04 0x0b0b0b0b # SMC_PULSE0
- mww 0xffffec08 0x00160016 # SMC_CYCLE0
- mww 0xffffec0c 0x00161003 # SMC_MODE0
-
- flash probe 0 # Identify flash bank 0
-
- mww 0xfffff870 0xffff0000 # PIO_ASR : Select peripheral function for D15..D31
- mww 0xfffff804 0xffff0000 # PIO_PDR : Disable PIO function for D15..D31
-
- mww 0xffffef1c 0x2 # EBI_CSA : Assign EBI Chip Select 1 to SDRAM
-
- mww 0xffffea08 0x85227259 # SDRAMC_CR : Configure SDRAM (2 x Samsung K4S561632H-UC75 : 4M x 16Bit x 4 Banks)
- #mww 0xffffea08 0x85227254 # SDRAMC_CR : Configure SDRAM (2 x Samsung K4S641632H-UC75 : 1M x 16Bit x 4 Banks)
-
- mww 0xffffea00 0x1 # SDRAMC_MR : issue a NOP command
- mww 0x20000000 0
- mww 0xffffea00 0x2 # SDRAMC_MR : issue an 'All Banks Precharge' command
- mww 0x20000000 0
- mww 0xffffea00 0x4 # SDRAMC_MR : issue 8 x 'Auto-Refresh' Command
- mww 0x20000000 0
- mww 0xffffea00 0x4
- mww 0x20000000 0
- mww 0xffffea00 0x4
- mww 0x20000000 0
- mww 0xffffea00 0x4
- mww 0x20000000 0
- mww 0xffffea00 0x4
- mww 0x20000000 0
- mww 0xffffea00 0x4
- mww 0x20000000 0
- mww 0xffffea00 0x4
- mww 0x20000000 0
- mww 0xffffea00 0x4
- mww 0x20000000 0
- mww 0xffffea00 0x3 # SDRAMC_MR : issue a 'Load Mode Register' command
- mww 0x20000000 0
- mww 0xffffea00 0x0 # SDRAMC_MR : normal mode
- mww 0x20000000 0
- mww 0xffffea04 0x5d2 # SDRAMC_TR : Set refresh timer count to 15us
-}
-
-
-
diff --git a/src/target/target/davinci.cfg b/src/target/target/davinci.cfg
deleted file mode 100644
index 0a3da27d..00000000
--- a/src/target/target/davinci.cfg
+++ /dev/null
@@ -1,170 +0,0 @@
-#
-# Utility code for DaVinci-family chips
-#
-
-# davinci_pinmux: assigns PINMUX$reg <== $value
-proc davinci_pinmux {soc reg value} {
- mww [expr [dict get $soc sysbase] + 4 * $reg] $value
-}
-
-# mrw: "memory read word", returns value of $reg
-proc mrw {reg} {
- set value ""
- ocd_mem2array value 32 $reg 1
- return $value(0)
-}
-
-# mmw: "memory modify word", updates value of $reg
-# $reg <== ((value & ~$clearbits) | $setbits)
-proc mmw {reg setbits clearbits} {
- set old [mrw $reg]
- set new [expr ($old & ~$clearbits) | $setbits]
- mww $reg $new
-}
-
-#
-# pll_setup: initialize PLL
-# - pll_addr ... physical addr of controller
-# - mult ... pll multiplier
-# - config ... dict mapping { prediv, postdiv, div[1-9] } to dividers
-#
-# For PLLs that don't have a given register (e.g. plldiv8), or where a
-# given divider is non-programmable, caller provides *NO* config mapping.
-#
-# REVISIT there are minor differences between the PLL controllers.
-# Handle those; maybe check the ID register. This version behaves
-# for at least the dm355. On dm6446 and dm357 the PLLRST polarity
-# is different. On dm365 there are more changes.
-#
-proc pll_setup {pll_addr mult config} {
- set pll_ctrl_addr [expr $pll_addr + 0x100]
- set pll_ctrl [mrw $pll_ctrl_addr]
-
- # 1 - clear CLKMODE (bit 8) iff using on-chip oscillator
- # NOTE: this assumes we should clear that bit
- set pll_ctrl [expr $pll_ctrl & ~0x0100]
- mww $pll_ctrl_addr $pll_ctrl
-
- # 2 - clear PLLENSRC (bit 5)
- set pll_ctrl [expr $pll_ctrl & ~0x0020]
- mww $pll_ctrl_addr $pll_ctrl
-
- # 3 - clear PLLEN (bit 0) ... enter bypass mode
- set pll_ctrl [expr $pll_ctrl & ~0x0001]
- mww $pll_ctrl_addr $pll_ctrl
-
- # 4 - wait at least 4 refclk cycles
- sleep 1
-
- # 5 - set PLLRST (bit 3)
- set pll_ctrl [expr $pll_ctrl | 0x0008]
- mww $pll_ctrl_addr $pll_ctrl
-
- # 6 - set PLLDIS (bit 4)
- set pll_ctrl [expr $pll_ctrl | 0x0010]
- mww $pll_ctrl_addr $pll_ctrl
-
- # 7 - clear PLLPWRDN (bit 1)
- set pll_ctrl [expr $pll_ctrl & ~0x0002]
- mww $pll_ctrl_addr $pll_ctrl
-
- # 8 - clear PLLDIS (bit 4)
- set pll_ctrl [expr $pll_ctrl & ~0x0010]
- mww $pll_ctrl_addr $pll_ctrl
-
- # 9 - optional: write prediv, postdiv, and pllm
- # NOTE: for dm355 PLL1, postdiv is controlled via MISC register
- mww [expr $pll_addr + 0x0110] [expr ($mult - 1) & 0xff]
- if { [dict exists $config prediv] } {
- set div [dict get $config prediv]
- set div [expr 0x8000 | ($div - 1)]
- mww [expr $pll_addr + 0x0114] $div
- }
- if { [dict exists $config postdiv] } {
- set div [dict get $config postdiv]
- set div [expr 0x8000 | ($div - 1)]
- mww [expr $pll_addr + 0x0128] $div
- }
-
- # 10 - optional: set plldiv1, plldiv2, ...
- # NOTE: this assumes some registers have their just-reset values:
- # - PLLSTAT.GOSTAT is clear when we enter
- # - ALNCTL has everything set
- set go 0
- if { [dict exists $config div1] } {
- set div [dict get $config div1]
- set div [expr 0x8000 | ($div - 1)]
- mww [expr $pll_addr + 0x0118] $div
- set go 1
- }
- if { [dict exists $config div2] } {
- 1et div [dict get $config div2]
- set div [expr 0x8000 | ($div - 1)]
- mww [expr $pll_addr + 0x011c] $div
- set go 1
- }
- if { [dict exists $config div3] } {
- set div [dict get $config div3]
- set div [expr 0x8000 | ($div - 1)]
- mww [expr $pll_addr + 0x011c] $div
- set go 1
- }
- if { [dict exists $config div4] } {
- set div [dict get $config div4]
- set div [expr 0x8000 | ($div - 1)]
- mww [expr $pll_addr + 0x0160] $div
- set go 1
- }
- if { [dict exists $config div5] } {
- set div [dict get $config div5]
- set div [expr 0x8000 | ($div - 1)]
- mww [expr $pll_addr + 0x0164] $div
- set go 1
- }
- if {$go != 0} {
- # write pllcmd.GO; poll pllstat.GO
- mww [expr $pll_addr + 0x0138] 0x01
- set pllstat [expr $pll_addr + 0x013c]
- while {[expr [mrw $pllstat] & 0x01] != 0} { sleep 1 }
- }
-
- # 11 - wait at least 5 usec for reset to finish
- # (assume covered by overheads including JTAG messaging)
-
- # 12 - clear PLLRST (bit 3)
- set pll_ctrl [expr $pll_ctrl & ~0x0008]
- mww $pll_ctrl_addr $pll_ctrl
-
- # 13 - wait at least 8000 refclk cycles for PLL to lock
- # if we assume 24 MHz (slowest osc), that's 1/3 msec
- sleep 3
-
- # 14 - set PLLEN (bit 0) ... leave bypass mode
- set pll_ctrl [expr $pll_ctrl | 0x0001]
- mww $pll_ctrl_addr $pll_ctrl
-}
-
-# NOTE: dm6446 requires EMURSTIE set in MDCTL before certain
-# modules can be enabled.
-
-# prepare a non-DSP module to be enabled; finish with psc_go
-proc psc_enable {module} {
- set psc_addr 0x01c41000
- # write MDCTL
- mmw [expr $psc_addr + 0x0a00 + (4 * $module)] 0x03 0x1f
-}
-
-# execute non-DSP PSC transition(s) set up by psc_enable
-proc psc_go {} {
- set psc_addr 0x01c41000
- set ptstat_addr [expr $psc_addr + 0x0128]
-
- # just in case PTSTAT.go isn't clear
- while { [expr [mrw $ptstat_addr] & 0x01] != 0 } { sleep 1 }
-
- # write PTCMD.go ... ignoring any DSP power domain
- mww [expr $psc_addr + 0x0120] 1
-
- # wait for PTSTAT.go to clear (again ignoring DSP power domain)
- while { [expr [mrw $ptstat_addr] & 0x01] != 0 } { sleep 1 }
-}
diff --git a/src/target/target/epc9301.cfg b/src/target/target/epc9301.cfg
deleted file mode 100644
index 6dbb91b3..00000000
--- a/src/target/target/epc9301.cfg
+++ /dev/null
@@ -1,31 +0,0 @@
-# Cirrus Logic EP9301 processor on an Olimex CS-E9301 board.
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME ep9301
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-if { [info exists CPUTAPID ] } {
- set _CPUTAPID $CPUTAPID
-} else {
- # force an error till we get a good number
- set _CPUTAPID 0xffffffff
-}
-
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-jtag_nsrst_delay 100
-jtag_ntrst_delay 100
-
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
-target create $_TARGETNAME arm920t -endian $_ENDIAN -chain-position $_TARGETNAME -work-area-virt 0 -work-area-phys 0x80014000 -work-area-size 0x1000 -work-area-backup 1
-
-#flash configuration
-#flash bank <driver> <base> <size> <chip_width> <bus_width> [driver_options ...]
-flash bank cfi 0x60000000 0x1000000 2 2 0
diff --git a/src/target/target/feroceon.cfg b/src/target/target/feroceon.cfg
deleted file mode 100644
index 552831a8..00000000
--- a/src/target/target/feroceon.cfg
+++ /dev/null
@@ -1,30 +0,0 @@
-######################################
-# Target: Marvell Feroceon CPU core
-######################################
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME feroceon
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-if { [info exists CPUTAPID ] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x20a023d3
-}
-
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
-target create $_TARGETNAME feroceon -endian $_ENDIAN -chain-position $_TARGETNAME
-
-reset_config trst_and_srst
-jtag_nsrst_delay 200
-jtag_ntrst_delay 200
-
diff --git a/src/target/target/imx21.cfg b/src/target/target/imx21.cfg
deleted file mode 100644
index fd2143e1..00000000
--- a/src/target/target/imx21.cfg
+++ /dev/null
@@ -1,32 +0,0 @@
-#use combined on interfaces or targets that can't set TRST/SRST separately
-reset_config trst_and_srst
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME imx21
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-
-# Note above there is 1 tap
-
-# The CPU tap
-if { [info exists CPUTAPID ] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x0792611f
-}
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-
-# Create the GDB Target.
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
-target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm926ejs
-
-arm7_9 dcc_downloads enable
diff --git a/src/target/target/imx27.cfg b/src/target/target/imx27.cfg
deleted file mode 100644
index 240a8498..00000000
--- a/src/target/target/imx27.cfg
+++ /dev/null
@@ -1,42 +0,0 @@
-#use combined on interfaces or targets that can't set TRST/SRST separately
-reset_config trst_and_srst
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME imx27
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-
-# Note above there are 2 taps
-
-# The bs tap
-if { [info exists BSTAPID ] } {
- set _BSTAPID $BSTAPID
-} else {
- set _BSTAPID 0x1b900f0f
-}
-jtag newtap $_CHIPNAME bs -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_BSTAPID
-
-# The CPU tap
-if { [info exists CPUTAPID ] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x07926121
-}
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-# Create the GDB Target.
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
-target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm926ejs
-$_TARGETNAME configure -work-area-virt 0xffff4c00 -work-area-phys 0xffff4c00 -work-area-size 0x8000 -work-area-backup 1
-# Internal to the chip, there is 45K of SRAM
-#
-
-arm7_9 dcc_downloads enable
diff --git a/src/target/target/imx31.cfg b/src/target/target/imx31.cfg
deleted file mode 100644
index 3fed2f82..00000000
--- a/src/target/target/imx31.cfg
+++ /dev/null
@@ -1,62 +0,0 @@
-# imx31 config
-#
-
-reset_config trst_and_srst
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME imx31
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-if { [info exists CPUTAPID ] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x07b3601d
-}
-
-if { [info exists SDMATAPID ] } {
- set _SDMATAPID $SDMATAPID
-} else {
- set _SDMATAPID 0x2190101d
-}
-
-#========================================
-# The "system jtag controller"
-# IMX31 reference manual, page 6-28 - figure 6-14
-if { [info exists SJCTAPID ] } {
- set _SJCTAPID $SJCTAPID
-} else {
- set _SJCTAPID 0x2b900f0f
-}
-jtag newtap $_CHIPNAME sjc -irlen 4 -ircapture 0x0 -irmask 0x0 -expected-id $_SJCTAPID
-
-# The "SDMA" - <S>mart <DMA> controller debug tap
-# Based on some IO pins - this can be disabled & removed
-# See diagram: 6-14
-# SIGNAL NAME:
-# SJC_MOD - controls multiplexer - disables ARM1136
-# SDMA_BYPASS - disables SDMA -
-#
-# Per ARM: DDI0211J_arm1136_r1p5_trm.pdf - the ARM 1136 as a 5 bit IR register
-jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUTAPID
-
-# No IDCODE for this TAP
-jtag newtap $_CHIPNAME whatchacallit -irlen 4 -ircapture 0 -irmask 0xf -expected-id 0x0
-
-# Per section 40.17.1, table 40-85 the IR register is 4 bits
-# But this conflicts with Diagram 6-13, "3bits ir and drs"
-jtag newtap $_CHIPNAME smda -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_SDMATAPID
-
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
-target create $_TARGETNAME arm11 -endian $_ENDIAN -chain-position $_TARGETNAME
-
-
-proc power_restore {} { puts "Sensed power restore. No action." }
-proc srst_deasserted {} { puts "Sensed nSRST deasserted. No action." }
diff --git a/src/target/target/imx35.cfg b/src/target/target/imx35.cfg
deleted file mode 100644
index d254c603..00000000
--- a/src/target/target/imx35.cfg
+++ /dev/null
@@ -1,50 +0,0 @@
-# imx35 config
-#
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME imx35
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-if { [info exists CPUTAPID ] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x07b3601d
-}
-
-if { [info exists SDMATAPID ] } {
- set _SDMATAPID $SDMATAPID
-} else {
- set _SDMATAPID 0x0882601d
-}
-
-#========================================
-# The "system jtag controller"
-# IMX31 reference manual, page 6-28 - figure 6-14
-if { [info exists SJCTAPID ] } {
- set _SJCTAPID $SJCTAPID
-} else {
- set _SJCTAPID 0x2b900f0f
-}
-
-jtag newtap $_CHIPNAME sjc -irlen 4 -ircapture 0x0 -irmask 0x0 -expected-id $_SJCTAPID
-
-jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUTAPID
-
-# No IDCODE for this TAP
-jtag newtap $_CHIPNAME whatchacallit -irlen 4 -ircapture 0 -irmask 0x0 -expected-id 0x0
-
-jtag newtap $_CHIPNAME smda -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_SDMATAPID
-
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
-target create $_TARGETNAME arm11 -endian $_ENDIAN -chain-position $_TARGETNAME
-
-proc power_restore {} { puts "Sensed power restore. No action." }
-proc srst_deasserted {} { puts "Sensed nSRST deasserted. No action." }
diff --git a/src/target/target/is5114.cfg b/src/target/target/is5114.cfg
deleted file mode 100644
index c28298c6..00000000
--- a/src/target/target/is5114.cfg
+++ /dev/null
@@ -1,49 +0,0 @@
-# script for Insilica IS-5114
-# AKA: Atmel AT76C114 - an ARM946 chip
-# ATMEL sold his product line to Insilica...
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME is5114
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- # this defaults to a little endian
- set _ENDIAN little
-}
-
-if { [info exists CPUTAPID ] } {
- set _CPUTAPID $CPUTAPID
-} else {
- # force an error till we get a good number
- set _CPUTAPID 0xffffffff
-}
-
-# jtag speed. We need to stick to 16kHz until we've finished reset.
-jtag_rclk 16
-
-reset_config trst_and_srst
-
-# Do not specify a tap id here...
-#OLD SYNTAX: jtag_device 8 0x1 0x1 0xfe
-jtag newtap $_CHIPNAME unknown1 -irlen 8 -ircapture 0x01 -irmask 1
-#OLD SYNTAX: jtag_device 4 0x1 0xf 0xe
-# This is the "arm946" chip.
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x0e -irmask 0xf
-#OLD SYNTAX: jtag_device 5 0x1 0x1 0x1e
-jtag newtap $_CHIPNAME unknown2 -irlen 5 -ircapture 1 -irmask 1
-
-
-#arm946e-s and
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
-target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm966e
-
-$_TARGETNAME configure -event reset-start { jtag_rclk 16 }
-$_TARGETNAME configure -event reset-init {
- # We can increase speed now that we know the target is halted.
- jtag_rclk 3000
-}
-$_TARGETNAME configure -work-area-phys 0x50000000 -work-area-virt 0x50000000 -work-area-size 16384 -work-area-backup 1
diff --git a/src/target/target/ixp42x.cfg b/src/target/target/ixp42x.cfg
deleted file mode 100644
index 12ace990..00000000
--- a/src/target/target/ixp42x.cfg
+++ /dev/null
@@ -1,32 +0,0 @@
-#xscale ixp42x CPU
-
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME ixp42x
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- # this defaults to a bigendian
- set _ENDIAN big
-}
-
-if { [info exists CPUTAPID ] } {
- set _CPUTAPID $CPUTAPID
-} else {
- # force an error till we get a good number
- set _CPUTAPID 0xffffffff
-}
-
-#use combined on interfaces or targets that can?t set TRST/SRST separately
-reset_config srst_only srst_pulls_trst
-#jtag scan chain
-
-jtag newtap $_CHIPNAME cpu -irlen 7 -ircapture 0x1 -irmask 0x7f -expected-id $_CPUTAPID
-
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
-target create $_TARGETNAME xscale -endian $_ENDIAN -chain-position $_TARGETNAME -variant ixp42x
-
diff --git a/src/target/target/lm3s3748.cfg b/src/target/target/lm3s3748.cfg
deleted file mode 100644
index 7321cb8a..00000000
--- a/src/target/target/lm3s3748.cfg
+++ /dev/null
@@ -1,49 +0,0 @@
-# Script for luminary lm3s3748
-#
-# NB! work in progress! Duplicated from lm3s811.cfg, but does
-# it need modification??
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME lm3s3748
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- # this defaults to a little endian
- set _ENDIAN little
-}
-
-if { [info exists CPUTAPID ] } {
- set _CPUTAPID $CPUTAPID
-} else {
- # force an error till we get a good number
- set _CPUTAPID 0x3ba00477
-}
-
-# RCLK
-jtag_khz 500
-
-jtag_nsrst_delay 100
-jtag_ntrst_delay 100
-
-#lm3s3748 Evaluation Board has only srst
-reset_config srst_only
-
-#jtag scan chain
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 1 -irmask 0xf -expected-id $_CPUTAPID
-
-
-# the luminary variant causes a software reset rather than asserting SRST
-# this stops the debug registers from being cleared
-# this will be fixed in later revisions of silicon
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
-target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME -variant lm3s
-
-# 8k working area at base of ram
-$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x20000000 -work-area-size 0x2000 -work-area-backup 0
-
-#flash configuration
-flash bank stellaris 0 0 0 0 0
diff --git a/src/target/target/lm3s6965.cfg b/src/target/target/lm3s6965.cfg
deleted file mode 100644
index 27b104ff..00000000
--- a/src/target/target/lm3s6965.cfg
+++ /dev/null
@@ -1,46 +0,0 @@
-# script for luminary lm3s6965
-
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME lm3s6965
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- # this defaults to a little endian
- set _ENDIAN little
-}
-
-if { [info exists CPUTAPID ] } {
- set _CPUTAPID $CPUTAPID
-} else {
- # force an error till we get a good number
- set _CPUTAPID 0x3ba00477
-}
-
-# jtag speed
-jtag_khz 500
-
-jtag_nsrst_delay 100
-jtag_ntrst_delay 100
-
-#LM3S6965 Evaluation Board has only srst
-reset_config srst_only
-
-#jtag scan chain
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 1 -irmask 0xf -expected-id $_CPUTAPID
-
-# the luminary variant causes a software reset rather than asserting SRST
-# this stops the debug registers from being cleared
-# this will be fixed in later revisions of silicon
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
-target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME -variant lm3s
-
-# 4k working area at base of ram
-$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x20000000 -work-area-size 0x4000 -work-area-backup 0
-
-#flash configuration
-flash bank stellaris 0 0 0 0 0
diff --git a/src/target/target/lm3s811.cfg b/src/target/target/lm3s811.cfg
deleted file mode 100644
index 2fa914fa..00000000
--- a/src/target/target/lm3s811.cfg
+++ /dev/null
@@ -1,45 +0,0 @@
-# Script for luminary lm3s811
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME lm3s811
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- # this defaults to a little endian
- set _ENDIAN little
-}
-
-if { [info exists CPUTAPID ] } {
- set _CPUTAPID $CPUTAPID
-} else {
- # force an error till we get a good number
- set _CPUTAPID 0x3ba00477
-}
-
-# jtag speed
-jtag_khz 500
-
-jtag_nsrst_delay 100
-jtag_ntrst_delay 100
-
-#LM3S811 Evaluation Board has only srst
-reset_config srst_only
-
-#jtag scan chain
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 1 -irmask 0xf -expected-id $_CPUTAPID
-
-# the luminary variant causes a software reset rather than asserting SRST
-# this stops the debug registers from being cleared
-# this will be fixed in later revisions of silicon
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
-target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME -variant lm3s
-
-# 8k working area at base of ram
-$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x20000000 -work-area-size 0x2000 -work-area-backup 0
-
-#flash configuration
-flash bank stellaris 0 0 0 0 0
diff --git a/src/target/target/lpc2103.cfg b/src/target/target/lpc2103.cfg
deleted file mode 100644
index cccc16d7..00000000
--- a/src/target/target/lpc2103.cfg
+++ /dev/null
@@ -1,39 +0,0 @@
-# NXP LPC2103 ARM7TDMI-S with 32kB Flash and 8kB SRAM, clocked with 12MHz crystal
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME lpc2103
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-if { [info exists CPUTAPID ] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x4f1f0f0f
-}
-
-# LPC2000 -> SRST causes TRST
-reset_config trst_and_srst srst_pulls_trst
-
-# reset delays
-jtag_nsrst_delay 100
-jtag_ntrst_delay 100
-
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
-
-target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi-s_r4
-
-# 8kB of internal SRAM
-$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x40000000 -work-area-size 0x2000 -work-area-backup 0
-
-# 32kB of internal Flash, core clocked with 12MHz crystal
-# flash bank lpc2000 <base> <size> 0 0 <target#> <variant> <clock> [calc_checksum]
-flash bank lpc2000 0x0 0x8000 0 0 0 lpc2000_v2 12000 calc_checksum
diff --git a/src/target/target/lpc2124.cfg b/src/target/target/lpc2124.cfg
deleted file mode 100644
index 4cdbc02c..00000000
--- a/src/target/target/lpc2124.cfg
+++ /dev/null
@@ -1,42 +0,0 @@
-#LPC-2124 CPU
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME lpc2124
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-if { [info exists CPUTAPID ] } {
- set _CPUTAPID $CPUTAPID
-} else {
- # force an error till we get a good number
- set _CPUTAPID 0x4f1f0f0f
-}
-
-
-#use combined on interfaces or targets that can't set TRST/SRST separately
-reset_config trst_and_srst srst_pulls_trst
-
-# reset delays
-jtag_nsrst_delay 100
-jtag_ntrst_delay 100
-
-jtag_khz 1000
-
-#jtag scan chain
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
-target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi-s_r4
-
-$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x40000000 -work-area-size 0x4000 -work-area-backup 0
-
-
-#flash bank <driver> <base> <size> <chip_width> <bus_width>
-flash bank lpc2000 0x0 0x40000 0 0 0 lpc2000_v1 14745 calc_checksum
diff --git a/src/target/target/lpc2129.cfg b/src/target/target/lpc2129.cfg
deleted file mode 100644
index b224c044..00000000
--- a/src/target/target/lpc2129.cfg
+++ /dev/null
@@ -1,41 +0,0 @@
-#LPC-2129 CPU
-
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME lpc2129
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-if { [info exists CPUTAPID ] } {
- set _CPUTAPID $CPUTAPID
-} else {
- # force an error till we get a good number
- set _CPUTAPID 0xffffffff
-}
-
-
-#use combined on interfaces or targets that can't set TRST/SRST separately
-reset_config trst_and_srst srst_pulls_trst
-
-# reset delays
-jtag_nsrst_delay 100
-jtag_ntrst_delay 100
-
-#jtag scan chain
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
-target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi-s_r4
-
-$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x40000000 -work-area-size 0x4000 -work-area-backup 0
-
-#flash bank <driver> <base> <size> <chip_width> <bus_width>
-flash bank lpc2000 0x0 0x40000 0 0 0 lpc2000_v1 14765 calc_checksum
diff --git a/src/target/target/lpc2148.cfg b/src/target/target/lpc2148.cfg
deleted file mode 100644
index d367a8f5..00000000
--- a/src/target/target/lpc2148.cfg
+++ /dev/null
@@ -1,56 +0,0 @@
-# Use RCLK. If RCLK is not available fall back to 500kHz.
-#
-# Depending on cabling you might be able to eek this up to 2000kHz.
-jtag_rclk 500
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME lpc2148
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-if { [info exists CPUTAPID ] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x4f1f0f0f
-}
-
-jtag_nsrst_delay 200
-jtag_ntrst_delay 200
-
-# NOTE!!! LPCs need reset pulled while RTCK is low. 0 to activate
-# JTAG, power-on reset is not enough, i.e. you need to perform a
-# reset before being able to talk to the LPC2148, attach is not possible.
-
-reset_config trst_and_srst srst_pulls_trst
-
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
-
-target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi-s_r4
-
-$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x40000000 -work-area-size 0x4000 -work-area-backup 0
-
-$_TARGETNAME configure -event reset-init {
- # Force target into ARM state.
- soft_reset_halt
-
- # Do not remap 0x0000-0x0020 to anything but the flash (i.e. select
- # "User Flash Mode" where interrupt vectors are _not_ remapped,
- # and reside in flash instead).
- #
- # See section 7.1 on page 32 ("Memory Mapping control register") in
- # "UM10139: Volume 1: LPC214x User Manual", Rev. 02 -- 25 July 2006.
- # http://www.standardics.nxp.com/support/documents/microcontrollers/pdf/user.manual.lpc2141.lpc2142.lpc2144.lpc2146.lpc2148.pdf
- mwb 0xE01FC040 0x01
-}
-
-# flash bank lpc2000 <base> <size> 0 0 <target#> <variant> <clock> [calc_checksum]
-flash bank lpc2000 0x0 0x7d000 0 0 0 lpc2000_v2 14765 calc_checksum
diff --git a/src/target/target/lpc2294.cfg b/src/target/target/lpc2294.cfg
deleted file mode 100644
index c3746c1f..00000000
--- a/src/target/target/lpc2294.cfg
+++ /dev/null
@@ -1,38 +0,0 @@
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME lpc2294
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-if { [info exists CPUTAPID ] } {
- set _CPUTAPID $CPUTAPID
-} else {
- # force an error till we get a good number
- set _CPUTAPID 0xffffffff
-}
-
-jtag_nsrst_delay 200
-jtag_ntrst_delay 200
-
-#use combined on interfaces or targets that can't set TRST/SRST separately
-reset_config trst_and_srst srst_pulls_trst
-
-#jtag scan chain
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
-target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi-s_r4
-$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x40000000 -work-area-size 0x4000 -work-area-backup 0
-
-#flash configuration
-#flash bank lpc2000 <base> <size> 0 0 <target#> <variant>
-flash bank lpc2000 0x0 0x40000 0 0 0 lpc2000_v1 14765 calc_checksum
-
-# For more information about the configuration files, take a look at:
-# openocd.texi
diff --git a/src/target/target/lpc2378.cfg b/src/target/target/lpc2378.cfg
deleted file mode 100644
index 16232383..00000000
--- a/src/target/target/lpc2378.cfg
+++ /dev/null
@@ -1,49 +0,0 @@
-# NXP LPC2378 ARM7TDMI-S with 512kB Flash and 32kB Local On-Chip SRAM (58kB total), clocked with 4MHz internal RC oscillator
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME lpc2378
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-if { [info exists CPUTAPID ] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x4f1f0f0f
-}
-
-#delays on reset lines
-jtag_nsrst_delay 200
-jtag_ntrst_delay 200
-
-# LPC2000 -> SRST causes TRST
-reset_config trst_and_srst srst_pulls_trst
-
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
-target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi-s_r4
-
-# LPC2378 has 32kB of SRAM on its main system bus (so-called Local On-Chip SRAM)
-$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x40000000 -work-area-size 0x8000 -work-area-backup 0
-
-$_TARGETNAME configure -event reset-init {
- # Force target into ARM state
- soft_reset_halt
- #do not remap 0x0000-0x0020 to anything but the flash
- mwb 0xE01FC040 0x01
-}
-
-# LPC2378 has 512kB of FLASH, but upper 8kB are occupied by bootloader.
-# After reset the chip uses its internal 4MHz RC oscillator
-#flash bank lpc2000 <base> <size> 0 0 <target#> <variant>
-flash bank lpc2000 0x0 0x0007D000 0 0 0 lpc2000_v2 4000 calc_checksum
-
-# 4MHz / 6 = 666kHz, so use 500
-jtag_khz 500
diff --git a/src/target/target/lpc2478.cfg b/src/target/target/lpc2478.cfg
deleted file mode 100644
index 84675705..00000000
--- a/src/target/target/lpc2478.cfg
+++ /dev/null
@@ -1,35 +0,0 @@
-# Testing feeedback wanted!
-set _CHIPNAME lpc2478
-set _ENDIAN little
-set _CPUTAPID 0x4f1f0f0f
-
-# Use RCLK. If RCLK is not available fall back to 500kHz.
-#
-# Depending on cabling you might be able to eek this up to 2000kHz.
-jtag_rclk 500
-
-jtag_nsrst_delay 200
-jtag_ntrst_delay 200
-
-#use combined on interfaces or targets that can't set TRST/SRST separately
-reset_config trst_and_srst srst_pulls_trst
-
-
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
-target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi-s_r4
-$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x40000000 -work-area-size 0x4000 -work-area-backup 0
-
-
-$_TARGETNAME configure -event reset-init {
- # Force target into ARM state
- soft_reset_halt
- # FIX!!!! should we remap the range below??? Is this applicable to
- # Copied from LPC2148.
- #do not remap 0x0000-0x0020 to anything but the flash
- mwb 0xE01FC040 0x01
-}
-
-
-flash bank lpc2000 0x0 0x7D000 0 0 0 lpc2000_v2 12000 calc_checksum
diff --git a/src/target/target/mega128.cfg b/src/target/target/mega128.cfg
deleted file mode 100644
index 964542c9..00000000
--- a/src/target/target/mega128.cfg
+++ /dev/null
@@ -1,42 +0,0 @@
-# for avr
-
- set _CHIPNAME avr
- set _ENDIAN little
-
-# jtag speed
-jtag_khz 4500
-
-reset_config srst_only
-jtag_nsrst_delay 100
-
-#jtag scan chain
-if { [info exists CPUTAPID ] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x8970203F
-}
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
-target create $_TARGETNAME avr -endian $_ENDIAN -chain-position $_TARGETNAME
-
-#$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x20000000 -work-area-size 16384 -work-area-backup 0
-
-flash bank avr 0 0 0 0 0
-
-#to use it, script will be like:
-#init
-#jtag_khz 4500
-#reset init
-#verify_ircapture disable
-#
-#halt
-#wait halt
-#poll
-#avr mass_erase 0
-#flash write_image E:/Versaloon/Software/CAMERAPROTOCOLAGENT.hex
-#reset run
-#shutdown
-#
-# For more information about the configuration files, take a look at:
-# openocd.texi
diff --git a/src/target/target/netx500.cfg b/src/target/target/netx500.cfg
deleted file mode 100644
index c639017b..00000000
--- a/src/target/target/netx500.cfg
+++ /dev/null
@@ -1,34 +0,0 @@
-#Hilscher netX 500 CPU
-
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME netx500
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-if { [info exists CPUTAPID ] } {
- set _CPUTAPID $CPUTAPID
-} else {
- # force an error till we get a good number
- set _CPUTAPID 0xffffffff
-}
-
-
-#use combined on interfaces or targets that can't set TRST/SRST separately
-reset_config trst_and_srst
-#jtag scan chain
-#
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-jtag_nsrst_delay 100
-jtag_ntrst_delay 100
-
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
-target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm926ejs
-
diff --git a/src/target/target/omap3530.cfg b/src/target/target/omap3530.cfg
deleted file mode 100644
index ad8f8ea8..00000000
--- a/src/target/target/omap3530.cfg
+++ /dev/null
@@ -1,57 +0,0 @@
-#File omap3530.cfg - as found on the BEAGLEBOARD
-# Assumption is it is generic for all OMAP3530
-
-#TI OMAP3 processor - http://www.ti.com
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME omap3
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- # this defaults to a little endianness
- set _ENDIAN little
-}
-
-if { [info exists CPUTAPID ] } {
- set _CPUTAPID $CPUTAPID
-} else {
- # force an error till we get a good number
- set _CPUTAPID 0x0B6D602F
-}
-
-#jtag scan chain
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0x0 -expected-id $_CPUTAPID -disable
-jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0xf -expected-id 0x0b7ae02f
-
-target create omap3.cpu cortex_m3 -endian little -chain-position omap3.cpu
-
-jtag configure $_CHIPNAME.cpu -event tap-enable {
- puts "Enabling Cortex-A8 @ OMAP3"
- irscan omap3.jrc 7 -endstate IRPAUSE
- drscan omap3.jrc 8 0x89 -endstate DRPAUSE
- irscan omap3.jrc 2 -endstate IRPAUSE
- drscan omap3.jrc 32 0xa3002108 -endstate RUN/IDLE
- irscan omap3.jrc 0x3F -endstate RUN/IDLE
- runtest 10
- puts "Cortex-A8 @ OMAP3 enabled"
-}
-
-proc omap3_dbginit { } {
- version
- jtag tapenable omap3.cpu
- targets
- # sleep 1000
- # dap apsel 1
- # sleep 1000
- # dap apsel 1
- # dap info 1
- omap3.cpu mww 0x54011FB0 0xC5ACCE55 4
- omap3.cpu mdw 0x54011314
- omap3.cpu mdw 0x54011314
- # omap3.cpu mdw 0x54011080
- omap3.cpu mww 0x5401d030 0x00002000 4
-}
diff --git a/src/target/target/omap5912.cfg b/src/target/target/omap5912.cfg
deleted file mode 100644
index 2942ad74..00000000
--- a/src/target/target/omap5912.cfg
+++ /dev/null
@@ -1,63 +0,0 @@
-#TI OMAP5912 dual core processor - http://www.ti.com
-#on a OMAP5912 OSK board http://www.spectrumdigital.com.
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME omap5912
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- # this defaults to a bigendian
- set _ENDIAN little
-}
-
-if { [info exists CPUTAPID ] } {
- set _CPUTAPID $CPUTAPID
-} else {
- # force an error till we get a good number
- set _CPUTAPID 0xffffffff
-}
-
-#use combined on interfaces or targets that can't set TRST/SRST separately
-reset_config trst_and_srst
-
-#jtag scan chain
-jtag newtap $_CHIPNAME unknown1 -irlen 38 -ircapture 0x0 -irmask 0x0
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0x0 -expected-id $_CPUTAPID
-jtag newtap $_CHIPNAME unknown2 irlen 8 -ircapture 0x0 -irmask 0x0
-
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
-target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm926ejs
-
-$_TARGETNAME configure -event reset-init {
- #
- # halt target
- #
- poll
- sleep 1
- halt
- wait_halt
- #
- # disable wdt
- #
- mww 0xfffec808 0x000000f5
- mww 0xfffec808 0x000000a0
-
- mww 0xfffeb048 0x0000aaaa
- sleep 500
- mww 0xfffeb048 0x00005555
- sleep 500
- #
- # detect flash
- #
- flash probe 0
-}
-
-# omap5912 lcd frame buffer as working area
-$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x20000000 -work-area-size 0x3e800 -work-area-backup 0
-
-#flash bank <driver> <base> <size> <chip_width> <bus_width>
-flash bank cfi 0x00000000 0x1000000 2 2 0
diff --git a/src/target/target/pic32mx.cfg b/src/target/target/pic32mx.cfg
deleted file mode 100644
index 139f801f..00000000
--- a/src/target/target/pic32mx.cfg
+++ /dev/null
@@ -1,40 +0,0 @@
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME pic32mx
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-if { [info exists CPUTAPID ] } {
- set _CPUTAPID $CPUTAPID
-} else {
- # force an error till we get a good number
- set _CPUTAPID 0x30938053
-}
-
-jtag_nsrst_delay 100
-jtag_ntrst_delay 100
-
-#use combined on interfaces or targets that can't set TRST/SRST separately
-reset_config srst_only
-
-#jtag scan chain
-#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
-jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUTAPID
-
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
-target create $_TARGETNAME mips_m4k -endian $_ENDIAN -chain-position $_TARGETNAME
-
-$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0xa0000000 -work-area-size 16384 -work-area-backup 0
-
-flash bank pic32mx 0xbd000000 0 0 0 0
-flash bank pic32mx 0xbfc00000 0 0 0 0
-
-# For more information about the configuration files, take a look at:
-# openocd.texi
diff --git a/src/target/target/pxa255.cfg b/src/target/target/pxa255.cfg
deleted file mode 100644
index c79ea4c9..00000000
--- a/src/target/target/pxa255.cfg
+++ /dev/null
@@ -1,104 +0,0 @@
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME pxa255
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-if { [info exists CPUTAPID ] } {
- set _CPUTAPID $CPUTAPID
-} else {
- # force an error till we get a good number
- set _CPUTAPID 0xffffffff
-}
-
-jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUTAPID
-
-jtag_nsrst_delay 200
-jtag_ntrst_delay 200
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
-target create $_TARGETNAME xscale -endian $_ENDIAN -chain-position $_TARGETNAME -variant pxa255
-$_TARGETNAME configure -event reset-init {
- xscale cp15 15 0x00002001 #Enable CP0 and CP13 access
- #
- # setup GPIO
- #
- mww 0x40E00018 0x00008000 #CPSR0
- sleep 20
- mww 0x40E0001C 0x00000002 #GPSR1
- sleep 20
- mww 0x40E00020 0x00000008 #GPSR2
- sleep 20
- mww 0x40E0000C 0x00008000 #GPDR0
- sleep 20
- mww 0x40E00054 0x80000000 #GAFR0_L
- sleep 20
- mww 0x40E00058 0x00188010 #GAFR0_H
- sleep 20
- mww 0x40E0005C 0x60908018 #GAFR1_L
- sleep 20
- mww 0x40E0000C 0x0280E000 #GPDR0
- sleep 20
- mww 0x40E00010 0x821C88B2 #GPDR1
- sleep 20
- mww 0x40E00014 0x000F03DB #GPDR2
- sleep 20
- mww 0x40E00000 0x000F03DB #GPLR0
- sleep 20
-
-
- mww 0x40F00004 0x00000020 #PSSR
- sleep 20
-
- #
- # setup memory controller
- #
- mww 0x48000008 0x01111998 #MSC0
- sleep 20
- mww 0x48000010 0x00047ff0 #MSC2
- sleep 20
- mww 0x48000014 0x00000000 #MECR
- sleep 20
- mww 0x48000028 0x00010504 #MCMEM0
- sleep 20
- mww 0x4800002C 0x00010504 #MCMEM1
- sleep 20
- mww 0x48000030 0x00010504 #MCATT0
- sleep 20
- mww 0x48000034 0x00010504 #MCATT1
- sleep 20
- mww 0x48000038 0x00004715 #MCIO0
- sleep 20
- mww 0x4800003C 0x00004715 #MCIO1
- sleep 20
- #
- mww 0x48000004 0x03CA4018 #MDREF
- sleep 20
- mww 0x48000004 0x004B4018 #MDREF
- sleep 20
- mww 0x48000004 0x000B4018 #MDREF
- sleep 20
- mww 0x48000004 0x000BC018 #MDREF
- sleep 20
- mww 0x48000000 0x00001AC8 #MDCNFG
- sleep 20
-
- sleep 20
-
- mww 0x48000000 0x00001AC9 #MDCNFG
- sleep 20
- mww 0x48000040 0x00000000 #MDMRS
- sleep 20
-}
-
-reset_config trst_and_srst
-
-
-
-#xscale debug_handler 0 0xFFFF0800 # debug handler base address
-
diff --git a/src/target/target/pxa270.cfg b/src/target/target/pxa270.cfg
deleted file mode 100644
index 34bb60d4..00000000
--- a/src/target/target/pxa270.cfg
+++ /dev/null
@@ -1,39 +0,0 @@
-#Marvell/Intel PXA270 Script
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME pxa270
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-#IDs for pxa270. Choose one. Are there others?#
-#set CPUTAPID 0x79265013
-#set CPUTAPID 0x49265013
-if { [info exists CPUTAPID ] } {
- set _CPUTAPID $CPUTAPID
-} else {
- # force an error till we get a good number
- set _CPUTAPID 0xffffffff
-}
-
-
-# set jtag_nsrst_delay to the delay introduced by your reset circuit
-# the rest of the needed delays are built into the openocd program
-jtag_nsrst_delay 260
-# set the jtag_ntrst_delay to the delay introduced by a reset circuit
-# the rest of the needed delays are built into the openocd program
-jtag_ntrst_delay 0
-
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
-jtag newtap $_CHIPNAME cpu -irlen 7 -ircapture 0x1 -irmask 0x7f -expected-id $_CPUTAPID
-
-target create $_TARGETNAME xscale -endian $_ENDIAN -chain-position $_TARGETNAME -variant pxa27x
-# maps to PXA internal RAM. If you are using a PXA255
-# you must initialize SDRAM or leave this option off
-$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x5c000000 -work-area-size 0x10000 -work-area-backup 0
diff --git a/src/target/target/readme.txt b/src/target/target/readme.txt
deleted file mode 100644
index ca23c64b..00000000
--- a/src/target/target/readme.txt
+++ /dev/null
@@ -1,41 +0,0 @@
-Prerequisites:
-The users of OpenOCD as well as computer programs interacting with OpenOCD are expecting that certain commands
-do the same thing across all the targets.
-
-Rules to follow when writing scripts:
-
-1. The configuration script should be defined such as , for example, the following sequences are working:
- reset
- flash info <bank>
-and
- reset
- flash erase_address <start> <len>
-and
- reset init
- load
-
-In most cases this can be accomplished by specifying the default startup mode as reset_init (target command
-in the configuration file).
-
-2. If the target is correctly configured, flash must be writable without any other helper commands. It is
-assumed that all write-protect mechanisms should be disabled.
-
-3. The configuration scripts should be defined such as the binary that was written to flash verifies
-(turn off remapping, checksums, etc...)
-
-flash write_image [file] <parameters>
-verify_image [file] <parameters>
-
-4. jtag_khz sets the maximum speed (or alternatively RCLK). If invoked
-multiple times only the last setting is used.
-
-interface/xxx.cfg files are always executed *before* target/xxx.cfg
-files, so any jtag_khz in interface/xxx.cfg will be overridden by
-target/xxx.cfg. jtag_khz in interface/xxx.cfg would then, effectively,
-set the default JTAG speed.
-
-Note that a target/xxx.cfg file can invoke another target/yyy.cfg file,
-so one can create target subtype configurations where e.g. only
-amount of DRAM, oscillator speeds differ and having a single
-config file for the default/common settings.
-
diff --git a/src/target/target/sam7se512.cfg b/src/target/target/sam7se512.cfg
deleted file mode 100644
index 6f0aa38c..00000000
--- a/src/target/target/sam7se512.cfg
+++ /dev/null
@@ -1,39 +0,0 @@
-
-# ATMEL sam7se512
-# Example: the "Elektor Internet Radio" - EIR
-# http://www.ethernut.de/en/hardware/eir/index.html
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME sam7se512
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-if { [info exists CPUTAPID ] } {
- set _CPUTAPID $CPUTAPID
-} else {
- # force an error till we get a good number
- set _CPUTAPID 0xffffffff
-}
-
-#use combined on interfaces or targets that can't set TRST/SRST separately
-reset_config srst_only srst_pulls_trst
-
-#jtag scan chain
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-# The target
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
-target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi
-
-$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 0
-
-#flash bank <driver> <base_addr> <size> <chip_width> <bus_width> <target_number> [<target_name> <banks> <sectors_per_bank> <pages_per_sector> <page_size> <num_nvmbits> <ext_freq_khz>]
-flash bank at91sam7 0 0 0 0 0 0 0 0 0 0 0 0 18432
-
diff --git a/src/target/target/sam7x256.cfg b/src/target/target/sam7x256.cfg
deleted file mode 100644
index 789f7dd6..00000000
--- a/src/target/target/sam7x256.cfg
+++ /dev/null
@@ -1,52 +0,0 @@
-#use combined on interfaces or targets that can't set TRST/SRST separately
-reset_config srst_only srst_pulls_trst
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME sam7x256
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-if { [info exists CPUTAPID ] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x3f0f0f0f
-}
-
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
-
-target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi
-$_TARGETNAME configure -event reset-init {
- # disable watchdog
- mww 0xfffffd44 0x00008000
- # enable user reset
- mww 0xfffffd08 0xa5000001
- # CKGR_MOR : enable the main oscillator
- mww 0xfffffc20 0x00000601
- sleep 10
- # CKGR_PLLR: 96.1097 MHz
- mww 0xfffffc2c 0x00481c0e
- sleep 10
- # PMC_MCKR : MCK = PLL / 2 ~= 48 MHz
- mww 0xfffffc30 0x00000007
- sleep 10
- # MC_FMR: flash mode (FWS=1,FMCN=60)
- mww 0xffffff60 0x003c0100
- sleep 100
-}
-
-$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 0
-
-#flash bank <driver> <base_addr> <size> <chip_width> <bus_width> <target_number> [<target_name> <banks> <sectors_per_bank> <pages_per_sector> <page_size> <num_nvmbits> <ext_freq_khz>]
-flash bank at91sam7 0 0 0 0 0 0 0 0 0 0 0 0 18432
-
-# For more information about the configuration files, take a look at:
-# openocd.texi
diff --git a/src/target/target/samsung_s3c2410.cfg b/src/target/target/samsung_s3c2410.cfg
deleted file mode 100644
index 3c0768bc..00000000
--- a/src/target/target/samsung_s3c2410.cfg
+++ /dev/null
@@ -1,35 +0,0 @@
-# Found on the 'TinCanTools' Hammer board.
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME s3c2410
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- # This config file was defaulting to big endian..
- set _ENDIAN little
-}
-
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0xffffffff
-}
-
-#use combined on interfaces or targets that cannot set TRST/SRST separately
-reset_config trst_and_srst
-
-#jtag scan chain
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
-target create $_TARGETNAME arm920t -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm920t
-
-$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x30800000 -work-area-size 0x20000 -work-area-backup 0
-
-# speed up memory downloads
-arm7_9 fast_memory_access enable
-arm7_9 dcc_downloads enable
diff --git a/src/target/target/samsung_s3c2440.cfg b/src/target/target/samsung_s3c2440.cfg
deleted file mode 100644
index 12bb4085..00000000
--- a/src/target/target/samsung_s3c2440.cfg
+++ /dev/null
@@ -1,35 +0,0 @@
-# Target configuration for the Samsung 2440 system on chip
-# Tested on a S3C2440 Evaluation board by keesj
-# Processor : ARM920Tid(wb) rev 0 (v4l)
-# Info: JTAG tap: s3c2440.cpu tap/device found: 0x0032409d (Manufacturer: 0x04e, Part: 0x0324, Version: 0x0)
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME s3c2440
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- # this defaults to a bigendian
- set _ENDIAN little
-}
-
-if { [info exists CPUTAPID ] } {
- set _CPUTAPID $CPUTAPID
-} else {
- # force an error till we get a good number
- set _CPUTAPID 0x0032409d
-}
-
-#jtag scan chain
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0x0f -expected-id $_CPUTAPID
-
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
-target create $_TARGETNAME arm920t -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm920t
-$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x200000 -work-area-size 0x4000 -work-area-backup 1
-
-#reset configuration
-reset_config trst_and_srst
-
diff --git a/src/target/target/samsung_s3c4510.cfg b/src/target/target/samsung_s3c4510.cfg
deleted file mode 100644
index 65e7fd84..00000000
--- a/src/target/target/samsung_s3c4510.cfg
+++ /dev/null
@@ -1,25 +0,0 @@
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME s3c4510
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-
-# This appears to be a "Version 1" arm7tdmi.
-if { [info exists CPUTAPID ] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x1f0f0f0f
-}
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
-target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME
-
diff --git a/src/target/target/samsung_s3c6410.cfg b/src/target/target/samsung_s3c6410.cfg
deleted file mode 100644
index 4991c811..00000000
--- a/src/target/target/samsung_s3c6410.cfg
+++ /dev/null
@@ -1,49 +0,0 @@
-# -*- tcl -*-
-# Target configuration for the Samsung s3c6410 system on chip
-# Tested on a SMDK6410
-# Processor : ARM1176
-# Info: JTAG device found: 0x0032409d (Manufacturer: 0x04e, Part: 0x0324, Version: 0x0)
-# [Duane Ellis 27/nov/2008: Above 0x0032409d appears to be copy/paste from other places]
-# [and I do not believe it to be accurate, hence the 0xffffffff below]
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME s3c6410
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- # this defaults to a bigendian
- set _ENDIAN little
-}
-
-if { [info exists BSTAPID ] } {
- set _BSTAPID $BSTAPID
-} else {
- # force an error till we get a good number
- set _BSTAPID 0x2b900f0f
-}
-
-if { [info exists CPUTAPID ] } {
- set _CPUTAPID $CPUTAPID
-} else {
- # force an error till we get a good number
- set _CPUTAPID 0x07b76f0f
-}
-
-#jtag scan chain
-
-# I think the "unknown" is the boundry scan tap
-jtag newtap $_CHIPNAME unknown -irlen 4 -ircapture 0x1 -irmask 0xe -expected-id $_BSTAPID
-jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUTAPID
-
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
-target create $_TARGETNAME arm11 -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm1176
-
-jtag_nsrst_delay 500
-jtag_ntrst_delay 500
-
-#reset configuration
-reset_config trst_and_srst
diff --git a/src/target/target/sharp_lh79532.cfg b/src/target/target/sharp_lh79532.cfg
deleted file mode 100644
index a239e3c5..00000000
--- a/src/target/target/sharp_lh79532.cfg
+++ /dev/null
@@ -1,26 +0,0 @@
-reset_config srst_only srst_pulls_trst
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME lh79532
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-if { [info exists CPUTAPID ] } {
- set _CPUTAPID $CPUTAPID
-} else {
- # sharp changed the number!
- set _CPUTAPID 0x00002061
-}
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
-target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME
-
-
diff --git a/src/target/target/smdk6410.cfg b/src/target/target/smdk6410.cfg
deleted file mode 100644
index 6ce07cae..00000000
--- a/src/target/target/smdk6410.cfg
+++ /dev/null
@@ -1,8 +0,0 @@
-# Target configuration for the Samsung s3c6410 system on chip
-# Tested on a SMDK6410
-# Processor : ARM1176
-# Info: JTAG device found: 0x0032409d (Manufacturer: 0x04e, Part: 0x0324, Version: 0x0)
-
-source [find target/samsung_s3c6410.cfg]
-
-flash bank cfi 0x00000000 0x00100000 2 2 0 jedec_probe \ No newline at end of file
diff --git a/src/target/target/smp8634.cfg b/src/target/target/smp8634.cfg
deleted file mode 100644
index c1d61882..00000000
--- a/src/target/target/smp8634.cfg
+++ /dev/null
@@ -1,32 +0,0 @@
-# script for Sigma Designs SMP8634 (eventually even SMP8635)
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME smp8634
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-if { [info exists CPUTAPID ] } {
- set _CPUTAPID $CPUTAPID
-} else {
- # force an error till we get a good number
- set _CPUTAPID 0x08630001
-}
-
-jtag_nsrst_delay 100
-jtag_ntrst_delay 100
-
-reset_config trst_and_srst separate
-
-# jtag scan chain
-# format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
-jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1
-
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
-target create $_TARGETNAME mips_m4k -endian $_ENDIAN -variant
diff --git a/src/target/target/stm32.cfg b/src/target/target/stm32.cfg
deleted file mode 100644
index 2fe17850..00000000
--- a/src/target/target/stm32.cfg
+++ /dev/null
@@ -1,58 +0,0 @@
-# script for stm32
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME stm32
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-# jtag speed
-jtag_khz 500
-
-jtag_nsrst_delay 100
-jtag_ntrst_delay 100
-
-#use combined on interfaces or targets that can't set TRST/SRST separately
-reset_config trst_and_srst
-
-#jtag scan chain
-if { [info exists CPUTAPID ] } {
- set _CPUTAPID $CPUTAPID
-} else {
- # See STM Document RM0008
- # Section 26.6.3
- set _CPUTAPID 0x3ba00477
-}
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-if { [info exists BSTAPID ] } {
- set _BSTAPID $BSTAPID
-} else {
- # See STM Document RM0008
- # Section 26.6.2
- # Low density devices, Rev A
- set _BSTAPID1 0x06412041
- # Medium density devices, Rev A
- set _BSTAPID2 0x06410041
- # Medium density devices, Rev B and Rev Z
- set _BSTAPID3 0x16410041
- # High density devices, Rev A
- set _BSTAPID4 0x06414041
-}
-jtag newtap $_CHIPNAME bs -irlen 5 -ircapture 0x1 -irmask 0x1 -expected-id $_BSTAPID1 -expected-id $_BSTAPID2 -expected-id $_BSTAPID3 -expected-id $_BSTAPID4
-
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
-target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
-
-$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x20000000 -work-area-size 16384 -work-area-backup 0
-
-flash bank stm32x 0 0 0 0 0
-
-# For more information about the configuration files, take a look at:
-# openocd.texi
diff --git a/src/target/target/str710.cfg b/src/target/target/str710.cfg
deleted file mode 100644
index 2d9d2fc4..00000000
--- a/src/target/target/str710.cfg
+++ /dev/null
@@ -1,45 +0,0 @@
-#start slow, speed up after reset
-jtag_khz 10
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME str710
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x3f0f0f0f
-}
-
-#use combined on interfaces or targets that can't set TRST/SRST separately
-reset_config trst_and_srst srst_pulls_trst
-
-#jtag scan chain
-
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0x0f -expected-id $_CPUTAPID
-
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
-target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi
-$_TARGETNAME configure -event reset-start { jtag_khz 10 }
-$_TARGETNAME configure -event reset-init { jtag_khz 6000 }
-$_TARGETNAME configure -event gdb-flash-erase-start {
- flash protect 0 0 7 off
- flash protect 1 0 1 off
-}
-
-$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x2000C000 -work-area-size 0x4000 -work-area-backup 0
-
-#flash bank str7x <base> <size> 0 0 <target#> <variant>
-flash bank str7x 0x40000000 0x00040000 0 0 0 STR71x
-flash bank str7x 0x400C0000 0x00004000 0 0 0 STR71x
-
-# For more information about the configuration files, take a look at:
-# openocd.texi
diff --git a/src/target/target/str730.cfg b/src/target/target/str730.cfg
deleted file mode 100644
index 5d01ec71..00000000
--- a/src/target/target/str730.cfg
+++ /dev/null
@@ -1,46 +0,0 @@
-#STR730 CPU
-
-jtag_khz 3000
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME str730
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x3f0f0f0f
-}
-
-#use combined on interfaces or targets that can't set TRST/SRST separately
-#reset_config trst_and_srst srst_pulls_trst
-reset_config trst_and_srst srst_pulls_trst
-
-#jtag scan chain
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0x0f -expected-id $_CPUTAPID
-
-#jtag nTRST and nSRST delay
-jtag_nsrst_delay 500
-jtag_ntrst_delay 500
-
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
-target create $_TARGETNAME arm7tdmi -endian little -chain-position 0 -variant arm7tdmi
-$_TARGETNAME configure -event reset-start { jtag_khz 10 }
-$_TARGETNAME configure -event reset-init { jtag_khz 3000 }
-$_TARGETNAME configure -event gdb-flash-erase-start {
- flash protect 0 0 7 off
-}
-
-$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x40000000 -work-area-size 0x4000 -work-area-backup 0
-
-#flash bank <driver> <base> <size> <chip_width> <bus_width>
-flash bank str7x 0x20000000 0x00040000 0 0 0 STR3x
-
diff --git a/src/target/target/str750.cfg b/src/target/target/str750.cfg
deleted file mode 100644
index 6b5e66c3..00000000
--- a/src/target/target/str750.cfg
+++ /dev/null
@@ -1,51 +0,0 @@
-#STR750 CPU
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME str750
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x4f1f0041
-}
-
-# jtag speed
-jtag_khz 10
-
-#use combined on interfaces or targets that can't set TRST/SRST separately
-#reset_config trst_and_srst srst_pulls_trst
-reset_config trst_and_srst srst_pulls_trst
-
-#jtag scan chain
-
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0x0f -expected-id $_CPUTAPID
-
-#jtag nTRST and nSRST delay
-jtag_nsrst_delay 500
-jtag_ntrst_delay 500
-
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
-target create $_TARGETNAME arm7tdmi -endian little -chain-position 0 -variant arm7tdmi
-
-$_TARGETNAME configure -event reset-start { jtag_khz 10 }
-$_TARGETNAME configure -event reset-init { jtag_khz 3000 }
-$_TARGETNAME configure -event gdb-flash-erase-start {
- flash protect 0 0 7 off
- flash protect 1 0 1 off
-}
-
-$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x40000000 -work-area-size 0x4000 -work-area-backup 0
-
-#flash bank <driver> <base> <size> <chip_width> <bus_width>
-flash bank str7x 0x20000000 0x00040000 0 0 0 STR75x
-flash bank str7x 0x200C0000 0x00004000 0 0 0 STR75x
-
diff --git a/src/target/target/str912.cfg b/src/target/target/str912.cfg
deleted file mode 100644
index 705326b5..00000000
--- a/src/target/target/str912.cfg
+++ /dev/null
@@ -1,70 +0,0 @@
-# script for str9
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME str912
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-# jtag speed. We need to stick to 16kHz until we've finished reset.
-jtag_rclk 16
-
-jtag_nsrst_delay 100
-jtag_ntrst_delay 100
-
-#use combined on interfaces or targets that can't set TRST/SRST separately
-reset_config trst_and_srst
-
-if { [info exists FLASHTAPID ] } {
- set _FLASHTAPID $FLASHTAPID
-} else {
- set _FLASHTAPID 0x04570041
-}
-jtag newtap $_CHIPNAME flash -irlen 8 -ircapture 0x1 -irmask 0x1 -expected-id $_FLASHTAPID
-
-if { [info exists CPUTAPID ] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x25966041
-}
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-
-if { [info exists BSTAPID ] } {
- set _BSTAPID $BSTAPID
-} else {
- set _BSTAPID 0x1457f041
-}
-jtag newtap $_CHIPNAME bs -irlen 5 -ircapture 0x1 -irmask 0x1 -expected-id $_BSTAPID
-
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
-target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm966e
-
-$_TARGETNAME configure -event reset-start { jtag_rclk 16 }
-
-$_TARGETNAME configure -event reset-init {
- # We can increase speed now that we know the target is halted.
- #jtag_rclk 3000
-
- # -- Enable 96K RAM
- # PFQBC enabled / DTCM & AHB wait-states disabled
- mww 0x5C002034 0x0191
-
- str9x flash_config 0 4 2 0 0x80000
- flash protect 0 0 7 off
-}
-
-$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x50000000 -work-area-size 16384 -work-area-backup 0
-
-#flash bank str9x <base> <size> 0 0 <target#> <variant>
-flash bank str9x 0x00000000 0x00080000 0 0 0
-flash bank str9x 0x00080000 0x00008000 0 0 0
-
-# For more information about the configuration files, take a look at:
-# openocd.texi
diff --git a/src/target/target/test_reset_syntax_error.cfg b/src/target/target/test_reset_syntax_error.cfg
deleted file mode 100644
index e573c1c0..00000000
--- a/src/target/target/test_reset_syntax_error.cfg
+++ /dev/null
@@ -1,17 +0,0 @@
-# Test script to check that syntax error in reset
-# script is reported properly.
-
-# at91eb40a target
-
-#jtag scan chain
-set _CHIPNAME syntaxtest
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf
-
-#target configuration
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
-target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi-s_r4
-
-$_TARGETNAME configure -event reset-init {
-
- syntax error
-}
diff --git a/src/target/target/test_syntax_error.cfg b/src/target/target/test_syntax_error.cfg
deleted file mode 100644
index 8727aa36..00000000
--- a/src/target/target/test_syntax_error.cfg
+++ /dev/null
@@ -1,4 +0,0 @@
-# This script tests a syntax error in the startup
-# config script
-
-syntax error here
diff --git a/src/target/target/ti_dm355.cfg b/src/target/target/ti_dm355.cfg
deleted file mode 100644
index 1bd5cda5..00000000
--- a/src/target/target/ti_dm355.cfg
+++ /dev/null
@@ -1,92 +0,0 @@
-#
-# Texas Instruments DaVinci family: TMS320DM355
-#
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME dm355
-}
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-#
-# For now, expect EMU0/EMU1 jumpered LOW (not TI's default) so ARM and ETB
-# are enabled without making ICEpick route ARM and ETB into the JTAG chain.
-#
-# Also note: when running without RTCK before the PLLs are set up, you
-# may need to slow the JTAG clock down quite a lot (under 2 MHz).
-#
-
-# Subsidiary TAP: ARM ETB11, with scan chain for 4K of ETM trace buffer
-if { [info exists ETB_TAPID ] } {
- set _ETB_TAPID $ETB_TAPID
-} else {
- set _ETB_TAPID 0x2b900f0f
-}
-jtag newtap $_CHIPNAME etb -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_ETB_TAPID
-
-# Subsidiary TAP: ARM926ejs with scan chains for ARM Debug, EmbeddedICE-RT, ETM.
-if { [info exists CPU_TAPID ] } {
- set _CPU_TAPID $CPU_TAPID
-} else {
- set _CPU_TAPID 0x07926001
-}
-jtag newtap $_CHIPNAME arm -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPU_TAPID
-
-# Primary TAP: ICEpick (JTAG route controller) and boundary scan
-if { [info exists JRC_TAPID ] } {
- set _JRC_TAPID $JRC_TAPID
-} else {
- set _JRC_TAPID 0x0b73b02f
-}
-jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f -expected-id $_JRC_TAPID
-
-################
-
-# various symbol definitions, to avoid hard-wiring addresses
-# and enable some sharing of DaVinci-family utility code
-global dm355
-set dm355 [ dict create ]
-
-# Physical addresses for controllers and memory
-# (Some of these are valid for many DaVinci family chips)
-dict set dm355 sram0 0x00010000
-dict set dm355 sram1 0x00014000
-dict set dm355 sysbase 0x01c40000
-dict set dm355 pllc1 0x01c40800
-dict set dm355 pllc2 0x01c40c00
-dict set dm355 psc 0x01c41000
-dict set dm355 gpio 0x01c67000
-dict set dm355 a_emif 0x01e10000
-dict set dm355 a_emif_cs0 0x02000000
-dict set dm355 a_emif_cs1 0x04000000
-dict set dm355 ddr_emif 0x20000000
-dict set dm355 ddr 0x80000000
-
-source [find target/davinci.cfg]
-
-################
-# GDB target: the ARM, using SRAM1 for scratch. SRAM0 (also 16K)
-# and the ETB memory (4K) are other options, while trace is unused.
-set _TARGETNAME $_CHIPNAME.arm
-
-target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME
-
-# NOTE that work-area-virt presumes a Linux 2.6.30-rc2+ kernel,
-# and that the work area is used only with a kernel mmu context ...
-$_TARGETNAME configure \
- -work-area-virt [expr 0xfffe0000 + 0x4000] \
- -work-area-phys [dict get $dm355 sram1] \
- -work-area-size 0x4000 \
- -work-area-backup 0
-
-arm7_9 dbgrq enable
-arm7_9 fast_memory_access enable
-arm7_9 dcc_downloads enable
-
-# trace setup
-etm config $_TARGETNAME 16 normal full etb
-etb config $_TARGETNAME $_CHIPNAME.etb
diff --git a/src/target/target/ti_dm6446.cfg b/src/target/target/ti_dm6446.cfg
deleted file mode 100644
index 68a7c207..00000000
--- a/src/target/target/ti_dm6446.cfg
+++ /dev/null
@@ -1,66 +0,0 @@
-#
-# Texas Instruments DaVinci family: TMS320DM6446
-#
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME dm6446
-}
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-#
-# For now, expect EMU0/EMU1 jumpered LOW (not TI's default) so ARM and ETB
-# are enabled without making ICEpick route ARM and ETB into the JTAG chain.
-#
-# Also note: when running without RTCK before the PLLs are set up, you
-# may need to slow the JTAG clock down quite a lot (under 2 MHz).
-#
-
-# Subsidiary TAP: ARM ETB11, with scan chain for 4K of ETM trace buffer
-if { [info exists ETB_TAPID ] } {
- set _ETB_TAPID $ETB_TAPID
-} else {
- set _ETB_TAPID 0x2b900f0f
-}
-jtag newtap $_CHIPNAME etb -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_ETB_TAPID
-
-# Subsidiary TAP: ARM926ejs with scan chains for ARM Debug, EmbeddedICE-RT, ETM.
-if { [info exists CPU_TAPID ] } {
- set _CPU_TAPID $CPU_TAPID
-} else {
- set _CPU_TAPID 0x07926001
-}
-jtag newtap $_CHIPNAME arm -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPU_TAPID
-
-# Subsidiary TAP: C64x+ DSP ... NOT CURRENTLY INCLUDED, must add via ICEpick.
-# Documentation for DSP JTAG interfaces evidently needs NDAs.
-
-# Primary TAP: ICEpick (JTAG route controller) and boundary scan
-if { [info exists JRC_TAPID ] } {
- set _JRC_TAPID $JRC_TAPID
-} else {
- set _JRC_TAPID 0x0b70002f
-}
-jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f -expected-id $_JRC_TAPID
-
-# GDB target: the ARM, using SRAM1 for scratch. SRAM0 (also 8K)
-# and the ETB memory (4K) are other options, while trace is unused.
-set _TARGETNAME $_CHIPNAME.arm
-
-target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME
-$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x0000a000 -work-area-size 0x2000 -work-area-backup 0
-
-arm7_9 dbgrq enable
-arm7_9 fast_memory_access enable
-arm7_9 dcc_downloads enable
-
-# trace setup
-# FIXME we ought to be able to say "... config $_TARGETNAME ..."
-# (not "config 0") facilitating additional targets (e.g. other chips)
-etm config 0 16 normal full etb
-etb config 0 $_CHIPNAME.etb
-
diff --git a/src/target/target/xba_revA3.cfg b/src/target/target/xba_revA3.cfg
deleted file mode 100644
index 007cb9e1..00000000
--- a/src/target/target/xba_revA3.cfg
+++ /dev/null
@@ -1,86 +0,0 @@
-#Written by: Michael Schwingen <rincewind@discworld.dascon.de>
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME xba_reva3
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- # default to big endian
- set _ENDIAN big
-}
-
-if { [info exists CPUTAPID ] } {
- set _CPUTAPID $CPUTAPID
-} else {
- # force an error till we get a good number
- set _CPUTAPID 0xffffffff
-}
-
-reset_config trst_and_srst separate
-
-jtag_nsrst_delay 100
-jtag_ntrst_delay 100
-
-#jtag scan chain
-jtag newtap $_CHIPNAME cpu -irlen 7 -ircapture 0x1 -irmask 0x7f -expected-id $_CPUTAPID
-
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
-target create $_TARGETNAME xscale -endian $_ENDIAN -chain-position $_TARGETNAME -variant ixp42x
-$_TARGETNAME configure -event reset-init {
- #############################################################################
- # setup expansion bus CS, disable external wdt
- #############################################################################
- mww 0xc4000000 0xbd113842 #CS0 : Flash, write enabled @0x50000000
- mww 0xc4000004 0x94d10013 #CS1
- mww 0xc4000008 0x95960003 #CS2
- mww 0xc400000c 0x00000000 #CS3
- mww 0xc4000010 0x80900003 #CS4
- mww 0xc4000014 0x9d520003 #CS5
- mww 0xc4000018 0x81860001 #CS6
- mww 0xc400001c 0x80900003 #CS7
-
- #############################################################################
- # init SDRAM controller: 16MB, one bank, CL3
- #############################################################################
- mww 0xCC000000 0x2A # SDRAM_CFG: 64MBit, CL3
- mww 0xCC000004 0 # disable refresh
- mww 0xCC000008 3 # NOP
- sleep 100
- mww 0xCC000004 2100 # set refresh counter
- mww 0xCC000008 2 # Precharge All Banks
- sleep 100
- mww 0xCC000008 4 # Auto Refresh
- mww 0xCC000008 4 # Auto Refresh
- mww 0xCC000008 4 # Auto Refresh
- mww 0xCC000008 4 # Auto Refresh
- mww 0xCC000008 4 # Auto Refresh
- mww 0xCC000008 4 # Auto Refresh
- mww 0xCC000008 4 # Auto Refresh
- mww 0xCC000008 4 # Auto Refresh
- mww 0xCC000008 1 # Mode Select CL3
-
- #mww 0xc4000020 0xffffee # CFG0: remove expansion bus boot flash
- #mirror at 0x00000000
-
- #big endian
- reg XSCALE_CTRL 0xF8
-
- #
- # detect flash
- #
- flash probe 0
-}
-
-$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x20010000 -work-area-size 0x8060 -work-area-backup 0
-
-
-flash bank cfi 0x50000000 0x400000 2 2 0
-
-init
-reset init
-# set big endian mode
-reg XSCALE_CTRL 0xF8
diff --git a/src/target/test/selftest.cfg b/src/target/test/selftest.cfg
deleted file mode 100644
index d1a00aed..00000000
--- a/src/target/test/selftest.cfg
+++ /dev/null
@@ -1,17 +0,0 @@
-
-add_help_text selftest "run selftest using working ram <tmpfile> <address> <size>"
-
-proc selftest {tmpfile address size} {
-
- for {set i 0} {$i < $size } {set i [expr $i+4]} {
- mww [expr $address+$i] $i
- }
-
- for {set i 0} {$i < 10 } {set i [expr $i+1]} {
- puts "Test iteration $i"
- dump_image $tmpfile $address $size
- verify_image $tmpfile $address bin
- load_image $tmpfile $address bin
- }
-
-} \ No newline at end of file
diff --git a/src/target/test/syntax1.cfg b/src/target/test/syntax1.cfg
deleted file mode 100644
index fb88d5ae..00000000
--- a/src/target/test/syntax1.cfg
+++ /dev/null
@@ -1,29 +0,0 @@
-jtag_nsrst_delay 200
-jtag_ntrst_delay 200
-
-#use combined on interfaces or targets that can't set TRST/SRST separately
-reset_config trst_and_srst srst_pulls_trst
-
-#LPCs need reset pulled while RTCK is low. 0 to activate JTAG, power-on reset is not enough
-jtag_reset 1 1
-jtag_reset 0 0
-
-#jtag scan chain
-#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
-jtag newtap lpc2148 one -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id 0x4f1f0f0f
-
-#target configuration
-#daemon_startup reset
-
-set _TARGETNAME [format "%s.cpu" lpc2148]
-target create lpc2148.cpu arm7tdmi -endian little -work-area-size 0x4000 -work-area-phys 0x40000000 -work-area-virt 0 -work-area-backup 0
-
-$_TARGETNAME configure -event reset-init {
-soft_reset_halt
-mvb 0xE01FC040 0x01
-}
-
-
-
-flash bank lpc2000 0x0 0x7d000 0 0 0 lpc2000_v2 14765
-