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* scripts: Phytec/LPC2350 config scriptsEthan Eade2010-02-042-0/+124
| | | | Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* AT91R40008/Ethernut 3 configurationHarald Kipp2010-02-022-32/+95
| | | | | | | | | | Moved board specific settings from target/at91r40008.cfg to a new file board/ethernut3.cfg. Set correct CPUTAPID. Reset delay increased, see MIC2775 data sheet. Increased work area size from 16k to 128k. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* tcl/str7x: Reset init unlocks the flashEdgar Grimberg2010-02-022-2/+17
| | | | | | | | | | | For STR7x flash, the device cannot be queried for the protect status. The solution is to remove the protection on reset init. The driver also initialises the sector protect field to unprotected. [dbrownell@users.sourceforge.net: line length shrinkage] Signed-off-by: Edgar Grimberg <edgar.grimberg@zylin.com> Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* flash/str7x: After reset init the flash is unlockedEdgar Grimberg2010-02-021-1/+9
| | | | | | | | | | | | | | The default state of the STR7 flash after a reset init is unlocked. The information in the flash driver now reflects this. The information about the lock status cannot be read from the flash chip, so the user is informed that flash info might not contain accurate information. [dbrownell@users.sourceforge.net: line length shrinkage] Signed-off-by: Edgar Grimberg <edgar.grimberg@zylin.com> Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* interface: Changed parport address to LPT1Edgar Grimberg2010-01-211-5/+3
| | | | | | Changed the parport address to LPT1, since it's the most obvious default value. Signed-off-by: Edgar Grimberg <edgar.grimberg@zylin.com>
* board configs -- unique names for flash chipsDavid Brownell2010-01-202-8/+6
| | | | | | | | Don't give the same names to both flash chips on two OMAP boards. For OSK, enable DCC downloads (removing a warning). Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* tcl/target/at91sam3u4e.cfg: changed case in dependent fileMichael Grzeschik2010-01-201-1/+1
| | | | | | | | openocd does not start with the target configfile due to the case in the dependent config file. Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de> Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* Added Openmoko USB JTAG interface config file.Vladimir Zapolskiy2010-01-111-0/+10
| | | | | | | | Added interface config file for JTAG/RS232 debug board originally integrated to Neo 1973 and Neo FreeRunner phones. Adapter was tested with i.MX31, S3C2410 and AT91SAM9260 processors. Signed-off-by: Vladimir Zapolskiy <vzapolskiy@gmail.com>
* parport (mostly) doc fixesDavid Brownell2010-01-091-0/+2
| | | | | | | | | | | | | | | | | | | The "parport_port" commands generally don't *require* a port_number; they're of the "apply any parameter, then print result" variety. Update the User's Guide accordingly. Some of those commands are intended to be write-once: parport_port, and parport_cable. Say so. Use proper EBNF for the parport_write_on_exit parameter. Parport address 0xc8b8 is evidently mutant. Say so in the "parport.cfg" file, to avoid breaking anyone with that mutant config. But update the User's Guide to include a sane example for the LP2 port. Finally document the "presto_serial" command. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* PIC32: enable ram executionSpencer Oliver2010-01-051-1/+17
| | | | | | add reset-init script to allow ram execution from reset, this is required for ejtag fastdata access. Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
* Added ST FlashLINK interface config file.Antonio Borneo2010-01-021-0/+10
| | | | | | | | The relevant cable config is already in OpenOCD, but not a config for the JTAG adapter. I have tested with FlashLINK on ARM926. Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* Fix parport_dcl5 config file.Antonio Borneo2009-12-301-1/+1
| | | | Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
* Added Open-BLDC board config file.Piotr Esden-Tempski2009-12-291-0/+7
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* Added floss-jtag interface config file.Piotr Esden-Tempski2009-12-291-0/+11
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* Fix Luminary FT2232 layout docs/configsDavid Brownell2009-12-284-6/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Most of this patch updates documentation and comments for various Luminary boards, supporting two bug fixes by helping to make sense of the current mess: - Recent rev C lm3s811 eval boards didn't work. They must use the ICDI layout, which sets up some signals that the older boards didn't need. This is actually safe and appropriate for *all* recent boards ... so just make "luminary.cfg" use the ICDI layout. - "luminary-lm3s811.cfg", was previously unusable! No VID/PID; and the wrong vendor string. Make it work, but reserve it for older boards where the ICDI layout is wrong. - Default the LM3748 eval board to "luminary.cfg", like the other boards. If someone uses an external JTAG adapter, all boards will use the same workaround (override that default). The difference between the two FT2232 layouts is that eventually the EVB layout will fail cleanly when asked to enable SWO trace, but the ICDI layout will as cleanly be able to enable it. Folk using "luminary.cfg" with Rev B boards won't see anything going wrong until SWO support is (someday) added. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* create tcl/board/dm365evm.cfgDavid Brownell2009-12-271-0/+147
| | | | | | | | | | | | | | | | This config is only lightly tested, and doesn't work well yet; but it's a start. * Notably missing is PLL configuration, since each DaVinci does that just a bit differently; and thus DDR2 setup. * The SRST workaround needed for the goof in the CPLD's VHDL depends on at least the not-yet-merged patch letting ARM9 (and ARM7) chips perform resets that don't use SRST. So this isn't yet suitable for debugging U-Boot. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* Driver for USB-JTAG, Altera USB-Blaster and compatiblesCatalin Patulea2009-12-262-0/+22
| | | | | | | The 10-pin JTAG layout used with these adapters is used by a variety of platforms including AVR. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* Olimex SAM9-L9260 board configuration update.Dean Glazeski2009-12-261-0/+52
| | | | | | | | This updates the board configuration for the SAM9-L9260 board with the configuration for the on-board NAND and dataflash. Included are commands for configuring the AT91SAM9 NAND flash driver. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* target.cfg: update to use new flash configuration syntaxSpencer Oliver2009-12-1711-15/+15
| | | | Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
* Remove duplicate Olimex-"tiny" interfaceDavid Brownell2009-12-161-10/+0
| | | | | We already have tcl/interface/olimex-jtag-tiny.cfg and don't need a clone of it.
* more tcl/{board,target} cleanupDavid Brownell2009-12-1512-23/+48
| | | | | | | | | | | | | | Remove more remnants of the old "jtag_device" syntax. Don't [format "%s.cpu" $_CHIPNAME] ... it's needless complexity. Remove various non-supported "-variant" target options; they're not needed often at all. Flag some of the board files as needing to have and use target files for the TAP and target declarations. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* testing/examples/.../*cfg: rm jtag_device callsDavid Brownell2009-12-151-3/+0
| | | | | | | That syntax has been obsolete forever and is now gone; remove a few remaining references. Shows how seldom this stuff gets used. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* target: add basic dsp563xx supportmkdorg@users.sourceforge.net2009-12-152-0/+48
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* imx31: move srst delay into config scriptØyvind Harboe2009-12-151-0/+2
| | | | | | reset init/run now works again. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* lm3748: use new Stellaris config fileDavid Brownell2009-12-142-33/+1
| | | | | | Use the new file, and remove the old target/lm3s3748.cfg one. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* Common target file for Stellaris chipsYegor Yefremov2009-12-141-0/+49
| | | | | | | | | Common target.cfg file for LM3S CPU family [dbrownell@users.sourceforge.net: rename, generalize more] Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com> Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* OMAP2420: define reset-assert eventDavid Brownell2009-12-071-0/+7
| | | | | | | | | Behave like OMAP3530: force global software reset. Given the patch to teach ARM11 how to use these events, and use VCR to catch the reset vector, this works better than either the current reset logic or than using SRST. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* Tcl and doc: update to match new 'arm mcr ...' etcDavid Brownell2009-12-016-11/+11
| | | | | | Make them match the C code. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* target: at91eb40a.cfg is a board, not a target.Øyvind Harboe2009-12-011-1/+4
| | | | | | | Also updated to use target name when creating flash and set jtag_khz to 16000. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* create target/pxa3xx.cfgMarek Vasut2009-11-291-0/+86
| | | | | | [dbrownell@users.sourceforge.net; remove pxa255 comment] Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* omap3530.cfg: use new "reset-assert" eventDavid Brownell2009-11-271-2/+2
| | | | | | Replaces previous "reset-assert-pre" workaround. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* omap3530.cfg: yes we have SRAM!David Brownell2009-11-251-0/+3
| | | | Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* arm926ejs: fix gaffe when converting from arm926ejs cp15 to mcrØyvind Harboe2009-11-233-3/+3
| | | | | | the first arg is the register number 15 = cp15. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* arm926ejs: retire cp15 commands, handled by mrc/mcr.Øyvind Harboe2009-11-233-3/+3
| | | | Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* target.cfg: TAP id for Hilscher netX 500David Brownell2009-11-201-9/+7
| | | | | | Based on email from "Martin Kaul <martin.kaul@leuze.de>". Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* update 'nand device' usage in scriptsZachary T Welch2009-11-193-4/+8
| | | | Add $_FLASHNAME variable to update 'nand device' command syntax.
* update 'flash bank' usage in scriptsZachary T Welch2009-11-1958-69/+138
| | | | | Sets $_FLASHNAME to "$_CHIPNAME.flash" and passes it as the first argument to 'flash bank'.
* ARM: "armv4_5" command prefix becomes "arm"David Brownell2009-11-165-5/+5
| | | | | | | | | | Rename the "armv4_5" command prefix to straight "arm" so it makes more sense for newer cores. Add a simple compatibility script. Make sure all the commands give the same "not an ARM" diagnostic message (and fail properly) when called against non-ARM targets. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM11: ETM + ETB supportDavid Brownell2009-11-134-4/+15
| | | | | | | | | | | Kick in ETM (and ETB) support for ARM11. Tested on OMAP 2420, so update that configuration. (That's an ARM1136ejs, ETB, OpenGL ES1.1, C55x DSP, etc.) Also update the other ARM11 ETM + ETB targets in the tree to set up these modules. (Not tested.) Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* iMX2* + ETB targets: hook up ETM and ETBDavid Brownell2009-11-132-1/+10
| | | | | | | ARM9 cores with an ETB will have a matching ETM. Hook them both up by default. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* target.cfg: label ETBs correctlyDavid Brownell2009-11-135-28/+26
| | | | | | | | | | | | | | | | | | Various cores with an ETB have its TAP misnamed ... either as a boundary scan TAP or as the iMX "Secure JTAG Controller" (which is, among other things, a JRC that could be used to shorten scan chains). Use the correct name for these TAPs, which we can recognize since their IDs were assigned by ARM and these chips all document the presence of an ETB. The 0x2b900f0f is ETB11; the 0x1b900f0f is an older module, just called "ETB". Also shrink the ETB's IR configuration; the default IR-Capture value is fine, and the mask can specify that all four bits are safe to check (per ARM documentation). Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* target.cfg: (re)move some bogus reset_config linesDavid Brownell2009-11-105-13/+3
| | | | | | | General rule, this is all board-specific and doesn't belong in target config files. Some of these were just cosmetic. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* stm32.cfg: remove reset_configThomas Kindler2009-11-101-3/+0
| | | | | | | | | | | | | | | Here's a patch for the double-reset problem on STM32. I've tested downloading and debugging with GDB and Eclipse, and everything seems to work fine. This effectively sets reset_config to none. trst_only would also be ok, but that's better left to a board configuration file since not all boards wire it up. The NVIC is used to trigger reset, which at least on this chip also pulses nSRST so the whole system does get rest -- exactly once. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM11: remove old mrc/mcr commandsØyvind Harboe2009-11-103-8/+8
| | | | | | Switch to new commands in config scripts Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* telo.cfg: fix search pathsØyvind Harboe2009-11-102-8/+8
| | | | | | | Add the missing "target/" prefix for scripts in the target folder. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* finish removing deprecated/obsolete commandsDavid Brownell2009-11-096-12/+2
| | | | | | | | | | | | | | | | | | | | It's been about a year since these were deprecated and, in most cases, removed. There's no point in carrying that documentation, or backwards compatibility for "jtag_device" and "jtag_speed", around forever. (Or a few remnants of obsolete code...) Removed a few obsolete uses of "jtag_speed": - The Calao stuff hasn't worked since July 2008. (Those Atmel targets need to work with a 32KHz core clock after reset until board-specific init-reset code sets up the PLL and enables a faster JTAg clock.) - Parport speed controls don't actually work (tops out at about 1 MHz on typical HW). - In general, speed controls need to live in board.cfg files (or sometimes target.cfg files), not interface.cfg ... Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* target.cfg: remove "-work-area-virt 0"David Brownell2009-11-0844-45/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The semantics of "-work-area-virt 0" (or phys) changed with the patch to require specifying physical or virtrual work area addresses. Specifying zero was previously a NOP. Now it means that address zero is valid. This patch addresses three related issues: - MMU-less processors should never specify work-area-virt; remove those specifications. Such processors include ARM7TDMI, Cortex-M3, and ARM966. - MMU-equipped processors *can* specify work-area-virt... but zero won't be appropriate, except in mischievous contexts (which hide null pointer exceptions). Remove those specs from those processors too. If any of those mappings is valid, someone will need to submit a patch adding it ... along with a comment saying what OS provides the mapping, and in which context. Example, say "works with Linux 2.6.30+, in kernel mode". (Note that ARM Linux doesn't map kernel memory to zero ...) - Clarify docs on that "-virt" and other work area stuff. Seems to me work-area-virt is quite problematic; not every operating system provides such static mappings; if they do, they're not in every MMU context... Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* JTAG: support KT-LINK adapterKrzysztof Kajstura2009-11-041-0/+10
| | | | Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* PXA255: support Intel "Lubbock" platformDavid Brownell2009-11-041-0/+110
| | | | | | | | | | | | | | | | | | Config for Intel's "Lubbock" PXA255 development board. Even more so than the PXA255 itself, this is obsolete. AFAIK this was the first generally available development platform for PXA255. Intel stopped providing these after other devel boards became available. One interesting thing about this board from the OpenOCD perspective is probably its flash configuration. Each bank is 32 bits wide, built from two 16-bit StrataFlash chips wired in parallel. This doubles throughput ... it reads/writes 32 bits in the time a single chip takes to write just 16 bits. This conf mostly works, given XScale bugfixes, but has some issues (notably: no access to the on-board SDRAM) flagged by FIXMEs. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* remove "-ircapture 0x1 -irmask 0x1" from stm32.cfgFreddie Chopin2009-11-011-2/+5
| | | | | | | | Gets rid of the runtime warning "stm32.bs: nonstandard IR mask" [dbrownell@users.sourceforge.net: line lengths, note issue, section ref] Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
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